Handle wide AND/NOR devices with Virtex carry logic.
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steve
parent
d71d52bfe9
commit
9a3c9507ed
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: d-virtex.c,v 1.19 2002/11/22 01:45:40 steve Exp $"
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#ident "$Id: d-virtex.c,v 1.20 2002/11/22 05:46:06 steve Exp $"
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#endif
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# include "device.h"
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@ -431,6 +431,226 @@ void edif_show_cellref_logic(ivl_net_logic_t net, const char*cellref)
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}
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}
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/*
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* This function draw wide AND-like devices. The input must have at
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* least 5 bits.
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*/
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static void wide_AND_logic(ivl_net_logic_t net, unsigned edif_uref)
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{
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char jbuf[1024];
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/* This is the number of input bits left to connect. */
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unsigned ibits = ivl_logic_pins(net) - 1;
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/* Index to the next input bit. */
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unsigned idx = 1;
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unsigned slice = 0;
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const char*lut4_init;
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const char*lut3_init;
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const char*lut2_init;
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const char*lut1_dev;
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switch (ivl_logic_type(net)) {
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case IVL_LO_AND:
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lut4_init = "\"8000\"";
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lut3_init = "\"80\"";
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lut2_init = "\"8\"";
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lut1_dev = "BUF";
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break;
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case IVL_LO_NOR:
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lut4_init = "\"0001\"";
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lut3_init = "\"01\"";
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lut2_init = "\"1\"";
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lut1_dev = "INV";
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break;
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default:
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assert(0);
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}
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assert(ibits > 4);
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while (ibits >= 4) {
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/* The least significant bits are ANDed together 4 at a
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time with LUT4 devices. The output of the LUT4 device
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connects to a MUXCY device that passes its output
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up to the next stage.
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The DI input of the MUXCY (S==0) is connected to
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ground, so that the ouput of the chain is pinned to 0
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if this slice does not AND to 1.
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If the LUT emits 1, S==1 and this slice passes the
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compare from below. So the CI of the MUXCY gets the O
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of the MUXCY one slice back. */
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fprintf(xnf, "(instance U%uL%u"
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" (viewRef net"
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" (cellRef LUT4 (libraryRef VIRTEX)))"
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" (property INIT (string %s)))\n",
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edif_uref, slice, lut4_init);
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fprintf(xnf, "(instance U%uM%u"
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" (viewRef net"
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" (cellRef MUXCY (libraryRef VIRTEX))))\n",
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edif_uref, slice);
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fprintf(xnf, "(instance U%uG%u"
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" (viewRef net"
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" (cellRef GND (libraryRef VIRTEX))))\n",
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edif_uref, slice);
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fprintf(xnf, "(net U%uLM%u (joined"
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" (portRef O (instanceRef U%uL%u))"
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" (portRef S (instanceRef U%uM%u))))\n",
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edif_uref, slice,
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edif_uref, slice,
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edif_uref, slice);
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fprintf(xnf, "(net U%uGM%u (joined"
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" (portRef GROUND (instanceRef U%uG%u))"
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" (portRef DI (instanceRef U%uM%u))))\n",
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edif_uref, slice,
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edif_uref, slice,
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edif_uref, slice);
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if (slice == 0) {
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fprintf(xnf, "(instance U%uV%u"
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" (viewRef net"
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" (cellRef VCC (libraryRef VIRTEX))))\n",
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edif_uref, slice);
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fprintf(xnf, "(net U%uMM%u (joined"
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" (portRef VCC (instanceRef U%uG%u))"
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" (portRef CI (instanceRef U%uM%u))))\n",
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edif_uref, slice,
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edif_uref, slice,
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edif_uref, slice);
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} else {
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fprintf(xnf, "(net U%uMM%u (joined"
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" (portRef O (instanceReg U%uM%u))"
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" (portReg CI (instanceRef U%uM%u))))\n",
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edif_uref, slice,
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edif_uref, slice-1,
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edif_uref, slice);
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}
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sprintf(jbuf, "(portRef I0 (instanceRef U%uL%u))",
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edif_uref, slice);
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edif_set_nexus_joint(ivl_logic_pin(net, idx+0), jbuf);
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sprintf(jbuf, "(portRef I1 (instanceRef U%uL%u))",
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edif_uref, slice);
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edif_set_nexus_joint(ivl_logic_pin(net, idx+1), jbuf);
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sprintf(jbuf, "(portRef I2 (instanceRef U%uL%u))",
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edif_uref, slice);
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edif_set_nexus_joint(ivl_logic_pin(net, idx+2), jbuf);
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sprintf(jbuf, "(portRef I3 (instanceRef U%uL%u))",
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edif_uref, slice);
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edif_set_nexus_joint(ivl_logic_pin(net, idx+3), jbuf);
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ibits -= 4;
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idx += 4;
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slice += 1;
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}
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if (ibits == 0) {
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sprintf(jbuf, "(portRef O (instanceRef U%uM%u))",
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edif_uref, slice-1);
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edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
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return;
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}
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switch (ibits) {
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case 1:
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fprintf(xnf, "(instance U%uL%u"
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" (viewRef net"
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" (cellRef %s (libraryRef VIRTEX))))\n",
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edif_uref, slice, lut1_dev);
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sprintf(jbuf, "(portRef I0 (instanceRef U%uL%u))",
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edif_uref, slice);
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edif_set_nexus_joint(ivl_logic_pin(net, idx+0), jbuf);
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break;
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case 2:
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fprintf(xnf, "(instance U%uL%u"
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" (viewRef net"
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" (cellRef LUT2 (libraryRef VIRTEX)))"
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" (property INIT (string %s)))\n",
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edif_uref, slice, lut2_init);
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sprintf(jbuf, "(portRef I0 (instanceRef U%uL%u))",
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edif_uref, slice);
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edif_set_nexus_joint(ivl_logic_pin(net, idx+0), jbuf);
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sprintf(jbuf, "(portRef I1 (instanceRef U%uL%u))",
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edif_uref, slice);
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edif_set_nexus_joint(ivl_logic_pin(net, idx+1), jbuf);
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break;
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case 3:
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fprintf(xnf, "(instance U%uL%u"
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" (viewRef net"
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" (cellRef LUT3 (libraryRef VIRTEX)))"
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" (property INIT (string %s)))\n",
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edif_uref, slice, lut3_init);
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sprintf(jbuf, "(portRef I0 (instanceRef U%uL%u))",
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edif_uref, slice);
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edif_set_nexus_joint(ivl_logic_pin(net, idx+0), jbuf);
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sprintf(jbuf, "(portRef I1 (instanceRef U%uL%u))",
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edif_uref, slice);
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edif_set_nexus_joint(ivl_logic_pin(net, idx+1), jbuf);
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sprintf(jbuf, "(portRef I2 (instanceRef U%uL%u))",
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edif_uref, slice);
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edif_set_nexus_joint(ivl_logic_pin(net, idx+2), jbuf);
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default:
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assert(0);
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}
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fprintf(xnf, "(instance U%uM%u"
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" (viewRef net"
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" (cellRef MUXCY (libraryRef VIRTEX))))\n",
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edif_uref, slice);
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fprintf(xnf, "(instance U%uG%u"
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" (viewRef net"
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" (cellRef GND (libraryRef VIRTEX))))\n",
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edif_uref, slice);
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fprintf(xnf, "(net U%uLM%u (joined"
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" (portRef O (instanceRef U%uL%u))"
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" (portRef S (instanceRef U%uM%u))))\n",
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edif_uref, slice,
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edif_uref, slice,
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edif_uref, slice);
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fprintf(xnf, "(net U%uGM%u (joined"
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" (portRef GROUND (instanceRef U%uG%u))"
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" (portRef DI (instanceRef U%uM%u))))\n",
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edif_uref, slice,
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edif_uref, slice,
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edif_uref, slice);
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fprintf(xnf, "(net U%uMM%u (joined"
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" (portRef O (instanceReg U%uM%u))"
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" (portReg CI (instanceRef U%uM%u))))\n",
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edif_uref, slice,
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edif_uref, slice-1,
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edif_uref, slice);
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sprintf(jbuf, "(portRef O (instanceRef U%uM%u))",
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edif_uref, slice);
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edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
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}
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static void edif_show_virtex_logic(ivl_net_logic_t net)
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{
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char jbuf[1024];
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@ -447,7 +667,6 @@ static void edif_show_virtex_logic(ivl_net_logic_t net)
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switch (ivl_logic_type(net)) {
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case IVL_LO_AND:
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assert(ivl_logic_pins(net) <= 5);
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assert(ivl_logic_pins(net) >= 3);
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switch (ivl_logic_pins(net)) {
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@ -472,6 +691,9 @@ static void edif_show_virtex_logic(ivl_net_logic_t net)
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ivl_logic_pin(net, 3),
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ivl_logic_pin(net, 4), "8000");
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break;
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default:
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wide_AND_logic(net, edif_uref);
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break;
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}
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break;
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@ -508,7 +730,6 @@ static void edif_show_virtex_logic(ivl_net_logic_t net)
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break;
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case IVL_LO_NOR:
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assert(ivl_logic_pins(net) <= 5);
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assert(ivl_logic_pins(net) >= 3);
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switch (ivl_logic_pins(net)) {
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@ -533,6 +754,9 @@ static void edif_show_virtex_logic(ivl_net_logic_t net)
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ivl_logic_pin(net, 3),
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ivl_logic_pin(net, 4), "0001");
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break;
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default:
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wide_AND_logic(net, edif_uref);
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break;
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}
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break;
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@ -1683,6 +1907,9 @@ const struct device_s d_virtex_edif = {
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/*
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* $Log: d-virtex.c,v $
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* Revision 1.20 2002/11/22 05:46:06 steve
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* Handle wide AND/NOR devices with Virtex carry logic.
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*
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* Revision 1.19 2002/11/22 01:45:40 steve
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* Implement bufif1 as BUFT
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*
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