Virtex and Virtex2 share much code.
This commit is contained in:
steve
parent
f7162eb538
commit
0e797dc7bc
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@ -16,7 +16,7 @@
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# 59 Temple Place - Suite 330
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# Boston, MA 02111-1307, USA
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#
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#ident "$Id: Makefile.in,v 1.9 2003/04/05 05:53:34 steve Exp $"
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#ident "$Id: Makefile.in,v 1.10 2003/06/25 02:55:57 steve Exp $"
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#
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#
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SHELL = /bin/sh
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@ -53,7 +53,7 @@ dep:
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mv $*.d dep
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D = d-generic.o d-generic-edif.o d-virtex.o d-virtex2.o
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O = edif.o fpga.o gates.o mangle.o tables.o xilinx.o $D
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O = edif.o fpga.o gates.o mangle.o tables.o generic.o xilinx.o $D
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ifeq (@WIN32@,yes)
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TGTLDFLAGS=-L.. -livl
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2348
tgt-fpga/d-virtex.c
2348
tgt-fpga/d-virtex.c
File diff suppressed because it is too large
Load Diff
1045
tgt-fpga/d-virtex2.c
1045
tgt-fpga/d-virtex2.c
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,41 @@
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/*
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* Copyright (c) 2003 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifndef HAVE_CVS_IDENT
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#ident "$Id: generic.c,v 1.1 2003/06/25 02:55:57 steve Exp $"
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#endif
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# include "generic.h"
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edif_t edf = 0;
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edif_xlibrary_t xlib = 0;
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edif_cell_t cell_0 = 0;
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edif_cell_t cell_1 = 0;
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edif_cell_t cell_ipad = 0;
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edif_cell_t cell_opad = 0;
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/*
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* $Log: generic.c,v $
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* Revision 1.1 2003/06/25 02:55:57 steve
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* Virtex and Virtex2 share much code.
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*
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*/
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@ -0,0 +1,51 @@
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#ifndef __generic_H
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#define __generic_H
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/*
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* Copyright (c) 2003 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifndef HAVE_CVS_IDENT
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#ident "$Id: generic.h,v 1.1 2003/06/25 02:55:57 steve Exp $"
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#endif
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# include "edif.h"
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extern edif_t edf;
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extern edif_xlibrary_t xlib;
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/*
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* The cell_* variables below are the various kinds of devices that
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* this family supports as primitives. If the cell type is used at
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* least once, then the edif_cell_t is non-zero and will also be
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* included in the library declaration. The constants underneath are
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* pin assignments for the cell.
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*/
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extern edif_cell_t cell_0;
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extern edif_cell_t cell_1;
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extern edif_cell_t cell_ipad;
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extern edif_cell_t cell_opad;
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/*
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* $Log: generic.h,v $
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* Revision 1.1 2003/06/25 02:55:57 steve
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* Virtex and Virtex2 share much code.
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*
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*/
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#endif
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@ -17,10 +17,18 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: xilinx.c,v 1.1 2003/04/05 05:53:34 steve Exp $"
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#ident "$Id: xilinx.c,v 1.2 2003/06/25 02:55:57 steve Exp $"
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#endif
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# include "edif.h"
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# include "generic.h"
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# include "xilinx.h"
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# include <stdlib.h>
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# include <string.h>
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#ifdef HAVE_MALLOC_H
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# include <malloc.h>
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#endif
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# include <assert.h>
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edif_cell_t xilinx_cell_buf(edif_xlibrary_t xlib)
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{
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@ -198,10 +206,485 @@ edif_cell_t xilinx_cell_xorcy(edif_xlibrary_t xlib)
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return cell;
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}
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/*
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* Make (or retrieve) a cell in the external library that reflects the
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* scope with its ports.
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*/
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void xilinx_show_scope(ivl_scope_t scope)
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{
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edif_cell_t cell;
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edif_cellref_t ref;
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unsigned port, idx;
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cell = edif_xlibrary_scope_cell(xlib, scope);
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ref = edif_cellref_create(edf, cell);
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for (idx = 0 ; idx < ivl_scope_sigs(scope) ; idx += 1) {
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edif_joint_t jnt;
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ivl_signal_t sig = ivl_scope_sig(scope, idx);
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if (ivl_signal_port(sig) == IVL_SIP_NONE)
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continue;
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port = edif_cell_port_byname(cell, ivl_signal_basename(sig));
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jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, 0));
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edif_add_to_joint(jnt, ref, port);
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}
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}
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void xilinx_pad(ivl_signal_t sig, const char*str)
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{
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unsigned idx;
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unsigned*pins;
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if (cell_ipad == 0) {
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cell_ipad = edif_xcell_create(xlib, "IPAD", 1);
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edif_cell_portconfig(cell_ipad, 0, "IPAD", IVL_SIP_OUTPUT);
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}
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if (cell_opad == 0) {
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cell_opad = edif_xcell_create(xlib, "OPAD", 1);
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edif_cell_portconfig(cell_opad, 0, "OPAD", IVL_SIP_OUTPUT);
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}
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/* Collect an array of pin assignments from the attribute
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string passed in as str. The format is a comma separated
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list of unsigned decimal integers. */
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pins = calloc(ivl_signal_pins(sig), sizeof(unsigned));
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for (idx = 0 ; idx < ivl_signal_pins(sig) ; idx += 1) {
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char*tmp;
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pins[idx] = strtoul(str, &tmp, 10);
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switch (*tmp) {
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case ',':
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tmp += 1;
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break;
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case 0:
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break;
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default:
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assert(0);
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}
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str = tmp;
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}
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/* Now go through the pins of the signal, creating pads and
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bufs and joining them to the signal nexus. */
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for (idx = 0 ; idx < ivl_signal_pins(sig) ; idx += 1) {
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edif_joint_t jnt;
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edif_cellref_t pad, buf;
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const char*name_str = ivl_signal_basename(sig);
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if (ivl_signal_pins(sig) > 1) {
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char name_buf[128];
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sprintf(name_buf, "%s[%u]", name_str, idx);
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name_str = strdup(name_buf);
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}
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switch (ivl_signal_port(sig)) {
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case IVL_SIP_INPUT:
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pad = edif_cellref_create(edf, cell_ipad);
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buf = edif_cellref_create(edf, xilinx_cell_ibuf(xlib));
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jnt = edif_joint_create(edf);
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edif_joint_rename(jnt, name_str);
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edif_add_to_joint(jnt, pad, 0);
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edif_add_to_joint(jnt, buf, BUF_I);
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jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, idx));
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edif_add_to_joint(jnt, buf, BUF_O);
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break;
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case IVL_SIP_OUTPUT:
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pad = edif_cellref_create(edf, cell_opad);
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buf = edif_cellref_create(edf, xilinx_cell_obuf(xlib));
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jnt = edif_joint_create(edf);
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edif_joint_rename(jnt, name_str);
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edif_add_to_joint(jnt, pad, 0);
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edif_add_to_joint(jnt, buf, BUF_O);
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jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, idx));
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edif_add_to_joint(jnt, buf, BUF_I);
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break;
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default:
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assert(0);
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}
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}
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free(pins);
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}
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/*
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* This function handles the case where the user specifies the cell to
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* use by attribute.
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*/
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static void edif_cellref_logic(ivl_net_logic_t net, const char*def)
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{
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char*str = strdup(def);
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char*pins;
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edif_cell_t cell;
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edif_cellref_t ref;
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edif_joint_t jnt;
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unsigned idx, port;
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pins = strchr(str, ':');
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assert(pins);
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*pins++ = 0;
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/* Locate the cell in the library, lookup by name. */
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cell = edif_xlibrary_findcell(xlib, str);
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assert(cell);
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ref = edif_cellref_create(edf, cell);
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for (idx = 0 ; idx < ivl_logic_pins(net) ; idx += 1) {
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char*tmp;
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assert(pins);
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tmp = strchr(pins,',');
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if (tmp != 0)
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*tmp++ = 0;
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else
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tmp = 0;
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port = edif_cell_port_byname(cell, pins);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, idx));
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edif_add_to_joint(jnt, ref, port);
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pins = tmp;
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}
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free(str);
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}
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static void lut_logic(ivl_net_logic_t net, const char*init3,
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const char*init4, const char*init5)
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{
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edif_cellref_t lut;
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edif_joint_t jnt;
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const char* init;
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assert(ivl_logic_pins(net) <= 5);
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assert(ivl_logic_pins(net) >= 3);
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switch (ivl_logic_pins(net)) {
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case 3:
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lut = edif_cellref_create(edf, xilinx_cell_lut2(xlib));
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init = init3;
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break;
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case 4:
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lut = edif_cellref_create(edf, xilinx_cell_lut3(xlib));
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init = init4;
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break;
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case 5:
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lut = edif_cellref_create(edf, xilinx_cell_lut4(xlib));
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init = init5;
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break;
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}
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edif_cellref_pstring(lut, "INIT", init);
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switch (ivl_logic_pins(net)) {
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case 5:
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 4));
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edif_add_to_joint(jnt, lut, LUT_I3);
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case 4:
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 3));
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edif_add_to_joint(jnt, lut, LUT_I2);
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case 3:
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 2));
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edif_add_to_joint(jnt, lut, LUT_I1);
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}
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
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edif_add_to_joint(jnt, lut, LUT_I0);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
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edif_add_to_joint(jnt, lut, LUT_O);
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}
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void xilinx_logic(ivl_net_logic_t net)
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{
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edif_cellref_t obj;
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edif_joint_t jnt;
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{ const char*cellref_attribute = ivl_logic_attr(net, "cellref");
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if (cellref_attribute != 0) {
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edif_cellref_logic(net, cellref_attribute);
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return;
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}
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}
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switch (ivl_logic_type(net)) {
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case IVL_LO_BUF:
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case IVL_LO_BUFZ:
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assert(ivl_logic_pins(net) == 2);
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obj = edif_cellref_create(edf, xilinx_cell_buf(xlib));
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
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edif_add_to_joint(jnt, obj, BUF_O);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
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edif_add_to_joint(jnt, obj, BUF_I);
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break;
|
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|
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case IVL_LO_NOT:
|
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assert(ivl_logic_pins(net) == 2);
|
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|
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obj = edif_cellref_create(edf, xilinx_cell_inv(xlib));
|
||||
|
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
|
||||
edif_add_to_joint(jnt, obj, BUF_O);
|
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|
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
|
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edif_add_to_joint(jnt, obj, BUF_I);
|
||||
break;
|
||||
|
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case IVL_LO_AND:
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assert(ivl_logic_pins(net) <= 5);
|
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assert(ivl_logic_pins(net) >= 3);
|
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lut_logic(net, "8", "80", "8000");
|
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break;
|
||||
|
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case IVL_LO_NOR:
|
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assert(ivl_logic_pins(net) <= 5);
|
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assert(ivl_logic_pins(net) >= 3);
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lut_logic(net, "1", "01", "0001");
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break;
|
||||
|
||||
case IVL_LO_OR:
|
||||
assert(ivl_logic_pins(net) <= 5);
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assert(ivl_logic_pins(net) >= 3);
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lut_logic(net, "E", "FE", "FFFE");
|
||||
break;
|
||||
|
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case IVL_LO_XNOR:
|
||||
assert(ivl_logic_pins(net) <= 5);
|
||||
assert(ivl_logic_pins(net) >= 3);
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lut_logic(net, "9", "69", "9669");
|
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break;
|
||||
|
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case IVL_LO_XOR:
|
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assert(ivl_logic_pins(net) <= 5);
|
||||
assert(ivl_logic_pins(net) >= 3);
|
||||
lut_logic(net, "6", "96", "6996");
|
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break;
|
||||
|
||||
default:
|
||||
fprintf(stderr, "UNSUPPORTED LOGIC TYPE: %u\n",
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||||
ivl_logic_type(net));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Any Xilinx device works with this adder.
|
||||
* Generic Xilinx add only works for single bit slices.
|
||||
*/
|
||||
void xilinx_add(ivl_lpm_t net)
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||||
{
|
||||
const char*ha_init = 0;
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edif_cellref_t lut;
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edif_joint_t jnt;
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switch (ivl_lpm_type(net)) {
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||||
case IVL_LPM_ADD:
|
||||
ha_init = "6";
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||||
break;
|
||||
case IVL_LPM_SUB:
|
||||
ha_init = "9";
|
||||
break;
|
||||
default:
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||||
assert(0);
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||||
}
|
||||
|
||||
/* If this is a single bit wide, then generate only a
|
||||
half-adder. Normally this is an XOR, but if this is a SUB
|
||||
then it is an XNOR. */
|
||||
if (ivl_lpm_width(net) == 1) {
|
||||
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||||
lut = edif_cellref_create(edf, xilinx_cell_lut2(xlib));
|
||||
|
||||
jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, 0));
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edif_add_to_joint(jnt, lut, LUT_O);
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||||
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||||
jnt = edif_joint_of_nexus(edf, ivl_lpm_data(net, 0));
|
||||
edif_add_to_joint(jnt, lut, LUT_I0);
|
||||
|
||||
jnt = edif_joint_of_nexus(edf, ivl_lpm_datab(net, 0));
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||||
edif_add_to_joint(jnt, lut, LUT_I1);
|
||||
|
||||
edif_cellref_pstring(lut, "INIT", ha_init);
|
||||
return;
|
||||
}
|
||||
|
||||
assert(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* The left shift is implemented as a matrix of MUX2_1 devices. The
|
||||
* matrix has as many rows as the device width, and a column for each
|
||||
* select.
|
||||
*/
|
||||
void xilinx_shiftl(ivl_lpm_t net)
|
||||
{
|
||||
unsigned width = ivl_lpm_width(net);
|
||||
unsigned nsel = 0, swid = 0;
|
||||
unsigned sdx, qdx;
|
||||
|
||||
edif_cellref_t* cells;
|
||||
edif_cellref_t**table;
|
||||
|
||||
edif_cellref_t pad0_cell;
|
||||
edif_joint_t pad0;
|
||||
|
||||
|
||||
/* First, find out how many select inputs we really need. We
|
||||
can only use the selects that are enough to shift out the
|
||||
entire width of the device. The excess can be used as an
|
||||
enable for the last column. When disabled, the last column
|
||||
emits zeros. */
|
||||
|
||||
while (nsel < ivl_lpm_selects(net)) {
|
||||
|
||||
nsel += 1;
|
||||
|
||||
swid = 1 << nsel;
|
||||
if (swid >= width)
|
||||
break;
|
||||
}
|
||||
|
||||
assert(nsel > 0);
|
||||
|
||||
/* Allocate a matrix of edif_cellref_t variables. A devices
|
||||
will be addressed by the expression table[sdx][qdx];
|
||||
This should make the algorighm code easier to read. */
|
||||
cells = calloc(nsel * width, sizeof(edif_cellref_t));
|
||||
table = calloc(nsel, sizeof(edif_cellref_t*));
|
||||
|
||||
for (sdx = 0 ; sdx < nsel ; sdx += 1)
|
||||
table[sdx] = cells + sdx*width;
|
||||
|
||||
/* Make a 0 valued pad bit. I wlil use this for all the shifin
|
||||
values that are beyond the input. */
|
||||
pad0_cell = edif_cellref_create(edf, cell_0);
|
||||
pad0 = edif_joint_create(edf);
|
||||
edif_add_to_joint(pad0, pad0_cell, 0);
|
||||
|
||||
/* The LUT matrix is <nsel> columns of <width> devices, with
|
||||
the last column a LUT4 devices. The extra input of the
|
||||
LUT4s in the last column are used as an enable to collect
|
||||
all the excess select inputs. */
|
||||
|
||||
/* Allocate the LUT devices of the matrix, and connect the
|
||||
select inputs to I2 of all the devices of the column. */
|
||||
for (sdx = 0 ; sdx < nsel ; sdx += 1) {
|
||||
const char*init_string = 0;
|
||||
ivl_nexus_t nex = ivl_lpm_select(net,sdx);
|
||||
edif_joint_t sdx_jnt = edif_joint_of_nexus(edf, nex);
|
||||
|
||||
edif_cell_t lut;
|
||||
|
||||
if (((sdx+1) == nsel) && (nsel < ivl_lpm_selects(net))) {
|
||||
lut = xilinx_cell_lut4(xlib);
|
||||
init_string = "00CA";
|
||||
} else {
|
||||
lut = xilinx_cell_lut3(xlib);
|
||||
init_string = "CA";
|
||||
}
|
||||
|
||||
for (qdx = 0 ; qdx < width ; qdx += 1) {
|
||||
table[sdx][qdx] = edif_cellref_create(edf, lut);
|
||||
edif_add_to_joint(sdx_jnt, table[sdx][qdx], LUT_I2);
|
||||
|
||||
edif_cellref_pstring(table[sdx][qdx], "INIT", init_string);
|
||||
}
|
||||
}
|
||||
|
||||
/* Connect the inputs of the SHIFTL device to the column 0 LUT
|
||||
inputs. The slice on the low end shifts in a 0 for a select
|
||||
input. */
|
||||
for (qdx = 0 ; qdx < width ; qdx += 1) {
|
||||
ivl_nexus_t nex0, nex1;
|
||||
edif_joint_t jnt0;
|
||||
edif_joint_t jnt1;
|
||||
|
||||
nex0 = ivl_lpm_data(net,qdx);
|
||||
jnt0 = edif_joint_of_nexus(edf, nex0);
|
||||
|
||||
if (qdx > 0) {
|
||||
nex1 = ivl_lpm_data(net,qdx-1);
|
||||
jnt1 = edif_joint_of_nexus(edf, nex1);
|
||||
} else {
|
||||
jnt1 = pad0;
|
||||
}
|
||||
|
||||
edif_add_to_joint(jnt0, table[0][qdx], LUT_I0);
|
||||
edif_add_to_joint(jnt1, table[0][qdx], LUT_I1);
|
||||
}
|
||||
|
||||
/* Make the inner connections between LUT devices. Each column
|
||||
connects to the previous column, shifted by the power of
|
||||
the column value. If the shifted input falls off the end,
|
||||
then pad with zero. */
|
||||
for (sdx = 1 ; sdx < nsel ; sdx += 1) {
|
||||
|
||||
for (qdx = 0 ; qdx < width ; qdx += 1) {
|
||||
unsigned shift = 1 << sdx;
|
||||
edif_joint_t jnt0 = edif_joint_create(edf);
|
||||
edif_joint_t jnt1 = (qdx >= shift)
|
||||
? edif_joint_create(edf)
|
||||
: pad0;
|
||||
|
||||
edif_add_to_joint(jnt0, table[sdx][qdx], LUT_I0);
|
||||
edif_add_to_joint(jnt1, table[sdx][qdx], LUT_I1);
|
||||
|
||||
edif_add_to_joint(jnt0, table[sdx-1][qdx], LUT_O);
|
||||
if (qdx >= shift)
|
||||
edif_add_to_joint(jnt1, table[sdx-1][qdx-shift], LUT_O);
|
||||
}
|
||||
}
|
||||
|
||||
/* Connect the output of the last column to the output of the
|
||||
SHIFTL device. */
|
||||
for (qdx = 0 ; qdx < width ; qdx += 1) {
|
||||
ivl_nexus_t nex = ivl_lpm_q(net,qdx);
|
||||
edif_joint_t jnt = edif_joint_of_nexus(edf, nex);
|
||||
|
||||
edif_add_to_joint(jnt, table[nsel-1][qdx], LUT_O);
|
||||
}
|
||||
|
||||
/* Connect the excess select inputs to the enable inputs of
|
||||
the LUT4 devices in the last column. */
|
||||
if (nsel < ivl_lpm_selects(net)) {
|
||||
edif_joint_t jnt;
|
||||
|
||||
/* XXXX Only support 1 excess bit for now. */
|
||||
assert((nsel + 1) == ivl_lpm_selects(net));
|
||||
|
||||
jnt = edif_joint_of_nexus(edf, ivl_lpm_select(net,nsel));
|
||||
for (qdx = 0 ; qdx < width ; qdx += 1)
|
||||
edif_add_to_joint(jnt, table[nsel-1][qdx], LUT_I3);
|
||||
}
|
||||
|
||||
free(cells);
|
||||
free(table);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* $Log: xilinx.c,v $
|
||||
* Revision 1.2 2003/06/25 02:55:57 steve
|
||||
* Virtex and Virtex2 share much code.
|
||||
*
|
||||
* Revision 1.1 2003/04/05 05:53:34 steve
|
||||
* Move library cell management to common file.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: xilinx.h,v 1.1 2003/04/05 05:53:34 steve Exp $"
|
||||
#ident "$Id: xilinx.h,v 1.2 2003/06/25 02:55:57 steve Exp $"
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -93,8 +93,25 @@ extern edif_cell_t xilinx_cell_xorcy(edif_xlibrary_t xlib);
|
|||
#define XORCY_CI 1
|
||||
#define XORCY_LI 2
|
||||
|
||||
/* === Inheritable Methods === */
|
||||
|
||||
extern void virtex_show_footer(ivl_design_t des);
|
||||
extern void virtex_generic_dff(ivl_lpm_t net);
|
||||
extern void virtex_eq(ivl_lpm_t net);
|
||||
extern void virtex_ge(ivl_lpm_t net);
|
||||
extern void virtex_add(ivl_lpm_t net);
|
||||
|
||||
extern void xilinx_show_scope(ivl_scope_t scope);
|
||||
extern void xilinx_pad(ivl_signal_t, const char*str);
|
||||
extern void xilinx_logic(ivl_net_logic_t net);
|
||||
extern void xilinx_add(ivl_lpm_t net);
|
||||
extern void xilinx_shiftl(ivl_lpm_t net);
|
||||
|
||||
/*
|
||||
* $Log: xilinx.h,v $
|
||||
* Revision 1.2 2003/06/25 02:55:57 steve
|
||||
* Virtex and Virtex2 share much code.
|
||||
*
|
||||
* Revision 1.1 2003/04/05 05:53:34 steve
|
||||
* Move library cell management to common file.
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in New Issue