Add virtex support for some basic logic, the DFF
and constant signals.
This commit is contained in:
steve
parent
5e1e79b3c4
commit
356552faad
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@ -16,14 +16,50 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ident "$Id: d-generic-edif.c,v 1.1 2001/09/02 21:33:07 steve Exp $"
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#ident "$Id: d-generic-edif.c,v 1.2 2001/09/02 23:53:55 steve Exp $"
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# include "device.h"
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# include "fpga_priv.h"
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# include <stdlib.h>
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# include <string.h>
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# include <malloc.h>
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# include <assert.h>
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struct nexus_recall {
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struct nexus_recall*next;
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ivl_nexus_t nex;
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char* joined;
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};
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static struct nexus_recall*net_list = 0;
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static unsigned uref = 0;
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static void set_nexus_joint(ivl_nexus_t nex, const char*joint)
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{
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size_t newlen;
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struct nexus_recall*rec;
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rec = (struct nexus_recall*)ivl_nexus_get_private(nex);
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if (rec == 0) {
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rec = malloc(sizeof(struct nexus_recall));
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rec->nex = nex;
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rec->joined = malloc(8);
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rec->joined[0] = 0;
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rec->next = net_list;
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net_list = rec;
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ivl_nexus_set_private(nex, rec);
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}
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newlen = strlen(rec->joined) + strlen(joint) + 2;
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rec->joined = realloc(rec->joined, newlen);
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strcat(rec->joined, " ");
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strcat(rec->joined, joint);
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}
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static void show_root_ports_edif(ivl_scope_t root)
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{
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char jbuf[1024];
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unsigned cnt = ivl_scope_sigs(root);
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unsigned idx;
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@ -54,6 +90,9 @@ static void show_root_ports_edif(ivl_scope_t root)
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fprintf(xnf, " (port %s (direction %s))\n",
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use_name, dir);
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sprintf(jbuf, "(portRef %s)", use_name);
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set_nexus_joint(ivl_signal_pin(sig, 0), jbuf);
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} else {
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unsigned pin;
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@ -61,11 +100,63 @@ static void show_root_ports_edif(ivl_scope_t root)
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fprintf(xnf, " (port (rename %s_%u "
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"\"%s[%u]\") (direction %s))\n", use_name,
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pin, use_name, pin, dir);
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sprintf(jbuf, "(portRef %s_%u)", use_name, pin);
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set_nexus_joint(ivl_signal_pin(sig, pin), jbuf);
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}
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}
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}
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}
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static const char*external_library_text =
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" (external VIRTEX (edifLevel 0) (technology (numberDefinition))\n"
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" (cell AND2 (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port O (direction OUTPUT))\n"
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" (port I0 (direction INPUT))\n"
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" (port I1 (direction INPUT)))))\n"
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" (cell BUF (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port O (direction OUTPUT))\n"
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" (port I (direction INPUT)))))\n"
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" (cell FDCE (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port Q (direction OUTPUT))\n"
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" (port D (direction INPUT))\n"
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" (port C (direction INPUT))\n"
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" (port CE (direction INPUT)))))\n"
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" (cell GND (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface (port G (direction OUTPUT)))))\n"
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" (cell NOR2 (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port O (direction OUTPUT))\n"
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" (port I0 (direction INPUT))\n"
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" (port I1 (direction INPUT)))))\n"
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" (cell NOR3 (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port O (direction OUTPUT))\n"
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" (port I0 (direction INPUT))\n"
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" (port I1 (direction INPUT))\n"
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" (port I2 (direction INPUT)))))\n"
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" (cell VCC (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface (port P (direction OUTPUT)))))\n"
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" )\n"
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;
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static void edif_show_header(ivl_design_t des)
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{
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ivl_scope_t root = ivl_design_root(des);
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@ -82,6 +173,7 @@ static void edif_show_header(ivl_design_t des)
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fprintf(xnf, " (program \"Icarus Verilog/fpga.tgt\")))\n");
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/* Write out the external references here? */
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fputs(external_library_text, xnf);
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/* Write out the library header */
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fprintf(xnf, " (library DESIGN\n");
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@ -102,10 +194,64 @@ static void edif_show_header(ivl_design_t des)
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fprintf(xnf, " (contents\n");
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}
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static void edif_show_consts(ivl_design_t des)
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{
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unsigned idx;
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char jbuf[128];
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for (idx = 0 ; idx < ivl_design_consts(des) ; idx += 1) {
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unsigned pin;
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ivl_net_const_t net = ivl_design_const(des, idx);
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const char*val = ivl_const_bits(net);
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for (pin = 0 ; pin < ivl_const_pins(net) ; pin += 1) {
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ivl_nexus_t nex = ivl_const_pin(net, pin);
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const char*name;
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const char*port;
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uref += 1;
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switch (val[pin]) {
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case '0':
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name = "GND";
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port = "G";
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break;
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case '1':
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name = "VCC";
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port = "P";
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break;
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default:
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name = "???";
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port = "?";
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break;
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}
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fprintf(xnf, "(instance U%u "
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"(viewRef Netlist_representation"
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" (cellRef %s (libraryRef VIRTEX))))\n",
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uref, name);
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sprintf(jbuf, "(portRef %s (instanceRef U%u))",
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port, uref);
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set_nexus_joint(nex, jbuf);
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}
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}
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}
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static void edif_show_footer(ivl_design_t des)
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{
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unsigned nref = 0;
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struct nexus_recall*cur;
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ivl_scope_t root = ivl_design_root(des);
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edif_show_consts(des);
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for (cur = net_list ; cur ; cur = cur->next) {
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fprintf(xnf, "(net N%u (joined %s))\n", nref, cur->joined);
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nref += 1;
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}
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fprintf(xnf, " )\n"); /* end the (contents ) sexp */
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fprintf(xnf, " )\n"); /* end the (view ) sexp */
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fprintf(xnf, " )\n"); /* end the (cell ) sexp */
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@ -126,21 +272,101 @@ static void edif_show_footer(ivl_design_t des)
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static void edif_show_logic(ivl_net_logic_t net)
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{
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char jbuf[1024];
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unsigned idx;
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uref += 1;
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switch (ivl_logic_type(net)) {
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case IVL_LO_AND:
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assert(ivl_logic_pins(net) <= 10);
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assert(ivl_logic_pins(net) >= 3);
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fprintf(xnf, "(instance (rename U%u \"%s\")",
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uref, ivl_logic_name(net));
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fprintf(xnf, " (viewRef Netlist_representation"
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" (cellRef AND%u (libraryRef VIRTEX))))\n",
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ivl_logic_pins(net) - 1);
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sprintf(jbuf, "(portRef O (instanceRef U%u))", uref);
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set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
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for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
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sprintf(jbuf, "(portRef I%u (instanceRef U%u))",
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idx-1, uref);
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set_nexus_joint(ivl_logic_pin(net, idx), jbuf);
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}
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break;
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case IVL_LO_BUF:
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assert(ivl_logic_pins(net) == 2);
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fprintf(xnf, " (instance");
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fprintf(xnf, " %s", ivl_logic_name(net));
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fprintf(xnf, "(instance (rename U%u \"%s\")",
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uref, ivl_logic_name(net));
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fprintf(xnf, " (viewRef Netlist_representation"
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" (cellRef BUF (libraryRef VIRTEX))))\n");
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sprintf(jbuf, "(portRef O (instanceRef U%u))", uref);
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set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
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sprintf(jbuf, "(portRef I (instanceRef U%u))", uref);
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set_nexus_joint(ivl_logic_pin(net, 1), jbuf);
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break;
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case IVL_LO_NOR:
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assert(ivl_logic_pins(net) <= 10);
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assert(ivl_logic_pins(net) >= 3);
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fprintf(xnf, "(instance (rename U%u \"%s\")",
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uref, ivl_logic_name(net));
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fprintf(xnf, " (viewRef Netlist_representation"
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" (cellRef NOR%u (libraryRef VIRTEX))))\n",
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ivl_logic_pins(net) - 1);
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sprintf(jbuf, "(portRef O (instanceRef U%u))", uref);
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set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
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for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
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sprintf(jbuf, "(portRef I%u (instanceRef U%u))",
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idx-1, uref);
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set_nexus_joint(ivl_logic_pin(net, idx), jbuf);
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}
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break;
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default:
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fprintf(stderr, "UNSUPPORT LOGIC TYPE: %u\n", ivl_logic_type(net));
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}
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}
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static void edif_show_dff(ivl_lpm_t net)
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{
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ivl_nexus_t nex;
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char jbuf[1024];
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assert(ivl_lpm_width(net) == 1);
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uref += 1;
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fprintf(xnf, "(instance (rename U%u \"%s\")", uref, ivl_lpm_name(net));
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fprintf(xnf, " (viewRef Netlist_representation"
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" (cellRef FDCE (libraryRef VIRTEX))))\n");
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nex = ivl_lpm_q(net, 0);
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sprintf(jbuf, "(portRef Q (instanceRef U%u))", uref);
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set_nexus_joint(nex, jbuf);
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nex = ivl_lpm_data(net, 0);
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sprintf(jbuf, "(portRef D (instanceRef U%u))", uref);
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set_nexus_joint(nex, jbuf);
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nex = ivl_lpm_clk(net);
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sprintf(jbuf, "(portRef C (instanceRef U%u))", uref);
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set_nexus_joint(nex, jbuf);
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if ((nex = ivl_lpm_enable(net))) {
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sprintf(jbuf, "(portRef CE (instanceRef U%u))", uref);
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set_nexus_joint(nex, jbuf);
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}
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}
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@ -158,6 +384,10 @@ const struct device_s d_generic_edif = {
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/*
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* $Log: d-generic-edif.c,v $
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* Revision 1.2 2001/09/02 23:53:55 steve
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* Add virtex support for some basic logic, the DFF
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* and constant signals.
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*
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* Revision 1.1 2001/09/02 21:33:07 steve
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* Rearrange the XNF code generator to be generic-xnf
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* so that non-XNF code generation is also possible.
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