Add ivl_synthesis_cell support for virtex2.
This commit is contained in:
steve
parent
21ff80075a
commit
79248d0592
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: d-generic-edif.c,v 1.14 2003/06/17 03:47:41 steve Exp $"
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#ident "$Id: d-generic-edif.c,v 1.15 2003/06/24 03:55:00 steve Exp $"
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#endif
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# include "device.h"
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@ -459,6 +459,7 @@ void edif_show_generic_dff(ivl_lpm_t net)
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const struct device_s d_generic_edif = {
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edif_show_header,
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edif_show_footer,
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0, /* show_cell_scope not implemented. */
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0, /* draw_pad not implemented */
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edif_show_logic,
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edif_show_generic_dff,
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@ -475,6 +476,9 @@ const struct device_s d_generic_edif = {
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/*
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* $Log: d-generic-edif.c,v $
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* Revision 1.15 2003/06/24 03:55:00 steve
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* Add ivl_synthesis_cell support for virtex2.
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*
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* Revision 1.14 2003/06/17 03:47:41 steve
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* Handle bufz as buf in generic fpga/edif target.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: d-generic.c,v 1.12 2002/10/28 02:05:56 steve Exp $"
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#ident "$Id: d-generic.c,v 1.13 2003/06/24 03:55:00 steve Exp $"
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#endif
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# include "device.h"
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@ -498,6 +498,7 @@ static void generic_show_add(ivl_lpm_t net)
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const struct device_s d_generic = {
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generic_show_header,
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generic_show_footer,
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0, /* show_scope */
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0, /* show_pad not implemented */
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generic_show_logic,
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generic_show_dff,
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@ -514,6 +515,9 @@ const struct device_s d_generic = {
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/*
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* $Log: d-generic.c,v $
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* Revision 1.13 2003/06/24 03:55:00 steve
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* Add ivl_synthesis_cell support for virtex2.
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*
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* Revision 1.12 2002/10/28 02:05:56 steve
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* Add Virtex code generators for left shift,
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* subtraction, and GE comparators.
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: d-virtex.c,v 1.22 2003/02/26 01:24:42 steve Exp $"
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#ident "$Id: d-virtex.c,v 1.23 2003/06/24 03:55:00 steve Exp $"
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#endif
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# include "device.h"
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@ -1924,6 +1924,7 @@ static void virtex_show_shiftl(ivl_lpm_t net)
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const struct device_s d_virtex_edif = {
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edif_show_header,
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edif_show_footer,
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0, /* show_scope not implemented */
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edif_show_virtex_pad,
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edif_show_virtex_logic,
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edif_show_generic_dff,
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@ -1940,6 +1941,9 @@ const struct device_s d_virtex_edif = {
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/*
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* $Log: d-virtex.c,v $
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* Revision 1.23 2003/06/24 03:55:00 steve
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* Add ivl_synthesis_cell support for virtex2.
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*
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* Revision 1.22 2003/02/26 01:24:42 steve
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* ivl_lpm_name is obsolete.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: d-virtex2.c,v 1.10 2003/04/05 05:53:34 steve Exp $"
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#ident "$Id: d-virtex2.c,v 1.11 2003/06/24 03:55:00 steve Exp $"
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#endif
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# include "device.h"
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@ -49,7 +49,10 @@ static edif_cell_t cell_1 = 0;
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static edif_cell_t cell_ipad = 0;
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static edif_cell_t cell_opad = 0;
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/*
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* This is a table of cell types that are accessible via the cellref
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* attribute to a gate.
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*/
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const static struct edif_xlib_celltable virtex2_celltable[] = {
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{ "BUFG", xilinx_cell_bufg },
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{ "MULT_AND", xilinx_cell_mult_and },
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@ -177,6 +180,33 @@ static void virtex2_show_footer(ivl_design_t des)
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edif_print(xnf, edf);
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}
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/*
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* Make (or retreive) a cell in the external library that reflects the
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* scope with its ports.
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*/
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static void virtex2_show_scope(ivl_scope_t scope)
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{
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edif_cell_t cell;
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edif_cellref_t ref;
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unsigned port, idx;
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cell = edif_xlibrary_scope_cell(xlib, scope);
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ref = edif_cellref_create(edf, cell);
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for (idx = 0 ; idx < ivl_scope_sigs(scope) ; idx += 1) {
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edif_joint_t jnt;
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ivl_signal_t sig = ivl_scope_sig(scope, idx);
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if (ivl_signal_port(sig) == IVL_SIP_NONE)
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continue;
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port = edif_cell_port_byname(cell, ivl_signal_basename(sig));
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jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, 0));
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edif_add_to_joint(jnt, ref, port);
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}
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}
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static void virtex2_pad(ivl_signal_t sig, const char*str)
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{
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unsigned idx;
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@ -1080,6 +1110,7 @@ static void virtex2_cmp_ge(ivl_lpm_t net)
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const struct device_s d_virtex2_edif = {
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virtex2_show_header,
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virtex2_show_footer,
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virtex2_show_scope,
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virtex2_pad,
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virtex2_logic,
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virtex2_generic_dff,
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@ -1096,6 +1127,9 @@ const struct device_s d_virtex2_edif = {
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/*
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* $Log: d-virtex2.c,v $
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* Revision 1.11 2003/06/24 03:55:00 steve
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* Add ivl_synthesis_cell support for virtex2.
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*
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* Revision 1.10 2003/04/05 05:53:34 steve
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* Move library cell management to common file.
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*
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@ -1,7 +1,7 @@
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#ifndef __device_H
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#define __device_H
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/*
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* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2001-2003 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: device.h,v 1.10 2002/10/28 02:05:56 steve Exp $"
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#ident "$Id: device.h,v 1.11 2003/06/24 03:55:00 steve Exp $"
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#endif
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# include <ivl_target.h>
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@ -41,6 +41,8 @@ struct device_s {
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/* These methods draw leading and trailing format text. */
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void (*show_header)(ivl_design_t des);
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void (*show_footer)(ivl_design_t des);
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/* Draw scopes marked by ivl_synthesis_cell */
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void (*show_cell_scope)(ivl_scope_t net);
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/* Draw pads connected to the specified signal. */
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void (*show_pad)(ivl_signal_t sig, const char*str);
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/* Draw basic logic devices. */
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@ -73,6 +75,9 @@ extern device_t device_from_arch(const char*arch);
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/*
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* $Log: device.h,v $
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* Revision 1.11 2003/06/24 03:55:00 steve
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* Add ivl_synthesis_cell support for virtex2.
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*
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* Revision 1.10 2002/10/28 02:05:56 steve
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* Add Virtex code generators for left shift,
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* subtraction, and GE comparators.
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: edif.c,v 1.4 2003/04/04 04:59:03 steve Exp $"
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#ident "$Id: edif.c,v 1.5 2003/06/24 03:55:00 steve Exp $"
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#endif
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# include "edif.h"
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@ -199,6 +199,45 @@ edif_cell_t edif_xlibrary_findcell(edif_xlibrary_t xlib,
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return 0;
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}
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edif_cell_t edif_xlibrary_scope_cell(edif_xlibrary_t xlib,
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ivl_scope_t scope)
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{
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unsigned port_count, idx;
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edif_cell_t cur;
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/* Check to see if the cell is already somehow defined. */
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cur = edif_xlibrary_findcell(xlib, ivl_scope_tname(scope));
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if (cur) return cur;
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/* Count the ports of the scope. */
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port_count = 0;
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for (idx = 0 ; idx < ivl_scope_sigs(scope) ; idx += 1) {
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ivl_signal_t sig = ivl_scope_sig(scope, idx);
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if (ivl_signal_port(sig) == IVL_SIP_NONE)
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continue;
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port_count += 1;
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}
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cur = edif_xcell_create(xlib, ivl_scope_tname(scope), port_count);
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port_count = 0;
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for (idx = 0 ; idx < ivl_scope_sigs(scope) ; idx += 1) {
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ivl_signal_t sig = ivl_scope_sig(scope, idx);
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if (ivl_signal_port(sig) == IVL_SIP_NONE)
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continue;
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edif_cell_portconfig(cur, port_count,
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ivl_signal_basename(sig),
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ivl_signal_port(sig));
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port_count += 1;
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}
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return cur;
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}
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edif_cell_t edif_xcell_create(edif_xlibrary_t xlib, const char*name,
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unsigned nports)
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{
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@ -491,6 +530,9 @@ void edif_print(FILE*fd, edif_t edf)
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/*
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* $Log: edif.c,v $
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* Revision 1.5 2003/06/24 03:55:00 steve
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* Add ivl_synthesis_cell support for virtex2.
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*
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* Revision 1.4 2003/04/04 04:59:03 steve
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* Add xlibrary celltable.
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*
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: edif.h,v 1.3 2003/04/04 04:59:03 steve Exp $"
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#ident "$Id: edif.h,v 1.4 2003/06/24 03:55:00 steve Exp $"
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#endif
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# include <stdio.h>
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@ -150,6 +150,11 @@ extern void edif_xlibrary_set_celltable(edif_xlibrary_t lib,
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extern edif_cell_t edif_xlibrary_findcell(edif_xlibrary_t lib,
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const char*cell_name);
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/* Similar to the above, but it gets the information it needs from the
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ivl_scope_t object. */
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extern edif_cell_t edif_xlibrary_scope_cell(edif_xlibrary_t xlib,
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ivl_scope_t scope);
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/* Create a new cell, attached to the external library. Specify the
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number of ports that the cell has. The edif_cell_portconfig
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function is then used to assign name and direction to each of the
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@ -211,6 +216,9 @@ extern void edif_print(FILE*fd, edif_t design);
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/*
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* $Log: edif.h,v $
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* Revision 1.4 2003/06/24 03:55:00 steve
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* Add ivl_synthesis_cell support for virtex2.
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*
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* Revision 1.3 2003/04/04 04:59:03 steve
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* Add xlibrary celltable.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: fpga.c,v 1.6 2002/08/12 01:35:02 steve Exp $"
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#ident "$Id: fpga.c,v 1.7 2003/06/24 03:55:00 steve Exp $"
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#endif
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# include "config.h"
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@ -27,6 +27,7 @@
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*/
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# include <ivl_target.h>
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# include <string.h>
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# include "fpga_priv.h"
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@ -38,8 +39,29 @@ const char*part = 0;
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const char*arch = 0;
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device_t device = 0;
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int scope_has_attribute(ivl_scope_t s, const char *name)
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{
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int i;
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const struct ivl_attribute_s *a;
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for (i=0; i<ivl_scope_attr_cnt(s); i++) {
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a = ivl_scope_attr_val(s, i);
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fprintf(stderr, "scope attribute key %s\n", a->key);
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if (strcmp(a->key,name) == 0)
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return 1;
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}
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return 0;
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}
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static int show_process(ivl_process_t net, void*x)
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{
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ivl_scope_t scope = ivl_process_scope(net);
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/* Ignore processes that are within scopes that are cells. The
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cell_scope will generate a cell to represent the entire
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scope. */
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if (scope_has_attribute(scope, "ivl_synthesis_cell"))
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return 0;
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fprintf(stderr, "fpga target: unsynthesized behavioral code\n");
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return 0;
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}
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@ -123,6 +145,9 @@ int target_design(ivl_design_t des)
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/*
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* $Log: fpga.c,v $
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* Revision 1.7 2003/06/24 03:55:00 steve
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* Add ivl_synthesis_cell support for virtex2.
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*
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* Revision 1.6 2002/08/12 01:35:02 steve
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* conditional ident string using autoconfig.
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*
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: fpga_priv.h,v 1.6 2002/08/12 01:35:03 steve Exp $"
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#ident "$Id: fpga_priv.h,v 1.7 2003/06/24 03:55:00 steve Exp $"
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#endif
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# include <stdio.h>
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@ -37,6 +37,11 @@ extern device_t device;
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extern const char*part;
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extern const char*arch;
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/*
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* Attribute lookup, should this be provided in ivl_target.h?
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*/
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int scope_has_attribute(ivl_scope_t s, const char *name);
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/*
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* These are mangle functions.
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*/
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@ -83,6 +88,9 @@ extern unsigned edif_uref;
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/*
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* $Log: fpga_priv.h,v $
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* Revision 1.7 2003/06/24 03:55:00 steve
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* Add ivl_synthesis_cell support for virtex2.
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*
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* Revision 1.6 2002/08/12 01:35:03 steve
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* conditional ident string using autoconfig.
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*
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@ -17,13 +17,24 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: gates.c,v 1.10 2002/10/28 02:05:56 steve Exp $"
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#ident "$Id: gates.c,v 1.11 2003/06/24 03:55:01 steve Exp $"
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#endif
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# include <ivl_target.h>
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# include "fpga_priv.h"
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# include <assert.h>
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static void show_cell_scope(ivl_scope_t scope)
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{
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if (device->show_cell_scope == 0) {
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fprintf(stderr, "fpga.tgt: ivl_synthesis_cell(scope)"
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" not supported by this target.\n");
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return;
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}
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device->show_cell_scope(scope);
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}
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static void show_gate_logic(ivl_net_logic_t net)
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{
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device->show_logic(net);
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@ -125,6 +136,11 @@ int show_scope_gates(ivl_scope_t net, void*x)
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{
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unsigned idx;
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if (scope_has_attribute(net, "ivl_synthesis_cell")) {
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show_cell_scope(net);
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return 0;
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}
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for (idx = 0 ; idx < ivl_scope_logs(net) ; idx += 1)
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show_gate_logic(ivl_scope_log(net, idx));
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@ -136,6 +152,9 @@ int show_scope_gates(ivl_scope_t net, void*x)
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/*
|
||||
* $Log: gates.c,v $
|
||||
* Revision 1.11 2003/06/24 03:55:01 steve
|
||||
* Add ivl_synthesis_cell support for virtex2.
|
||||
*
|
||||
* Revision 1.10 2002/10/28 02:05:56 steve
|
||||
* Add Virtex code generators for left shift,
|
||||
* subtraction, and GE comparators.
|
||||
|
|
@ -156,21 +175,5 @@ int show_scope_gates(ivl_scope_t net, void*x)
|
|||
* so that non-XNF code generation is also possible.
|
||||
*
|
||||
* Start into the virtex EDIF output driver.
|
||||
*
|
||||
* Revision 1.5 2001/09/01 04:30:44 steve
|
||||
* Generic ADD code.
|
||||
*
|
||||
* Revision 1.4 2001/09/01 02:28:42 steve
|
||||
* Generate code for MUX devices.
|
||||
*
|
||||
* Revision 1.3 2001/09/01 02:01:30 steve
|
||||
* identity compare, and PWR records for constants.
|
||||
*
|
||||
* Revision 1.2 2001/08/30 04:31:04 steve
|
||||
* Mangle nexus names.
|
||||
*
|
||||
* Revision 1.1 2001/08/28 04:14:20 steve
|
||||
* Add the fpga target.
|
||||
*
|
||||
*/
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue