Add the fpga target.

This commit is contained in:
steve 2001-08-28 04:14:20 +00:00
parent 2002c03cef
commit f063bf833f
12 changed files with 612 additions and 4 deletions

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@ -9,7 +9,7 @@
echo "Autoconf in root..."
autoconf
for dir in vpip vvp tgt-vvp
for dir in vpip vvp tgt-vvp tgt-fpga
do
echo "Autoconf in $dir..."
( cd $dir ; autoconf )

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@ -202,6 +202,6 @@ AC_SUBST(shared)
AC_MSG_RESULT($shared)
AC_CONFIG_SUBDIRS(vpip vvp tgt-vvp)
AC_CONFIG_SUBDIRS(vpip vvp tgt-vvp tgt-fpga)
AC_OUTPUT(Makefile vpi/Makefile ivlpp/Makefile vvm/Makefile driver/Makefile tgt-null/Makefile tgt-stub/Makefile tgt-verilog/Makefile tgt-pal/Makefile)

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@ -81,11 +81,14 @@
<ivl>%B/ivl %[v-v] %W %[s-s%s] %[N-N%N] %[T-T%T] -tvvm -Fcprop -Fnodangle -fVPI_MODULE_PATH=%B %f %m -o%o.cc -- -
# -- (not supported yet)
# This is the XNF code generator.
[-txnf]
<ivl>%B/ivl %[v-v] %[s-s%s] %[N-N%N] %[T-T%T] -tvvm -Fsynth -Fsyn-rules -Fcprop -Fnodangle -o%o -- -
<ivl>%B/ivl %[v-v] %[s-s%s] %[N-N%N] %[T-T%T] -txnf -Fsynth -Fsyn-rules -Fcprop -Fnodangle -o%o -- -
# And this is another XNF code generator, under development.
[-tfpga]
<ivl>%B/ivl %[v-v] %[s-s%s] %[N-N%N] %[T-T%T] %f -tdll -fDLL=%B/fpga.tgt -Fsynth -Fsyn-rules -Fcprop -Fnodangle -o%o -- -
# --
# This is the pal code generator. The target module requires the -fpart=<type>

7
tgt-fpga/.cvsignore Normal file
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@ -0,0 +1,7 @@
configure
config.cache
config.log
config.status
Makefile
fpga.tgt
dep

90
tgt-fpga/Makefile.in Normal file
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@ -0,0 +1,90 @@
#
# This source code is free software; you can redistribute it
# and/or modify it in source code form under the terms of the GNU
# Library General Public License as published by the Free Software
# Foundation; either version 2 of the License, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU Library General Public License for more details.
#
# You should have received a copy of the GNU Library General Public
# License along with this program; if not, write to the Free
# Software Foundation, Inc.,
# 59 Temple Place - Suite 330
# Boston, MA 02111-1307, USA
#
#ident "$Id: Makefile.in,v 1.1 2001/08/28 04:14:20 steve Exp $"
#
#
SHELL = /bin/sh
VERSION = 0.0
prefix = @prefix@
exec_prefix = @exec_prefix@
srcdir = @srcdir@
VPATH = $(srcdir)
bindir = @bindir@
libdir = @libdir@
includedir = $(prefix)/include
CC = @CC@
INSTALL = @INSTALL@
INSTALL_PROGRAM = @INSTALL_PROGRAM@
INSTALL_DATA = @INSTALL_DATA@
CPPFLAGS = @CPPFLAGS@ @DEFS@ @PICFLAG@
CXXFLAGS = @CXXFLAGS@
LDFLAGS = @LDFLAGS@
all: fpga.tgt
%.o: %.c
@[ -d dep ] || mkdir dep
$(CC) -Wall -I$(srcdir)/.. $(CPPFLAGS) -MD -c $< -o $*.o
mv $*.d dep
O = fpga.o gates.o d-generic.o mangle.o
ifeq (@WIN32@,yes)
TGTLDFLAGS=-L.. -livl
TGTDEPLIBS=../libivl.a
else
TGTLDFLAGS=
TGTDEPLIBS=
endif
fpga.tgt: $O $(TGTDEPLIBS)
$(CC) @shared@ -o $@ $O $(TGTLDFLAGS)
Makefile: Makefile.in config.status
./config.status
clean:
rm -f *.o dep/*.d
distclean: clean
rm -f Makefile config.status config.log config.cache fpga.tgt
check: all
install: all installdirs $(libdir)/ivl/fpga.tgt
$(libdir)/ivl/fpga.tgt: ./fpga.tgt
$(INSTALL_DATA) ./fpga.tgt $(libdir)/ivl/fpga.tgt
installdirs: ../mkinstalldirs
$(srcdir)/../mkinstalldirs $(libdir)/ivl
uninstall:
rm -f $(libdir)/ivl/fpga.tgt
-include $(patsubst %.o, dep/%.d, $O)

65
tgt-fpga/configure.in Normal file
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@ -0,0 +1,65 @@
dnl Process this file with autoconf to produce a configure script.
AC_INIT(fpga.c)
dnl Checks for programs.
AC_PROG_CC
AC_PROG_INSTALL
AC_CANONICAL_HOST
# $host
AC_CYGWIN
AC_SUBST(CYGWIN)
# The -fPIC flag is used to tell the compiler to make position
# independent code. It is needed when making shared objects.
AC_MSG_CHECKING("for flag to make position independent code")
PICFLAG=-fPIC
case "${host}" in
*-*-cygwin*)
PICFLAG=
;;
*-*-hpux*)
PICFLAG=+z
;;
esac
AC_SUBST(PICFLAG)
AC_MSG_RESULT($PICFLAG)
AC_MSG_CHECKING("for shared library link flag")
shared=-shared
case "${host}" in
*-*-cygwin*)
shared="-mdll -Wl,--enable-auto-image-base"
if test $ac_cv_mingw32 = yes; then
shared="-shared -Wl,--enable-auto-image-base"
fi
;;
*-*-hpux*)
shared="-b"
;;
esac
AC_SUBST(shared)
AC_MSG_RESULT($shared)
AC_MSG_CHECKING("for Win32")
WIN32=no
case "${host}" in
*-*-cygwin*)
WIN32=yes
;;
esac
AC_SUBST(WIN32)
AC_MSG_RESULT($WIN32)
AC_OUTPUT(Makefile)

99
tgt-fpga/d-generic.c Normal file
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@ -0,0 +1,99 @@
/*
* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ident "$Id: d-generic.c,v 1.1 2001/08/28 04:14:20 steve Exp $"
# include "device.h"
# include "fpga_priv.h"
# include <assert.h>
/*
* This is the device emitter for the most generic FPGA. It doesn't
* know anything special about device types, so can't handle complex
* logic.
*/
static void generic_show_logic(ivl_net_logic_t net)
{
char name[1024];
ivl_nexus_t nex;
mangle_logic_name(net, name, sizeof name);
switch (ivl_logic_type(net)) {
case IVL_LO_AND:
assert(ivl_logic_pins(net) == 3);
fprintf(xnf, "SYM, %s, AND, LIBVER=2.0.0\n", name);
nex = ivl_logic_pin(net, 0);
draw_pin(nex, "O", 'O');
nex = ivl_logic_pin(net, 1);
draw_pin(nex, "I0", 'I');
nex = ivl_logic_pin(net, 2);
draw_pin(nex, "I1", 'I');
break;
case IVL_LO_BUF:
assert(ivl_logic_pins(net) == 2);
fprintf(xnf, "SYM, %s, BUF, LIBVER=2.0.0\n", name);
nex = ivl_logic_pin(net, 0);
draw_pin(nex, "O", 'O');
nex = ivl_logic_pin(net, 1);
draw_pin(nex, "I", 'I');
break;
default:
fprintf(stderr, "fpga.tgt: unknown logic type %u\n",
ivl_logic_type(net));
break;
}
fprintf(xnf, "END\n");
}
static void generic_show_dff(ivl_lpm_t net)
{
char name[1024];
ivl_nexus_t nex;
mangle_lpm_name(net, name, sizeof name);
fprintf(xnf, "SYM, %s, DFF, LIBVER=2.0.0\n", name);
nex = ivl_lpm_q(net, 0);
draw_pin(nex, "Q", 'O');
nex = ivl_lpm_data(net, 0);
draw_pin(nex, "D", 'I');
nex = ivl_lpm_clk(net);
draw_pin(nex, "CLK", 'I');
fprintf(xnf, "END\n");
}
const struct device_s d_generic = {
0, /* no parent */
generic_show_logic,
generic_show_dff
};
/*
* $Log: d-generic.c,v $
* Revision 1.1 2001/08/28 04:14:20 steve
* Add the fpga target.
*
*/

57
tgt-fpga/device.h Normal file
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@ -0,0 +1,57 @@
#ifndef __device_H
#define __device_H
/*
* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ident "$Id: device.h,v 1.1 2001/08/28 04:14:20 steve Exp $"
# include <ivl_target.h>
/*
* This code generator supports a variety of device types. It does
* this by keeping a device "driver" structure for each device
* type. The device structure contains pointers to functions that emit
* the proper XNF for a given type of device.
*
* If a device supports a method, the function pointer is filled in
* with a pointer to the proper function.
*
* If a device inherits from a parent class, then it put a pointer to
* a function that invokes the parent method.
*
* If a device does not support the method, then the pointer is null.
*/
typedef const struct device_s* device_t;
struct device_s {
/* This is the parent device type. */
struct device_s* parent;
/* Draw basic logic devices. */
void (*show_logic)(ivl_net_logic_t net);
/* This method emits a D type Flip-Flop */
void (*show_dff)(ivl_lpm_t net);
};
/*
* $Log: device.h,v $
* Revision 1.1 2001/08/28 04:14:20 steve
* Add the fpga target.
*
*/
#endif

90
tgt-fpga/fpga.c Normal file
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@ -0,0 +1,90 @@
/*
* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT) && !defined(macintosh)
#ident "$Id: fpga.c,v 1.1 2001/08/28 04:14:20 steve Exp $"
#endif
# include "config.h"
/*
* This is a null target module. It does nothing.
*/
# include <ivl_target.h>
# include "fpga_priv.h"
/* This is the opened xnf file descriptor. It is the output that this
code generator writes to. */
FILE*xnf = 0;
const char*part = 0;
device_t device = 0;
extern const struct device_s d_generic;
static int show_process(ivl_process_t net, void*x)
{
fprintf(stderr, "fpga target: unsynthesized behavioral code\n");
return 0;
}
/*
* This is the main entry point that ivl uses to invoke me, the code
* generator.
*/
int target_design(ivl_design_t des)
{
const char*path = ivl_design_flag(des, "-o");
ivl_scope_t root = ivl_design_root(des);
xnf = fopen(path, "w");
if (xnf == 0) {
perror(path);
return -1;
}
fprintf(xnf, "LCANET,6\n");
fprintf(xnf, "PROG,iverilog,$Name: $,\"Icarus Verilog/fpga.tgt\"\n");
part = ivl_design_flag(des, "part");
if (part && (part[0]!=0)) {
fprintf(xnf, "PART,%s\n", part);
}
device = &d_generic;
/* Catch any behavioral code that is left, and write warnings
that it is not supported. */
ivl_design_process(des, show_process, 0);
/* Scan the scopes, looking for gates to draw into the output
netlist. */
show_scope_gates(root, 0);
fprintf(xnf, "EOF\n");
return 0;
}
/*
* $Log: fpga.c,v $
* Revision 1.1 2001/08/28 04:14:20 steve
* Add the fpga target.
*
*/

48
tgt-fpga/fpga_priv.h Normal file
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@ -0,0 +1,48 @@
#ifndef __fpga_priv_H
#define __fpga_priv_H
/*
* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ident "$Id: fpga_priv.h,v 1.1 2001/08/28 04:14:20 steve Exp $"
# include <stdio.h>
# include "device.h"
/* This is the opened xnf file descriptor. It is the output that this
code generator writes to. */
extern FILE*xnf;
extern int show_scope_gates(ivl_scope_t net, void*x);
extern void draw_pin(ivl_nexus_t nex, const char*nam, char dir);
extern device_t device;
/*
* These are mangle functions.
*/
extern void mangle_logic_name(ivl_net_logic_t net, char*buf, size_t nbuf);
extern void mangle_lpm_name(ivl_lpm_t net, char*buf, size_t nbuf);
/*
* $Log: fpga_priv.h,v $
* Revision 1.1 2001/08/28 04:14:20 steve
* Add the fpga target.
*
*/
#endif

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tgt-fpga/gates.c Normal file
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@ -0,0 +1,83 @@
/*
* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ident "$Id: gates.c,v 1.1 2001/08/28 04:14:20 steve Exp $"
# include <ivl_target.h>
# include "fpga_priv.h"
# include <assert.h>
void draw_pin(ivl_nexus_t nex, const char*nam, char dir)
{
const char*use_name = nam;
const char*nex_name = ivl_nexus_name(nex);
int invert = 0;
if (use_name[0] == '~') {
invert = 1;
use_name += 1;
}
fprintf(xnf, " PIN, %s, %c, %s", use_name, dir, nex_name);
if (invert)
fprintf(xnf, ",,INV");
fprintf(xnf, "\n");
}
static void show_gate_logic(ivl_net_logic_t net)
{
device->show_logic(net);
}
static void show_gate_lpm(ivl_lpm_t net)
{
switch (ivl_lpm_type(net)) {
case IVL_LPM_FF:
device->show_dff(net);
break;
default:
fprintf(stderr, "fpga.tgt: unknown LPM type %u\n",
ivl_lpm_type(net));
break;
}
}
int show_scope_gates(ivl_scope_t net, void*x)
{
unsigned idx;
for (idx = 0 ; idx < ivl_scope_logs(net) ; idx += 1)
show_gate_logic(ivl_scope_log(net, idx));
for (idx = 0 ; idx < ivl_scope_lpms(net) ; idx += 1)
show_gate_lpm(ivl_scope_lpm(net, idx));
return ivl_scope_children(net, show_scope_gates, 0);
}
/*
* $Log: gates.c,v $
* Revision 1.1 2001/08/28 04:14:20 steve
* Add the fpga target.
*
*/

66
tgt-fpga/mangle.c Normal file
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@ -0,0 +1,66 @@
/*
* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ident "$Id: mangle.c,v 1.1 2001/08/28 04:14:20 steve Exp $"
# include "fpga_priv.h"
# include <string.h>
static size_t mangle_scope_name(ivl_scope_t net, char*buf, size_t nbuf)
{
unsigned cnt = 0;
ivl_scope_t parent = ivl_scope_parent(net);
if (parent) {
cnt = mangle_scope_name(parent, buf, nbuf);
buf += cnt;
nbuf -= cnt;
*buf++ = '/';
nbuf -= 1;
cnt += 1;
}
strcpy(buf, ivl_scope_basename(net));
cnt += strlen(buf);
return cnt;
}
void mangle_logic_name(ivl_net_logic_t net, char*buf, size_t nbuf)
{
size_t cnt = mangle_scope_name(ivl_logic_scope(net), buf, nbuf);
buf[cnt++] = '/';
strcpy(buf+cnt, ivl_logic_basename(net));
}
void mangle_lpm_name(ivl_lpm_t net, char*buf, size_t nbuf)
{
size_t cnt = mangle_scope_name(ivl_lpm_scope(net), buf, nbuf);
buf[cnt++] = '/';
strcpy(buf+cnt, ivl_lpm_basename(net));
}
/*
* $Log: mangle.c,v $
* Revision 1.1 2001/08/28 04:14:20 steve
* Add the fpga target.
*
*/