Rework scheduling of concat, part, buf/not and resolv for efficiency.
The concat and resolv functors are best evaluated lazily, because each evaluation is costly and there is a high probability that an evaluation will be invalidated when new input comes in. Also optimization the recv_vec4_pv method of the resolver, which is commonly used, and adjust the order of handling of vvp_fun_part to work more efficiently.
This commit is contained in:
Stephen Williams
parent
2f4e5bf5b6
commit
2e95a740da
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@ -20,6 +20,7 @@
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# include "compile.h"
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# include "vvp_net.h"
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# include "schedule.h"
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# include <stdlib.h>
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# include <iostream>
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#ifdef HAVE_MALLOC_H
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@ -27,18 +28,41 @@
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#endif
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# include <assert.h>
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/* vvp_fun_concat
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* This node function creates vectors (vvp_vector4_t) from the
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* concatenation of the inputs. The inputs (4) may be vector or
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* vector8 objects, but they are reduced to vector4 values and
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* strength information lost.
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*
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* The expected widths of the input vectors must be given up front so
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* that the positions in the output vector (and also the size of the
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* output vector) can be worked out. The input vectors must match the
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* expected width.
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*/
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class vvp_fun_concat : public vvp_net_fun_t, private vvp_gen_event_s {
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public:
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vvp_fun_concat(unsigned w0, unsigned w1,
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unsigned w2, unsigned w3);
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~vvp_fun_concat();
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void recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit);
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private:
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void run_run();
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vvp_net_t*net_;
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vvp_vector4_t input_[4];
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};
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vvp_fun_concat::vvp_fun_concat(unsigned w0, unsigned w1,
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unsigned w2, unsigned w3)
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: val_(w0+w1+w2+w3)
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: net_(0)
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{
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wid_[0] = w0;
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wid_[1] = w1;
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wid_[2] = w2;
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wid_[3] = w3;
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for (unsigned idx = 0 ; idx < val_.size() ; idx += 1)
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val_.set_bit(idx, BIT4_X);
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input_[0] = vvp_vector4_t(w0);
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input_[1] = vvp_vector4_t(w1);
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input_[2] = vvp_vector4_t(w2);
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input_[3] = vvp_vector4_t(w3);
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}
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vvp_fun_concat::~vvp_fun_concat()
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@ -49,22 +73,38 @@ void vvp_fun_concat::recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit)
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{
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unsigned pdx = port.port();
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if (bit.size() != wid_[pdx]) {
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if (bit.size() != input_[pdx].size()) {
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cerr << "internal error: port " << pdx
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<< " expects wid=" << wid_[pdx]
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<< " expects wid=" << input_[pdx].size()
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<< ", got wid=" << bit.size() << endl;
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assert(0);
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}
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unsigned off = 0;
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for (unsigned idx = 0 ; idx < pdx ; idx += 1)
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off += wid_[idx];
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if (input_[pdx] .eeq(bit))
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return;
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for (unsigned idx = 0 ; idx < wid_[pdx] ; idx += 1) {
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val_.set_bit(off+idx, bit.value(idx));
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input_[pdx] = bit;
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if (net_ == 0) {
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net_ = port.ptr();
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schedule_generic(this, 0, false);
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}
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}
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void vvp_fun_concat::run_run()
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{
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vvp_net_t*ptr = net_;
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net_ = 0;
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unsigned off = 0;
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unsigned owid = input_[0].size() + input_[1].size() + input_[2].size() + input_[3].size();
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vvp_vector4_t res (owid);
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for (unsigned idx = 0 ; idx < 4 && (off<owid) ; idx += 1) {
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res.set_vec(off, input_[idx]);
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off += input_[idx].size();
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}
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vvp_send_vec4(port.ptr()->out, val_);
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vvp_send_vec4(ptr->out, res);
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}
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void compile_concat(char*label, unsigned w0, unsigned w1,
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42
vvp/logic.cc
42
vvp/logic.cc
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@ -140,7 +140,6 @@ void vvp_fun_eeq::run_run()
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vvp_fun_buf::vvp_fun_buf()
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{
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net_ = 0;
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count_functors_logic += 1;
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}
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@ -157,25 +156,12 @@ void vvp_fun_buf::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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if (ptr.port() != 0)
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return;
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if (input_ .eeq( bit ))
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if (input_ .eq_xz( bit ))
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return;
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input_ = bit;
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if (net_ == 0) {
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net_ = ptr.ptr();
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schedule_generic(this, 0, false);
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}
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}
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void vvp_fun_buf::run_run()
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{
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vvp_net_t*ptr = net_;
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net_ = 0;
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vvp_vector4_t tmp (input_);
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tmp.change_z2x();
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vvp_send_vec4(ptr->out, tmp);
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input_.change_z2x();
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vvp_send_vec4(ptr.ptr()->out, input_);
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}
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vvp_fun_bufz::vvp_fun_bufz()
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@ -394,7 +380,6 @@ void vvp_fun_muxz::run_run()
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vvp_fun_not::vvp_fun_not()
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{
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net_ = 0;
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count_functors_logic += 1;
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}
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@ -411,30 +396,13 @@ void vvp_fun_not::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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if (ptr.port() != 0)
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return;
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if (input_ .eeq( bit ))
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if (input_ .eq_xz( bit ))
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return;
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input_ = bit;
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if (net_ == 0) {
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net_ = ptr.ptr();
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schedule_generic(this, 0, false);
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}
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vvp_send_vec4(ptr.ptr()->out, ~input_);
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}
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void vvp_fun_not::run_run()
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{
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vvp_net_t*ptr = net_;
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net_ = 0;
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vvp_vector4_t result (input_);
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for (unsigned idx = 0 ; idx < result.size() ; idx += 1) {
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vvp_bit4_t bitbit = ~ result.value(idx);
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result.set_bit(idx, bitbit);
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}
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vvp_send_vec4(ptr->out, result);
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}
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vvp_fun_or::vvp_fun_or(unsigned wid, bool invert)
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: vvp_fun_boolean_(wid), invert_(invert)
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12
vvp/logic.h
12
vvp/logic.h
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@ -69,7 +69,7 @@ class vvp_fun_eeq : public vvp_fun_boolean_ {
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* The retransmitted vector has all Z values changed to X, just like
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* the buf(Q,D) gate in Verilog.
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*/
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class vvp_fun_buf: public vvp_net_fun_t, private vvp_gen_event_s {
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class vvp_fun_buf: public vvp_net_fun_t {
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public:
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explicit vvp_fun_buf();
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@ -77,12 +77,8 @@ class vvp_fun_buf: public vvp_net_fun_t, private vvp_gen_event_s {
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void recv_vec4(vvp_net_ptr_t p, const vvp_vector4_t&bit);
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private:
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void run_run();
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private:
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vvp_vector4_t input_;
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vvp_net_t*net_;
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};
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/*
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@ -152,7 +148,7 @@ class vvp_fun_muxr : public vvp_net_fun_t, private vvp_gen_event_s {
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sel_type select_;
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};
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class vvp_fun_not: public vvp_net_fun_t, private vvp_gen_event_s {
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class vvp_fun_not: public vvp_net_fun_t {
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public:
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explicit vvp_fun_not();
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@ -160,12 +156,8 @@ class vvp_fun_not: public vvp_net_fun_t, private vvp_gen_event_s {
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void recv_vec4(vvp_net_ptr_t p, const vvp_vector4_t&bit);
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private:
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void run_run();
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private:
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vvp_vector4_t input_;
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vvp_net_t*net_;
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};
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class vvp_fun_or : public vvp_fun_boolean_ {
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27
vvp/part.cc
27
vvp/part.cc
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@ -28,7 +28,7 @@
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# include <assert.h>
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vvp_fun_part::vvp_fun_part(unsigned base, unsigned wid)
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: base_(base), wid_(wid)
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: base_(base), val_(wid)
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{
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net_ = 0;
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}
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@ -41,10 +41,18 @@ void vvp_fun_part::recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit)
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{
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assert(port.port() == 0);
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if (val_ .eeq( bit ))
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vvp_vector4_t tmp = val_;
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for (unsigned idx = 0 ; idx < tmp.size() ; idx += 1) {
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if ((idx + base_) < bit.size())
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tmp.set_bit(idx, bit.value(base_+idx));
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else
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tmp.set_bit(idx, BIT4_X);
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}
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if (val_ .eeq( tmp ))
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return;
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val_ = bit;
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val_ = tmp;
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if (net_ == 0) {
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net_ = port.ptr();
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@ -63,6 +71,11 @@ void vvp_fun_part::recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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{
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assert(bit.size() == wid);
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if (base >= base_+val_.size())
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return;
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if ((base+wid) <= base_)
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return;
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vvp_vector4_t tmp = val_;
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if (tmp.size() == 0)
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tmp = vvp_vector4_t(vwid);
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@ -76,13 +89,7 @@ void vvp_fun_part::run_run()
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{
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vvp_net_t*ptr = net_;
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net_ = 0;
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vvp_vector4_t res (wid_, BIT4_X);
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for (unsigned idx = 0 ; idx < wid_ ; idx += 1) {
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if (idx + base_ < val_.size())
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res.set_bit(idx, val_.value(base_+idx));
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}
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vvp_send_vec4(ptr->out, res);
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vvp_send_vec4(ptr->out, val_);
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}
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vvp_fun_part_pv::vvp_fun_part_pv(unsigned b, unsigned w, unsigned v)
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@ -44,18 +44,14 @@ void resolv_functor::recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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unsigned base, unsigned wid, unsigned vwid)
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{
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assert(bit.size() == wid);
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vvp_vector4_t res (vwid);
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for (unsigned idx = 0 ; idx < base ; idx += 1)
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res.set_bit(idx, BIT4_Z);
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vvp_vector8_t tmp (bit,6,6);
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vvp_vector8_t tmpw (vwid);
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for (unsigned idx = 0 ; idx < wid ; idx += 1)
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res.set_bit(idx+base, bit.value(idx));
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tmpw.set_bit(idx+base, tmp.value(idx));
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for (unsigned idx = base+wid ; idx < vwid ; idx += 1)
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res.set_bit(idx, BIT4_Z);
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recv_vec4(port, res);
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recv_vec8(port, tmpw);
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}
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void resolv_functor::recv_vec8(vvp_net_ptr_t port, const vvp_vector8_t&bit)
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@ -779,6 +779,41 @@ bool vvp_vector4_t::eeq(const vvp_vector4_t&that) const
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return true;
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}
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bool vvp_vector4_t::eq_xz(const vvp_vector4_t&that) const
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{
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if (size_ != that.size_)
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return false;
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if (size_ < BITS_PER_WORD) {
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unsigned long mask = (1UL << size_) - 1;
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return ((abits_val_|bbits_val_)&mask) == ((that.abits_val_|that.bbits_val_)&mask)
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&& (bbits_val_&mask) == (that.bbits_val_&mask);
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}
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if (size_ == BITS_PER_WORD) {
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return ((abits_val_|bbits_val_) == (that.abits_val_|that.bbits_val_))
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&& (bbits_val_ == that.bbits_val_);
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}
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unsigned words = size_ / BITS_PER_WORD;
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for (unsigned idx = 0 ; idx < words ; idx += 1) {
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if ((abits_ptr_[idx]|bbits_ptr_[idx]) != (that.abits_ptr_[idx]|that.bbits_ptr_[idx]))
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return false;
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if (bbits_ptr_[idx] != that.bbits_ptr_[idx])
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return false;
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}
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unsigned long mask = size_%BITS_PER_WORD;
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if (mask > 0) {
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mask = (1UL << mask) - 1;
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return ((abits_ptr_[words]|bbits_ptr_[words])&mask) == ((that.abits_ptr_[words]|that.bbits_ptr_[words])&mask)
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&& (bbits_ptr_[words]&mask) == (that.bbits_ptr_[words]&mask);
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}
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return true;
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}
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bool vvp_vector4_t::has_xz() const
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{
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if (size_ < BITS_PER_WORD) {
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@ -40,7 +40,6 @@ class vvp_net_t;
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class vvp_net_fun_t;
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/* Core net function types. */
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class vvp_fun_concat;
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class vvp_fun_drive;
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class vvp_fun_part;
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@ -154,6 +153,8 @@ class vvp_vector4_t {
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// Test that the vectors are exactly equal
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bool eeq(const vvp_vector4_t&that) const;
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// Test that the vectors are equal, with x and z comparing equal.
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bool eq_xz(const vvp_vector4_t&that) const;
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// Return true if there is an X or Z anywhere in the vector.
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bool has_xz() const;
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@ -791,31 +792,6 @@ class vvp_net_fun_t {
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/* **** Some core net functions **** */
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/* vvp_fun_concat
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* This node function creates vectors (vvp_vector4_t) from the
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* concatenation of the inputs. The inputs (4) may be vector or
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* vector8 objects, but they are reduced to vector4 values and
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* strength information lost.
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*
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* The expected widths of the input vectors must be given up front so
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* that the positions in the output vector (and also the size of the
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* output vector) can be worked out. The input vectors must match the
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* expected width.
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*/
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class vvp_fun_concat : public vvp_net_fun_t {
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public:
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vvp_fun_concat(unsigned w0, unsigned w1,
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unsigned w2, unsigned w3);
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~vvp_fun_concat();
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void recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit);
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private:
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unsigned wid_[4];
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vvp_vector4_t val_;
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};
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/* vvp_fun_repeat
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* This node function create vectors by repeating the input. The width
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* is the width of the output vector, and the repeat is the number of
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