Fix reverse bit ordered bit select in continuous assignment.
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steve
parent
e79f62c5fa
commit
7b6678b2a1
30
elab_net.cc
30
elab_net.cc
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 1999-2000 Stephen Williams (steve@icarus.com)
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* Copyright (c) 1999-2002 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: elab_net.cc,v 1.97 2002/08/21 02:28:03 steve Exp $"
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#ident "$Id: elab_net.cc,v 1.98 2002/08/31 03:48:50 steve Exp $"
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#endif
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# include "config.h"
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@ -1173,7 +1173,7 @@ NetNet* PEConcat::elaborate_net(Design*des, NetScope*scope,
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}
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/*
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* This provate method handles the special case that we have a
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* This private method handles the special case that we have a
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* non-constant bit-select of an identifier. We already know that the
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* signal that is represented is "sig".
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*/
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@ -1188,12 +1188,25 @@ NetNet* PEIdent::elaborate_net_bitmux_(Design*des, NetScope*scope,
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/* Elaborate the selector. */
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NetNet*sel = msb_->elaborate_net(des, scope, 0, 0, 0, 0);
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unsigned sig_width = sig->pin_count();
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NetMux*mux = new NetMux(scope, scope->local_hsymbol(), 1,
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sig->pin_count(),
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sel->pin_count());
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sig_width, sel->pin_count());
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for (unsigned idx = 0 ; idx < sig->pin_count() ; idx += 1)
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connect(mux->pin_Data(0, idx), sig->pin(idx));
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/* Connect the signal bits to the mux. Account for the
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direction of the numbering (lsb to msb vs. msb to lsb) by
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swapping the connection order. */
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if (sig->msb() > sig->lsb()) {
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sel = add_to_net(des, sel, -sig->lsb());
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for (unsigned idx = 0 ; idx < sig_width ; idx += 1)
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connect(mux->pin_Data(0, idx), sig->pin(idx));
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} else {
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sel = add_to_net(des, sel, -sig->msb());
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for (unsigned idx = 0 ; idx < sig_width ; idx += 1)
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connect(mux->pin_Data(0, idx), sig->pin(sig_width-idx-1));
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}
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for (unsigned idx = 0 ; idx < sel->pin_count() ; idx += 1)
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connect(mux->pin_Sel(idx), sel->pin(idx));
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@ -2161,6 +2174,9 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
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/*
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* $Log: elab_net.cc,v $
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* Revision 1.98 2002/08/31 03:48:50 steve
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* Fix reverse bit ordered bit select in continuous assignment.
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*
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* Revision 1.97 2002/08/21 02:28:03 steve
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* Carry mux output delays.
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*
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51
netmisc.cc
51
netmisc.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: netmisc.cc,v 1.3 2002/08/12 01:35:00 steve Exp $"
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#ident "$Id: netmisc.cc,v 1.4 2002/08/31 03:48:50 steve Exp $"
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#endif
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# include "config.h"
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@ -26,6 +26,52 @@
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# include "netmisc.h"
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# include "PExpr.h"
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NetNet* add_to_net(Design*des, NetNet*sig, long val)
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{
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if (val == 0)
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return sig;
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NetScope*scope = sig->scope();
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unsigned long abs_val = (val >= 0)? val : (-val);
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unsigned width = sig->pin_count();
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verinum val_v (abs_val, width);
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NetConst*val_c = new NetConst(scope, scope->local_hsymbol(), val_v);
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NetNet*val_s = new NetNet(scope, scope->local_hsymbol(),
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NetNet::IMPLICIT, width);
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val_s->local_flag(true);
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NetNet*res = new NetNet(scope, scope->local_hsymbol(),
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NetNet::IMPLICIT, width);
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res->local_flag(true);
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NetAddSub*add = new NetAddSub(scope, scope->local_hsymbol(), width);
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for (unsigned idx = 0 ; idx < width ; idx += 1)
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connect(sig->pin(idx), add->pin_DataA(idx));
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for (unsigned idx = 0 ; idx < width ; idx += 1)
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connect(val_c->pin(idx), add->pin_DataB(idx));
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for (unsigned idx = 0 ; idx < width ; idx += 1)
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connect(val_s->pin(idx), add->pin_DataB(idx));
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for (unsigned idx = 0 ; idx < width ; idx += 1)
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connect(res->pin(idx), add->pin_Result(idx));
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if (val < 0)
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add->attribute("LPM_Direction", verinum("SUB"));
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else
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add->attribute("LPM_Direction", verinum("ADD"));
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des->add_node(add);
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des->add_node(val_c);
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return res;
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}
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NetExpr* elab_and_eval(Design*des, NetScope*scope, const PExpr*pe)
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{
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@ -44,6 +90,9 @@ NetExpr* elab_and_eval(Design*des, NetScope*scope, const PExpr*pe)
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/*
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* $Log: netmisc.cc,v $
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* Revision 1.4 2002/08/31 03:48:50 steve
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* Fix reverse bit ordered bit select in continuous assignment.
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*
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* Revision 1.3 2002/08/12 01:35:00 steve
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* conditional ident string using autoconfig.
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*
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12
netmisc.h
12
netmisc.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: netmisc.h,v 1.15 2002/08/12 01:35:00 steve Exp $"
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#ident "$Id: netmisc.h,v 1.16 2002/08/31 03:48:50 steve Exp $"
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#endif
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# include "netlist.h"
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@ -33,6 +33,13 @@
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extern NetExpr*pad_to_width(NetExpr*expr, unsigned wid);
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extern NetNet*pad_to_width(Design*des, NetNet*n, unsigned w);
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/*
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* This function takes as input a NetNet signal and adds a constant
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* value to it. If the val is 0, then simply return sig. Otherwise,
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* return a new NetNet value that is the output of an addition.
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*/
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extern NetNet*add_to_net(Design*des, NetNet*sig, long val);
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/*
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* In some cases the lval is accessible as a pointer to the head of
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* a list of NetAssign_ objects. This function returns the width of
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@ -50,6 +57,9 @@ extern NetExpr* elab_and_eval(Design*des, NetScope*scope, const PExpr*pe);
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/*
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* $Log: netmisc.h,v $
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* Revision 1.16 2002/08/31 03:48:50 steve
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* Fix reverse bit ordered bit select in continuous assignment.
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*
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* Revision 1.15 2002/08/12 01:35:00 steve
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* conditional ident string using autoconfig.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: vvp_process.c,v 1.65 2002/08/27 05:39:57 steve Exp $"
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#ident "$Id: vvp_process.c,v 1.66 2002/08/31 03:48:50 steve Exp $"
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#endif
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# include "vvp_priv.h"
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@ -270,7 +270,8 @@ static int show_stmt_assign(ivl_statement_t net)
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}
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clr_vector(res);
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if (res.base > 3)
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clr_vector(res);
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}
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@ -403,7 +404,8 @@ static int show_stmt_assign_nb(ivl_statement_t net)
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}
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clr_vector(res);
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if (res.base > 3)
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clr_vector(res);
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}
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return 0;
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@ -1267,6 +1269,9 @@ int draw_func_definition(ivl_scope_t scope)
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/*
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* $Log: vvp_process.c,v $
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* Revision 1.66 2002/08/31 03:48:50 steve
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* Fix reverse bit ordered bit select in continuous assignment.
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*
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* Revision 1.65 2002/08/27 05:39:57 steve
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* Fix l-value indexing of memories and vectors so that
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* an unknown (x) index causes so cell to be addresses.
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