Add support for OR/NOR/bufif0/bufif1.
This commit is contained in:
steve
parent
800e9dd76a
commit
63fb5ea03c
164
tgt-fpga/d-lpm.c
164
tgt-fpga/d-lpm.c
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: d-lpm.c,v 1.1 2003/08/07 04:04:01 steve Exp $"
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#ident "$Id: d-lpm.c,v 1.2 2003/08/07 05:18:04 steve Exp $"
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#endif
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/*
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@ -47,7 +47,10 @@ static edif_cell_t lpm_cell_buf(void)
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edif_cell_portconfig(tmp, 0, "Result", IVL_SIP_OUTPUT);
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edif_cell_portconfig(tmp, 1, "Data", IVL_SIP_INPUT);
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edif_cell_pstring(tmp, "LPM_TYPE", "LPM_OR");
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/* A buffer is an inverted inverter. */
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edif_cell_port_pstring(tmp, 0, "LPM_Polarity", "INVERT");
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edif_cell_pstring(tmp, "LPM_TYPE", "LPM_INV");
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edif_cell_pinteger(tmp, "LPM_Width", 1);
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edif_cell_pinteger(tmp, "LPM_Size", 1);
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return tmp;
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@ -70,6 +73,99 @@ static edif_cell_t lpm_cell_inv(void)
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return tmp;
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}
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static edif_cell_t lpm_cell_bufif0(void)
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{
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static edif_cell_t tmp = 0;
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if (tmp != 0)
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return tmp;
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tmp = edif_xcell_create(xlib, "BUFIF1", 3);
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edif_cell_portconfig(tmp, 0, "TriData", IVL_SIP_OUTPUT);
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edif_cell_portconfig(tmp, 1, "Data", IVL_SIP_INPUT);
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edif_cell_portconfig(tmp, 2, "EnableDT", IVL_SIP_INPUT);
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edif_cell_port_pstring(tmp, 2, "LPM_Polarity", "INVERT");
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edif_cell_pstring(tmp, "LPM_TYPE", "LPM_BUSTRI");
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edif_cell_pinteger(tmp, "LPM_Width", 1);
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return tmp;
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}
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static edif_cell_t lpm_cell_bufif1(void)
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{
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static edif_cell_t tmp = 0;
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if (tmp != 0)
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return tmp;
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tmp = edif_xcell_create(xlib, "BUFIF1", 3);
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edif_cell_portconfig(tmp, 0, "TriData", IVL_SIP_OUTPUT);
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edif_cell_portconfig(tmp, 1, "Data", IVL_SIP_INPUT);
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edif_cell_portconfig(tmp, 2, "EnableDT", IVL_SIP_INPUT);
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edif_cell_pstring(tmp, "LPM_TYPE", "LPM_BUSTRI");
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edif_cell_pinteger(tmp, "LPM_Width", 1);
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return tmp;
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}
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static edif_cell_t lpm_cell_or(unsigned siz)
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{
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unsigned idx;
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edif_cell_t cell;
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char name[32];
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sprintf(name, "or%u", siz);
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cell = edif_xlibrary_findcell(xlib, name);
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if (cell != 0)
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return cell;
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cell = edif_xcell_create(xlib, strdup(name), siz+1);
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edif_cell_portconfig(cell, 0, "Result0", IVL_SIP_OUTPUT);
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for (idx = 0 ; idx < siz ; idx += 1) {
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sprintf(name, "Data%ux0", idx);
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edif_cell_portconfig(cell, idx+1, strdup(name), IVL_SIP_INPUT);
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}
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edif_cell_pstring(cell, "LPM_TYPE", "LPM_OR");
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edif_cell_pinteger(cell, "LPM_Width", 1);
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edif_cell_pinteger(cell, "LPM_Size", siz);
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return cell;
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}
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static edif_cell_t lpm_cell_nor(unsigned siz)
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{
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unsigned idx;
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edif_cell_t cell;
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char name[32];
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sprintf(name, "nor%u", siz);
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cell = edif_xlibrary_findcell(xlib, name);
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if (cell != 0)
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return cell;
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cell = edif_xcell_create(xlib, strdup(name), siz+1);
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edif_cell_portconfig(cell, 0, "Result0", IVL_SIP_OUTPUT);
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edif_cell_port_pstring(cell, 0, "LPM_Polarity", "INVERT");
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for (idx = 0 ; idx < siz ; idx += 1) {
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sprintf(name, "Data%ux0", idx);
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edif_cell_portconfig(cell, idx+1, strdup(name), IVL_SIP_INPUT);
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}
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edif_cell_pstring(cell, "LPM_TYPE", "LPM_OR");
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edif_cell_pinteger(cell, "LPM_Width", 1);
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edif_cell_pinteger(cell, "LPM_Size", siz);
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return cell;
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}
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static void lpm_show_header(ivl_design_t des)
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{
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unsigned idx;
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@ -142,6 +238,27 @@ static void lpm_show_footer(ivl_design_t des)
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edif_print(xnf, edf);
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}
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static void hookup_logic_gate(ivl_net_logic_t net, edif_cell_t cell)
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{
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unsigned pin, idx;
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edif_joint_t jnt;
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edif_cellref_t ref = edif_cellref_create(edf, cell);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
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pin = edif_cell_port_byname(cell, "Result0");
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edif_add_to_joint(jnt, ref, pin);
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for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
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char name[32];
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, idx));
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sprintf(name, "Data%ux0", idx-1);
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pin = edif_cell_port_byname(cell, name);
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edif_add_to_joint(jnt, ref, pin);
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}
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}
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static void lpm_logic(ivl_net_logic_t net)
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{
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edif_cell_t cell;
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@ -163,6 +280,36 @@ static void lpm_logic(ivl_net_logic_t net)
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edif_add_to_joint(jnt, ref, 1);
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break;
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case IVL_LO_BUFIF0:
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assert(ivl_logic_pins(net) == 3);
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cell = lpm_cell_bufif0();
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ref = edif_cellref_create(edf, cell);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
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edif_add_to_joint(jnt, ref, 0);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
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edif_add_to_joint(jnt, ref, 1);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 2));
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edif_add_to_joint(jnt, ref, 2);
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break;
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case IVL_LO_BUFIF1:
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assert(ivl_logic_pins(net) == 3);
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cell = lpm_cell_bufif1();
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ref = edif_cellref_create(edf, cell);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
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edif_add_to_joint(jnt, ref, 0);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
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edif_add_to_joint(jnt, ref, 1);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 2));
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edif_add_to_joint(jnt, ref, 2);
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break;
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case IVL_LO_NOT:
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assert(ivl_logic_pins(net) == 2);
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cell = lpm_cell_inv();
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@ -175,6 +322,16 @@ static void lpm_logic(ivl_net_logic_t net)
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edif_add_to_joint(jnt, ref, 1);
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break;
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case IVL_LO_OR:
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cell = lpm_cell_or(ivl_logic_pins(net)-1);
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hookup_logic_gate(net, cell);
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break;
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case IVL_LO_NOR:
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cell = lpm_cell_nor(ivl_logic_pins(net)-1);
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hookup_logic_gate(net, cell);
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break;
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default:
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fprintf(stderr, "UNSUPPORTED LOGIC TYPE: %u\n",
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ivl_logic_type(net));
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@ -365,6 +522,9 @@ const struct device_s d_lpm_edif = {
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/*
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* $Log: d-lpm.c,v $
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* Revision 1.2 2003/08/07 05:18:04 steve
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* Add support for OR/NOR/bufif0/bufif1.
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*
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* Revision 1.1 2003/08/07 04:04:01 steve
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* Add an LPM device type.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: edif.c,v 1.6 2003/08/07 04:04:01 steve Exp $"
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#ident "$Id: edif.c,v 1.7 2003/08/07 05:18:04 steve Exp $"
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#endif
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# include "edif.h"
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@ -74,6 +74,7 @@ struct edif_xlibrary_s {
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struct __cell_port {
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const char*name;
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const char*ename;
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struct cellref_property_*property;
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ivl_signal_port_t dir;
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};
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@ -265,6 +266,7 @@ edif_cell_t edif_xcell_create(edif_xlibrary_t xlib, const char*name,
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for (idx = 0 ; idx < nports ; idx += 1) {
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cell->ports[idx].name = "?";
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cell->ports[idx].dir = IVL_SIP_NONE;
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cell->ports[idx].property = 0;
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}
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cell->next = xlib->cells;
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@ -282,6 +284,17 @@ void edif_cell_portconfig(edif_cell_t cell, unsigned idx,
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cell->ports[idx].dir = dir;
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}
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void edif_cell_port_pstring(edif_cell_t cell, unsigned idx,
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const char*name, const char*value)
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{
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struct cellref_property_*prp = malloc(sizeof(struct cellref_property_));
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prp->name = name;
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prp->ptype = PRP_STRING;
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prp->value_.str = value;
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prp->next = cell->ports[idx].property;
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cell->ports[idx].property = prp;
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}
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unsigned edif_cell_port_byname(edif_cell_t cell, const char*name)
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{
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unsigned idx = 0;
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@ -386,6 +399,22 @@ void edif_add_to_joint(edif_joint_t jnt, edif_cellref_t cell, unsigned port)
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jnt->links = jc;
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}
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static void fprint_property(FILE*fd, const struct cellref_property_*prp)
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{
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fprintf(fd, "(property %s ", prp->name);
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switch (prp->ptype) {
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case PRP_NONE:
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break;
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case PRP_STRING:
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fprintf(fd, "(string \"%s\")", prp->value_.str);
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break;
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case PRP_INTEGER:
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fprintf(fd, "(integer %ld)", prp->value_.num);
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break;
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}
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fprintf(fd, ")");
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}
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/*
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* This function takes all the data structures that have been
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* assembled by the code generator, and writes them into an EDIF
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@ -441,26 +470,18 @@ void edif_print(FILE*fd, edif_t edf)
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default:
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break;
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}
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for (prp = pp->property ; prp ; prp=prp->next) {
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fprintf(fd, " ");
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fprint_property(fd, prp);
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}
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fprintf(fd, ")");
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}
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for (prp = cell->property ; prp ; prp = prp->next) {
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fprintf(fd, "\n (property %s",
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prp->name);
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switch (prp->ptype) {
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case PRP_NONE:
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assert(0);
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case PRP_STRING:
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fprintf(fd, " (string \"%s\")",
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prp->value_.str);
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break;
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case PRP_INTEGER:
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fprintf(fd, " (integer %ld)",
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prp->value_.num);
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break;
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}
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fprintf(fd, ")");
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fprintf(fd, "\n ");
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fprint_property(fd, prp);
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}
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fprintf(fd, ")))\n");
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}
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@ -520,19 +541,10 @@ void edif_print(FILE*fd, edif_t edf)
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"(cellRef %s (libraryRef %s)))",
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ref->u, ref->cell->name, ref->cell->xlib->name);
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for (prp = ref->property ; prp ; prp = prp->next)
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switch (prp->ptype) {
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case PRP_STRING:
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fprintf(fd, " (property %s (string \"%s\"))",
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prp->name, prp->value_.str);
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break;
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case PRP_INTEGER:
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fprintf(fd, " (property %s (integer %ld))",
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prp->name, prp->value_.num);
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break;
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case PRP_NONE:
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assert(0);
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}
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for (prp = ref->property ; prp ; prp = prp->next) {
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fprintf(fd, " ");
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fprint_property(fd, prp);
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}
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fprintf(fd, ")\n");
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}
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@ -580,18 +592,9 @@ void edif_print(FILE*fd, edif_t edf)
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fprintf(fd, " (cellRef %s (libraryRef DESIGN))\n", edf->name);
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for (prp = edf->property ; prp ; prp = prp->next) {
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switch (prp->ptype) {
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case PRP_STRING:
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fprintf(fd, " (property %s (string \"%s\"))\n",
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prp->name, prp->value_.str);
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break;
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case PRP_INTEGER:
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fprintf(fd, " (property %s (integer %ld))\n",
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prp->name, prp->value_.num);
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break;
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case PRP_NONE:
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assert(0);
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}
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fprintf(fd, " ");
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fprint_property(fd, prp);
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fprintf(fd, "\n");
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}
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fprintf(fd, " )\n");
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@ -604,6 +607,9 @@ void edif_print(FILE*fd, edif_t edf)
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/*
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* $Log: edif.c,v $
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* Revision 1.7 2003/08/07 05:18:04 steve
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* Add support for OR/NOR/bufif0/bufif1.
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*
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* Revision 1.6 2003/08/07 04:04:01 steve
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* Add an LPM device type.
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*
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: edif.h,v 1.5 2003/08/07 04:04:01 steve Exp $"
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#ident "$Id: edif.h,v 1.6 2003/08/07 05:18:04 steve Exp $"
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#endif
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# include <stdio.h>
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@ -172,6 +172,10 @@ extern edif_cell_t edif_xcell_create(edif_xlibrary_t, const char*name,
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extern void edif_cell_portconfig(edif_cell_t cell, unsigned idx,
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const char*name, ivl_signal_port_t dir);
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/* Attach a property to a cell port. */
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extern void edif_cell_port_pstring(edif_cell_t cell, unsigned idx,
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const char*name, const char*value);
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/* Cells may have properties attached to them. These properties are
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included in the library declaration for the cell, instead of the
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cell instances. */
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@ -225,6 +229,9 @@ extern void edif_print(FILE*fd, edif_t design);
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/*
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* $Log: edif.h,v $
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* Revision 1.6 2003/08/07 05:18:04 steve
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* Add support for OR/NOR/bufif0/bufif1.
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*
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* Revision 1.5 2003/08/07 04:04:01 steve
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* Add an LPM device type.
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*
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