Proper sliced >= comparator.
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steve
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3878f3c770
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2be1b1a096
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: d-virtex2.c,v 1.3 2003/03/30 03:43:44 steve Exp $"
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#ident "$Id: d-virtex2.c,v 1.4 2003/03/31 00:04:21 steve Exp $"
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#endif
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# include "device.h"
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@ -999,144 +999,125 @@ static void virtex2_cmp_ge(ivl_lpm_t net)
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return;
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}
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/* Handle the case where the device is two slices
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wide. In this case, we can use a LUT4 to do all
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the calculation. Use this truth table:
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Q AA BB
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--+------
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1 | 00 00
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0 | 00 01
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0 | 00 10
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0 | 00 11
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1 | 01 00
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1 | 01 01
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0 | 01 10
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0 | 01 11
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1 | 10 00
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1 | 10 01
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1 | 10 10
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0 | 10 11
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1 | 11 xx
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The I3-I0 inputs are A1 A0 B1 B0 in that order. */
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check_cell_lut4();
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lut = edif_cellref_create(edf, cell_lut4);
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edif_cellref_pstring(lut, "INIT", "F731");
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jnt = edif_joint_of_nexus(edf, ivl_lpm_data(net, 0));
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edif_add_to_joint(jnt, lut, LUT_I2);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_datab(net, 0));
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edif_add_to_joint(jnt, lut, LUT_I0);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_data(net, 1));
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edif_add_to_joint(jnt, lut, LUT_I3);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_datab(net, 1));
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edif_add_to_joint(jnt, lut, LUT_I1);
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/* There are only two slices, so this is all we need. */
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if (ivl_lpm_width(net) == 2) {
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/* Handle the case where the device is two slices
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wide. In this case, we can use a LUT4 to do all
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the calculation. Use this truth table:
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Q AA BB
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--+------
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1 | 00 00
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0 | 00 01
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0 | 00 10
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0 | 00 11
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1 | 01 00
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1 | 01 01
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0 | 01 10
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0 | 01 11
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1 | 10 00
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1 | 10 01
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1 | 10 10
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0 | 10 11
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1 | 11 xx
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The I3-I0 inputs are A1 A0 B1 B0 in that order. */
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check_cell_lut4();
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lut = edif_cellref_create(edf, cell_lut4);
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edif_cellref_pstring(lut, "INIT", "F731");
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jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, 0));
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edif_add_to_joint(jnt, lut, LUT_O);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_data(net, 0));
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edif_add_to_joint(jnt, lut, LUT_I2);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_datab(net, 0));
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edif_add_to_joint(jnt, lut, LUT_I0);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_data(net, 1));
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edif_add_to_joint(jnt, lut, LUT_I3);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_datab(net, 1));
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edif_add_to_joint(jnt, lut, LUT_I1);
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return;
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}
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/* The general case is more complicated, but we can take
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advantage of the MULTAND and MUXCY devices to pack two bit
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slices of input into each LUT4 device. The logic works like
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this:
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/* The general case requires that we make the >= comparator
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from slices. This is an iterative design. Each slice has
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the truth table:
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The goal is to calculate:
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An Bn | A >= B
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------+-------
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0 0 | CI
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0 1 | 0
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1 0 | 1
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1 1 | CI
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A >= B.
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The CI for each slice is the output of the compare of the
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next less significant bits. We get this truth table by
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connecting a LUT2 to the S input of a MUXCY. When the S
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input is (1), it propagates its CI. This suggests that the
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init value for the LUT be "9" (XNOR).
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This is the same as the expression:
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When the MUXCY S input is 0, it propagates a local
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input. We connect to that input An, and we get the desired
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and complete truth table for a slice.
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~(A < B)
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This iterative definition needs to terminate at the least
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significant bits. In fact, we have a non-iterative was to
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deal with the two least significant slices. We take the
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output of the LUT4 device for the least significant bits,
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and use that to generate the initial CI for the chain. */
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so the problem is changed to calculating A < B an inverting
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the result. In fact, A<B can be further transformed to the
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expression:
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check_cell_lut2();
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check_cell_muxcy();
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check_cell_muxcy_l();
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B-A > 0
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muxcy_prev = edif_cellref_create(edf, cell_muxcy_l);
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jnt = edif_joint_create(edf);
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This can in fact be implemented using carry chain
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arithmetic. Each bit slice of a normal subtractor uses a
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LUT2, a MUXCY and an XORCY. However, since we do not care
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about the result of the subtract (only whether it
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overflows) then we can skip the XORCY.
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edif_add_to_joint(jnt, lut, LUT_O);
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edif_add_to_joint(jnt, muxcy_prev, MUXCY_S);
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{ edif_cellref_t p0 = edif_cellref_create(edf, cell_0);
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edif_cellref_t p1 = edif_cellref_create(edf, cell_0);
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, p0, 0);
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edif_add_to_joint(jnt, muxcy_prev, MUXCY_DI);
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, p1, 0);
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edif_add_to_joint(jnt, muxcy_prev, MUXCY_CI);
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}
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Furthermore, pairs of LUT2 and MUXCY devices can be reduced
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to a single LUT4, MUXCY and MULTAND device. */
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for (idx = 2 ; idx < ivl_lpm_width(net) ; idx += 1) {
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edif_cellref_t muxcy;
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/* For now, only support even widths. */
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assert(ivl_lpm_width(net)%2 == 0);
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muxcy_prev = 0;
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for (idx = 0 ; idx < ivl_lpm_width(net) ; idx += 2) {
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edif_cellref_t muxcy, multand;
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check_cell_lut4();
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check_cell_muxcy();
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check_cell_mult_and();
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lut = edif_cellref_create(edf, cell_lut4);
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lut = edif_cellref_create(edf, cell_lut2);
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muxcy = edif_cellref_create(edf, cell_muxcy);
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multand = edif_cellref_create(edf, cell_mult_and);
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edif_cellref_pstring(lut, "INIT", "8421");
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jnt = edif_joint_of_nexus(edf, ivl_lpm_data(net, idx+0));
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edif_add_to_joint(jnt, lut, LUT_I2);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_data(net, idx+1));
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edif_add_to_joint(jnt, lut, LUT_I3);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_datab(net, idx+0));
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edif_add_to_joint(jnt, lut, LUT_I0);
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edif_add_to_joint(jnt, multand, MULT_AND_I0);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_datab(net, idx+1));
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edif_add_to_joint(jnt, lut, LUT_I1);
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edif_add_to_joint(jnt, multand, MULT_AND_I1);
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edif_cellref_pstring(lut, "INIT", "9");
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, lut, LUT_O);
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edif_add_to_joint(jnt, lut, LUT_O);
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edif_add_to_joint(jnt, muxcy, MUXCY_S);
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, multand, MULT_AND_LO);
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edif_add_to_joint(jnt, muxcy, MUXCY_DI);
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edif_add_to_joint(jnt, muxcy, MUXCY_CI);
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edif_add_to_joint(jnt, muxcy_prev, MUXCY_O);
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if (idx == 0) {
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muxcy_prev = edif_cellref_create(edf, cell_1);
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, muxcy_prev, 0);
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edif_add_to_joint(jnt, muxcy, MUXCY_CI);
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} else {
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, muxcy_prev, MUXCY_O);
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edif_add_to_joint(jnt, muxcy, MUXCY_CI);
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}
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jnt = edif_joint_of_nexus(edf, ivl_lpm_data(net, idx));
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edif_add_to_joint(jnt, lut, LUT_I0);
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edif_add_to_joint(jnt, muxcy, MUXCY_DI);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_datab(net, idx));
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edif_add_to_joint(jnt, lut, LUT_I1);
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muxcy_prev = muxcy;
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}
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/* At this point, muxcy_prev[MUXCY_O] in the truth of the
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expression B-A > 0. Connect an inverter to this and we get
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our desired result. */
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check_cell_inv();
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lut = edif_cellref_create(edf, cell_inv);
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, muxcy_prev, MUXCY_O);
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edif_add_to_joint(jnt, lut, BUF_I);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, 0));
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edif_add_to_joint(jnt, lut, BUF_O);
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edif_add_to_joint(jnt, muxcy_prev, MUXCY_O);
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}
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const struct device_s d_virtex2_edif = {
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@ -1158,6 +1139,9 @@ const struct device_s d_virtex2_edif = {
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/*
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* $Log: d-virtex2.c,v $
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* Revision 1.4 2003/03/31 00:04:21 steve
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* Proper sliced >= comparator.
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*
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* Revision 1.3 2003/03/30 03:43:44 steve
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* Handle wide ports of macros.
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*
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