Separate the virtex and generic-edif code generators.
This commit is contained in:
steve
parent
298a352cbd
commit
acde444439
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@ -16,7 +16,7 @@
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# 59 Temple Place - Suite 330
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# Boston, MA 02111-1307, USA
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#
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#ident "$Id: Makefile.in,v 1.2 2001/09/02 21:33:07 steve Exp $"
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#ident "$Id: Makefile.in,v 1.3 2001/09/06 04:28:39 steve Exp $"
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#
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#
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SHELL = /bin/sh
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@ -49,7 +49,7 @@ all: fpga.tgt
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$(CC) -Wall -I$(srcdir)/.. $(CPPFLAGS) -MD -c $< -o $*.o
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mv $*.d dep
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D = d-generic.o d-generic-edif.o
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D = d-generic.o d-generic-edif.o d-virtex.o
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O = fpga.o gates.o mangle.o tables.o $D
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ifeq (@WIN32@,yes)
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@ -16,7 +16,7 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ident "$Id: d-generic-edif.c,v 1.2 2001/09/02 23:53:55 steve Exp $"
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#ident "$Id: d-generic-edif.c,v 1.3 2001/09/06 04:28:40 steve Exp $"
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# include "device.h"
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# include "fpga_priv.h"
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@ -32,9 +32,9 @@ struct nexus_recall {
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};
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static struct nexus_recall*net_list = 0;
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static unsigned uref = 0;
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unsigned edif_uref = 0;
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static void set_nexus_joint(ivl_nexus_t nex, const char*joint)
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void edif_set_nexus_joint(ivl_nexus_t nex, const char*joint)
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{
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size_t newlen;
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struct nexus_recall*rec;
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@ -91,7 +91,7 @@ static void show_root_ports_edif(ivl_scope_t root)
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use_name, dir);
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sprintf(jbuf, "(portRef %s)", use_name);
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set_nexus_joint(ivl_signal_pin(sig, 0), jbuf);
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edif_set_nexus_joint(ivl_signal_pin(sig, 0), jbuf);
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} else {
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unsigned pin;
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@ -101,12 +101,50 @@ static void show_root_ports_edif(ivl_scope_t root)
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"\"%s[%u]\") (direction %s))\n", use_name,
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pin, use_name, pin, dir);
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sprintf(jbuf, "(portRef %s_%u)", use_name, pin);
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set_nexus_joint(ivl_signal_pin(sig, pin), jbuf);
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edif_set_nexus_joint(ivl_signal_pin(sig, pin), jbuf);
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}
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}
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}
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}
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void edif_show_header_generic(ivl_design_t des, const char*library)
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{
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ivl_scope_t root = ivl_design_root(des);
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/* write the primitive header */
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fprintf(xnf, "(edif %s\n", ivl_scope_name(root));
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fprintf(xnf, " (edifVersion 2 0 0)\n");
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fprintf(xnf, " (edifLevel 0)\n");
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fprintf(xnf, " (keywordMap (keywordLevel 0))\n");
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fprintf(xnf, " (status\n");
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fprintf(xnf, " (written\n");
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fprintf(xnf, " (timeStamp 0 0 0 0 0 0)\n");
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fprintf(xnf, " (author \"unknown\")\n");
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fprintf(xnf, " (program \"Icarus Verilog/fpga.tgt\")))\n");
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/* Write out the external references here? */
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fputs(library, xnf);
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/* Write out the library header */
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fprintf(xnf, " (library DESIGN\n");
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fprintf(xnf, " (edifLevel 0)\n");
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fprintf(xnf, " (technology (numberDefinition))\n");
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/* The root module is a cell in the library. */
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fprintf(xnf, " (cell %s\n", ivl_scope_name(root));
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fprintf(xnf, " (cellType GENERIC)\n");
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fprintf(xnf, " (view Netlist_representation\n");
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fprintf(xnf, " (viewType NETLIST)\n");
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fprintf(xnf, " (interface\n");
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show_root_ports_edif(root);
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fprintf(xnf, " )\n"); /* end the (interface ) sexp */
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fprintf(xnf, " (contents\n");
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}
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static const char*external_library_text =
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" (external VIRTEX (edifLevel 0) (technology (numberDefinition))\n"
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" (cell AND2 (cellType GENERIC)\n"
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@ -156,42 +194,9 @@ static const char*external_library_text =
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" )\n"
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;
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static void edif_show_header(ivl_design_t des)
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{
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ivl_scope_t root = ivl_design_root(des);
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/* write the primitive header */
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fprintf(xnf, "(edif %s\n", ivl_scope_name(root));
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fprintf(xnf, " (edifVersion 2 0 0)\n");
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fprintf(xnf, " (edifLevel 0)\n");
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fprintf(xnf, " (keywordMap (keywordLevel 0))\n");
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fprintf(xnf, " (status\n");
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fprintf(xnf, " (written\n");
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fprintf(xnf, " (timeStamp 0 0 0 0 0 0)\n");
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fprintf(xnf, " (author \"unknown\")\n");
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fprintf(xnf, " (program \"Icarus Verilog/fpga.tgt\")))\n");
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/* Write out the external references here? */
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fputs(external_library_text, xnf);
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/* Write out the library header */
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fprintf(xnf, " (library DESIGN\n");
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fprintf(xnf, " (edifLevel 0)\n");
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fprintf(xnf, " (technology (numberDefinition))\n");
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/* The root module is a cell in the library. */
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fprintf(xnf, " (cell %s\n", ivl_scope_name(root));
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fprintf(xnf, " (cellType GENERIC)\n");
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fprintf(xnf, " (view Netlist_representation\n");
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fprintf(xnf, " (viewType NETLIST)\n");
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fprintf(xnf, " (interface\n");
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show_root_ports_edif(root);
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fprintf(xnf, " )\n"); /* end the (interface ) sexp */
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fprintf(xnf, " (contents\n");
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edif_show_header_generic(des, external_library_text);
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}
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static void edif_show_consts(ivl_design_t des)
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@ -209,7 +214,7 @@ static void edif_show_consts(ivl_design_t des)
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const char*name;
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const char*port;
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uref += 1;
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edif_uref += 1;
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switch (val[pin]) {
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case '0':
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@ -229,17 +234,17 @@ static void edif_show_consts(ivl_design_t des)
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fprintf(xnf, "(instance U%u "
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"(viewRef Netlist_representation"
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" (cellRef %s (libraryRef VIRTEX))))\n",
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uref, name);
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edif_uref, name);
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sprintf(jbuf, "(portRef %s (instanceRef U%u))",
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port, uref);
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set_nexus_joint(nex, jbuf);
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port, edif_uref);
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edif_set_nexus_joint(nex, jbuf);
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}
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}
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}
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static void edif_show_footer(ivl_design_t des)
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void edif_show_footer(ivl_design_t des)
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{
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unsigned nref = 0;
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struct nexus_recall*cur;
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@ -275,7 +280,7 @@ static void edif_show_logic(ivl_net_logic_t net)
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char jbuf[1024];
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unsigned idx;
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uref += 1;
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edif_uref += 1;
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switch (ivl_logic_type(net)) {
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@ -284,33 +289,33 @@ static void edif_show_logic(ivl_net_logic_t net)
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assert(ivl_logic_pins(net) >= 3);
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fprintf(xnf, "(instance (rename U%u \"%s\")",
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uref, ivl_logic_name(net));
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edif_uref, ivl_logic_name(net));
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fprintf(xnf, " (viewRef Netlist_representation"
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" (cellRef AND%u (libraryRef VIRTEX))))\n",
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ivl_logic_pins(net) - 1);
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sprintf(jbuf, "(portRef O (instanceRef U%u))", uref);
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set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
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sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
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for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
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sprintf(jbuf, "(portRef I%u (instanceRef U%u))",
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idx-1, uref);
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set_nexus_joint(ivl_logic_pin(net, idx), jbuf);
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idx-1, edif_uref);
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edif_set_nexus_joint(ivl_logic_pin(net, idx), jbuf);
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}
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break;
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case IVL_LO_BUF:
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assert(ivl_logic_pins(net) == 2);
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fprintf(xnf, "(instance (rename U%u \"%s\")",
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uref, ivl_logic_name(net));
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edif_uref, ivl_logic_name(net));
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fprintf(xnf, " (viewRef Netlist_representation"
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" (cellRef BUF (libraryRef VIRTEX))))\n");
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sprintf(jbuf, "(portRef O (instanceRef U%u))", uref);
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set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
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sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
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sprintf(jbuf, "(portRef I (instanceRef U%u))", uref);
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set_nexus_joint(ivl_logic_pin(net, 1), jbuf);
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sprintf(jbuf, "(portRef I (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(ivl_logic_pin(net, 1), jbuf);
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break;
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case IVL_LO_NOR:
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@ -318,18 +323,18 @@ static void edif_show_logic(ivl_net_logic_t net)
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assert(ivl_logic_pins(net) >= 3);
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fprintf(xnf, "(instance (rename U%u \"%s\")",
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uref, ivl_logic_name(net));
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edif_uref, ivl_logic_name(net));
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fprintf(xnf, " (viewRef Netlist_representation"
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" (cellRef NOR%u (libraryRef VIRTEX))))\n",
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ivl_logic_pins(net) - 1);
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sprintf(jbuf, "(portRef O (instanceRef U%u))", uref);
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set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
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sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
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for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
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sprintf(jbuf, "(portRef I%u (instanceRef U%u))",
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idx-1, uref);
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set_nexus_joint(ivl_logic_pin(net, idx), jbuf);
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idx-1, edif_uref);
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edif_set_nexus_joint(ivl_logic_pin(net, idx), jbuf);
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}
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break;
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@ -338,34 +343,34 @@ static void edif_show_logic(ivl_net_logic_t net)
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}
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}
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static void edif_show_dff(ivl_lpm_t net)
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void edif_show_generic_dff(ivl_lpm_t net)
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{
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ivl_nexus_t nex;
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char jbuf[1024];
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assert(ivl_lpm_width(net) == 1);
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uref += 1;
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edif_uref += 1;
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fprintf(xnf, "(instance (rename U%u \"%s\")", uref, ivl_lpm_name(net));
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fprintf(xnf, "(instance (rename U%u \"%s\")", edif_uref, ivl_lpm_name(net));
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fprintf(xnf, " (viewRef Netlist_representation"
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" (cellRef FDCE (libraryRef VIRTEX))))\n");
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nex = ivl_lpm_q(net, 0);
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sprintf(jbuf, "(portRef Q (instanceRef U%u))", uref);
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set_nexus_joint(nex, jbuf);
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sprintf(jbuf, "(portRef Q (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(nex, jbuf);
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nex = ivl_lpm_data(net, 0);
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sprintf(jbuf, "(portRef D (instanceRef U%u))", uref);
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set_nexus_joint(nex, jbuf);
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sprintf(jbuf, "(portRef D (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(nex, jbuf);
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nex = ivl_lpm_clk(net);
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sprintf(jbuf, "(portRef C (instanceRef U%u))", uref);
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set_nexus_joint(nex, jbuf);
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sprintf(jbuf, "(portRef C (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(nex, jbuf);
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if ((nex = ivl_lpm_enable(net))) {
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sprintf(jbuf, "(portRef CE (instanceRef U%u))", uref);
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set_nexus_joint(nex, jbuf);
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sprintf(jbuf, "(portRef CE (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(nex, jbuf);
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}
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}
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@ -374,7 +379,7 @@ const struct device_s d_generic_edif = {
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edif_show_header,
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edif_show_footer,
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edif_show_logic,
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edif_show_dff,
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edif_show_generic_dff,
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0,
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0,
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0,
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@ -384,6 +389,9 @@ const struct device_s d_generic_edif = {
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/*
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* $Log: d-generic-edif.c,v $
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* Revision 1.3 2001/09/06 04:28:40 steve
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* Separate the virtex and generic-edif code generators.
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*
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* Revision 1.2 2001/09/02 23:53:55 steve
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* Add virtex support for some basic logic, the DFF
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* and constant signals.
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@ -0,0 +1,175 @@
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/*
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* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ident "$Id: d-virtex.c,v 1.1 2001/09/06 04:28:40 steve Exp $"
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# include "device.h"
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# include "fpga_priv.h"
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# include <stdlib.h>
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# include <string.h>
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# include <malloc.h>
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# include <assert.h>
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/*
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* This is the EDIF code generator for VIRTEX style parts. It uses the
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* VIRTEX primitives from the unified library.
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*/
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static const char*virtex_library_text =
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" (external VIRTEX (edifLevel 0) (technology (numberDefinition))\n"
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" (cell AND2 (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port O (direction OUTPUT))\n"
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" (port I0 (direction INPUT))\n"
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" (port I1 (direction INPUT)))))\n"
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" (cell BUF (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port O (direction OUTPUT))\n"
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" (port I (direction INPUT)))))\n"
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" (cell FDCE (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port Q (direction OUTPUT))\n"
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" (port D (direction INPUT))\n"
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" (port C (direction INPUT))\n"
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" (port CE (direction INPUT)))))\n"
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" (cell GND (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface (port G (direction OUTPUT)))))\n"
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" (cell NOR2 (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port O (direction OUTPUT))\n"
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" (port I0 (direction INPUT))\n"
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" (port I1 (direction INPUT)))))\n"
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" (cell NOR3 (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port O (direction OUTPUT))\n"
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" (port I0 (direction INPUT))\n"
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" (port I1 (direction INPUT))\n"
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" (port I2 (direction INPUT)))))\n"
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" (cell VCC (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface (port P (direction OUTPUT)))))\n"
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" )\n"
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;
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static void edif_show_header(ivl_design_t des)
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{
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edif_show_header_generic(des, virtex_library_text);
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}
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static void edif_show_logic(ivl_net_logic_t net)
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{
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char jbuf[1024];
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||||
unsigned idx;
|
||||
|
||||
edif_uref += 1;
|
||||
|
||||
switch (ivl_logic_type(net)) {
|
||||
|
||||
case IVL_LO_AND:
|
||||
assert(ivl_logic_pins(net) <= 10);
|
||||
assert(ivl_logic_pins(net) >= 3);
|
||||
|
||||
fprintf(xnf, "(instance (rename U%u \"%s\")",
|
||||
edif_uref, ivl_logic_name(net));
|
||||
fprintf(xnf, " (viewRef Netlist_representation"
|
||||
" (cellRef AND%u (libraryRef VIRTEX))))\n",
|
||||
ivl_logic_pins(net) - 1);
|
||||
|
||||
sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
|
||||
edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
|
||||
|
||||
for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
|
||||
sprintf(jbuf, "(portRef I%u (instanceRef U%u))",
|
||||
idx-1, edif_uref);
|
||||
edif_set_nexus_joint(ivl_logic_pin(net, idx), jbuf);
|
||||
}
|
||||
break;
|
||||
|
||||
case IVL_LO_BUF:
|
||||
assert(ivl_logic_pins(net) == 2);
|
||||
fprintf(xnf, "(instance (rename U%u \"%s\")",
|
||||
edif_uref, ivl_logic_name(net));
|
||||
fprintf(xnf, " (viewRef Netlist_representation"
|
||||
" (cellRef BUF (libraryRef VIRTEX))))\n");
|
||||
|
||||
sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
|
||||
edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
|
||||
|
||||
sprintf(jbuf, "(portRef I (instanceRef U%u))", edif_uref);
|
||||
edif_set_nexus_joint(ivl_logic_pin(net, 1), jbuf);
|
||||
break;
|
||||
|
||||
case IVL_LO_NOR:
|
||||
assert(ivl_logic_pins(net) <= 10);
|
||||
assert(ivl_logic_pins(net) >= 3);
|
||||
|
||||
fprintf(xnf, "(instance (rename U%u \"%s\")",
|
||||
edif_uref, ivl_logic_name(net));
|
||||
fprintf(xnf, " (viewRef Netlist_representation"
|
||||
" (cellRef NOR%u (libraryRef VIRTEX))))\n",
|
||||
ivl_logic_pins(net) - 1);
|
||||
|
||||
sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
|
||||
edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
|
||||
|
||||
for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
|
||||
sprintf(jbuf, "(portRef I%u (instanceRef U%u))",
|
||||
idx-1, edif_uref);
|
||||
edif_set_nexus_joint(ivl_logic_pin(net, idx), jbuf);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
fprintf(stderr, "UNSUPPORT LOGIC TYPE: %u\n", ivl_logic_type(net));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
const struct device_s d_virtex_edif = {
|
||||
edif_show_header,
|
||||
edif_show_footer,
|
||||
edif_show_logic,
|
||||
edif_show_generic_dff,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* $Log: d-virtex.c,v $
|
||||
* Revision 1.1 2001/09/06 04:28:40 steve
|
||||
* Separate the virtex and generic-edif code generators.
|
||||
*
|
||||
*/
|
||||
|
||||
|
|
@ -2,16 +2,36 @@
|
|||
FPGA LOADABLE CODE GENERATOR FOR Icarus Verilog
|
||||
|
||||
Copyright 2001 Stephen Williams
|
||||
$Id: fpga.txt,v 1.1 2001/09/02 23:58:49 steve Exp $
|
||||
$Id: fpga.txt,v 1.2 2001/09/06 04:28:40 steve Exp $
|
||||
|
||||
The FPGA code generator supports a variety of FPGA devices, writing
|
||||
XNF or EDIF depending on the target. You can select the architecture
|
||||
of the device, and the detailed part name. The architecture is used to
|
||||
select library primitives, and the detailed part name is written into
|
||||
the generated file for the use of downstream tools.
|
||||
|
||||
INVOKING THE FPGA TARGET
|
||||
|
||||
This code generator is invoked with the -tfpga flag to iverilog. The
|
||||
code generator understands the part= and the arch= parameters, which
|
||||
can be set with the -p flag of iverilog:
|
||||
The code generator is invoked with the -tfpga flag to iverilog. It
|
||||
understands the part= and the arch= parameters, which can be set with
|
||||
the -p flag of iverilog:
|
||||
|
||||
iverilog -parch=virtex -fpart=v50-pq240-6 -tfpga foo.vl
|
||||
|
||||
This example selects the virtext architecture, and give the detailed
|
||||
part number as v50-pq240-6. The output is written into a.out unless a
|
||||
different output file is specified with the -o flag.
|
||||
|
||||
The following is a list of architecture types that this code generator
|
||||
supports.
|
||||
|
||||
* arch=generic-edif
|
||||
|
||||
This is generic EDIF code. It doesn't necessarily work because the
|
||||
external library is not available to the code generator. But, what it
|
||||
does is generate generic style gates that a portability library can
|
||||
map to target gates if desired.
|
||||
|
||||
* arch=generic-xnf
|
||||
|
||||
If this is selected, then the output is formatted as an XNF file,
|
||||
|
|
@ -25,7 +45,8 @@ code for your part.
|
|||
If this is selected, then the output is formatted as an EDIF 200 file,
|
||||
suitable for Virtex class devices. This is supposed to know that you
|
||||
are targeting a Virtex part, so can generate primitives instead of
|
||||
using external macros.
|
||||
using external macros. It includes the VIRTEX internal library, and
|
||||
should work properly for any Virtex part.
|
||||
|
||||
|
||||
XNF ROOT PORTS
|
||||
|
|
@ -65,6 +86,9 @@ definitions, including the proper direction marks.
|
|||
|
||||
---
|
||||
$Log: fpga.txt,v $
|
||||
Revision 1.2 2001/09/06 04:28:40 steve
|
||||
Separate the virtex and generic-edif code generators.
|
||||
|
||||
Revision 1.1 2001/09/02 23:58:49 steve
|
||||
Add documentation for the code generator.
|
||||
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ident "$Id: fpga_priv.h,v 1.3 2001/09/02 21:33:07 steve Exp $"
|
||||
#ident "$Id: fpga_priv.h,v 1.4 2001/09/06 04:28:40 steve Exp $"
|
||||
|
||||
# include <stdio.h>
|
||||
# include "device.h"
|
||||
|
|
@ -43,8 +43,47 @@ extern void xnf_mangle_lpm_name(ivl_lpm_t net, char*buf, size_t nbuf);
|
|||
|
||||
extern const char*xnf_mangle_nexus_name(ivl_nexus_t net);
|
||||
|
||||
/*
|
||||
* These are generic EDIF functions that EDIF targets use.
|
||||
*
|
||||
* edif_show_header_generic
|
||||
* This function draws the header part of the EDIF file, including
|
||||
* the ports of the module, if there are any. Also include the
|
||||
* library string where the external library would go.
|
||||
*
|
||||
* edif_show_footer
|
||||
* This completes the net items, draws the constant references, then
|
||||
* writes out the final declarations of the EDIF file.
|
||||
*
|
||||
* edif_set_nexus_joint
|
||||
* This stores joint information in the nexus, and save the nexus in
|
||||
* a list the edif_show_footer function later uses that list to draw
|
||||
* all the join records.
|
||||
*
|
||||
* edif_show_generic_dff
|
||||
* The edif DFF is an FDCE. This function draws an FDCE for the lpm
|
||||
* DFF of the design.
|
||||
*
|
||||
* edif_uref
|
||||
* This global variable keeps count of the devices drawn. Since the
|
||||
* EDIF format has very simple names, each device instead has a uref
|
||||
* and a name of the form U%u. A (rename U% "foo") preserves the
|
||||
* real name.
|
||||
*/
|
||||
extern void edif_show_header_generic(ivl_design_t des, const char*library);
|
||||
extern void edif_show_footer(ivl_design_t des);
|
||||
extern void edif_set_nexus_joint(ivl_nexus_t nex, const char*joint);
|
||||
|
||||
extern void edif_show_generic_dff(ivl_lpm_t net);
|
||||
|
||||
extern unsigned edif_uref;
|
||||
|
||||
|
||||
/*
|
||||
* $Log: fpga_priv.h,v $
|
||||
* Revision 1.4 2001/09/06 04:28:40 steve
|
||||
* Separate the virtex and generic-edif code generators.
|
||||
*
|
||||
* Revision 1.3 2001/09/02 21:33:07 steve
|
||||
* Rearrange the XNF code generator to be generic-xnf
|
||||
* so that non-XNF code generation is also possible.
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ident "$Id: tables.c,v 1.1 2001/09/02 21:33:07 steve Exp $"
|
||||
#ident "$Id: tables.c,v 1.2 2001/09/06 04:28:40 steve Exp $"
|
||||
|
||||
# include "fpga_priv.h"
|
||||
# include <string.h>
|
||||
|
|
@ -24,6 +24,7 @@
|
|||
|
||||
extern const struct device_s d_generic;
|
||||
extern const struct device_s d_generic_edif;
|
||||
extern const struct device_s d_virtex_edif;
|
||||
|
||||
|
||||
const struct device_table_s {
|
||||
|
|
@ -32,7 +33,7 @@ const struct device_table_s {
|
|||
} device_table[] = {
|
||||
{ "generic-edif", &d_generic_edif },
|
||||
{ "generic-xnf", &d_generic },
|
||||
{ "virtex", &d_generic_edif },
|
||||
{ "virtex", &d_virtex_edif },
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
|
|
@ -53,6 +54,9 @@ device_t device_from_arch(const char*arch)
|
|||
|
||||
/*
|
||||
* $Log: tables.c,v $
|
||||
* Revision 1.2 2001/09/06 04:28:40 steve
|
||||
* Separate the virtex and generic-edif code generators.
|
||||
*
|
||||
* Revision 1.1 2001/09/02 21:33:07 steve
|
||||
* Rearrange the XNF code generator to be generic-xnf
|
||||
* so that non-XNF code generation is also possible.
|
||||
|
|
|
|||
Loading…
Reference in New Issue