Add to synth2 support for synthesis of
synchronous logic. This includes DFF enables modeled by if/then/else.
This commit is contained in:
steve
parent
8fbacc966e
commit
eb81062d85
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@ -16,7 +16,7 @@
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# 59 Temple Place - Suite 330
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# Boston, MA 02111-1307, USA
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#
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#ident "$Id: Makefile.in,v 1.133 2002/08/12 00:27:10 steve Exp $"
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#ident "$Id: Makefile.in,v 1.134 2002/09/16 00:30:33 steve Exp $"
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#
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#
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SHELL = /bin/sh
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@ -126,7 +126,7 @@ net_design.o net_event.o net_expr.o net_force.o net_func.o \
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net_link.o net_modulo.o net_nex_input.o net_nex_output.o \
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net_proc.o net_scope.o net_udp.o pad_to_width.o \
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parse.o parse_misc.o pform.o pform_dump.o \
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set_width.o \
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set_width.o sync.o \
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verinum.o verireal.o target.o targets.o \
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Attrib.o HName.o LineInfo.o Module.o PDelays.o PEvent.o \
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PExpr.o PGate.o \
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33
netlist.h
33
netlist.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: netlist.h,v 1.261 2002/09/12 15:49:43 steve Exp $"
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#ident "$Id: netlist.h,v 1.262 2002/09/16 00:30:33 steve Exp $"
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#endif
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/*
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@ -1214,10 +1214,17 @@ class NetProc : public LineInfo {
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// process. Most process types are not.
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virtual bool is_asynchronous();
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// Return true if this represents the root of a synchronous
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// process. Most process types are not.
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virtual bool is_synchronous();
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// synthesize as asynchronous logic, and return true.
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virtual bool synth_async(Design*des, NetScope*scope,
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const NetNet*nex_map, NetNet*nex_out);
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virtual bool synth_sync(Design*des, NetScope*scope, NetFF*ff,
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const NetNet*nex_map, NetNet*nex_out);
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virtual void dump(ostream&, unsigned ind) const;
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private:
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@ -1530,6 +1537,9 @@ class NetCondit : public NetProc {
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bool synth_async(Design*des, NetScope*scope,
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const NetNet*nex_map, NetNet*nex_out);
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bool synth_sync(Design*des, NetScope*scope, NetFF*ff,
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const NetNet*nex_map, NetNet*nex_out);
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virtual bool emit_proc(struct target_t*) const;
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virtual int match_proc(struct proc_match_t*);
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virtual void dump(ostream&, unsigned ind) const;
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@ -1735,11 +1745,18 @@ class NetEvWait : public NetProc {
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// process. This method checks.
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virtual bool is_asynchronous();
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// It is possible that this is the root of a synchronous
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// process? This method checks.
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virtual bool is_synchronous();
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virtual void nex_output(NexusSet&out);
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virtual bool synth_async(Design*des, NetScope*scope,
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const NetNet*nex_map, NetNet*nex_out);
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virtual bool synth_sync(Design*des, NetScope*scope, NetFF*ff,
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const NetNet*nex_map, NetNet*nex_out);
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virtual void dump(ostream&, unsigned ind) const;
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private:
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@ -2116,13 +2133,20 @@ class NetProcTop : public LineInfo, public Attrib {
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NetScope*scope();
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const NetScope*scope() const;
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/* Return true of this process represents combinational logic. */
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/* Return true if this process represents combinational logic. */
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bool is_asynchronous();
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/* Create asynchronous logic from this thread and return true,
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or return false if that cannot be done. */
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bool synth_async(Design*des);
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/* Return true if this process represents synchronous logic. */
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bool is_synchronous();
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/* Create synchronous logic from this thread and return true,
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or return false if that cannot be done. */
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bool synth_sync(Design*des);
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void dump(ostream&, unsigned ind) const;
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bool emit(struct target_t*tgt) const;
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@ -3027,6 +3051,11 @@ extern ostream& operator << (ostream&, NetNet::Type);
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/*
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* $Log: netlist.h,v $
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* Revision 1.262 2002/09/16 00:30:33 steve
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* Add to synth2 support for synthesis of
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* synchronous logic. This includes DFF enables
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* modeled by if/then/else.
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*
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* Revision 1.261 2002/09/12 15:49:43 steve
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* Add support for binary nand operator.
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*
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@ -0,0 +1,75 @@
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/*
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* Copyright (c) 2002 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: sync.cc,v 1.1 2002/09/16 00:30:33 steve Exp $"
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#endif
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# include "config.h"
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# include "functor.h"
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# include "netlist.h"
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# include <assert.h>
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/*
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* Most process statements are not roots of synchronous logic.
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*/
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bool NetProc::is_synchronous()
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{
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return false;
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}
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bool NetEvWait::is_synchronous()
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{
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for (unsigned idx = 0 ; idx < nevents_ ; idx += 1) {
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NetEvent*ev = events_[idx];
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if (ev->nprobe() == 0)
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return false;
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for (unsigned pdx = 0 ; pdx < ev->nprobe() ; pdx += 1) {
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NetEvProbe*pr = ev->probe(pdx);
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/* No level sensitive clocks. */
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if (pr->edge() == NetEvProbe::ANYEDGE)
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return false;
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}
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}
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/* So we know that there is a clock source. Check that the
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input to the storage is asynchronous. */
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return true; //statement_->is_asynchronous();
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}
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bool NetProcTop::is_synchronous()
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{
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if (type_ == NetProcTop::KINITIAL)
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return false;
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return statement_->is_synchronous();
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}
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/*
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* $Log: sync.cc,v $
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* Revision 1.1 2002/09/16 00:30:33 steve
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* Add to synth2 support for synthesis of
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* synchronous logic. This includes DFF enables
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* modeled by if/then/else.
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*
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*/
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119
synth2.cc
119
synth2.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: synth2.cc,v 1.8 2002/08/18 22:07:16 steve Exp $"
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#ident "$Id: synth2.cc,v 1.9 2002/09/16 00:30:33 steve Exp $"
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#endif
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# include "config.h"
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@ -27,6 +27,19 @@
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# include "compiler.h"
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# include <assert.h>
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bool NetProc::synth_async(Design*des, NetScope*scope,
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const NetNet*nex_map, NetNet*nex_out)
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{
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return false;
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}
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bool NetProc::synth_sync(Design*des, NetScope*scope, NetFF*ff,
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const NetNet*nex_map, NetNet*nex_out)
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{
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/* Synthesize the input to the DFF. */
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return synth_async(des, scope, nex_map, nex_out);
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}
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static unsigned find_nexus_in_set(const NetNet*nset, const Nexus*nex)
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{
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unsigned idx = 0;
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@ -241,12 +254,6 @@ bool NetEvWait::synth_async(Design*des, NetScope*scope,
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return statement_->synth_async(des, scope, nex_map, nex_out);
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}
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bool NetProc::synth_async(Design*des, NetScope*scope,
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const NetNet*nex_map, NetNet*nex_out)
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{
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return false;
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}
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bool NetProcTop::synth_async(Design*des)
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{
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NexusSet nex_set;
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@ -263,6 +270,92 @@ bool NetProcTop::synth_async(Design*des)
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return flag;
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}
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bool NetCondit::synth_sync(Design*des, NetScope*scope, NetFF*ff,
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const NetNet*nex_map, NetNet*nex_out)
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{
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/* If this is an if/then/else, then it is likely a
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combinational if, and I should synthesize it that way. */
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if (if_ && else_) {
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return synth_async(des, scope, nex_map, nex_out);
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}
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assert(if_);
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assert(!else_);
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/* Synthesize the input to the DFF. */
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bool flag = if_->synth_async(des, scope, nex_map, nex_out);
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if (flag == false)
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return flag;
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assert(expr_);
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/* Synthesize the enable expression. */
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NetNet*ce = expr_->synthesize(des);
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assert(ce->pin_count() == 1);
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connect(ff->pin_Enable(), ce->pin(0));
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return true;
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}
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bool NetEvWait::synth_sync(Design*des, NetScope*scope, NetFF*ff,
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const NetNet*nex_map, NetNet*nex_out)
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{
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/* Synthesize the input to the DFF. */
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bool flag = statement_->synth_sync(des, scope, ff, nex_map, nex_out);
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assert(nevents_ == 1);
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NetEvent*ev = events_[0];
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assert(ev->nprobe() == 1);
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NetEvProbe*pclk = ev->probe(0);
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assert(pclk->pin_count() == 1);
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connect(ff->pin_Clock(), pclk->pin(0));
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if (pclk->edge() == NetEvProbe::NEGEDGE)
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ff->attribute("Clock:LPM_Polarity", verinum("INVERT"));
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return flag;
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}
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bool NetProcTop::synth_sync(Design*des)
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{
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NexusSet nex_set;
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statement_->nex_output(nex_set);
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NetFF*ff = new NetFF(scope(), scope()->local_hsymbol().c_str(),
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nex_set.count());
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des->add_node(ff);
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ff->attribute("LPM_FFType", verinum("DFF"));
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/* The D inputs to the DFF device will receive the output from
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the statments of the process. */
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NetNet*nex_d = new NetNet(scope(), scope()->local_hsymbol().c_str(),
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NetNet::WIRE, nex_set.count());
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nex_d->local_flag(true);
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for (unsigned idx = 0 ; idx < nex_set.count() ; idx += 1) {
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connect(nex_d->pin(idx), ff->pin_Data(idx));
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}
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/* The Q outputs of the DFF will connect to the actual outputs
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of the process. Thus, the DFF will be between the outputs
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of the process and the outputs of the substatement. */
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NetNet*nex_q = new NetNet(scope(), "tmpq", NetNet::WIRE,
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nex_set.count());
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for (unsigned idx = 0 ; idx < nex_set.count() ; idx += 1) {
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connect(nex_set[idx], nex_q->pin(idx));
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connect(nex_q->pin(idx), ff->pin_Q(idx));
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}
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/* Synthesize the input to the DFF. */
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bool flag = statement_->synth_sync(des, scope(), ff, nex_q, nex_d);
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delete nex_q;
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return flag;
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}
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class synth2_f : public functor_t {
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public:
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@ -281,6 +374,13 @@ void synth2_f::process(class Design*des, class NetProcTop*top)
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if (top->attribute("ivl_synthesis_off").as_ulong() != 0)
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return;
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if (top->is_synchronous()) do {
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bool flag = top->synth_sync(des);
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assert(flag);
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des->delete_process(top);
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return;
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} while (0);
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if (! top->is_asynchronous()) {
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bool synth_error_flag = false;
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if (top->attribute("ivl_combinational").as_ulong() != 0) {
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@ -324,6 +424,11 @@ void synth2(Design*des)
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/*
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* $Log: synth2.cc,v $
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* Revision 1.9 2002/09/16 00:30:33 steve
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* Add to synth2 support for synthesis of
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* synchronous logic. This includes DFF enables
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* modeled by if/then/else.
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*
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* Revision 1.8 2002/08/18 22:07:16 steve
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* Detect temporaries in sequential block synthesis.
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*
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