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1496 Commits
Author SHA1 Message Date
Martin Whitaker dacd613f94 Backported fix for br991 from devel branch. 2015-08-19 08:49:28 +01:00
Cary R 8d8cdf774b A concatenation and the expression being replicated must have a non-zero width 2015-08-18 16:32:53 -07:00
Martin Whitaker d9a1cfd85f Fix for br988 - support begin/end blocks nested inside generate blocks.
This is syntax permitted in 1364-2001 but removed in 1364-2005.
2015-08-07 23:28:24 +01:00
Cary R d3bdc60201 Correctly display events when dumping using the FST format
This patch is from Tony Bybell and fixes a segmentation fault when dumping
an event to a FST file.
2015-07-22 00:30:35 -07:00
Martin Whitaker 2e4810f172 Fix for br977 - preprocessor macros substitute text inside token.
When replacing macro formal parameters, the preprocessor should not
replace matching strings that are not complete tokens. The test for
this was incorrect, and failed when a match was found at the start
of the replacement text.
2015-05-17 20:16:40 +01:00
Cary R 3da546c7d2 Update fstapi.c to latest from GTKWave 2015-05-08 16:38:28 -07:00
Martin Whitaker 7b23a5c3c1 Fix br972 - assertion failure with combinational loop on logic function.
Backported from development.
2015-04-25 20:03:19 +01:00
Martin Whitaker 7d12216b14 Backported sorry messages for variable RHS on procedural force/CA. 2015-04-25 13:16:24 +01:00
Martin Whitaker 2f4b460f6e Fix for compiler crash on source code errors in always @* block loops.
Backported from devel, but due to the extra complexity of for loop
handling in v0.9, makes less effort to elaborate all the code before
giving up.
2015-04-13 16:42:40 +01:00
Martin Whitaker 904113db02 Backported fix for br970 from devel branch. 2015-04-13 16:41:03 +01:00
Cary R e2330a7eeb Update fstapi files to latest from GTKWave 2015-04-02 14:59:59 -07:00
Cary R e162258e9a V0.9: update fstapi.h to latest from GTKWave 2015-02-25 17:38:36 -08:00
Cary R 72e4c72069 VHDL: fix assert to check that the third octal token is a digit 2015-02-25 17:34:33 -08:00
Martin Whitaker 1f9703f1bc Fix for br968.
vthr_vec_get_value() assumed the source vector was unsigned.
2015-01-10 18:03:31 +00:00
Cary R c8184c31ef Update lz4 files from GTKWave 2014-12-28 09:26:13 -08:00
Martin Whitaker 82ef3780ec Fix for br967 - allow real value for repeat statement loop length. 2014-12-13 19:48:01 +00:00
Cary R 7d042accfd Revert: Back port variable initialization fix from development.
It turns out that the new feature was actually a bug.
2014-12-04 16:47:26 -08:00
Cary R 0bccde2e17 Back port variable initialization fix from development. 2014-12-02 13:56:43 -08:00
Cary R 387a923d50 Update lz4 files from GTKWave 2014-11-29 07:37:19 -08:00
Cary R 5569679de8 V0.9: Patch from github #44 2014-11-04 11:48:19 -08:00
Martin Whitaker a75fc86cb1 Fix for br961 - function return type elaborated in wrong scope.
The return type of a function should be elaborated in the context of
the enclosing scope, not in the context of the function itself.
2014-10-30 21:37:31 +00:00
Cary R 68e6fb48c9 V0.9: Update lz4 files from GTKWave 2014-10-27 15:41:28 -07:00
Cary R b18aedfa80 V0.9: Back port fixes for putting modpath delays and delay calculations 2014-10-27 14:40:50 -07:00
Cary R bf08fcd5e7 V0.9: Update files from GTKWave 2014-07-31 16:42:43 -07:00
Cary R 3a91148004 V0.9: fix memory leak in VAMS $simparam$str 2014-07-28 11:03:15 -07:00
Cary R c3171862ab V0.9: Add support for power operator in eval_const() 2014-07-07 18:18:04 -07:00
Cary R 0961eae27e Add support for one argumenr $urandom_range() 2014-06-14 14:17:13 -07:00
Cary R f7752caaac Update files from GTKWave to the latest from svn 2014-06-14 14:02:46 -07:00
Martin Whitaker 6183bf6cd7 Fix for GitHub issue 26 - compiler crash when module port has no internal net.
The compiler correctly reports an error when a module port has no
associated internal net/reg, but could crash when the module was
instantiated.
2014-05-23 23:15:14 +01:00
Cary R 9b38de596e Update FST files to latest from GTKWave 2013-10-25 15:07:17 -07:00
Cary R 0509bdd53e Mostly fix a portability problem in $rtoi (run time) 2013-10-11 17:33:21 -07:00
Cary R 4989afb153 V0.9: Fix another real to vpiIntVal conversion in the run time 2013-10-11 11:39:33 -07:00
Cary R 530c9cd895 V0.9: Fix $rtoi to correctly convert NaN and +/- infinity 2013-10-11 11:39:18 -07:00
Cary R 0d6925fe5b V0.9: Fix real to vpiIntVal conversion in run time 2013-10-11 11:38:52 -07:00
Martin Whitaker 65d751690b Fix for br937.
When writing a string value, vpi_put_value cannot assume the target vector
is a multiple of 8 bits wide.
2013-09-28 17:19:05 +01:00
Cary R f8219bf8ff v0.9: The seed passed to $random() should not change the implicit seed. 2013-09-23 17:52:50 -07:00
Stephen Williams 8288f7305d Prepare for Icarus Verilog version 0.9.7 release 2013-08-19 12:10:31 -07:00
Cary R 8b6ccc65d6 Update to latest FST API files from GTKWave 2013-08-09 11:35:07 -07:00
Cary R 452c1650f4 Update FST files to latest from GTkWave 2013-07-16 11:27:52 -07:00
Cary R 00337d2418 Fix space issue in vvp/vvp_net.cc 2013-07-15 16:19:23 -07:00
Cary R bf2b086669 Back port vector8 changes from development to eliminate compile warnings 2013-07-15 16:16:04 -07:00
Cary R 4289ae23f9 Update fstap files to the latest from GTKWave 2013-06-14 16:35:44 -07:00
Martin Whitaker 4efb601fee V0.9: Fix for br930 - support attributes on old-style port declarations. 2013-05-19 11:05:01 +01:00
Cary R c8c0a298e4 V0.9 Update fstapi.c to latest from SVN 2013-04-16 15:14:01 -07:00
Martin Whitaker f99ca8672c Fix VHDL code generator crash when a terneray operator has a real operand. 2013-04-12 23:50:16 +01:00
Martin Whitaker 19e266159e Fix for br924.
Prevent compiler crashes after a function argument fails to be
elaborated (back-ported from development).
2013-03-31 19:57:37 +01:00
Cary R 2777a8b00b V0.9: A concatenation may also need a BUFZ to hold the drive strength
Just like a select a concatenation needs a BUFZ to hold the drive strength.
2013-02-12 18:37:09 -08:00
Cary R c84eec1d60 V0.9: minor fixes to br916 patch 2013-02-04 11:45:42 -08:00
Martin Whitaker 0f4658135e V0.9: Stopgap fix for br916.
Currently, when a variable expression is passed to a system task,
the expression value is stored in thread memory. Values stored
in thread memory cannot safely be passed to $strobe or $monitor,
because the thread memory may get reused or deallocated before
the $strobe or $monitor task actually executes. As a temporary
measure, we just trap this case and terminate with a "sorry"
message. A proper fix would require the expression value to be
calculated at the time the $strobe or $monitor executes, not at
the time it is called.
2013-02-04 11:45:35 -08:00
Martin Whitaker 200951275c Fix logic value returned for unambiguous HiZ1 strength.
If a strength aware net has an unambiguous HiZ1 strength, VVP treats
it as a logic '1'. It should be treated as a logic 'z'. An ambiguous
HiZ1/HiZ0 strength should also be treated as a logic 'z'.
2013-01-28 19:07:08 -08:00
Cary R 9b1c1a5d48 Fix space issue 2013-01-25 10:34:34 -08:00
Cary R edf741106d V0.9: Handle undefined L-value selects
L-value bit selects were incorrectly converting an undefined index to 0.

L-value part selects were asserting if an undefined index was given.

This patch unifies how all these are handle (including indexed part selects).

The base is set to an undefined value and an appropriate width is used.
A warning message is always printed since this is not a simple out of
range issue. It is the responsibility of the code generator to skip the
assignment, but we always want to execute the R-value since it could have
a side effect.
2013-01-25 10:32:52 -08:00
Cary R 4b805a2b89 Remove space issues 2013-01-21 19:29:34 -08:00
Martin Whitaker 8ae15b93cf Fix for bug 915 (was 3592746).
probe_expr_width() must be called before calling elab_and_eval(), to
determine the expression type.
2013-01-21 19:12:07 -08:00
Martin Whitaker 66338431f5 Fix for bug 913 (was 3587570).
probe_expr_width() must be called before calling elab_and_eval(), to
determine the expression type.
2013-01-21 19:02:08 -08:00
Martin Whitaker 0a06cf5d28 V0.9: Fix display of net array words when data type is signed.
When VVP compiles a .array statement for a net array, it does not
know the data type, so initialises the array signed_flag to false.
We need to set the signed_flag to the correct value once we know
the data type, to allow the VPI routines to correctly format the
data.
2013-01-21 18:46:59 -08:00
Martin Whitaker 15fee99abb Fix for pr3571573.
This patchs adds an implementation of recv_vec4_pv() to the vvp_fun_concat
class. This was already present in devel, so just needed to be backported
to v0.9.
2013-01-21 18:24:39 -08:00
Cary R 0ab44eca13 Update fstapi.c from GTKWave to fix MinGW compile. 2012-11-27 09:19:29 -08:00
Cary R 760ab91a36 Update fstapi.c and lxt2_write.c to latest from GTKWave
This just fixes warnings in cppcheck
2012-11-15 15:33:05 -08:00
Stephen Williams fc41668cf1 Make use of LDFLAGS when linking *.tgt files
Submitted by Ahmed El-Mahmoudy
2012-11-03 10:27:59 -07:00
Stephen Williams b8bcb016aa Fix licensing issues.
Remove des.v, which has incompatible restrictions.
Repair some copyright names (Remove Picture Elements)
Update FSF address.
2012-10-01 09:06:51 -07:00
Stephen Williams a233e21cd8 Prepare for 0.9.6 release. 2012-09-05 18:20:12 -07:00
Stephen Williams 87c691654e Spelling fixes. 2012-09-05 17:55:20 -07:00
Cary R 1f6aec6e26 Add %u support to the scanf routines. 2012-09-05 14:24:09 -07:00
Cary R 61cfb9e1fd Add support for %z to the scanf() routines 2012-09-04 18:46:37 -07:00
Cary R 01c4cd3dad Windows (mingw) _vsnprintf() returns -1 not the required size on overflow.
Windows and hence mingw does not follow the standard regarding the return
value of vsnprintf(). The mingw code needs to iteratively search for a
buffer large enough to print the output.
2012-08-31 10:57:31 -07:00
Cary R 62f1aa135b Cleanup after the va_copy()
I missed that va_end() needs to be called on the new ap created by va_copy().
2012-08-31 09:22:36 -07:00
Cary R 5794098aa4 Save the va_list so it can be reused if needed.
The second call to vsnprintf() needs to have a copy of the argument list
so it can run correctly. On some system vsnprintf() destorys the original
argument list.
2012-08-30 20:04:25 -07:00
Cary R 9d5f438872 Allocate a string buffer as needed in the code generator and vvp display code
When sending a string to a system task/function allocate the space needed
to avoid truncating the string vs using a large fixed buffer.

In vvp allocate and use an exactly sized buffer for the MCD print routine if
the fixed buffer is not large enough. Using a fixed buffer keeps normal
printing fast.
2012-08-30 19:12:23 -07:00
Martin Whitaker 267ba427a3 Fix for pr3561350.
When a new NetEBMult object is created, the compiler guesses the
expression width based on the sum of the operand widths. When we
duplicate an expression, we need to override this with the width
from the original expression.
2012-08-29 10:29:56 -07:00
Martin Whitaker a3987a112b V0.9: Fix for pr3557493.
defparam assignments found inside a generate block were being stored
in the enclosing module scope. They should be stored in the generate
block scope.
2012-08-21 17:46:50 -07:00
Cary R e8b40e14b9 Update lxt, lxt2 and fst files to latest from GTKWave 2012-08-16 14:56:32 -07:00
Cary R 34bb00144f V0.9: back port some cross compile changes 2012-08-13 18:09:00 -07:00
Cary R 0a518c1786 V0.9: update uninstall include directory rule 2012-08-13 17:12:00 -07:00
Martin Whitaker cd029fe35d Fix time scaling in PLI TF routines for MinGW.
When built with MinGW, pow() may not always generate an exact integer
result when supplied with integer operands. Converting the result to an
integer before we use it seems to be enough to work round this issue.
2012-08-06 13:39:40 -07:00
Martin Whitaker 693574107b V0.9: Add missing semi-colons in parser rules.
Also add null actions to prevent older versions of bison failing due
to type clashes, plus a few minor spelling/formatting fixes.
2012-08-01 15:39:56 -07:00
Martin Whitaker db3b1d9bf0 Handle error case of zero width in indexed part select.
The compiler doesn't currently check that the width of an indexed
part select is non-zero. If code contains this erroneous case, the
compiler can crash (with an assertion failure). This patch causes
the compiler to output a suitable error message and recover. It
also fixes a potential crash if an illegal expresson is encountered.
(cherry picked from commit c4ff8300d3)
2012-07-27 18:49:48 -07:00
Martin Whitaker d3563bc210 V0.9: Allow a UDP instance to have a simple real delay.
The parser does not distinguish between module and UDP instances, so
a UDP delay is handled by the rules used for parsing module parameter
overrides. Although these rules had been relaxed to accept the case of
a simple decimal value (e.g. #10), they did not allow a simple real
value (e.g. #0.1).
2012-07-27 18:35:08 -07:00
Martin Whitaker 52f15498b9 V0.9: Fix elaboration order in generate blocks.
Currently, localparam declarations inside generate blocks are
elaborated after any nested generate constructs are elaborated.
This prevents the localparams being used by the nested constructs.
Reversing the elaboration order fixes this bug.
2012-07-01 12:15:02 -07:00
Martin Whitaker 27cb31db4b V0.9: Fix for pr3527022.
This patch adds support for an explicit range or type in a parameter
declaration that is part of a module parameter port list.
2012-05-18 13:57:18 -07:00
Cary R a6ca1a7ce8 V0.9: For a delayed vpi_put_value() copy any pointer data members.
When vpi_put_value() is asked to delay the assignment any pointer data
needs to be duplicated so that the caller can clean up the locally
allocated memory without causing memory access problems.
2012-04-02 15:31:32 -07:00
Martin Whitaker ca2319153f V0.9 - Fix for pr3499807.
Output a "sorry" message to inform the user that tranif delays are
not supported.
2012-03-12 09:06:16 -07:00
Cary R 0210d49cf8 V0.9: Fix the formatting of time values that are less than 1
This patch is a modification of a user contributed patch that fixes the
time formatting when the time is less than 1 and $timeformat() is used.
2012-01-23 18:52:49 -08:00
Cary R c292f77f28 V0.9: Remove crash for function def with zero args and warn on calls
Normal Verilog does not allow a function to be defined without at
least an input argument. This patch fixes a crash that was happening
when a function with no arguments was defined. It also adds checks
and prints a descriptive error message when calling a function without
an argument.

The development branch allows this in SV.
2012-01-09 19:12:55 -08:00
Cary R 5f47d660a1 V0.9: remove unneeded -s flags for flex
I added these in a previous patch, but they are not needed and
generate a warning.
2012-01-07 11:35:43 -08:00
Cary R b47fad7d19 V0.9: Update lex/yacc builds to be consistent and to support parallel builds
Not all the lex/yacc (flex/bison) targets were using a consistent syntax.
This patch fixes that and explicitly serializes the *.c/*.cc and *.h build.
Not doing this was causing problem when using make -j. The issue appears to
be that if two targets are specified for a rule (e.g. file.cc file.h: file.y)
make does not realize they are both built by the same call so the rule is
executed twice. Once for the .cc target and once for the .h target. This is
not a problem for a serial build. To work around this only use the .c/.cc
file in the main target and then make the .h file depend on the .c/.cc file
as a sub-target.
2012-01-04 18:40:37 -08:00
Cary R e1789e7fb9 V0.9: To reduce error divide by an integer vs multiple by a fraction.
This same change was done in the vpi directory. This patch fixes the
issues in the libveriuser directory. This fixed a fail in the vpi
timescale test under MinGW.
2011-12-16 19:09:48 -08:00
Martin Whitaker 2b67a6d465 Add support for param declarations with signed type but no range
The standard allows a parameter (or localparam) declaration of the
form "parameter signed my_param = ...". The parser currently rejects
this. A small adjustment is also required in the parameter evaluation
code to correctly apply the type.
2011-12-16 13:52:18 -08:00
Martin Whitaker c96619527a Fix for pr3452808.
The tran island rework included an optimisation that meant that an
island port would only be resolved once the initial value for the net
attached to that port had propagated to the port. However, v0.9 does
not propagate initial values in some cases, so this optimisation
cannot be used.
2011-12-10 12:09:26 -08:00
Cary R 0fa7764eac V0.9:Don't pad a real argument to a user task.
The compiler was incorrectly padding real arguments to tasks if they were
assigned to vectored arguments greater than 1 bit wide. This was asserting
for some cases and generating incorrect code for others.
2011-12-05 19:07:10 -08:00
Cary R c60877999c V0.9: Define turn_sig_to_wire_on_release_ to false in constructor.
Not giving this a default value was leaving the value undefined under
some circumstances. This was producing incorrect results on Cygwin.
2011-11-25 17:06:02 -08:00
Cary R fff46da881 v0.9: Treat an empty @* as something that will never trigger.
An @* with no sensitivities should be treated as something that will
never trigger vs something that will run continuously. This patch makes
this change and adds a warning when an @* has no sensitivities since
this is almost certainly a coding bug.
2011-11-23 17:34:00 -08:00
Cary R 34d8eb27c7 V0.9: Add support for a named block to only have variable definitions.
It is legal for a named block to contain variable definitions and
no statements. This patch fixes this for both style of blocks. It
also organizes the block parsing code to be a bit more clear, adds
an error case for fork/join and changes on check for size() > 0 for
the more efficient ! empty().
2011-11-22 20:48:43 -08:00
Stephen Williams e97ca19a25 Add --always and --dirty to git describe. 2011-11-19 09:05:36 -08:00
Cary R 68c6e578ae V0.9: For wire and/or nets we need all the net resolution to be and/or.
If a wired and/or net has more than four connections all the other
resolution branches must also be wired and/or. All other nets can
just be tri since tri0/tri1 only needs the final resolution to be
an active pull up/down.
2011-11-19 08:48:31 -08:00
Cary R 8e1c507984 V0.9: Assert that sync/async set/clear are not supported for a DFF primitive.
Since synthesis is not currently supported we do not support/generate
sync/async set or clear control inputs. This is further complicated by
the fact that the VVP DFF primitive is not fully implemented.
2011-11-17 14:42:07 -08:00
Cary R da49a4a798 V0.9: Report that a vectored full connection only supports a single src/dst
In a specify block a full connection is defined to only support a single
source and destination path. This patch adds an error message when this
is found, except we skip the error if all the paths are a single bit
wide. This exemption was added to match the functionality found in
NC-Verilog and presumably Verilog-XL.

A message was also added in place of an assert if the source signals was
not found in the current scope.
2011-11-10 17:57:59 -08:00
Cary R aab491a762 V0.9: Add check that a parallel connection uses the same width input/output.
This patch uses the full_flag to verify that the input and output have the
same width for a parallel connection. Icarus always uses a full connection
so this is just a portability issue with other simulators.

The pform dump code was also modified to correctly display the polarity
and full/parallel connection type.
2011-11-10 17:46:34 -08:00
Cary R 3dca540a29 V0.9: Fix space issues.
This patch removes space before EOL, etc.
2011-11-03 19:20:06 -07:00
Ole Henrik Jahren 36f72a8521 Add missing hyphen to --ldlibs option in iverilog-vpi man page
(cherry picked from commit d2dc0e535f)
2011-11-03 19:09:20 -07:00
Stephen Williams 1a3ce11a79 Prepare for version 0.9.5 2011-11-01 09:57:50 -07:00
Cary R 2fbe7434f2 Use UINT_MAX instead of -1 to set unsigned to maximum value.
The Sun C compiler warns when -1 is used to initialize an unsigned.
(cherry picked from commit 7d588d699b)
2011-10-31 17:23:15 -07:00
Cary R 85faab8a08 V0.9: Reduce the error when scaling a real time value.
When scaling a time value we would often use the power operator to
create constants 10**-N that were then multiplied with the original
value. The problem with this is that there is some errors in the
representation of the fractional number. It is better to create a
integer value 10**N and then divide the original value by this
exact constant. You still have the calculation error, but the scale
value is now an exactly real value.
2011-10-31 10:44:43 -07:00
Cary R e160f5c562 Remove old comment. 2011-10-31 10:40:33 -07:00
Cary R 9481262c06 V0.9: Major rework of the $sscanf()/$fscanf() code.
Add support for %m, suppression '*' and a maximum field width along with
a number of other fixes/enhancements. There is still no support for
%u, %v or %z.
2011-10-31 10:40:27 -07:00
Cary R 3d99bb13c4 Make some messages consistent.
This patch makes some of the VPI messages consistent with the rest.
2011-10-31 10:36:46 -07:00
Martin Whitaker af07b87419 Restore ability to supply LDFLAGS to MinGW configure.
The fix to get a C99 compliant strtod() in MinGW mistakenly set the
LDFLAGS value rather than appending to it. This meant that a LDFLAGS
supplied by the user on the configure command line would be ignored.
(cherry picked from commit c4433e47c1)
2011-10-31 10:30:57 -07:00
Martin Whitaker f4dec1710d Fix for tf_getlongsimtime link error on MinGW/Cygwin.
MinGW and Cygwin don't currently support weak function definitions.
For these platforms, make tf_getlongsimtime a strong symbol.
(cherry picked from commit 7f62579524)
2011-10-26 18:50:02 -07:00
Martin Whitaker fa88ac03dd Workaround for MinGW non-standard strtod.
MinGW has reverted to using the Microsoft msvcrt0 implementation
of the strtod() function. This implementation doesn't accept "INF"
"NaN". MinGW does provide a C99 compliant implementation of this
function called __strtod(). We need to force the linker to replace
all references to strtod() with references to __strtod().
(cherry picked from commit b6cb065404)
2011-10-26 18:49:05 -07:00
Cary R c6bc46b9a4 Update fstapi.c to latest from GTkWave
There was a change in how the FST data was flushed.
(cherry picked from commit 0b978dac48)
2011-10-26 18:48:13 -07:00
Cary R eb5a385433 v0.9: Report that forcing a word to/from a variable array in not supported.
This patch adds error messages that forcing a word to/from a variable
array is not currently supported. This is because variable arrays no
longer are fully populated and don't have an access functor for each
word. Forcing a word from/to a net array does work as expected since
each word in a net array is created.

Technically forcing a variable array word is not supported in 1364-2005.
Reading from an array word, which is supported,  will be fixed in
development once the expression rework is finished.

The error message printed when forcing a bit/part select l-value was
also improved.
2011-10-25 19:43:01 -07:00
Cary R 0ad589eaca V0.9: Improve the out of range check in tgt-vhdl/stmt.cc
Promote the unsigned values to long to get a good comparison and on a
machine where an unsigned is the same size as a long (32 bit) assert
that the unsigned values are constrained to fit into a long. It's unlikely
the values needed to create invalid results would ever happen, but this
patch makes sure it doesn't go undetected.
2011-10-25 19:05:21 -07:00
Cary R 17344563a8 V0.9: Remove some scan-build warnings.
One of these is a real bug, the others are just minor optimizations.
2011-10-20 16:54:50 -07:00
Cary R 617243f298 Update various dumper files from GTKWave SVN
Update some of the files we get from GTKWave to match the latest from SVN.
(cherry picked from commit b9af189229)
2011-10-20 16:51:15 -07:00
Cary R aa1bfafbc2 V0.9: Fix autoconf warning.
This just copies the same change that was done for development over to V0.9.
2011-10-19 18:17:19 -07:00
Cary R 4dae0471de V0.9: Remove some gcc/g++ (4.6.1) warnings.
This patch remove some unused variable warnings found with gcc/g++ 4.6.1
on Ubuntu 11.10.
2011-10-19 18:16:06 -07:00
Martin Whitaker f8bc2b6198 V0.9 Fix for pr3420994.
The VPI object data model diagrams show a one to many relationship
between the "mod path" and "path term" objects. This means that the
correct way to obtain handles to "path term" objects is to use the
vpi_iterate and vpi_scan functions.

Support for the old method of obtaining handles to "path term" objects
using the vpi_handle function is retained for backwards compatibility.
2011-10-19 14:41:42 -07:00
Martin Whitaker 88d845a612 Corrected tf_getlongsimtime() to match behaviour of other simulators.
The PLI tf_getlongsimtime() function is a non-standard function provided
for compatibility with some commercial simulators. To match the behaviour
of those simulators, it should return the raw simulation time, not a
scaled time.
(cherry picked from commit a3813c006d)
2011-10-16 16:36:44 -07:00
Cary R e47f18f79f When printing a Dec numeric value use the string size and the minimum size.
The vpiDecStrVal case for the get_numeric() function needs to use the
existing string width as the minimum result size. -1 can be represented as
a signed value with a width of 1. This gives a display width of -1 which
is too small for the -1 string value. This was creating valgrind issues.
In general the string value should be the minimum so this is a safe change.
(cherry picked from commit 5a9e4aaec7)
2011-10-16 16:34:52 -07:00
Cary R b7b2d710b1 V0.9: Free the iterator if there are extra arguments.
To avoid extra memory usage on error free the iterator if there are
extra arguments.
2011-10-16 16:33:09 -07:00
Cary R f874e81606 Remove two unused argument warnings
(cherry picked from commit dc2c67e25f)
2011-10-16 16:25:38 -07:00
Cary R 78d5b3f278 Update lxt_write and lxt2_write files from GTKWave
Update the lxt_write.[ch] and lxt2_write.[ch] files to the latest from
GTKWave. This is just comment changes.
(cherry picked from commit cff0deeacc)
2011-10-01 09:49:54 -07:00
Martin Whitaker fc8195fd61 V0.9 Remove more clang warnings.
clang warns that the yyinput function generated by flex is never used.
2011-09-25 10:23:41 -07:00
Cary R 4f2a41f186 V0.9: Remove clang/clang++ warnings.
This patch makes the code consistently use struct/class in the C++ files,
it removes a couple shadow warnings and where a class pointer is passed to
the C routines it defines the pointer as a class for C++ and as struct for C.
2011-09-25 10:23:34 -07:00
Alexander Klimov 5c6c8deba3 Fix long division.
On a 64-bit machine the following module shows incorrect division
results:

`define X {4'b 1000, `N'b 0}
`define Y {1'b  1, `N'b 0}
module b;
   reg [`N:0] y = `Y;
   reg [3:0] z1, z2;
   initial begin
      z1 = `X / `Y;
      z2 = `X /  y;
      $display("%3d %b %b", `N, z1, z2);
   end
endmodule // b

$ for N in {60..65}; do /usr/bin/iverilog -DN=$N -oa b.v && /usr/bin/vvp a; done
 60 1000 1000
 61 1000 1000
 62 1000 0111
 63 1000 0101
 64 1000 1000
 65 1000 1000

The first chunk of the patch (result -> tmp_result) fixes this:

$ for N in {60..65}; do iverilog -DN=$N -oa b.v && vvp a; done
 60 1000 1000
 61 1000 1000
 62 1000 1000
 63 1000 1000
 64 1000 1000
 65 1000 1000

The second chunk fixes

`define X 264'h 800000000000000000000000000000000000000000000000000000000000000000
`define Y 192'h c6df998d06b97b0db1f056638484d609c0895e8112153524
module c;
   reg [191:0] y = `Y;
   reg [72:0] z1, z2;
   initial begin
      z1 = `X / `Y;
      z2 = `X /  y;
      $display("%x %x %b", z1, z2, z1 == z2);
   end
endmodule // c

$ /usr/bin/iverilog -oa c.v && /usr/bin/vvp a
0a4c4a2c1dacd76220c 0809033397ca3427927 0

$ iverilog -oa c.v && vvp a
0a4c4a2c1dacd76220c 0a4c4a2c1dacd76220c 1
(cherry picked from commit 766bf45dcf)
2011-09-17 18:57:00 -07:00
Cary R 354abcc9bd V0.9: For MinGW driver report an error if the two \\ are not found in the exe path
We need to print a message and fail if the two \\ characters are not found
in the executable path.
2011-09-11 11:30:21 -07:00
Cary R 662e765dc5 V0.9: For MinGW report an error if the two \\ are not found in the exe path
We need to print a message and fail if the two \\ characters are not found
in the executable path.
2011-09-06 19:31:15 -07:00
Cary R 0af5b0b16e V0.9: Fix verinum negative comparisons.
For mixed sized negative operands the verinum comparisons were sometimes
returning the wrong value.
2011-07-19 20:22:50 -07:00
Cary R bfb1678dee V0.9: Fix incorrect function in tgt-stub/expression.c.
This fixes a bug where the unary expression code was using the incorrect
function to check to see if the data type was real.
2011-06-26 11:28:11 -07:00
Cary R a7645b2191 V0.9: Fix spacing issues. 2011-06-26 11:26:27 -07:00
Martin Whitaker ebfe869067 v0.9 fix for pr3296466.
The compiler was handling bi-directional pass switches using the default
case for primitive gates, where the first port is treated as an output
and the remaining ports are treated as inputs. This patch adds a special
case for pass switches, so that the first two ports are treated as
bi-directional.

This patch also reworks the tran island code to allow it to handle cases
where tran primitives cross-connect different bits of the same vector.
2011-06-12 17:50:15 -07:00
Cary R a59b778d75 V0.9: Always process specparams since they can be used outside a specify block.
The -gno-specify flag should only control the delay and timing checks.
It should not also remove the specparams since they can be used outside
of a specify block.
2011-06-04 10:58:34 -07:00
Martin Whitaker 9ac9f36e3c (V0.9) Modified rules for primitive gate port expression widths.
The IEEE standard states that the port expressions used for arrays
of primitive gates must be the exact width required, but is silent
about the requirements for single instances. The consensus among
other simulators is that for input ports of single instances, the
expression is silently truncated to a single bit.

This patch also fixes a compiler crash if an error is found when
elaborating a primitive gate port expression.
2011-06-04 10:54:23 -07:00
Cary R 409898eb3b Update fstapi.c to match the latest from GTKWave
(cherry picked from commit feba73119a)
2011-05-29 09:14:38 -07:00
Cary R 134bd22e0b V0.9: Report the correct gate port number.
The error message was reporting the error message as zero based
instead of one based.
2011-05-29 09:13:00 -07:00
Cary R 9e853b4c04 Fix bug in queue average with a very large number of entries.
Icarus is not actually fast enough to run into this issue in a
reasonable amount of time. I discovered this by thinking about
the algorithm and verified the fix with custom code.
(cherry picked from commit 35488ac254)
2011-05-29 09:11:28 -07:00
Cary R 95eec63579 V0.9: Fix spelling problem reported in pr3301924 2011-05-29 09:08:06 -07:00
Martin Whitaker 16db50bed6 Fix for pr3301924.
If a relative path name is passed to the Windows LoadModule function,
it is applied in turn to each path in the DLL search path. For the
ivl_dlopen function, we actually want to mimic the Unix behaviour,
where a relative path is relative to the current working directory.
On systems where the KB2264107 security fix has been applied, the
CWD is excluded from the DLL search path, so we no longer get the
required behaviour. This patch reworks the ivl_dlopen function to
give the correct behaviour under Windows.

This patch also adds a flush of the stderr stream after reporting
VPI call errors. This fixes a race between the stdout and stderr
streams when running the regression tests in a MinGW shell.
(cherry picked from commit 767bb87ee2)
2011-05-29 09:07:20 -07:00
Cary R 88bf49d692 V0.9: Properly terminate a snprintf() call.
snprintf() copies at most N characters, but the string may not be
terminated correctly. This patch uses sizeof() so that the snprintf()
call matches the size of the buffer and adds code to insert a NULL as
the last character of the string.
2011-05-07 11:49:51 -07:00
Stephen Williams 735a789f20 cfparse.y needs stdio.h
Based on patch subbmitted to sourceforge tracker by
Greg Steuck (gnezdo)
(cherry picked from commit c02d6953ef)
2011-04-27 11:18:55 -07:00
Stephen Williams dbbe27ebce fix bad declarations from previous patch. 2011-04-27 11:16:47 -07:00
Cary R d3f7e4f1e6 V0.9: Back port the down payment on const-correctness patch from Larry
This patch is a back port of the applicable changes made in the patch
originally submitted by Larry for development on (9/27/2010).
2011-04-27 11:11:08 -07:00
Cary R dfedd3dda1 Remove some OpenBSD time variable warnings.
Since time is a function OpenBSD does not like us using a variable
named time. This patch fixes that in the sys_queue.c file.
2011-04-27 11:09:37 -07:00
Cary R 8e4008ae19 $q_full should return x for an invalid id.
After some more thought I believe it is better for $q_full to return
'bx instead of 2 when $q_full is given an invalid id. This will make
the typical full/not full checks both return false. We still return
an error code in the status variable.
(cherry picked from commit 10b2310c52)
2011-04-20 18:21:23 -07:00
Cary R 323f12ebfd V0.9: Convert a single % at the end of a format string to %%.
If there is a single % at the end of a format string then automatically
convert this to %% so that we get a single % in the output.
2011-04-20 18:16:54 -07:00
Cary R a51ea8f3b2 V0.9: Add (back-port) the stochastic (queue) tasks/function.
This patch back-ports the stochastic tasks/function from
development. See the development branch patches for more
information.
2011-04-20 17:43:46 -07:00
Cary R 6f2fd4e169 V0.9: Fix a few problems with the power operator.
The power operator defines 2**-1 and -2**-1 to be zero. This patch fixes
both the procedural and continuous assignments to work correctly. It also
fixes a problem in the compiler power code so that the one constant value
always has at least two bits.
2011-04-20 17:40:09 -07:00
Stephen Williams 4c9853551c flex and bison handled in makefiles with variables
Greg Steuck submitted this patch.
2011-03-29 08:54:58 -07:00
Cary R 524544da2d Update the FST dumper to include the vpiDefName if it's unique.
This patch adds the vpiDefName for a module if it is different than
the vpiName. This will be used in a future version of GTKWave.
(cherry picked from commit 085a5c8d02)
2011-03-23 12:01:54 -07:00
Stephen Williams 90bad1a36c Prepare for 0.9.4 release. 2011-03-17 12:26:38 -07:00
Cary R 28ca2a42de v0.9: Remove the last version.h references 2011-03-17 11:53:38 -07:00
Cary R 7011019f2d V0.9: Add #! support for MinGW since newer shells support this. 2011-03-15 18:57:36 -07:00
Cary R ea78ae51c7 For an input report the expression is pruned vs padded.
There was a single message when the expression width was larger
than the port width. This patch makes it a bit more clear by
saying that the expression was pruned.
(cherry picked from commit 1fbe777c81)
2011-03-14 17:05:46 -07:00
Cary R 6b4de9aa82 A '$' is also allowed in identifier names (dumpers)
Update the dumper escaped identifier check to allow a '$'
character after the first character in a normal identifier.
(cherry picked from commit 2e0accf812)
2011-03-14 17:04:47 -07:00
Martin Whitaker b1b54ff531 Fix for pr3194155 (v0.9).
Currently the compiler coerces input ports to inout ports whenever
there is an internal driver connected to the internal port net.
This generates an error if the port is externally connected to
something other than a structural net. This patch modifies the
compiler to ensure port coercion only occurs in valid cases.
2011-03-14 17:00:56 -07:00
Martin Whitaker 9084c4aab1 Miscellaneous improvements and fixes to shift elaboration (v0.9).
This patch ensures that the result of a shift is an undefined value
if the right operand is an undefined value. It also improves the
code generated for right shifts where the right operand is constant
(which fixes the compiler crash on pr3098439b in the test suite).
2011-03-14 16:57:36 -07:00
Cary R 337eb3f8e7 V0.9: Fix spacing issues
Fix space before tab and space/tab before EOL.
2011-03-08 19:21:56 -08:00
Cary R b6223f39c9 V0.9: Don't normalize the port base (lidx) twice.
eval_part_select_() has already normalized the base number so don't
do it again.
2011-03-02 19:39:02 -08:00
Cary R 9d0e85afe1 V0.9: Don't delete L-value concat signals and give a better error message.
This patch removes the code that was deleting the signals in an L-value
concat if the concatenation failed to elaborate. This is incorrect since
the signal could be used in another context that is processed later. The
error message when an output/inout port fails to elaborate was also
improved to give the expression that is connected to the port.
2011-02-28 19:43:54 -08:00
Cary R 8de917347e V0.9: Allows multiple attribute instances.
This patch adds the ability to have multiple attribute instances
(e.g. (* foo = 1 *) (* bar = 2 *)).
2011-02-28 19:40:56 -08:00
Cary R cedee1137e Update fstapi files to latest from GTKWave 3.3.19
Update the fstapi.{c,h} file to match the latest from GTKWave.
(cherry picked from commit ed0469bac5)
2011-02-28 18:22:21 -08:00
Cary R 8ad73b013e The select not the original parameter get the file/line info.
When taking a variable part select of a parameter we need to
give file and line information to the select not the parameter.
(cherry picked from commit 0106578fb6)
2011-02-28 18:19:00 -08:00
Cary R 9d519ffa78 Don't include local signals in @* sensitivity list.
A locally created signal should not be included in the sensitivity
list created by @*.
2011-01-31 14:57:18 -08:00
Cary R 8841f81f51 V0.9: Add support for giving both strengths to a pull device.
In the standard a pull device can be given both a 1 and 0 strength.
Only the appropriate one is actually used. This patch adds support
for giving both pull strength to a pull device.
2011-01-31 14:53:19 -08:00
Cary R 3b89043f68 v0.9: Fix some bugs in task integer/real arguments.
This patch fixes the following problem in the compiler:

  An integer task argument should be marked as an integer port.

  An implicit register can be converted to either a reg or an integer.

  An old style task port should default to <no type> unless reg or some
  other type is provided. ANSI style is always defined. For example:
    input ri;
    output ro;
    inout rio;
    real ri, ro, rio;
  should define all three task ports to be of type real.
2011-01-31 14:43:38 -08:00
Cary R d08d7d8858 Keep nulls in a verinum and keep as string when padding is mod 8.
For diagnostics and to know what is really going on in the compiler
we need to keep any NULL that is in a verinum string or when
displayed as/converted to a string.

When padding a verinum string if the padding is in multiples of eight
then keep the string property.
(cherry picked from commit dc17190f4d)
2011-01-18 17:15:39 -08:00
Cary R 6336432461 is_cell needs to be defined for root scopes.
This patch fixes a small bug found with the vlog95 back end. A root scope
should define is_cell instead of leaving it undefined. Normally I would
expect a root scope to not be a cell, but I don't think the standard
prohibits this from happening, so copy the value from the definition.
(cherry picked from commit 1a1b0d7551)
2011-01-18 17:14:21 -08:00
Cary R b67ee0f1e8 Add a vpath for the local lexor_keyword.cc
This patch doesn't completely fix the problem, but with it the problem
is at least manageable. The issues was that when the lexor_keyword.gperf
file is updated and you are building outside the source directory the
Makefile would create a local lexor_keyword.cc as expected. The problem
is that it always looked in the source directory for the file. This
patch adds a special vpath rule that says to look in the build directory
first and then in the source directory for lexor_keyword.cc.

This works as expected except for the first time the lexor_keyword.cc
file is generated locally. During the make invocation it compares the
source lexor_keyword.cc file to the gperf file and notices it is out of
date. It then generates a new file in the build directory, but the make
rule is still using the source file which didn't change so it doesn't
rebuild as needed. To get the new file to compile you need to run make
a second time to get the rule to execute using the local version of the
file. This extra make invocation is only needed when the local file is
first created since after that the rule always uses the local file.

I plan to look at resolving the remaining issue, but there is much
subtlety in this since you effectively need to break/rebuild the make
dependency tree to get this to build correctly in a single run.
(cherry picked from commit e67dcf5216)
2011-01-18 17:12:29 -08:00
Cary R 1c8f00e90d V0.9: Fix the display of characters with the MSB set (cast to unsigned char).
When a verinum is displayed as a string we need to make sure that any
character that will be displayed as an octal constant must be converted
correctly. Also change to isprint() instead of isgraph() since it is the
same as isgraph() plus a space.
2011-01-12 16:32:08 -08:00
Cary R 5a536b88c9 V0.9: Add a warning that ifnone with an edge-sensitive path is not supported.
Cadence allows an ifnone with an edge-sensitive path. Until we understand
exactly what this is and how to implement it this patch adds a warning
that an ifnone with an edge-sensitive path is not supported.
2011-01-12 16:08:13 -08:00
Cary R f1cfd624cb V0.9: Update some warning messages
Update some of the tgt-vvp warning messages.
2011-01-12 16:03:14 -08:00
Cary R e5e2acfd24 Update fstapi.{c,h} files to match GTKWave 3.3.17.
The files generated after this patch is applied are not backwardly
compatible with older versions of the API.
(cherry picked from commit 25c1795fb7)
2010-12-02 16:17:12 -08:00
Cary R 3f7d635afd V0.9: Fail if the user defines a real variable as a vector.
Using reg real [1:0] var you can define a real variable with a
range. This was crashing the run time. This patch catches this
in the compiler and prints an appropriate message.
2010-11-25 09:34:25 -08:00
Larry Doolittle 8c1b5be360 fix boring C lint in header
With warnings turned sufficiently high in gcc, I get:
  .../vpi_user.h:568: warning: function declaration isn't a prototype
when building VPI modules.  Patch is trivial.
(cherry picked from commit 186779c29b)
2010-11-25 09:10:40 -08:00
Cary R 2e4810ac8a V0.9: Assert if the vcdid overflows.
It should never happen, but if it does assert vs generating an
invalid VCD identifier.
2010-11-25 09:08:25 -08:00
Cary R f7e0f622fa V0.9: Update fstapi.c to match GTKWave 3.3.15 release 2010-11-25 09:07:01 -08:00
Cary R 15bff3a23b Ignore system tasks/functions NULL arguments in @* calculation.
System tasks and functions can be defined to have NULL arguments.
This patch makes the @* sensitivity list calculation skip these
NULL (constant) arguments.
(cherry picked from commit 9477154e5b)
2010-11-25 09:03:59 -08:00
Cary R 8dea333521 V0.9: Ignore COND in SDF timing check back annotations
When back annotating from a SDF file we already ignore timing checks so
we may as well ignore the COND statement that can be used with them.

Also update a few other changes from development.
2010-11-25 09:00:33 -08:00
Cary R 709a076ecf V0.9: Handle escaped characters in a SDF identifier.
This patch adds the ability to parse a SDF identifier that contains
escaped characters.
2010-11-25 08:57:18 -08:00
Cary R 9a826152a6 V0.9: Add support for passing -0.0 to vvp. 2010-11-18 17:00:17 -08:00
Cary R 3612e53f7c V0.9: Add support for taking ! of a constant real value. 2010-11-18 16:51:51 -08:00
Cary R c88caa764d Another GTKWave file update,
(cherry picked from commit 1ce595da2b)
2010-11-09 17:08:17 -08:00
Cary R 1c8e191918 V0.9: back port fixes from development.
This patch back ports some fixes from development. It adds the ability
to do signed === and !== correctly, adds support for && and || of real
values in eval_tree and fixes an obscure bug in t-dll.cc.
2010-11-09 16:40:50 -08:00
Cary R 29a69bacd0 Update GTKWave files to the latest from GTKWave CVS.
This update fixes a rare bug in the FST file creation process along
with a general sync of the files.
(cherry picked from commit a359cc301c)
2010-11-02 11:30:53 -07:00
Cary R 09b80051bd V0.9: Add probe_expr_width() for specparam value.
This patch adds a call to probe_expr_width() before a specparam
value is evaluated. This calculates the expression type/width.
2010-10-06 15:21:40 -07:00
Cary R 87cd9a89e0 V0.9: Resize an unsized signed constant if it is less than integer_width.
An unsized signed constant that is smaller than integer_width needs
to be resized up to either the integer_width or the expression width
whichever is smaller.
2010-10-06 15:18:13 -07:00
Stephen Williams 213b687563 Edit missed version_base.h version stamp 2010-09-27 10:42:32 -07:00
Stephen Williams 248924f64b Clean up for v0.9.3 2010-09-27 09:10:42 -07:00
Stephen Williams c7d1bf5d6a Updated Mingw build instructions from Martin. 2010-09-27 09:07:34 -07:00
Cary R 85ebc1162b Remove MinGW shadow warning.
Remove a shadow warning in a MinGW specific code block.
2010-09-24 15:37:46 -07:00
Larry Doolittle 20f78515c8 Spelling fixes
All fixes are in comments, except for one error message (was "iternal error")
2010-09-22 13:42:55 -07:00
Cary R 01ad32e375 Update fstapi.c to the latest from GTKWave-3.3.12
(cherry picked from commit 0dad9e3adb)
2010-09-22 09:16:20 -07:00
Cary R 04b9cf5715 v0.9: Fix signed/unsigned compare warnings.
Fix all the Icarus files that can be so that we do not have any
signed/unsigned compare warnings. It also removes const as a
return qualifier for two routines in discipline.h.
2010-09-22 09:14:39 -07:00
Cary R 633006bc6e V0.9: Pad and sign convert array index expressions as needed.
This patch mimics what was done for vectors, but is simpler since
arrays don't use the endian information. It also needs to address
the fact that .array/port assumes the expression is unsigned so
any signed expression must be padded to make it larger than the
maximum array word when it is converted to unsigned.
2010-09-19 13:52:28 -07:00
Cary R e6b04cc5d0 V0.9: Normalize variable bit/indexed part selects using a fixed routine.
This patch modifies all the variable bit and indexed part selects
to use a common routine. This routine determines the minimum
width needed to calculate the result correctly, pads the expression
if needed and then converts the expression to signed if required to
make the calculation correct.
2010-09-19 13:52:20 -07:00
Cary R 3333a5e520 Fix generation of PS files and hence PDF files on cygwin.
The Cygwin man command requires that you have a / in the path
if you want to avoid looking at the normal search path. This
patch addes ./ before the manual page file name. Which should
work on any system. It also makes the vvp generation create a
PS file like is done in the other Makefiles.

By default we generate normal manual pages. You can then
create PostScript version and from these you can generate a
PDF version.
(cherry picked from commit 5ae3e48cdb)
2010-09-19 13:50:52 -07:00
Cary R f4bec3b713 Resize constants in eval_expr when needed.
If we are given an unsized constant that is smaller then the requested
width then resize the constant to fit.
(cherry picked from commit acb55916da)
2010-09-13 16:19:09 -07:00
Cary R cc024fde2b V0.9: An if statement is optional and results in no delay.
While checking for an infinite loop in an always block I missed
the case where an if statement does not have a statement. This
was resulting in a segmentation fault.
2010-09-13 14:07:56 -07:00
Martin Whitaker 0a94253261 Fix for pr3064375.
The search for similar events, used to elide duplicates, was ignoring
the event edge sensitivity. This allowed events that should have been
triggered on different edges of the same signal to be merged.
2010-09-12 09:17:10 -07:00
Stephen Williams d46b6cdcbb git ignore emacs backup files. 2010-09-12 08:59:46 -07:00
Stephen Williams 008082c8cb Clear up compile warning on gcc44 compilers. 2010-09-12 08:59:19 -07:00
Cary R 64d713dd6d Don't elide unconnected module ports.
When performing a translation we do not want to elide any module
ports. Dropping ports can result in port mismatch issues.
(cherry picked from commit b252dc0192)
2010-09-10 17:56:49 -07:00
Cary R 97a3bf5aeb V0.9: Report and fail gracefully for recursive parameter definitions.
If someone accidentally makes a parameter depend on itself
we need to report this not crash. This patch fixes the crash
and prints an appropriate string of messages to figure out
the loop. Icarus currently supports forward references of
parameters so more complicated loops can be created. These
are also caught.
2010-09-08 17:12:04 -07:00
Cary R 7c4d07bda6 V0.9: Warn the user that synthesis is no longer maintained.
Add code to print a warning if the user tries to use the -S flag.
We need this warning since synthesis is not currently being actively
maintained or supported in any branch after V0.8.
2010-09-04 16:40:23 -07:00
Patrick Doyle a45aa9f37a Keep expression width when evaluating expressions ahead of time.
Added 'expr_wid' parameter to calls to 'eval_expr()' within
PEBinary::elaborate_eval_expr_base_()'.  This makes a specific problem
go away and may even be the correct thing to do.
(cherry picked from commit 2ffc2d36f2)
2010-08-19 17:33:47 -07:00
Stephen Williams 46b45daea8 Fix broken search for similar events.
The search for similar events, used to elide duplicates, was easily
confounded by duplicate pins connected to a probe. This caused the
similarity count to get messed up, and bad things happened. Change
the method to use set comparisons instead.
2010-08-18 20:52:43 -07:00
Stephen Williams 2ab2ff6b72 Add $info, $warning and $error as aliases to $display
Submitted by [email protected]
2010-08-06 21:38:20 -07:00
Cary R 3c2e4a3a7b Update fstapi.c to latest from gtkwave 3.3.10
(cherry picked from commit 44b08a4630)
2010-08-06 21:34:42 -07:00
Cary R 39b91f604a V0.9: Cleanup some compiler warnings under CentOS 5.5
This patch cleans up a couple of warnings when compiling on CentOS 5.5
using gcc 4.1.2.
2010-08-06 21:31:19 -07:00
Cary R c09b4035da The switch gates do not support a strength specification.
This patch splits the switch types out of the gates to allow
them to be defined to not take a strength specification.
(cherry picked from commit df4722b92c)
2010-08-06 21:26:35 -07:00
Cary R 6c996c1056 V0.9: We have already verified that we have a 64 bit immediate value.
These checks are not needed since we have already verified that
we have a 64 bit immediate value. This is likely old code that
should have been removed when the original functionality was
changed.
2010-08-06 21:18:23 -07:00
Cary R 9d6d9fd9d6 V0.9: Add unlimited tail recursion for the real ternary operator.
This patch modifies the real ternary operator code to support
unlimited tail recursion without overflowing the thread
registers. Head recursion is still limited by the available
registers.

It fixes the thread word checks to use a new define that has
the correct number of thread words (16). It adds a message
instead of just an assert if the thread words are exhausted.

And it also changes some of the error messages to use vvp.tgt
in the message to be consistent with the other messages.
2010-08-06 21:10:57 -07:00
Cary R 86f4e9560e V0.9: Only set the multiply width if it is greater than zero and vectorable
We only need to set the width of a multiple if the width is greater
than zero and if the expression is vectorable. This matches what is
done for addition.
2010-07-06 20:20:10 -07:00
Cary R 1e06094d1d Update fstapi files to match the GTKWave 3.3.8 release.
This patch updates fstapi.{c,h} to match the ones in the GTKWave
3.3.8 release.
(cherry picked from commit ed29161614)
2010-07-06 20:19:05 -07:00
Cary R 8e9c282ed4 V0.9: Fix some on error memory leaks in vvp.
This patch modifies the vvp main code to cleanup if there was an
error compiling the input file. There are still a few issues, but
this takes care of most of them.
2010-06-18 16:04:17 -07:00
Cary R 4a7bab0813 V0.9: On error there is no need to pop the scope.
The error routines for task and function definitions were incorrectly
popping the scope. This should not be done since no scope was pushed.
Also assert that the current_task/function is 0 to catch that kind of
error like the other definition rules.
2010-06-18 16:02:37 -07:00
Cary R b2fd383d05 V0.9: Fix shadow warnings found on OpenBSD.
gcc on OpenBSD reported shadow warnings for variables, arguments named
log, time and exp. This patch renanes those variables to logic, timerec
and expr.
2010-06-18 16:01:10 -07:00
Cary R 34c34e33cf V0.9: back port of SunPro compiler support.
This patch combines all the changes needed to back port support for
the SunPro compilers to the stable branch.
2010-06-18 15:57:52 -07:00
Cary R 22faa019d1 Update fstapi.c to match latest from GTKWave.
(cherry picked from commit 263dff6fbe)
2010-06-11 17:40:23 -07:00
Cary R 1f35d57854 V0.9: Fix int/long warning. 2010-06-11 17:38:46 -07:00
Cary R a916f8e34e V0.9: Cache vpi_call error messages so we can include file and line info.
This patch caches the vpi_call error messages (task/function does
not exist, task being called as a function and function being
called as a task). This allows us to display the file name and line
number information for the invalid usage.
2010-06-11 17:38:39 -07:00
Cary R 6d56e356b4 Don't crash when using define value for an include argument.
When pushing the current file path we need to get past any `define
expansions that have been pushed onto the stack to find the real
file path.

This patch is partially based on a patch submitted by Steve Tell.
(cherry picked from commit b2d479eaf6)
2010-06-11 17:36:57 -07:00
Cary R e11f4cf69e Don't crash if parameter/localparam defined from constant user function.
This patch avoids a crash when trying to use a parameter/localparam that
has been assigned a value from a constant user function. Icarus does not
currently support constant user functions so it creates a parameter with
a NULL value. This patch fixes a few places where this could crash the
compiler.
(cherry picked from commit 3f203c4363)
2010-06-11 17:35:41 -07:00
Cary R 597c3da220 V0.9: Fix shadow warnings add -Wshadow and update Makefile.in for SunPro
This patch combines a couple of things from the development patch.
It adds the -Wshadow flag and updates all the Makefile.in files to
support the gcc or SunPro compiler. It also fixes all the shadow
warnings. For the most part this is a copy of few patches from
development.
2010-06-11 15:56:48 -07:00
Cary R d165f32113 Add escaped identifier support to the FST dumper and some clean up.
This patch adds escaped identifier support to the FST dumper and
cleans up the VCD and FST code a bit. Also a simple spelling fix.
(cherry picked from commit 3fe68c4c04)
2010-06-11 15:55:04 -07:00
Cary R 5d320760eb Fix memory leak on error in driver/main.c.
(cherry picked from commit 09d59d744d)
2010-06-11 15:52:21 -07:00
Stephen Williams 1a725e063b Remove malloc.h support and for C++ files use <c...> include files.
The functions (malloc, free, etc.) that used to be provided in
malloc.h are now provided in cstdlib for C++ files and stdlib.h for
C files. Since we require a C99 compliant compiler it makes sense
that malloc.h is no longer needed.

This patch also modifies all the C++ files to use the <c...>
version of the standard C header files (e.g. <cstdlib> vs
<stdlib.h>). Some of the files used the C++ version and others did
not. There are still a few other header changes that could be done,
but this takes care of much of it.

(Cherry-picked from 1993bf6f69)
2010-06-01 11:27:16 -07:00
Cary R 21aec4d995 Remove OpenBSD compilation warning.
This is a trivial change to remove a warning when compiling using
the latest version of OpenBSD.
(cherry picked from commit 8122432e47)
2010-06-01 11:00:18 -07:00
Cary R fbaecdff87 V0.9 back port of dumpers only sort scope list when needed.
We need a slightly different patch for V0.9 than development. The fst
patch already has this change and the lxt2 file in V0.9 also needs
this change. See the development patch for more information.
2010-06-01 10:57:58 -07:00
Cary R a346507e93 V0.9: add fst dumper support.
This patch adds fst dumper support just like was done for development.
These changes match the latest code for development except V0.9 does
not currently support returning a value from vpi_register_systf() and
it does not support vpip_make_systf_system_defined(). If these are
added sys_fst.c will need to be updated.
2010-06-01 10:57:49 -07:00
Cary R 7af35ed08f Fix config.h.in HAVE_ALLOCA_H and HAVE_FSEEKO defines
This patch fixes the config.h.in file to correctly undefine
these two defines so that configure can define them when
available.
(cherry picked from commit 5a6683197a)
2010-06-01 10:52:42 -07:00
Cary R 632a1b8024 Fix some large/negative immediate value compiler bugs.
Fix how immediate values are checked and allow a large negative
value to be returned from get_number_immediate().
(cherry picked from commit 7969a58eeb)
2010-06-01 10:13:30 -07:00
Cary R 743d16ce60 Fix lxt2 space/speed flags.
The lxt2 routine was referencing the lxt not the lxt2 versions
of the space/speed flags. This also adds the lx2 version of the
flags. These were already supported in the sys_table.c file.
(cherry picked from commit f268af3580)
2010-05-21 17:30:05 -07:00
Cary R 644610828e lxt_write.c and lxt2_write.c reference <config.h> not "vpi_config.h"
Since the base lxt_write.c and lxt2_write.c files reference <config.h>
instead of "vpi_config.h" all their definitions need to be moved to
the main config.h include file.
(cherry picked from commit 3f433b325f)
2010-05-17 20:57:47 -07:00
Cary R afd18466cc Update lxt_write.c to fix OpenSolaris compile warning.
(cherry picked from commit ffa1f1139b)
2010-05-13 19:08:34 -07:00
Cary R bda4a30847 Update lxt_write.c and lxt2_write.c to latest files from GTKWave.
These files were updated based on a patch I sent Tony.
(cherry picked from commit c8d160a007)
2010-05-13 18:50:04 -07:00
Cary R d3f60a2a98 $dist_erlang needs to use rtl_dist_erlang.
The erlang distribution calltf routine was incorrectly using the
normal distribution.
(cherry picked from commit 26b95b94f7)
2010-05-03 15:34:57 -07:00
Cary R c781db5779 Remove bitchar_to_idx() function in tgt-vvp/vvp_process.c
This function is no longer used and was likely replaced with a
different scheme, so serves no useful purpose.
(cherry picked from commit 8dfe9961c8)
2010-05-03 15:33:02 -07:00
Cary R c36e1f0703 tgt-stub/memory.c is no longer needed/valid
The tgt-stub/memory.c file is not used and uses an obsolete ivl
interface so it serves no useful purpose.
(cherry picked from commit 6451523f73)
2010-05-03 15:28:44 -07:00
Cary R eed962c787 Update lxt_write.h and lxt2_write.h from GTKWave
This patch updates the lxt_write.h and lxt2_write.h header files
to the latest ones from GTKWave CVS. It also adds HAVE_INTTYPES_H
to the vpi_config.h.in header.
(cherry picked from commit bf54c838a6)
2010-05-03 15:24:55 -07:00
Cary R 385b211851 V0.9 - Don't free a NULL iterator in $dumpvars.
This patch fixes two places where Icarus under certain conditions
would try to free a NULL iterator value in $dumpvars(). $dumpvars()
can have a NULL argument to indicate that all variables should be
dumped. Under two error conditions the code was trying to free
this NULL argument reference.

The standard does not define if vpi_free_object() can support a
NULL reference. Icarus does not currently allow it (it asserts).
2010-05-03 15:22:00 -07:00
Cary R 7a363625d4 Add support for bit <-> real conversion for output ports.
This patch adds support for converting bit based ports to real signals.
You can only do this for single instances. Arrayed instance would
create multiple instances driving the same real signal.

Any real port can be connected to a bit based signal. The only limitation
is that the signal width must be an integer multiple of the instance
count since all the real conversions must have the same width.

Also add an error message for an arrayed instance with real to real
output connections. Again multiple drivers.

This patch also adds errors for inout real and bit based inout ports
driving a real signal. There is no logical way to deal with the full
capabilities of inout and real ports/signals. So for now they are not
allowed.
(cherry picked from commit e0001de3ba)
2010-05-03 15:18:02 -07:00
Cary R d614a81b2b Remove obsolete VAMS $log function.
This patch remove the old VAMS $log function. It could create confusion
with the Verilog $log task. Recent versions of VAMS and 1364-2005 use
$log10 for the base 10 logarithm.
(cherry picked from commit 2eb01605b1)
2010-05-03 15:09:16 -07:00
Stephen Williams 8ac5412a35 Account for unsized arguments to comparisons.
Comparison expressions have sorta-self-determined arguments.
Handle the special cause that some of the arguments may be
themselves unsized, and so expecting to be even wider then
otherwise.
(cherry picked from commit c4098cffdf)
2010-04-27 12:02:15 -07:00
Cary R c56b31c632 V0.9 Remove some gcc-4.3.4 warnings (Cygwin)
The latest gcc with the latest Cygwin complains when passing a char to
the toupper, tolower, isspace, isalnum, isprint, isdigit or isalpha
functions/macros. These functions are defined to take an integer. This
patch adds cast to int as needed to remove the warnings. After this
there are still two warnings related to a signed/unsigned comparison
in yy_get_next_buffer() (part of flex).
2010-04-14 13:12:31 -07:00
Cary R 2b63da8920 Fix thread modulus code to sign extend correctly.
When the width of a long long match the vector width we do not need
to sign extend and using the << operator for this case is undefined.
(cherry picked from commit 23a1ec9f53)
2010-04-14 13:09:22 -07:00
Cary R dbcbaab847 Fix a comment typo
(cherry picked from commit 6f9e364dab)
2010-04-14 13:08:13 -07:00
Cary R b7cba671ba Do not search up for a symbol if a hierarchical path was given.
When searching for a symbol we do not want to search up the
hierarchical stack if the symbol we are searching for was
prefixed with a hierarchical path.
(cherry picked from commit 3aaacd4c79)
2010-04-14 13:01:17 -07:00
Cary R 65ba9c3bf5 Set negative absolute SDF delays to zero.
The SDF standard allows negative absolute delays, but simulation
tools cannot handle this so set negative delays to zero.
(cherry picked from commit 301bbe94a0)
2010-04-02 17:15:01 -07:00
Cary R a0681e580f The SDF timing spec list can have zero or more elements.
The SDF file format supports zero or more timing specs. Previously
the parser was one or more. Things like tie high/low cells do not
have any delay information so zero or more is needed and matches
the standard.
(cherry picked from commit 68b1273d2d)
2010-03-30 11:33:59 -07:00
Cary R 855daae00f Fix line number error with to end of line comments.
The single line comment "//" was getting double counted.
(cherry picked from commit cbce1ddc04)
2010-03-30 11:33:41 -07:00
Cary R 4ee4d735c3 Use WIN32 instead of CYGWIN in tgt-null
(cherry picked from commit 99eac44ad1)
2010-03-25 12:49:21 -07:00
Cary R 6da47b1eba Perform bit <-> real conversions for module inputs.
This patch makes the compiler perform either bit to real or
real to bit conversion when needed on module input signals.
(cherry picked from commit 8e69764834)
2010-03-25 12:46:14 -07:00
Cary R baa3352ef1 vpi_get_value should return an appropriate value during compiletf.
The vpi_get_value() function should not crash when called during
the compiletf phase. This patch fixes this by returning 'bx for
any vectors in thread space. It also fixes some other minor things
that my test code uncovered. Most of the other objects work as
expected.
(cherry picked from commit bc7a5a9725)
2010-03-25 12:42:39 -07:00
Cary R 059068f070 Ignore zero replication constants.
This patch enhances elaboration to drop/ignore zero replication
count constants. Not doing this was causing problems later in
the compiler. We still pass non-constant expressions since
both user and system functions must be run for their possible
side effects. Constants can never have a side effect so just
dropping them is acceptable.
(cherry picked from commit 9a94d55738)
2010-03-22 18:11:58 -07:00
Cary R 53c206f2c5 Fix space issues.
(cherry picked from commit 2a463f00b3)
2010-03-22 18:10:50 -07:00
Cary R 19858807fe Add scope information for named blocks (begin/fork).
This patch adds the appropriate scope changes to get the scope
information correct for named blocks.
(cherry picked from commit 440cbba1d6)
2010-03-22 18:07:54 -07:00
Cary R 1c03cdafaf Fix trailing garbage in previous patch .
(cherry picked from commit 9cbb9251b4)
2010-03-16 15:51:52 -07:00
Cary R e3b16d72a3 NB-assign needs to convert reals at the l-value width.
This patch mimics what was done for normal assignments to get the
width correct for nonblocking assignments when converting a real
r-value to a l-value vector.
(cherry picked from commit d5c10af4f4)
2010-03-16 15:51:38 -07:00
Cary R 86fad34813 Make taking an edge of a named event an error.
A named event does not have an edge so taking a posedge or negedge
is illegal. This patch adds an error message for this. Before the
edge was being ignored for named events, but this is incompatible
with other tools.
(cherry picked from commit 4af24b6b9e)
2010-03-16 15:48:34 -07:00
Stephen Williams 73a9880417 Fix broken $() substitution in command files.
(cherry picked from commit 8d65d0735a)
2010-03-16 15:24:26 -07:00
Cary R 5680dec04c Add missing strtoul argument
The previous patch missed this some how. I don't know how it compiled
correctly before!
(cherry picked from commit 08d0337e50)
2010-03-08 14:58:30 -08:00
Cary R d14c3449e4 Ignore bit selects in SDF INTERCONNECT lines.
Icarus does not support interconnect delays so INTERCONNECT is
currently ignored. The SDF parser does not currently support a
bit select as a port_instance. Since we are already ignoring
the INTERCONNECT I added support for bit selects there. This
is probably the most common place to find them.
2010-03-08 14:57:07 -08:00
Stephen Williams 526b114d18 Minor fixes to README.txt file.
(cherry picked from commit b48b833dab)
2010-03-05 16:03:23 -08:00
Martin Whitaker 1e09352f11 Fix for pr2943394 (v0.9 branch).
This patch fixes the behaviour when a variable or net is released
when it is not currently forced.
2010-02-10 17:23:42 -08:00
Martin Whitaker 7363e4326d Fix for LXT/LXT2 output using MinGW.
When using MinGW, routines registered via atexit() inside a
DLL are only called when the DLL is detached. If not detached
manually, DLLs are automatically detached *after* all remaining
open files are closed. This meant that by the time the LXT or
LXT2 close_dumpfile routine was called, the dump file handle
was no longer valid, so any remaining output was lost. This
patch fixes the problem by manually detaching the VPI modules.
(cherry picked from commit 4818db887e)
2010-02-10 17:21:14 -08:00
Stephen Williams 90144cfb3c Merge branch 'v0_9-branch' of ssh://[email protected]/~steve-icarus/git/verilog into v0_9-branch 2010-02-03 09:00:13 -08:00
Cary R 971576589e Fix some MinGW compile warnings.
This patch fixes some compile warnings found using the latest
MinGW compiler.
2010-02-02 21:00:56 -08:00
Alan M. Feldstein 65744da19c Use appropriate makefile dependencies option for Sun Studio 12 C++ compiler. 2010-02-02 20:56:03 -08:00
Alan M. Feldstein dec724b8f3 Not all C++ compilers recognize (or need) -Wall. 2010-02-02 20:50:21 -08:00
Alan M. Feldstein 24355dae67 Not all C compilers recognize (or need) -Wall. 2010-02-02 20:49:50 -08:00
Cary R c337b0ef0c Fix an obscure memory leak and fix formatting.
This patch fixes an obscure memory leak and make the formatting
of these two routines match the rest of the code in the file.
(cherry picked from commit 7866e92761)
2010-01-25 14:56:25 -08:00
Martin Whitaker 8fc049eefd Fix for pr2922063.
When handling the $signed/$unsigned system functions, the compiler
was applying the new signed/unsigned property to the NetExpr object
representing the input argument. This caused the input argument to
be evaluated incorrectly. This patch fixes this by applying the new
property to the NetExpr object created to pad the result to the
required size.

In testing this fix, it was also discovered that the width of the
input argument expression was not being calculated correctly. This
patch also fixes this issue.
(cherry picked from commit 14b2037ce4)
2010-01-25 14:49:11 -08:00
Nick Gasson 2be20d49ed Fix build with gcc-4.5
New version of GCC does not like the X::X() construct.
(cherry picked from commit b855b0368d)
2010-01-25 14:47:04 -08:00
Cary R 03411aba85 realloc() to the correct string.
Someone had mistyped the destination of the realloc. It should
have been the original string not the input buffer.
(cherry picked from commit 6eb5f593f0)
2010-01-25 14:44:38 -08:00
Martin Whitaker 70d2f7e353 Fix for pr2929913 (v0.9 backport).
After changing an array word, vvp propagates the change to every port
attached to the array. The code did not properly handle the case of
an array port declared in an automatic scope with an associated array
declared in a static scope.
2010-01-25 14:41:54 -08:00
Cary R c03aed2b17 Fix some constant bit/part select bugs and add warnings.
This patch fixes a few bugs in constant bit/part selects and
adds optional warnings for out of bound or undefined selects.
(cherry picked from commit 5a0363ebd3)
2010-01-25 14:37:10 -08:00
Cary R 2d1b8e4c81 Add +timescale to the command file.
This patch adds a +timescale command to the command file
syntax that can be used to set the default time scale of
the simulation.
2010-01-25 14:32:59 -08:00
Cary R 9afa95dff7 A signal select is signed if the select not the signal is signed.
The padding for a signal select was using the signal to determine
if the padding should be singed or not. In reality this should be
unsigned padding unless the select was enclosed in a $signed().
(cherry picked from commit 458258d554)
2010-01-09 11:43:43 -08:00
Cary R 2718f85222 vpi_get_vlog_info should return the version information.
This patch fixes vpi_get_vlog_info to return the VERSION.
(cherry picked from commit ea4bae7c33)
2010-01-09 11:40:15 -08:00
Stephen Williams a08de693d4 Step to the 0.9.2 release.
Advance version stamps.
2009-12-30 08:45:06 -08:00
Stephen Williams 37837f3904 Fix references to version_base.h in Makefiles.
(cherry picked from commit d2dd0daa3c)
2009-12-28 09:50:34 -08:00
Cary R daa01a05d8 A constant real number is not unsized.
We can have unsized bit values, but reals always have a size.
(cherry picked from commit ebac088511)
2009-12-28 09:34:57 -08:00
Cary R 9cd7a22dbe Having lround() does not mean llround() is available.
We need to check for both lround() and llround() for at
least Cygwin.
(cherry picked from commit a1e2bfc93c)
2009-12-25 18:16:52 -05:00
Martin Whitaker f733030b41 Add warning about casting large integer values to reals.
The compiler and vvp runtime don't correctly handle casts to reals
when the source value is more than 63 bits in magnitude. This is
fixed in devel, but can't be backported to v0.9 because it adds new
vvp instructions. This patch causes the compiler to output a warning
about potentiall incorrect results.
2009-12-25 17:53:08 -05:00
Martin Whitaker 99f7d1197c Make vvp thread word storage consistently 64 bits (backport to v0.9).
The vvp thread word storage had previously been changed to always store
64-bit values, but some instructions still only operate on native long
values. This patch ensures all instructions that modify thread words
support 64-bit values.
2009-12-25 17:51:56 -05:00
Cary R 7817e479a4 V0.9 - Add suffix support for windows (both MinGW and Cygwin).
dlltool which is used by both MinGW and Cygwin to create dynamic
libraries must have the name of the executable it creates the
library/information from exactly match the installed executable
name. If we have a suffix then it must be used. This patch adds
that to the build process for vvp since it can be installed with
a suffix. It also modifies the check routines since you must run
vvp with a suffix if the library it links to was built for a
suffixed executable.
2009-12-25 11:53:36 -05:00
Cary R 0c97cabe18 Use the correct line information in crop_to_width()
This was using its own information instead of the input nets information.
2009-12-25 11:37:50 -05:00
Cary R e56c142dff Reuse the number of input information.
This was already assigned to a variable so lets use that instead of
geting it again.
2009-12-25 11:37:35 -05:00
Cary R 7e06a87b8e Properly extend/crop a user function argument in a continuous assignment.
When passing an argument to a user function in a continuous assignment
we need to sign extend the value if it is signed and too short. We need
to crop an argument if it is too long.
2009-12-25 11:37:16 -05:00
Cary R 0c3eef4c41 Function arg. expressions need to use the expr. width and arg. width.
When evaluating a function argument expression we need to use either
the expression width or the argument width which ever is larger. This
matches the way normal assignments work. We then only take the bits
needed at the end.
2009-12-25 11:33:12 -05:00
Cary R 3b22be5507 A ternary can be signed.
If the two branches of a ternary are signed then the result will
also be signed.
2009-12-25 11:28:03 -05:00
Nick Gasson 287b19f22d VHDL: fix spurious resize seen in pr2911213
Another case when ivl_scope_sig list was used instead of
ivl_scope_param.
2009-12-25 11:26:46 -05:00
Cary R 8de7fc6161 Add suffix support to MinGW.
This patch adds suffix support to the relative path that MinGW
calculates in both the iverilog and vvp executables.
2009-12-25 11:22:25 -05:00
Cary R 663ab34ae7 V0.9 Add casts/etc. in vvp directory to remove Cygwin compile warnings. 2009-12-15 07:29:06 -08:00
Cary R b5c819051b Fix out of bounds select warning text in man page.
(cherry picked from commit 8144283b0d)
2009-12-15 07:26:12 -08:00
Cary R fdbc212349 Fixe .cast documentation.
(cherry picked from commit a228d53cc2)
2009-12-15 07:24:42 -08:00
Nick Gasson d35d542b9e VHDL: ensure with-select statement choices completely cover input space
Newer versions of GHDL seem to be stricter when checking this than
older versions. ModelSim still accepts an incomplete with-select,
however.

This patch makes the output 'U' if none of the conditions match.
(cherry picked from commit 9c568d8f47)
2009-12-15 07:22:26 -08:00
Cary R 8139551908 Add CFLAGS to vvp/Makefile.in
We do have one C program in the vvp directory so add CFLAGS to
the Makefile. This patch also modifies the two local programs
tables and version to use -Wall.
(cherry picked from commit 1a25b3deda)
2009-12-12 08:36:02 -08:00
Nick Gasson 021ae6c08f VHDL: emit function parameters in correct order
The function draw_scope was extracting the input/output parameters
just by looking at the (unordered) list of signals in the function
scope rather than using the ivl_scope_ports list.
(cherry picked from commit a9c85cf5b6)
2009-12-12 08:34:47 -08:00
Cary R b8b1bc4a36 Add some casts in libveriuser to remove warnings.
The Cygwin compiler is a bit picky. This patch adds some casts
to remove compilation warnings. In the past I have had warnings
off because of problems with the STL, but for C directories
like this it makes sense to enable the warnings. It also does
not recognize that an assert(0) or assert(false) ends a routine
so it complains about no return at end of function or variables
not being defined.
(cherry picked from commit 6ae1f64c3c)
2009-12-12 08:31:31 -08:00
Cary R 327cdc77a3 Add some casts in tgt-vhdl to remove warnings.
The Cygwin compiler is a bit picky. This patch adds some casts
to remove compilation warnings. In the past I have had warnings
off because of problems with the STL, but we may as well get
rid of the warnings we can. It also does not recognize that an
assert(0) or assert(false) ends a routine so it complains about
no return at end of function or variables not being defined.
(cherry picked from commit 3f12a401eb)
2009-12-12 08:31:15 -08:00
Cary R a8e1643ae9 Add some casts in vpi to remove warnings.
The Cygwin compiler is a bit picky. This patch adds some casts
to remove compilation warnings. In the past I have had warnings
off because of problems with the STL, but for C directories
like this it makes sense to enable the warnings. It also does
not recognize that an assert(0) or assert(false) ends a routine
so it complains about no return at end of function or variables
not being defined.
(cherry picked from commit f31a4e6d20)
2009-12-12 08:30:40 -08:00
Cary R 02a986b35d Add some casts in main directory to remove warnings.
The Cygwin compiler is a bit picky. This patch adds some casts
to remove compilation warnings. In the past I have had warnings
off because of problems with the STL, but for this directory we
mas as well remove the warnings we can. It also does not
recognize that an assert(0) or assert(false) ends a routine so
it complains about no return at end of function or variables
not being defined.
(cherry picked from commit 81d4cbc4bd)
2009-12-12 08:26:55 -08:00
Cary R 8759eaf720 Remove extra MinGW only varaible in t-dll.cc.
(cherry picked from commit 1f375ef16a)
2009-12-12 08:26:34 -08:00
Cary R daff9ed30d Remove version.exe with a -f to avoid a warning.
If version.exe does not exist and we don't have a -f then we
will get a warning.
(cherry picked from commit 05a3929b1a)
2009-12-12 08:26:09 -08:00
Martin Whitaker e4a319cfe2 Fix for pr2909414.
Currently the compiler only applies defparam statements that are
found in the initial root module hierarchy. This patch ensures that
defparam statements within scopes created by generate constructs or
instance arrays are also applied.
(cherry picked from commit e2be397aa8)
2009-12-12 08:22:09 -08:00
Cary R 3d5c6c6f30 Remove unused MinGW variable.
There was an unused variable in driver/main.c under MinGW.
(cherry picked from commit 392ac1200c)
2009-12-11 09:25:07 -08:00
Cary R c44ce66a87 Add debug_eval_tree code for the pow operator.
The power operator was missing eval_tree debug information.
This patch fixes that deficiency.
(cherry picked from commit a85880a8bb)
2009-12-09 19:10:12 -08:00
Cary R ce8a84db3c For MinGW make driver/main.c always create a path with a back slash
The MinGW executable should be able to support a path with mixed
separators, but to make things consistent all the path in the main
driver program (driver/main.c) now always use a '\' or convert a
path to use '\' (e.g. getenv() returns a path with a '/').
(cherry picked from commit e9c653dfa3)
2009-12-09 19:08:59 -08:00
Martin Whitaker 33c852d2b4 Reduce memory use for simulations that run in zero time.
The fix for pr1830834 causes vvp to only delete a completed thread
when the simulation time next advances. If a procedural model is
being simulated which makes many task or function calls within a
single time step, this can lead to excessive memory use. This patch
modifies the behaviour so that thread deletion is only delayed if
that thread has caused a sync event to be placed in the event queue.
This should catch all cases where the thread private data can be
accessed after a thread has terminated.
(cherry picked from commit c7b0aef414)
2009-12-09 19:05:26 -08:00
Cary R 1eb593e8ad Make the verinum pow operator work correctly.
The functionality of the integer power operator is specified in
1364-2005 on page 45-46 and specifically Table 5-6. This patch
fixes the verinum pow operator to work as specified in this
table. It also fixes an error in the == operator when both
operators are signed and only the left argument is negative.
(cherry picked from commit eea816e423)
2009-12-09 19:02:28 -08:00
Cary R 8ef7344ea5 Update wavealloca.h to fix MinGW compilation warning
This patch fixes a warning when compiling vpi/sys_lxt2.c under
MinGW regarding the definition of alloca().
(cherry picked from commit 59ebd47ba6)
2009-12-09 19:00:53 -08:00
Stephen Williams 5479aaf721 Add explicit dependencies on generated header files.
These explicit dependencies are not normally needed (because they
are covered by automatic dependency generation) but when the "-jN"
flag is passed to gmake, they help gmake schedule parallel builds.
2009-12-04 15:20:03 -08:00
Stephen Williams b85b2d8a26 More portable use of tail.
Apparently, tail +2 is not portable, but tail -n +2 should work.
2009-12-04 14:57:36 -08:00
Cary R 8b7ffa1a17 Update lxt/lxt2 files to latest from GTKWave.
This patch updated the four file lxt_write.{c,h} and
lxt2_write.{c,h} to the latest ones from GTKWave. This
required adding the wavealloc.h include file and an
update to configure.in and vpi/vpi_config.h.in to add
checks/definitions for ALLOCA and FSEEKO.
(cherry picked from commit b6f7354cee)
2009-12-03 08:21:12 -08:00
Cary R 9b6e9f5832 Add support for spaces in many paths/files names
This patch adds support for spaces in the path to the temporary files.
Adds support for spaces in output files and in library paths.

A space in the installation path is only supported under MinGW
(windows) at this time.
(cherry picked from commit dba2a6e434)
2009-12-03 08:19:32 -08:00
Cary R ab926ccee4 Convert a few sprintfs to snprintf
This patch converts a few sprintf statements to snprintf
to protect against buffer overflow.

It also converts a few sizeof calls from sizeof(x) to
sizeof x like other places in the code.
(cherry picked from commit f44c1cadde)
2009-12-03 08:18:20 -08:00
Cary R 3351004945 Remove unneeded definitions in drivers/globals.h
There were a bunch of unneeded definitions in drivers/globals.h.
All of these were only used in main.c so do not need to be in a
header file.
2009-12-03 08:15:24 -08:00
Cary R 7684814593 Minor rework of how driver-vpi is supported.
Add driver-vpi to either SUBDIRS or NOTUSED depending on if we
are building for MinGW or not. This is more logical and allows
the clean and distclean targets to be simplified.
(cherry picked from commit 145133bdb0)
2009-12-03 08:08:41 -08:00
Stephen Williams 3f29f96695 Fix delays in continuous assignment to support 64bit delays.
Remove the 32bit restriction on a few cases of delays in continuous
assignment expressions.
(cherry picked from commit de1f17d429)
2009-12-01 10:21:57 -08:00
Stephen Williams 7210061f2c Make all should build the iverilog-vpi.man file.
The "make install" target may not in general be able to build
the iverilog-vpi.man file, so make sure it it build by make all.
(cherry picked from commit 2e60a181c0)
2009-12-01 07:40:48 -08:00
Cary R 2396faac39 Add basic support for spaces in the install path for MinGW.
This patch adds support for spaces in the install path on MinGW.
It does this by converting the Long version of the iverilog path
into a Short version that does not have spaces in it. If we don't
do this then we can not add support for other arguments with
spaces in the path or filename. It also modifies the driver-vpi
program to support spaces in the saved ivl path. This is done by
just enclosing the include and library path argument in double
quotes.

The issue on MinGW is that if you put the executable argument to
system in double quotes to escape embedded spaces then you can
not put the arguments in double quotes as well. If you convert
to a Short name then the spaces are removed and we can in the
future escape the arguments as needed.
(cherry picked from commit dd425e8945)
2009-12-01 07:40:13 -08:00
Cary R c7126c3c1f Some more generic fixes for building in a remote directory
This patch fixes a few more issues related to building
in a remote directory. The start of the problem was
that the version file was not getting built correctly.
This necessitated using vpath instead of VPATH to only
allow the %.cc files. After that a few other places
needed to have $(srcdir) added.

The distclean target was also enhance so that when
building from a remote directory (srcdir != .) we
remove all the extra files and directories.
(cherry picked from commit 6909737bf2)
2009-12-01 07:38:11 -08:00
Cary R 14bc857c54 Make MinGW compile using a remote build directory.
This patch fixes a few MinGW specific issues that prevented it
from building in a remote directory.
(cherry picked from commit 8abe0d7d71)
2009-12-01 07:37:58 -08:00
Stephen Williams f49f3f56cf Make version.exe so that subdirs can get access to it.
(cherry picked from commit 342ec152bc)
2009-12-01 07:37:33 -08:00
Cary R c89ae29bf2 Fix some extra/invalid font switches in iverilog.man.
Cleanup some unneeded \fP statements and remove the invalid and
unneeded \fp statement. Slightly reword the __ICARUS__ definition.
(cherry picked from commit 74634864cf)
2009-12-01 07:34:19 -08:00
Stephen Williams d570437a17 Unify the version stamp in the version_*.h header files.
Try to put all the version stamps into common version_base.h
and version_stamp.h header files. All the source programs then
get their version from these header files.

Also handle the version stamps in the man pages by using the
version_*.h header file contents to edit the version strings
in the man page title bar markers.
(cherry picked from commit 966e29db3b)

Conflicts:

	driver/iverilog.man.in
	iverilog-vpi.man.in
	version_base.in
	vpi/vams_simparam.c
	vvp/vvp.man.in
2009-11-27 12:37:11 -08:00
Stephen Williams 0cc8285a01 Handle case that delay output is pending when new event arrives
If the delay has an event pending for the current time, then use
that as a reference for calculating the next delay. If that is not
done, then the delay calculated against the wrong reference might
result in zero, and bad results.
(cherry picked from commit f07577db11)
2009-11-25 07:50:35 -08:00
Stephen Williams d090fd7a17 Fix vpi_control operation codes to be standard
Apparently, the vpi_user.h definitions for vpiStop et al were added
before they were standardized by 1364-2000, and never corrected.
Change the values to be standard. (Submitted by Matt Trostel.)

I also added some binary compatibility for existing .vpi modules
that were compiled with the older constant values.
(cherry picked from commit 711365521d)
2009-11-05 06:41:51 -08:00
Cary R 09cdf5268e Add more non-breaking hyphens in the manual pages.
This has been started, but this patch adds a bunch more (all?) of
the non-breaking hyphens needed in the manual pages.
2009-11-03 14:47:12 -08:00
Martin Whitaker c1f750ff98 Fix vvp code generator bug for CA function calls with array word arguments.
If a function in a continuous assignment is passed an array word as
an argument, syntactically incorrect vvp code is generated. This is
because the code calls draw_net_input to generate the input labels
part way through writing out the .ufunc statement. If an input is
an array word, draw_net_input causes a .array/port statement to be
emitted, which gets written out in the middle of the .ufunc statement.
This patch fixes the problem by collecting the necessary input labels
prior to starting writing the .ufunc statement.
(cherry picked from commit 9950704735)
2009-11-01 11:09:07 -08:00
Cary R c7414f79b0 Add a waring that timing check delayed signals will not be driven.
The $setuphold and $recrem timing checks can create delayed signals
that are needed to get a model to work correctly when negative timing
check values are used. Since we do not support timing checks and just
ignore them this can create simulation problems when a user tries to
use these delayed signals since they are not driven.

This patch adds a waring when the circuit is being compiled that these
delayed signals will not be driven. This will be needed until we get
time to add the real timing checks are mimic the delayed properties of
the timing check.
(cherry picked from commit a5060b8adc)
2009-11-01 11:02:15 -08:00
Cary R 95eec69102 Cleanup a few more issues found with cppcheck.
Minor fixes and code reorganization to remove a few more issues
that cppcheck is complaining about. It has a few false warnings
and some issues that need more investigation.
(cherry picked from commit ae49197a14)
2009-11-01 11:00:53 -08:00
Stephen Williams 23ea74a126 Implement cbAtStartOfSimTime callback.
(cherry picked from commit 1b7a42ffcd)
2009-11-01 10:53:13 -08:00
Stephen Williams 70f15b472f Fix the vpiObjTypeVal for signals to be scalar or vector.
Scalar signals have a preferred type of vpiScalarVal, but vectors
have a preferred type of vpiVectorVal. Use the signal width to
distinguish.
(cherry picked from commit 5fb89262df)
2009-11-01 10:52:43 -08:00
Cary R 73d9a37020 Cleanup Makefile clean targets.
This patch removes bin32 from the clean targets since it is no
longer user/created. It adds autom4te.cache to the distclean
target in the main directory. It removes the files in driver
that are not created (lexor.c parse.c, etc.). The *.cc.output
files are no longer created so removing them is not needed.
(cherry picked from commit cf2f99ec3d)
2009-10-29 10:55:20 -07:00
Cary R 13921f0c0c Add a warning message if an environment variable is not found.
Instead of silently skipping the substitution we now print a warning
message if an environment variable substitution is not found.
(cherry picked from commit 83aa1363ea)
2009-10-29 10:54:12 -07:00
Cary R 29f5c882eb Add support for ${var} substitutions in the command file.
We still support $(var).

(cherry picked from commit 4cb39f584d)

Conflicts:

	driver/iverilog.man
2009-10-29 10:52:25 -07:00
Stephen Williams 98c3391acb Fix index out of bounds error message.
When displaying an index out-of-bounds message, use the index
given in the source code, not the canonical (translated) value.
(cherry picked from commit 37b11e0355)
2009-10-28 19:20:00 -07:00
Stephen Williams f5728c4a39 Add appropriate hysteresis to tranif input pins.
The tranif input pins are normally nothing special, but sometimes
they are fed back from the switch body. In this case, the control
needs to see the current *output* from the fed back port, in order
to get the results that people expect.
(cherry picked from commit 33158355ba)

Conflicts:

	tgt-vvp/draw_net_input.c
	vvp/island_tran.cc
2009-10-28 16:32:40 -07:00
Cary R cca3b0ed5a V0.9: Fix memory.h include issues.
The local "memory.h" file is no longer used in V0.9 or development,
so it does not need to be included in vvp/codes.h. The VHDL target
does not use the system <memory.h> header file so there is no need
to have a define for it in the vhld_config.h.in file.
2009-10-26 11:16:50 -07:00
Cary R 391ef78d42 Add error message that only 32 bit immediate CA delays are supported.
The .delay (x,y,z) functor and the get_number_immediate() function
only supports 32 bit delay values. This patch adds an error message
if the user passes a larger, but valid value.
(cherry picked from commit 1f0857606a)
2009-10-26 11:14:19 -07:00
Jared Casper ab5b9271f3 Still more build system cleanup.
- Add missing dependency of configure on aclocal.m4.

- Remove config stamp files in make distclean (and fix another for
  loop in base make distclean that I missed)

- Add stamp files to .gitignore
(cherry picked from commit c167b3a01f)
2009-10-26 11:12:04 -07:00
Jared Casper 7eb4825435 More build system tweaks, fixing pr2881797.
Use the time stamp file technique recommended by the autoconf manual
to prevent unneccesary rebuilds because of an unchanged config.h.
Uses the automake trick of generating the stamp files in the
_AC_AM_CONFIG_HEADER_HOOK macro instead of littering the source
directory with stamp-h.in files.

Add an extra ./config.status run after ./config.status --recheck
because with --recheck it doesn't actually try to remake the generated
files (and thus doesn't make the timestamp files).  Thus without the
extra run, each stamp-*-h target would need to independently run
./config.status to make sure it wasn't changed by the configuration
change.

An orthogonal fix of how config.status is called in subdirectories.
When in a subdirectory and config.status is called with
../config.status and $(srcdir) is a relative path, config.status gets
confused.  Fixed by replacing '../config.status --file=Makefile.in'
with 'cd ..; ./config.status --file=<dir>/Makefile.in'
(cherry picked from commit 7ead2aa88b)
2009-10-20 10:04:01 -07:00
Cary R 58511ab212 More valgrind cleanup.
This patch adds code to cleanup system functions driving a
continuous assignment. It also modifies the user function
cleanup to not interfere with this. It also adds a count
of the nets and signals that were not cleaned up that is
pnly printed when running valgrind. They are not flagged
y valgrind since they are pool managed objects. There are
a few signals that need to be cleaned up and local nets
are missed so there are a lot of nets.

(Cherry picked from dec524a151)
2009-10-20 10:00:05 -07:00
Cary R b3ca7e1774 Update the simulator subversion. 2009-10-20 09:51:14 -07:00
Jared Casper 5e8e59484b Base Makefile improvements.
Instead of calling make in subdirectories using a sh for loop, use GNU
make's $(foreach ) to create a string of commands connected with &&.
This way an error in a subdirectory will stop the build, instead of
continuing on to the next subdirectory, which the old version does.

Also added rules to regenerate configure when configure.in changes,
and to run config.status --recheck when that happens.
(cherry picked from commit d098db0a06)
2009-10-19 07:57:55 -07:00
Stephen Williams 517b4e3248 Get drive of pull-ups right.
The drive for a pullup comes from ivl_nexus_pt_drive1. Get this
wrong and a pullup turns into a HiZ.
(cherry picked from commit 6b17dcc587)
2009-10-14 10:14:37 -07:00
Cary R a6fdb4b6e6 Clean up user function calls from thread space.
This patch adds cleanup code that cleans up the memory that is
allocated by the of_EXEC_UFUNC command. This knocks a few more
files off the valgrind list.
(cherry picked from commit 02ca7fe7fc)
2009-10-14 10:11:06 -07:00
Cary R ad786a2aa3 Don't replace parameter overrides that did not evaluate.
Trying to replace a parameter override that did not evaluate
correctly can lead to a crash, so just skip the substitution.
(cherry picked from commit 8abf303753)
2009-10-14 10:05:20 -07:00
Cary R e92c4638ed $clog2() should return an integer value.
The constant $clog2() was returning a value that had an integer
width, but it did not have the sign bit set. This could result
in incorrect math expressions. This patch sets the sign bit for
the constant $clog2() result.
(cherry picked from commit bc60536eb9)
2009-10-14 10:02:20 -07:00
Cary R fd4b849091 In driver-vpi only look at the first CC word when checking compiler path.
In the MinGW version of iverilog-vpi (C version located in driver-vpi)
we must only look at the first word of the IVERILOG_VPI_CC definition.
A recent change to the configuration process made this equal to
"gcc -std=gnu99" which will not be found when looking for the
gcc executable. We nee to look for "<path>\\bin\\gcc.exe". This
patch modifies the driver to only use the first word when looking for
the compiler, but uses the full value when compiling.
(cherry picked from commit d9d8d4b093)
2009-10-14 09:59:39 -07:00
Cary R 98e5e36f03 We must have autoconf version 2.60 or later.
When AC_PROG_CC_C99 was added recently we created an implicit
requirement for autoconf version 2.60. This patch makes that
implicit requirement and explicit requirement.
(cherry picked from commit ff39575dc0)
2009-10-14 09:57:44 -07:00
Cary R 1a0d475907 Fix obscure valgrind memory leak.
(cherry picked from commit 3303cc144f)
2009-10-14 09:55:57 -07:00
Cary R 807a66f0a2 Add a configure check to see if uint64_t and unsigned long are identical.
This is needed to get vvp to compile under MacOS 10.6 and possibly other
64 bit systems that define uint64_t as unsigned long long vs unsigned
long (both are 64 bits).
(cherry picked from commit 39f243b18e)
2009-10-08 16:43:02 -07:00
Cary R 92e7587320 Format the --enable-suffix help correctly.
(cherry picked from commit 537ba93fe4)
2009-10-08 11:42:31 -07:00
Stephen Williams 04be3a6323 Do not cprop through ternaries if the selector is an l-value.
It turns out that it is possible for an otherwise constant net
mux to be non-constant if there is a force that can drive the
net. This can be detected as an l-value reference to an otherwise
constant selector.
(cherry picked from commit abc4eb9d52)
2009-10-06 07:20:44 -07:00
Cary R d2a900d187 Fix bug in vector8 operator=
operator= would try to overwrite it self under some circumstances.
This was found with valgrind and using -O0. It works with -O2.
(cherry picked from commit 9ea6604439)
2009-10-03 09:01:44 -07:00
Cary R eb9d79ec61 Check if the compiler supports C99 and better check for some math functions.
Add a configuration check that says we would like to use C99 if the
compiler supports it. Also change the lround(), nan(), fmin() and
fmax() checks to look in the default libraries as well as the math
library.

Update the iverilog-vpi sh script to correctly quote CC since it
may now have two words (gcc -std=gnu99).

Add a missing int for main in draw_tt.c.
(cherry picked from commit ed7e9f8be5)
2009-10-01 12:01:11 -07:00
Cary R e8dada7337 The concat object can get out of sequence so don't optimize a repeat.
Under some situation the optimized repeat expression can get out
of sync while it is being processed this causes the code to
reference freed memory. This happens when the repeat expression
is converted to an unsigned integer, but the repeat expression
is used in a different path. It was easier to just remove the
optimization then track down the convoluted call sequence that
was causing this and then figure out what needed to be fixed.
The repeat expression must be constant, so is likely not too
complicated so this optimization is very minor and should not
be missed.
(cherry picked from commit 3259354d29)
2009-10-01 12:00:39 -07:00
Cary R 3dfc1d5097 Fix &A<> to support an undefined word index.
This patch adds support to &A<> for an undefined word index.
It mostly matches what was done for &PV<>.
(cherry picked from commit 4b50473939)
2009-09-24 16:06:21 -07:00
Cary R 6bbf97a05d Warn that a signed part select may not work for signals < 32 bits.
If a signed signal is driving a part select in a CA and the width
is less than 32 bits. the value will be zero extended and will
not work for negative values. This patch adds a warning that this
could happen. This will be fixed in development.
(cherry picked from commit e1af002a32)
2009-09-24 13:44:22 -07:00
Cary R e7815c3984 Optimize a full L-value indexed part select, etc.
This patch adds an optimization when a constant indexed part
select covers the entire L-value. It also fixes a few issues
in the code generator related to part selects.
(cherry picked from commit 09fa57742a)
2009-09-24 13:32:57 -07:00
Cary R fb01245501 Only process the first 32 bits of the part select base.
When reading from thread space only read the first 32 bits
(sizeof int) for the part select base. This matches the other
parts of the PV_get_base() code.
(cherry picked from commit c82baa2793)
2009-09-24 13:29:50 -07:00
Cary R d0a45ffe9d Warn that &A<> may have problems with a signed select from thread space.
Like the &PV<> code we should warn the user that a signed select
from thread space may not work correctly for &A<>. This will be fixed
in development.
(cherry picked from commit 1851cba955)
2009-09-24 12:16:54 -07:00
Stephen Williams 9c624a2403 Better portability for rpm install section.
(cherry picked from commit d3d84dde6a)
2009-09-23 15:56:16 -07:00
Stephen Williams 4d4a693248 Improve some assert messages
Replace some assert functions with ivl_assert.
2009-09-16 14:45:55 -07:00
Cary R 1872652019 Don't check the scope for array words.
We do not want to check an array word scope to see if the scope
was already included since a scope does not include array words.
They must be explicitly specified.
(cherry picked from commit 0b6bd343e8)
2009-09-15 20:51:11 -07:00
Cary R d68fea3f58 Warn that events can not be user task or function arguments.
This patch makes events passed as arguments to user tasks or functions
a compile time error with an appropriate error message.
(cherry picked from commit 4d57ede0e5)
2009-09-15 20:45:49 -07:00
Cary R b0e2185ade Fix 64 bit problem in vvp/vpi_signal.c
This is based on a suggested fix from Martin. It fixes the crash
for two tests in the test suite. As a bonus it is more efficient.
(cherry picked from commit 43f41572cb)
2009-09-15 20:40:14 -07:00
Cary R 6aaf2f84a8 Squash some gcc 4.3.3 warnings.
This patch clears all the gcc 4.3.3 warning that can be fixed.
The remaining warning is dictated by older versions of the
1364 standard.
(cherry picked from commit 6d5d06cae4)
2009-09-15 20:38:57 -07:00
Cary R 7ad50f4454 Revert one change from previous patch.
I was mistaken in changing the cast in the comparison.
(cherry picked from commit 5a11a8a9c2)
2009-09-15 20:35:48 -07:00
Cary R 19b0d5b7c9 Fix another 64 bit problem in a part select.
This patch fixes a problem in the .part/v select when the index is
undefined. The default value needs to be INT_MIN, so when the long
is cast to an int the value is in range.
(cherry picked from commit 1b300cb2f6)
2009-09-15 20:35:35 -07:00
Cary R ae87aff745 Fix .part/v to only use a 32 bit value.
To get better functionality in V0.9 and development until we
add a select that is sign aware to .part/v this patch uses
a 32 bit integer (int) for the select value. This allows a
normal Verilog integer to produce the correct results. A
warning for smaller signed index vectors is planned, but it
needs more input.
(cherry picked from commit 27f032760e)
2009-09-15 20:35:24 -07:00
Cary R 9c09394785 Add support for 'bx from a signal to &PV<>
&PV<> was just using vpi_get_value() when a signal was driving
the select. This incorrectly returned 0 for 'bx or 'bz. This
patch adds a check for an undefined value and returns INT_MIN
for this case.
(cherry picked from commit 1b0dd8c8e5)
2009-09-13 08:38:08 -07:00
Cary R 3f8f81568a Add file/line information to named events and better expr. error.
This patch adds file and line number information to named events.
It also modifies the draw_eval_expr_wid() routine to fail with
an appropriate message for named events. This checking needs to
be pushed into the elaboration stage, but this will give a better
message than we had before.
(cherry picked from commit dff6a1ebff)
2009-09-13 08:34:59 -07:00
Martin Whitaker bb5d30ead5 Add user control over implicit sensitivity list warnings.
This patch adds two new warning classes that can be enabled or
disabled via the -W command line option. The first controls
whether a warning is generated if a part select within an
always @* statement causes the entire vector to be added to
the implicit sensitivity list. The second controls whether a
warning is generated if a word select within an always @*
statement causes the entire array to be added to the implicit
sensitivity list. The first class is not automatically enabled
by -Wall, the second class is.
(cherry picked from commit fc49420cb5)
2009-09-13 08:27:54 -07:00
Nick Gasson 4e77abca44 Allow labelled begin blocks to contain processes in VHDL target
This is a simple fix for a crash that occured when a process
was inside a labelled begin inside a generate statement.
(cherry picked from commit face1a1d15)
2009-09-03 18:16:47 -07:00
Nick Gasson 902ae19bbf Handle generate scopes with signals in VHDL target
This uniques the name of each copy of a signal and adds
it to the containing VHDL entity.
(cherry picked from commit 388c9c6747)
2009-09-03 18:16:35 -07:00
Nick Gasson 5587e42e2e Translate simple generate loops to VHDL
This handles generate loops and genvars with no local variables
(cherry picked from commit bc7ec04cab)
2009-09-03 18:16:18 -07:00
Cary R f8f363a0b6 Remove old configure files in vvp directory.
(cherry picked from commit 5f08f40cad)
2009-09-03 18:15:23 -07:00
Cary R f34485d415 Support negative index for %assign/av opcodes.
If the array index is negative these opcodes need to just return.
(cherry picked from commit 9d765820bf)
2009-09-03 18:12:40 -07:00
Cary R df177e9e14 Major rewrite of indexed part selects.
This patch is a major rewrite of the indexed part selects (+: and -:).

It made the following enhancements:

1. Make indexed part selects work correctly with both big and little
   endian vectors.

2. Add a warning flag that warns about constant out of bounds/or 'bx
   indexed selects.

3. Moved the -: parameter code to its own routine.

4. Added support for straddling before part selects in a CA.

5. Added more assert(! number_is_unknown) statements.

6. Add warning for &PV<> select with a signed index signal that is
  less than the width of an int. This will be fixed later.

7. Add support for loading a 'bx/'bz constant into a numeric register.

8. Add a number of signed value fixes to the compiler/code generator.

9. Major fix of draw_select_expr() in the code generator.
(cherry picked from commit 2b17366ad5)
2009-09-03 18:07:51 -07:00
Cary R 5d4c8d616a Propagate sign in synthesize for math operators.
The sign of the expression needs to be propagated for the
math operators when they are synthesized.
(cherry picked from commit a49463e728)
2009-09-03 18:02:40 -07:00
Cary R 72c02a8285 Pass file/line information for part selects.
Propagate the file and line information for a part select
expression and LPM (continuous assign).
(cherry picked from commit 06997c63ed)
2009-09-03 18:02:24 -07:00
Cary R 043c86ba02 Enhance %shiftr/i0 and $shiftl/i0 to work with negative shifts.
The %shiftr/i0 and %shiftl/i0 opcodes are used for some part
selects and if we have a negative shift we want the value to be
padded with 'bx. This patch enhances the two %shift/i0 opcodes
to work with negative shifts and for negative shifts pad with
'bx instead of 'b0.

It also fixes %ix/get/s to use a uint64_t instead of a unsigned
long to avoid problems with sign extension on 32 bit machines.
(cherry picked from commit ecb00017cb)
2009-09-03 18:02:02 -07:00
Cary R b9d0783ad9 Assert number is not unknown for many cases in tgt-vvp.
This patch adds a number of asserts that a number is not unknown
in places where this should never happen.
(cherry picked from commit d108221fef)
2009-09-03 18:01:43 -07:00
Cary R 047ee137ed Add vvp support for out of bound variable part selects.
This patch adds support for variable part selects with out of bound
and 'bx index values.
(cherry picked from commit 1306a6db81)
2009-09-03 18:01:27 -07:00
Cary R ef814a9ef4 Add a -Wselect-range warning class.
This patch adds support for a -Wselect-range warning class to the
driver and ivl programs. This is part of -Wall. The actual checks
will be added in a later patch.

Cherry-picked from e576e1eb2c
2009-09-03 18:00:31 -07:00
Cary R fa0ecb3761 Convert IVL_LPM_CONCAT to use ivl_lpm_size() instead of ivl_lpm_selects()
It was documented that a IVL_LPM_CONCAT would use _size() instead
of _selects(). This patch adds the functionality to _size() and
converts all the Icarus provided code generators to use _size().
_select() will be kept for compatibility in V0.9.
(cherry picked from commit 4cd790a2d2)
2009-09-03 17:52:35 -07:00
Cary R f2a81cf660 Fix subtle bug in scope checking.
This check looks to be defined to check the child scope not the
top level scope.
(cherry picked from commit 872962ef18)
2009-09-03 17:49:18 -07:00
Cary R e1b4d531a1 Update config.guess and config.sub to latest version.
This patch updates the config.guess and config.sub files to the
latest ones from automake 1.11.
(cherry picked from commit 9669ccd011)
2009-09-03 17:48:17 -07:00
Cary R a418995988 Update MinGW requirements, etc.
The old readline library was causing problem. I updated the mingw.txt
file to use the gnuwin32 version of readline (5.0-1) which works. I
also mentioned that I plan to rewrite the directions using a newer
version of MinGW.
(cherry picked from commit a51f2dca50)
2009-09-03 17:46:53 -07:00
Cary R 8c36e20fd4 Add support for an undefined index for the %load/a* opcodes.
These opcodes need to return 'bx or 0.0 for the real opcode when
the array index is undefined.

The patch also documents the auto incrementing of the bit
index register done by the %load/avx.p opcode.
(cherry picked from commit 8623f804f2)
2009-09-03 17:40:01 -07:00
Cary R 2c982a6edb Add missing limits.h include in vpi_signal.cc
(cherry picked from commit 83c7a24cff)
2009-09-03 17:37:52 -07:00
Cary R a298bfb22a For a part select driving another part select the extra bits must be 'bz.
When a part select is driving another part select any bits outside the
original select must be 'bz instead of 'bx. If we initialize the temporary
buffer to 'bz this should work as required. It there are multiple drivers
then a resolver comes into play and this should not matter.
(cherry picked from commit e31b6bd20c)
2009-09-03 17:35:16 -07:00
Cary R cce61d7134 Ignore a zero MCD for $fflush, $fdisplay*, $fwrite* and $fstrobe*.
(cherry picked from commit ed4e2eb046)
2009-09-03 17:30:12 -07:00
Martin Whitaker aad5443a36 Fix for pr2842185 and for genvar scopes.
When checking for name collisions, the compiler looks for genvar
declarations in the enclosing module rather than in the current
scope, which leads to false positives. The compiler also places
all genvar declarations in the enclosing module scope, even when
the declarations are inside a generate block which has its own
scope. This patch fixes both these faults. It also fixes some
typos and outdated information in comments.
(cherry picked from commit da010db739)
2009-09-03 17:24:45 -07:00
Martin Whitaker f5f104f8a6 Fix for pr2837451.
pr2827132 changed the val_ field in vvp_fun_part_sa to only store
the bit values for the selected part, not the entire source vector,
but omitted to modify the recv_vec4_pv method to handle this change.
This patch rectifies that omission.
(cherry picked from commit 7c6176357f)
2009-08-18 17:33:30 -07:00
Cary R b7ff68c3f4 Fix a few more minor memory leaks.
This patch fixes a few more memory leaks that can happen under
error conditions.
(cherry picked from commit 35f3d7f60e)
2009-08-18 15:00:12 -07:00
Cary R 69986a5bc7 Do not schedule a new event if the previous event has the same value.
If the previous event has exactly the same value as this event then
we do not add this event to the event queue.
(cherry picked from commit 2e820ca6f0)
2009-08-18 14:56:14 -07:00
Cary R c0f4b0374a Warn that we do not support non-blocking assignment to real array words.
A while ago we changed how variable arrays were accessed. This change
did not get propagated to the non-blocking assignment for real array
words. This patch adds a warning that this is not currently supported.
We can add this to development, but not V0.9 (interface change).
(cherry picked from commit 88b18d4212)
2009-08-18 14:52:35 -07:00
Cary R 817b1ef3d4 UDPs need to evaluate their arguments before generation
When generating a .udp call the arguments need to be evaluated
before the .udp is. This allows things like .resolv to be built
correctly.
(cherry picked from commit cb5c4299fb)
2009-08-18 14:48:30 -07:00
Cary R f9774758a3 UDPs can only take two delay values.
Check in the compiler that a UDP is only given two delay values.
(cherry picked from commit 7916e148f8)
2009-08-18 14:45:31 -07:00
Cary R eb2fed7015 Fix some memory leaks/issues found with cppcheck.
I ran cppcheck on the code and it found a few obscure memory leaks and
a few other issues. This patch fixes most of them.
(cherry picked from commit 2e166b7279)
2009-08-18 14:36:32 -07:00
Stephen Williams 5af47cda12 Fix man page formatting for portability. 2009-08-10 06:34:18 -07:00
Cary R 0aad444bbf Add full $ferror() support, bug fixes, etc.
This patch adds $ferror() support. This is enhanced over what the standard
says needs to be supported. All file I/O routines set/clear the errno flag,
This allows $ferror() to check when an invalid fd/MCD is passed to a
system task. The $ferror() fd is only checked if errno is not set since
all the other routines will set EBADF when they are called. This allows us
to test the output from $fopen() which sets the fd to zero (an invalid fd)
when it has a problem.

The following bugs (changes) are also fixed:

Fix $fdisplay*, $fwrite*, $fstrobe*, $fflush, $fclose to not accept 0 as
a valid MCD.

For the $fdisplay*, $fwrite* and $fstrobe tasks an invalid fd/MCD is now
a warning instead of an error like the other file I/O routines.

Modify $fputc() to be a function and return a value like $ungetc().

Modify $ungetc() to return a value like the standard dictates (-1 on
error else 0) and pass the value as a full int to get EOF as an error.

Remove some extra checks that could not happen in $fseek() and to
be safe convert the numeric codes to the system symbolic values.

Skip $fstrobe callback when the fd/MCD is closed. The standard says
we need to cancel the callback, but we currently do not have the
ability to do that so just skipping this will work for now.

Free the argument handle when $fscanf() is called with an invalid fd
(memory leak).
(cherry picked from commit ce89a68735)
2009-08-02 11:07:23 -07:00
Cary R e63c75d1a3 Add a warning when we reach 1024 files.
It's not too likely we will ever reach this, but we should be nice
and print a message instead of just failing. We could set errno,
but for now the warning will have to be enough.
(cherry picked from commit b0ac550791)
2009-08-02 11:04:24 -07:00
Cary R a5b0872016 Fix memory leak, unneeded argument.
Very minor issues dosify was not closing files so memory leaks could
show up and vpi/sys_readmem.c was passing the file after it was
closed to the lexor cleanup code. The lexor cleanup code does not
need an argument.
(cherry picked from commit 52fbb3f734)
2009-08-02 11:01:31 -07:00
Cary R f6b9db1c78 Add full genvar support and name space checking.
This patch adds genvars to the elaboration process. It adds checks
that a genvar is defined for a generate loop and that a genvar does
not conflict with any other items in its name space.
(cherry picked from commit 72a98e85cb)
2009-07-29 08:56:01 -07:00
Martin Whitaker 597097eaef Fix for pr2821633.
Currently, edge event functors declared in automatically allocated
scopes that are used to detect edges on signals declared in static
scopes are unable to correctly determine edge information for the
first signal delta they receive because they do not know the old
state of the signal. This patch causes the state of static signals
received by these event functors to be recorded as static state in
the functors, so the old state of the signals can be initialised
to the correct value when a new automatic context is created.
(cherry picked from commit d7fe9c613c)
2009-07-29 08:52:50 -07:00
Martin Whitaker 47512e351f Suppress unnecessary update of part select functor output.
Currently a part select functor will send updates to nodes connected
to its output whenever any part of its input vector changes. This
patch ensures updates are only sent when the selected part of the
input vector changes.
(cherry picked from commit 1453c5b0bb)
2009-07-29 08:50:28 -07:00
Cary R 506c09f5f8 Fix power operator width in self-determined context.
In a self determined context the width of the power operator
is defined to be the left argument width.
(cherry picked from commit e98000426e)
2009-07-29 08:47:25 -07:00
Cary R 693fb93962 Fix CA replication of zero issues.
This patch fixes a CA to evaluate and ignore a replication of zero.
It also fixes a minor glitch in the data type calculation code. This
was causing a problem if a zero width replication was the first
element in a concatenation/replication since the data type was hard
coded to the first element of the concatenation/replication. It now
uses the first defined element in the concatenation/replication to
determine the data type.
(cherry picked from commit b629d913d2)
2009-07-29 08:44:15 -07:00
Cary R 8ca5926db9 Fix procedural concatenation/repetition problems
This patch evaluates the whole concatenation expression and
makes the concatenation padding sign aware. This is needed
when $signed({...}) is passed as an argument.

A repetition is just N copies of the base expression not N
evaluations of the base expression. This is only a problem
when functions have side effects. It's also faster to copy.
The evaluation must also be done when the replication count
is zero (see 1364-2005).
(cherry picked from commit e362a86b16)
2009-07-29 08:44:05 -07:00
Cary R 7acafd128f The scanf functions must return EOF if source starts at the end of input.
The $fscanf() and $sscanf() functions are defined to return EOF when
the end of input is reached before any matches or match failures have
occurred.
(cherry picked from commit c5ee1fdbf5)
2009-07-29 08:40:47 -07:00
Cary R d0a12f5b14 When skipping C-style comments in a skipped `ifdef include the '\n'
When a C-style comment /* */ is being skipped because it is in a
skipped `ifdef, `ifndef, etc. directive then we need to output a
'\n' at any comment end of line.
(cherry picked from commit e932c41587)
2009-07-29 08:37:59 -07:00
Cary R 8964a175f8 Find the width of net arrays correctly.
Add code to the generic get_array_word_size() function to correctly
find the width of net arrays and use this routine in the _vthr_
code as needed.
(cherry picked from commit 212bd4134a)
2009-07-29 08:34:49 -07:00
Cary R 97d70f9069 base if for ivl pbase is for ivlpp 2009-07-29 08:31:43 -07:00
Cary R 0dc0fbf78d Add check for prec > unit in `timescale directive. 2009-07-29 08:28:14 -07:00
Cary R 786b3a0ca9 Real constants are always signed.
Set the signed_flag_ for real constants.
2009-07-29 08:21:36 -07:00
Cary R 24a60ce6af Add compiler warnings for more constant out of bounds array accesses.
This patch adds compiler warning messages for all/most constant out
of bounds array access.
2009-07-06 15:08:56 -07:00
Cary R 4c640f67cb More VCD enhancements.
Make the code smarter so it can keep fewer items in the lists.
Scopes and explicitly given variables are all that is kept.
Includes a few other refinements.
2009-07-06 15:06:15 -07:00
Cary R cfe68fe6b4 Add basic support for events and cleanup VCD dumper.
This patch adds support for dumping named events to the VCD
dumper only. The LXT and LXT2 will be added once this has
been tested more. It also reworks the $dumpvars routine
to be more consistent concerning warning messages for duplicate
signal dump requests and fixes some bugs.

For events you will get extra events at T0 and at $dumpon. I
plan to fix this, but that is much more involved.

For duplicate signal warnings. Implicit duplicates loaded
automatically from a scope will not display a warning. Only
an explicit signal request will print a warning if it was
already included. All other will be silently ignored. This
should limit the warning to only what the user cares about.

For example:

  $dumpvars(0, var, scope_that_includes_var);

Will work without a warning message.

  $dumpvars(0, scope_that_includes_var, var);

Will generate a warning since the var was already included
by the scope request.

Other enhancements include the start of including type
information in the output. For now integer is added, the
other type information will require changes to the code
generator and hence will only be done in development.
2009-07-06 15:06:02 -07:00
Cary R 78149e9d15 Use correct sign for signal and constant addition.
This was incorrectly using the expression sign not checking if
the two sub-expressions are both signed. This likely used to
work, but in the context of $signed which sets the expression
to signed so we can have a signed expression without both
sub-expressions being signed.
2009-07-06 15:01:23 -07:00
Cary R bbe037bf9f Print a warning for an implicit sensitivity list that has selects.
An implicit sensitivity list that has selects (bit, part, indexed
part or array) will include more than the user expects so print a
warning to let them know what will happen. Other simulators have
the same behavior, but I believe this is incorrect and needs to
be fixed to only include the appropriate parts. The warnings can
go when we fix this functionality, but we need them now to warn
the user that they may not be getting what they expect. One other
simulator warns for array selects.

This patch also adds the array index to the sensitivity list.
2009-06-23 09:53:31 -07:00
Cary R d3bf6be7b2 Fix real variable array and net array bugs.
This patch fixes a number of bugs related to real variable and net
arrays. Specifically the following:

1. When iterating over (scanning) a net array start at base index 0
   not index 1.

2. Don't fail when iterating over (scanning) a real variable array.

3. Run the array_word_change() routine when a real variable array
   word is changed. This allows array ports and value change
   callbacks to work correctly.

4. Update the array_word_change() routine to work with real variable
   arrays.

5. Update the array port code to support real variable arrays.

6. find_name() needs to also iterate over net array words just like
   memory array words.

7. Initialize all real array words to 0.0 when the array is created.
2009-06-23 09:50:13 -07:00
Cary R 6146a98278 Make the dumpers match better (VCD, LXT, LXT2).
This patch removes some of the unneeded differences in the
various dumper routines. This is the start of a complete
refactoring, but the first task is to make them as common
as possible and this is the start of that.
2009-06-23 09:43:22 -07:00
Cary R 63c7285113 For real expressions evaluate non-real sub-exprs as bits and convert.
When processing procedural real expressions we need to evaluate
non-real sub-expressions as bit based expressions and then
convert the result to a real value. This is particularly import
for integer division.
2009-06-23 09:37:41 -07:00
Cary R 79e0203280 Use a default buffer size of 512 vs 256 for displaying.
This patch changes the initial buffer size when displaying results
to 512 from 256. This initial buffer is used as the default for the
floating point results and failed when %f is given a large, but
valid value. To make this even more safe we add the precision to
the size to make sure we do not overflow the buffer.
2009-06-23 09:31:18 -07:00
Cary R ad419dfbe4 Parse the config declarations and report they will be ignored.
This patch adds code to parse config declarations and reports
that they are not currently supported and will be ignored.
2009-06-23 09:25:21 -07:00
Cary R 75d71fe312 Some compiler cleanup and minor memory leak fixes.
This patch cleans up some unneeded code. Releases some allocated
memory before the compiler quits and fixes a couple minor memory
leaks in the compiler and vvp code generator.
2009-06-23 09:14:03 -07:00
Cary R 5a30355faf Ignore specify pulsestyle_* and *showcancelled directives.
This patch adds code to silently ignore the specify directives:
  pulsestyle_onevent
  pulsestyle_ondetect
  showcancelled
  noshowcancelled.
2009-06-08 11:12:04 -07:00
Cary R 623e897e55 Some delay expressions need to probe their width (ternary)
The ternary operator requires that the expression width be defined.
This requires that the delay expression has test_width() run on it.
2009-06-08 11:09:10 -07:00
Cary R 0bb6360ac7 Allocate the fd table dynamically in 32 entry chunks.
The fd table used to be statically allocated with only 32 entries.
Three of these were preallocated for stdin, stdout and stderr
leaving only 29 for the user.  This patch makes the allocation of
this table dynamic with a hard limit at 1024 total fds. The table
is increased in 32 bit chunks.
2009-06-08 11:06:43 -07:00
Cary R 4b850e1e74 Fix bugs in &= and |= for vvp_vector4_t
Someone got a bit too creative in reducing the original equations
I wrote to handle this. This patch reverts the previous code and
uses my original equations. This passes for both wide and narrow
vectors. The equations are slightly more complicated, but the old
z2x conversion had some overhead. I would expect the time to be
about the same, but you now get the correct results.
2009-06-08 09:45:25 -07:00
Cary R 8ce807a263 Parse all the 1364-1995 and 1364-2001 timing checks.
This patch adds code to parse and ignore the following timing checks:

$nochange  1364-1995
$skew      1364-1995
$fullskew  1364-2001
$removal   1364-2001
$timeskew  1364-2001

The other checks were already supported. These have not been tested,
but they use the same basic terms as the other checks. We can fully
test these when we actually implement them.
2009-06-08 09:26:54 -07:00
Cary R cc9524bd89 Fix some keywords, add -g2001-noconfig and fix up uwire/wone.
This patch adds -g2001-noconfig command line flag. The compiler
already supported this with `begin_keywords. Document this in
the manual page and fix a few other issues.

Fix endgenerate to be a 2001 keyword and add a few missing
keywords at the appropriate standard level e.g.(unsigned).

Add uwire and deprecate wone. wone used to just convert without
a warning to a wire. uwire will display a warning that it is
being converted to a wire without a check. wone is converted to
a uwire with a warning and then prints the uwire message. The
uwire message will be replaced with a real check fairly soon.
2009-06-08 09:20:27 -07:00
nog 13e07d6b7c Avoid stepping on free'd memory during recursive macro expansion
During macro expansion (with arguments), there is one global buffer
(exp_buf) that keeps getting reallocated to fit all the macro's text
that's currently being expanded.  The problem with this scheme is that if
a macro with arguments needs to be expanded from the macro text of another
macro with arguments, it may happen that the second expansion forces
the above exp_buf buffer to be reallocated.  Which is fine until the
previous macro processing resumes where (struct include_stack_t *)->str
now points to uninitialised memory.  Basically, the code that can trigger
such behaviour is as follows:

`define FOO(a)	(a+3)
`define BAR(b)	(`FOO(b)+2)

`BAR(x)

Ofcourse, you need to get lucky to get the exp_buf to be realloced at the
right point, but it's possible.

I don't see the advantage in keeping all the expanding macro's text
together, so my solution is to simply allocate a new buffer and pass it
as (struct include_stack_t *)->str to the flex parsing function and free
it at the end.
2009-06-08 08:51:31 -07:00
Cary R bbf11b830b Add support for unconnected_drive.
Icarus has recognized this directive, but it did not do anything
with the information. This patch adds the functionality for most
common cases. It adds this by changing the input net type from
wire/tri to tri1 or tri0 depending on the pull. The issue is that
if the input net is not a wire or tri this is not safe and should
really be done as an external pull gate connected to the input.
We will need to handle this is it ever comes up. For now a sorry
message is printed.
2009-06-08 08:42:12 -07:00
Cary R d345fb7654 Add more default net types
Previously Icarus only supported a default net type of wire or none.
This patch adds the rest of the supported net types (all except
uwire and trireg) to the `default_nettype directive. It also fixes
make_implicit_net_() to use the default_nettype instead of always
using implicit (the same as wire).
2009-06-08 08:25:21 -07:00
Cary R 3186e3dc54 Rework the timescale directive and cleanup line a bit.
This patch reworks the `timescale directive to do a better
job of parsing the line, it refactors some of the code and
should produce better error messages. It also tightens up
parsing the numeric constant, etc. to better match the
Verilog standard.

The parsing of `line has been enhanced to only allow 0, 1 or
2 for the level and a single line comment at the end of the
line is ignored.
2009-06-07 21:45:31 -07:00
Cary R d4d50fd97d Use strchr() instead of index().
strchr() is more portable and index() is not available under
MinGW so replace index() with strchr().
2009-06-07 21:30:42 -07:00
Cary R 3337c9d51a Make ivl warn that it does not support ifndef or elsif
We added support for these two directives some time ago,
but ivl was never updated to warn that it did not support
them and you needed to use ivlpp.
2009-05-24 10:36:33 -07:00
Cary R dfda202f14 Add better error checking to the two line directives.
Icarus supports both a #line and `line directive. This patch
reworks the parsing of these to provide better error detection
and full checking.
2009-05-24 10:34:06 -07:00
Cary R 5ca440dc1c Add support for `resetall and other directive changes.
This patch adds support for the `resetall directive.

It also changes `celldefine, `endcelldefine and `resetall
to no longer grab text following them. These directives do
not take an argument so they should not be grabbing any
text and silently discarding it.

The `timescale processing was reworked to handle being
reset and hooks were added to easily change the default
time units and precision when we add that feature request.
2009-05-24 10:28:42 -07:00
Cary R 96908e2fc5 Add compiler support for `celldefine, vpiCellInstance
This patch adds support to the compiler and stub backend for
`celldefine. This matches the compiler portion of the full
support that was added to 0.10.devel. This does not change
vvp or the vvp interface since changing the interface is not
allowed in a stable branch.
2009-05-24 10:21:37 -07:00
Cary R 9f07e3c16e Print a better error message for a '~' token in front of ('&' | '|' | '^')
Some users may expect this to work so this patch catches these
specific cases and tells the user to use the singe unary operators
'~&', etc. instead.
2009-05-24 10:18:51 -07:00
Cary R 3ae3e34732 Cleanup if an invalid option is given.
Cleanup the temporary files and memory if iverilog is given
an invalid option.
2009-05-24 10:16:13 -07:00
Cary R 372efd8c30 Fix memory leak when parsing command files.
These are not leaks in the true sense of the word, but it is
memory that is not being freed before the program finishes
so valgrind will complain about this.
2009-05-24 10:15:45 -07:00
Larry Doolittle ac7f55f22a Remove fresh const lint
It looks pretty stupid and non-c++-y, but it does remove two compiler warnings
vvp/stop.cc: In function 'void stop_handler(int)':
vvp/stop.cc:492: warning: deprecated conversion from string constant to 'char*'
vvp/stop.cc:493: warning: deprecated conversion from string constant to 'char*'
2009-05-24 10:14:01 -07:00
Cary R b74736c784 Display and error for hierarchical references in a parameter r-value expr.
Display and error message when the user uses a hierarchical reference
in a parameter r-value expression.
2009-05-19 08:38:46 -07:00
Cary R 7988ef04d8 Add support for displaying a real parameter using %d.
This patch modifies the real parameter get_value routine to use
the standard vpip_real_get_value() routine. This routine has
support for an integer and a decimal string value.
2009-05-19 08:33:02 -07:00
Cary R 61214108fe Add support for initializing outputs declared as output reg.
The standard allows an output declared as "output reg" to be
given an initialization assignment in the output declaration.
this patch adds that functionality. Specifically:

  output reg out = 1'b0;

works as expected.
2009-05-19 08:28:39 -07:00
Cary R 356a19c918 Add escaping to the stringification of macros.
Icarus support returning a string version of a macro ``<MACRO>.
The problem was that it did not escape '\' or '"' so if the
macro to be escaped had either of these it would create an
invalid string. This patch fixes this by translating these two
codes to their octal equivalent when the macro is converted.
2009-05-19 08:25:41 -07:00
Cary R f1c5b58845 Fix the %assign/v0/x1 operators for width equal negative offset case.
This patch fixes the three %assign/v0/x1 operators to correctly
notice that the select has fallen off the start of the vector
for the case that the negative offset equaled the width.
2009-05-19 08:22:12 -07:00
Cary R fad37da1dc Fix %t to work with real system functions.
Fix %t to get the real value when the argument comes from a real
valued system function.
2009-05-06 14:25:03 -07:00
Cary R 80f74d0d24 Add a warning message for some array words when dumping.
When dumping an array word the name is implicitly converted to
an escaped identifier. If this implicit name conflicts with an
explicitly created escaped identifier this patch will print a
warning message warning that the array word will conflict with
an escaped identifier.
2009-05-06 14:22:26 -07:00
Cary R d25f689f55 Vec8 delays should schedule like vec4 delays.
This patch adds code to calculate the vec8 delays using the
same method that is used to calculate the vec4 delays.
2009-05-06 14:19:37 -07:00
Cary R 42618741d9 Calculate the width of an array word correctly.
When finding the width of an array word we need to skip any word
selects for the array dimensions.
2009-05-06 14:16:21 -07:00
Cary R 9bcfc8ab6d Check for name space collisions.
This patch adds code to check for most of the name space
collisions. genvars are not checked correctly since they
are not completely implemented.
2009-04-27 18:07:03 -07:00
Cary R de75e71152 Dump the streams when entering interactive mode.
This patch adds code to automatically dump the output stream
including any dump file when entering interactive mode. When
the user typed ^C or $stop was executed.
2009-04-21 15:11:25 -07:00
Cary R 5f8f7bc6fc Add support for dumping non-constant array selects as a constant select.
Dumping array words is an enhancement that we have added to Icarus.
The problem was that if you wanted to dump the whole array you would
like to use a for loop as follows:

for (lp = 0; lp < max ; lp = lp + 1) $dumpvars(0, array[lp]);

This used to work, but some of the VPI rework broke it because it
counted on the word select to be constant. This patch restores the
functionality by converting the variable word select into a constant
word select in the calltf routine. This is done without warning and
only for the $dumpvars() routine.

Adding this functionality necessitated adding support for vpiIndex
to the &A<> routines.
2009-04-21 15:09:01 -07:00
Cary R f7fb754ee8 It is an error to select part of a scalar value.
In 1364-2005 it is an explicit error to take the select of a scalar
or real value. We added the checks for real a while ago. This patch
adds the functionality for scalar values. In the future we may want
to push the scalar property to the run time.
2009-04-21 15:02:14 -07:00
Cary R e59a6b8df7 Warn the user if they use both a default and `timescale based delay.
This patch add code to print a warning message if it finds both a
default and `timescale based delays. The -Wall or more specifically
the -Wtimescale flag can be used to find the module with the missing
`timescale directive.
2009-04-21 14:56:25 -07:00
Cary R f149a30045 Handle $stop and $finish at the interactive prompt.
This patch adds interactive support for $stop and $finish.
$stop displays a message that the simulator is already stopped.
$finish acts exactly like (calls) the interactive "finish"
command. Having $stop do nothing and $finish not finish until
you exit interactive mode is not very intuitive.
2009-04-21 14:54:44 -07:00
Cary R ddaba5b017 Print a better error message for the optional system tasks/funcs
This patch adds better error messages (compiletf) for the optional
system tasks and functions (Annex C 1364-2005). Doing this also
makes calling them fail more gracefully (it is no longer a RE).
2009-04-21 14:42:12 -07:00
Cary R dff535923f Generate better error messages for concat. with indefinite width.
This patch generates a more user friendly error message for a
concatenation with an indefinite width operand.
2009-04-21 14:38:52 -07:00
Cary R d66471c449 Add $readmempath to set a search path for $readmem{b,h}.
This patch add a new system function $readmempath. It accepts
a ":" separated list of directories that $readmem{b,h} will
use when trying to open a given file. If the file given to
$readmem{b,h} starts with a '/' (an absolute path) the search
list will not be used. A new call to $readmempath will replace
the previous search list with the given list. The search list
elements are check to see if they exist and are directories.
If not a warning will be displayed and they will not be added
to the list.
2009-04-21 14:35:29 -07:00
Cary R b16e3ab59e Allow macro expansions to take arguments with multiple arguments.
This patch allows a macro expansion to have an argument which
itself has multiple arguments (handle nested ",").
(cherry picked from commit 047828ded0)
2009-04-08 19:16:26 -07:00
Cary R d7b76e9390 Add support for recursive modules inside generate blocks
This patch adds support for recursive module loops if the
loop contains a generate block. The assumption is that the
user is doing the right thing in the generate block to make
the loop terminate. For this case there is also a check
that limits the number of loops (default 10). This prevents
the system from crashing when the user did not correctly
terminate the looping structure. The limit can be changed
by the user if needed.
(cherry picked from commit 5e723bfd61)
2009-04-08 19:12:39 -07:00
Cary R 6f692e7984 Use the port that has already been fetched.
This patch reuses the port that has already been fetched vs
fetching it again.
(cherry picked from commit a7741d2bd5)
2009-04-08 19:11:22 -07:00
Cary R dfe7279488 Check for both the library and include file when adding history.
When adding history (add_history) use both the existence of the
library and the header file to determine if history can be
supported. Add a new USE_HISTORY that is the and of these two.
(cherry picked from commit 4b2e5e5914)
2009-04-08 19:09:52 -07:00
Cary R b9ea0036de For div/mod only sign extend if both arguments are signed.
Only sign extend the operands for division or modulus if
both of them are signed. Previously only the individual
operand signedness was being considered.
(cherry picked from commit d074a37a2d)
2009-04-08 19:07:24 -07:00
Cary R fc24624fa2 Add support for empty task port lists with a warning.
The standard does not allow this, but it appears that other
simulators do. This patch adds the functionality, but prints
a warning message for the invalid task definition.
(cherry picked from commit 46350da5f0)
2009-04-08 19:05:03 -07:00
Cary R cca3d5907c Skip leading space for some codes in scanf routines.
Most conversion codes in the scanf routines are supposed to
skip leading space. This patch adds that functionality.
(cherry picked from commit e987162cb9)
2009-04-05 14:01:53 -07:00
Cary R ec809c9137 Fix constant CA delays to support two/three values.
This patch fixes the code generator to correctly create three value
constant delays. It also fixes a bug in the compiler related to the
precalculation of the high-Z delay when only two delays are given.
Previously if was using a pointer not a value comparison to find
the minimum value.

Variable delays should work when one or three values are given.
For the two value case we need to do a comparison at run time and
that will require changing the compiler/run time interface so that
can only go into the V0.10 branch. This patch can be applied to
both development and V0.9. I have added a sorry message and an
assert for this case. I will add the variable two delay case at a
later time. We also do not support mixing constant and variable
delays on a single statement. That is a much bigger change and
can wait until someone asks for it.
(cherry picked from commit b1cb80b32e)
2009-04-05 13:58:22 -07:00
Cary R 682e54841c Add support for getting the size of a real array word.
This patch adds code to get the size of a real array word.
We currently define the size if a real to be 1.
(cherry picked from commit 337c9e7577)
2009-04-03 06:56:54 -07:00
Cary R 7d2734c9cc If a PGAssign is driven by a select then make a driver.
When a PGAssign is driven by (r-value) a bit, part or indexed
select and the strength is not the default (supply). Then
we need to create a driver (BUFZ) to convey the strength
information.
(cherry picked from commit 85e2bf3e55)
2009-04-03 06:54:20 -07:00
Cary R 74df582c73 Show verireal constants with a decimal point.
When displaying a verireal constant value force the display
of the decimal point and trailing zeros. This prevents 2.0,
etc. from being display as "2". which can be confused with
decimal two.
(cherry picked from commit 74ea0ecb4a)
2009-04-03 06:51:32 -07:00
Cary R 10b8055a38 Report an error when trying to take the concatenation of a real value.
This patch adds checks in various places to prevent the user from
taking a concatenation of a real value.
(cherry picked from commit 464310f522)
2009-04-03 06:48:59 -07:00
Cary R 95848eb2f8 Enhance the real selection is invalid error messages.
This patch enhances the error messages emitted when trying to
select part of a real value. It now includes the signal name
so it is easier to debug.
(cherry picked from commit 3517f11c2c)
2009-04-03 06:45:28 -07:00
Cary R efc3bbd29e Report an error when trying to take the select of a real value.
This patch adds checks in various places to prevent the user from
taking a select of a real value (bit, part and indexed selects).
(cherry picked from commit 5852f1eb7a)
2009-04-03 06:45:04 -07:00
Cary R c56f21a20c A right shift is only signed for an ARS.
The signed_flag should only be set when the expression is signed
and an ARS is used a normal RS should never be signed.
(cherry picked from commit caab6cab9d)
2009-04-03 06:41:50 -07:00
Cary R 17210d5423 Add limited support for getting and putting to real array words
This patch adds basic support for getting and putting values to
real array words. This will be finished during the VPI rework.
(cherry picked from commit 1dbc517164)
2009-04-03 06:36:31 -07:00
Cary R b1af2f8535 Arrays can have bit selects of individual words.
The l-value code was not handling the case of a bit select for
an individual array word.
(cherry picked from commit ad39445eed)
2009-03-31 08:05:16 -07:00
Cary R aa28430832 When determining if a signal is an array use array_dimensions_
The previous code looked for more than one array word to determine
if the given signal was an array or not. The problem with this is
that a single word memory was considered a signal. This is fixed
here by looking for an array_dimension to be greater than zero.
(cherry picked from commit 3d449f60a2)
2009-03-31 07:54:27 -07:00
Cary R ceea5d568c Fix problems in rshift code.
This patch fixes the following problems in the right shift code.

The >>> result is only signed if the l-arg is also signed.

The r-arg is always unsigned.

Only sign extend the l-arg when the >>> operator is used.
This relates to an optimization for certain constant shifts.

Removed some obsoleted/outdated code.
(cherry picked from commit d7f272d14c)
2009-03-31 07:40:28 -07:00
Larry Doolittle 710ad582ed Make VHDL code generator skip over virtual pins
Fixes pr2701438
(cherry picked from commit a05ac4b5f4)
2009-03-31 07:34:19 -07:00
Stephen Williams 183137b60c BUFZ devices are strength-aware
When vvp_vector8_t objects come in, pass them out as vec8. The
BUFZ device is used in situations where this acts much like a
simple wire.
2009-03-28 10:08:39 -07:00
Cary R 9c7c719cac Use AC_HELP_STRING instead of AS_HELP_STRING.
The later causes a warning under MinGW. The former appears
to work everywhere.
2009-03-27 06:37:21 -07:00
Cary R 2f3061c158 We are deprecating the $log function in favor of $log10.
When the VAMS math functions were originally built we did a
straight copy of the log() function to $log(). This can
conflict with other Verilog-D definitions of $log. We
need to deprecate this function and remove it before the
next major release.
2009-03-27 06:32:46 -07:00
Cary R af08ff64c7 Add message the the $dumpports* task are not available
These are in the standard and we did not have error messages
for them. This patch make calling these tasks a compiletf
fatal error.
2009-03-27 06:29:44 -07:00
Cary R 036c176e8b Add the $fread() system function.
This patch adds the $fread() system function. Icarus does not
currently allow missing arguments in functions so the following
standard specified functionality is not supported:

  res = $fread(mem, fd,,count);

It also fixes a memory leak in fopen related to the get_filename
refactoring I recently did.
2009-03-26 11:51:22 -07:00
Cary R 327e8d0ec0 Use a single = in configure.in test
The ability to use == is an extension so use the more common =.
2009-03-26 11:45:11 -07:00
Larry Doolittle cfb45e56e2 Address pr2710081, version_tag.h guards
Tested with both bash and dash on Debian, has the desired effect.
No promises for cygwin.
2009-03-26 11:42:42 -07:00
Cary R 809044cbf8 Add guards in CREATE_VERSION script.
This patch adds the same guards that the other two scripts
create for the version_tag.h file.
2009-03-26 11:38:32 -07:00
Larry Doolittle 2a53255445 Add support for virtual reg arrays to tgt-stub
This patch adds support for virtualized register arrays to the
tgt-stub back end.

Based Cary's patch, but with a slightly different style.
Both work fine.
2009-03-26 11:03:42 -07:00
Stephen Williams 4205752bb0 Clean up release builder scripts.
The version.h file is generated by the Makefile, we should
prefill the version_tag.h file.
2009-03-20 14:29:18 -07:00
Cary R d237e35076 Make vvp use inttypes for the 64 bit printing info.
To get the correct print format for a 64 bit value it is much
better to use <inttypes.h> (when available) than building our
own value. This allows MinGW to use the non-standard I64.
2009-03-20 13:58:32 -07:00
Stephen Williams 90f37fe3cb Slightly more portable version of configure test. 2009-03-19 18:31:21 -07:00
Stephen Williams 4be2f61b53 Get ready for the 0.9 first release. 2009-03-19 10:17:12 -07:00
Purdea Andrei f8aa9073ac fixing: %0b format prints nothing for a 0 input
the following example returns ||. This patch fixes it to return |0|.
module t();
wire [3:0] b;
initial
    $monitor("|%0b|", b);
assign b = 0;
endmodule
(cherry picked from commit c9d2400dd0)
2009-03-19 09:11:49 -07:00
Cary R 9ea20d6677 Cleanup lxt and lxt2 EOS data.
This patch cleans up the memory allocated in the lxt and lxt2
$dumpvars routines.
(cherry picked from commit be158dd45f)
2009-03-19 09:05:05 -07:00
Cary R 9fec1f7e45 Handle zero repetition in a synthesized concatenation.
It is valid to have a repetition of zero inside a concatenation
that has other elements with a defined width. This patch adds
this functionality to the synthesize method. It also prints
an error if you try to synthesize a zero width constant.
(cherry picked from commit fa8a3d6c2e)
2009-03-17 16:04:49 -07:00
Stephen Williams c47ea0721c fix the arithmetic of multi-word division.
The Multiword division was not handling some degenerate high
guesses for the intermediate division result guess. The end result
was an assertion. Recover from this case.

(Does the addinb back of bp need to be optimized better?)
(cherry picked from commit 6715426833)
2009-03-17 16:04:28 -07:00
Stephen Williams ef12137931 Pass unsigned-ness of arithmetic operators through operands.
The arithmetic operands are signed only if both operands are signed.
If the expression is unsigned, then the expression as a whole needs
to be processed as unsigned in order to get padding right.
(cherry picked from commit c4a62dee0d)
2009-03-17 16:04:09 -07:00
Larry Doolittle 0e8a12eebf Don't make useless arrays of nexa
When a pin array is virtual, dll_target::signal() doesn't need
to make a corresponding set of stub nexa.

This patch includes new detection of oversized arrays, configurable
with the ARRAY_SIZE_LIMIT flag.  This limit only applies to devirtualized
arrays; virtual arrays are only limited by your architecture's
unsigned int type.

The concept and earlier versions of this patch have been successfully
stress-tested by multiple people.  This one causes no testsuite
regressions on my machine.

Closes: pr2023076
(cherry picked from commit 3a18bda8ee)
2009-03-15 13:54:08 -07:00
Cary R 9473e823ed You must assert a logical not NULL.
This fixes a small problem where an assert was being called
with NULL instead of 0.
(cherry picked from commit ac4cb1bbe9)
2009-03-15 13:53:55 -07:00
Larry Doolittle c75f9db315 Add user interface to pin virtualization
Flag is DISABLE_VIRTUAL_PINS.  Try to give a helpful hint for
how to work around any problems our regression testing might
have missed.
(cherry picked from commit 67381431ed)
2009-03-15 13:53:41 -07:00
Larry Doolittle 1d31a91b4f Remove valgrind errors triggered by virtual pins
NetBus wasn't initializing pin direction.
I hope Link::PASSIVE is correct for busses!
No test suite regressions.
(cherry picked from commit f344515e38)
2009-03-15 13:53:28 -07:00
Larry Doolittle b795d8c1d8 Virtualize Pins until needed
Reduces resource usage when compiling large memories.
Normal usage patterns still create large nexus arrays
in t-dll.cc:dll_target::signal().

This patch is extensively tested; it shouldn't break anything.

The existing debug "optimizer" flag is (ab)used to control
message printing when large (>1000 element) arrays are
devirtualized or nexus-ized.

The new global variable disable_virtual_pins is available
to force allocation of Pin arrays when they are declared,
but no user interface is provided.

See extensive discussion on iverilog-devel, March 4-5 2009,
title "pr2023076: large memories".
(cherry picked from commit 5bc41e1a17)
2009-03-15 13:52:57 -07:00
Larry Doolittle 5ec7731e04 Detect overflows converting to long
The code is ugly, but the results are good.
No regressions in existing testsuite, needs a new entry.
2009-03-13 15:17:51 -07:00
Larry Doolittle bb29e1d588 Drop useless CVS stuff in .txt files
Remove useless, redundant, misleading, and misspelled $Id$ and $Log$
cruft from all .txt files.
(cherry picked from commit 86bf6c447b)
2009-03-13 09:42:17 -07:00
Larry Doolittle 74fd1865cb Minor tweaks ahead of memory virtualization
Limit memory sizes to whatever fits in unsigned; crash if
the conversion from unsigned long to unsigned overflows,
instead of just wrapping.  I don't know what happens on
a 32-bit machine if you ask for an 8 Gig memory, but with
a 64-bit machine and this patch, it crashes with an assert.

Set direction on PartSelect Links before connecting them.

May or may not be considered orthogonal to upcoming
memory virtualization patches.
2009-03-09 14:46:13 -07:00
Larry Doolittle b40b6fb50d Spelling fixes
Mostly comments, but includes user-visible debug messages.
(cherry picked from commit b0c4a87133)
2009-03-09 14:44:07 -07:00
Stephen Williams 19b68f6332 Fix broken definition of is_linked().
(cherry picked from commit fff2598709)
2009-03-09 14:43:18 -07:00
Cary R c96e4da9e4 More constant function not supported warnings.
This patch adds more places that need to warn about constant
functions not being available.
2009-03-05 17:09:43 -08:00
Cary R d143597996 Add better constant user functions are not supported messages.
This patch adds messages in various places to warn that constant
user functions are not supported. It uses a global variable to
indicate when we are in a constant context. This is a bit of a
kludge, but works well without needing to change a bunch of code.

It is interesting to note that ports are elaborated late enough
that if we had the constant function evaluation code they would
evaluate correctly. This also applies to the function return
range, the concatenation repeat, specparams and initial values.

Signal definitions are early enough that elaboration is what is
failing because the function body is not available (has not been
elaborated). The same thing applies to both parameters and
localparms.
2009-02-27 21:29:54 -08:00
Cary R 82805b9351 Add compiletf routines for the scanf functions.
This patch adds compiletf routines for the $sscanf/$fscanf
functions. It does not enhance the conversion routines it
only adds better error/warning messages.

It also removed the redundant IS_MCD in some of the fileio
calltf routines. This is already checked in vpi_get_file().

I also added the vpiNetArray type to allow us to distinguish
arrays of nets from other arrays (memories). Much more is
needed here, but this solved the problem of the day. The
problem was that we needed to make sure we could assign to
the word of a variable array, but not the word of a net array.
It's actually probably not needed since Icarus converts the
net array word reference to just the net, but I thought it
prudent to make sure things didn't slip by.
2009-02-27 18:00:59 -08:00
Cary R ddea64445c More compiletf cleanup and refactoring.
This patch adds compiletf routines for the mti random functions
and adds a common routine to check for extra arguments. It also
adds file and line information to the rest of the compiletf
routines that were missing them.
2009-02-26 21:42:32 -08:00
Cary R fa1160c4ab Fix/enhance readmem/writemem routines, etc.
This patch adds compilef routines for the readmemb/h and
writememb/h system tasks. It also fixes some errors related
to arrays with negative range values. You can not specify a
negative address in the file, but arrays with negative range
values or negative start/finish argument to the tasks are
supported. It also generates an error when reading invalid
character from the input file.

A significant amount of the code is common between the two
styles of tasks so this has been grouped into common
routines.

It also adds a common routine for getting a string that will
be used as a file name. This routine is used by any task
that requires a file name value. If a filename has a
non-printable character it will be displayed as a \octal
constant to show what the character is.

Updates the dumping routines to match each other better,
improves some error messages and fixes a bug in the LXT2
dumper when dumping greater than 32 bit delays.
2009-02-26 20:46:02 -08:00
Stephen Williams fa02455f36 Delays expressions are 64bit integers.
Fix the PDelay processing to account for the fact that delay expressions
are 64bits. Use int64_t instead of unsigned long.
2009-02-25 21:30:05 -08:00
Stephen Williams c6ed0a9d2c Update the rpm spec file to handle package suffixes.
If the builder wants to build the package with an install suffix,
the %{suff} variable makes that easy. Just define that value as
needed, and there you go.
2009-02-25 14:49:16 -08:00
Stephen Williams a10bd139ab Fix dependency file (-M) generation.
The dependency file may be written by ivlpp as it loads its own
dependencies. Make sure this doesn't mess up the dependencies that
are already written by the main program. This requires that ivl,
ivlpp and iverilog (driver) cooperate on the opening of the
dependency file.
2009-02-25 13:59:28 -08:00
Stephen Williams 1c17412223 Allow constant delay literals to be handled as 64bits.
This is mostly a minor definition change in the parsing of literal
numbers by the vvp lexor. Allow for 64bit numbers in the .delay
records, and have the code generator also able to cope with the
situation.
2009-02-24 13:50:18 -08:00
Stephen Williams 2d6105a3f2 At configure time, make sure prefix, exec_prefix and libdir are OK.
Icarus Verilog internally is not white-space clean. We need to make
sure the configured paths that cause the most trouble are clean and
usable. It is still possible to mess things up downstream, but at least
this should help.
2009-02-24 09:10:10 -08:00
Cary R 158e9fd2be Keep the left and right array range value order information.
Previously Icarus normalized the results so array [7:0] would
be the same as array [0:7]. This works just fine for
simulation, but the VPI calls can select the left or right
value and this was incorrect for the [7:0] case since it was
being normalized to [0:7]. This patch swaps the two values in
the a.out file and from this creates the previous first/last
values and a new flag that can be used to get the correct
left and right values for the VPI interface.
2009-02-24 07:33:42 -08:00
Stephen Williams f1e702bdd5 Blind support for "integer foreign" attributes. (Stefan Theide)
Allows iverilog to parse attribute like syntax that a common
simuator puts into automatically generated verilog code. This
syntax cannot be found in any of the IEEE standards.
2009-02-23 16:37:34 -08:00
Nick Gasson 64e85304b5 VHDL translation for timescale
This patch generates delays with the correct VHDL units. Taking
into account the source module's timescale and precision.
2009-02-23 16:23:56 -08:00
Cary R 66ce204771 The default type of a signal is a vector.
In Icarus all signals are vectors so when asking for the vpiObjTypeVal
we need to return the vpiVectorVal.
2009-02-23 16:19:48 -08:00
Nick Gasson 5660e67b8b Support IVL_EX_DELAY in VHDL target
This patch adds a translation of 64-bit delay expressions to
vhdl_const_time objects.
2009-02-23 15:30:51 -08:00
Stephen Williams 6828620977 Properly detect wire arrays in l-values.
Wires are not allowed as l-values of procedural assignments, even if
the wire is an array. Fix the checker to detect this case event when
the l-value is an array.
2009-02-19 09:32:53 -08:00
Stephen Williams 8e4952d753 Shift of zero always returns zero.
This is an optimization that also avoids some code generator
problems downstream.
2009-02-19 09:22:56 -08:00
Stephen Williams b23825e45d Make certain all index expressions have their width probed.
It is possible for an identifier to have multiple index expressions.
(For example, a part select of a memory word.) Make sure all the
index expressions are probed for width and type.

And also, note that the unary ! returns BOOL or LOGIC, not just
the type of its operand. It is slightly different from the other
unary operators in that way.
2009-02-18 16:02:58 -08:00
Stephen Williams d94e65de4f Handle some cases of self-determined repeat concatenations.
The test_width for repeat-concatenations is tricky because it
requires the evaluated value for the repeat expression. It should
be OK to call elab_and_eval on that expression even during the
test_width for the containing expression. We'll see.
2009-02-17 11:17:32 -08:00
Cary R 5ae86bd6b4 Add support for 64 bit delays in procedural non-blocking assignments.
This patch adds support for 64 bit non-blocking delays in procedural
code. We fixed the procedural delay operator (blocking delays) earlier.
This patch mostly mimics what was done there. The continuous assignment
delay operator still needs to be fixed.
2009-02-17 10:32:11 -08:00
Cary R 93ad8ff95f Add logical support for real values and error for invalid real arguments.
This patch adds logical support for real values (!, && and ||). It
also prints an appropriate error message when a real value is
incorrectly given to an operator that does not allow real arguments
(bit-wise, reduction, shift and repeat/concatenation).
2009-02-16 12:12:15 -08:00
Stephen Williams c2d1038c29 Fix propagation of calculated TRAN values through the island.
Two bugs:
(1) propagating values through the branch accidentally also
did a part select.
(2) Not all nodes of the branch nexus didn't receive a calculated
values, even though they were all marked as done.

In the process, I cleaned up the code a bit, and documented it for
better understanding.
2009-02-16 12:07:29 -08:00
Cary R 9f0e0c6c55 Add support for the other edges in a SDF file.
This patch adds support for the other edges 01, 10, etc. These still
need to be verified in the context of IOPATHs, but they are ignored
in the timing checks and that's what was needed.
2009-02-10 11:51:36 -08:00
Cary R bb799e7e8f SDF files can have null delays.
A SDF file can have null delays and for that case you are to use
the existing delay value (do not change it). This patch adds that
functionality.
2009-02-10 11:47:04 -08:00
Nick Gasson a931eaa586 Fix another case where VHDL input may be driven
This fixes another corner case where the VHDL code generator
would incorrectly generate code that drives an input with an
output.
2009-02-09 13:44:43 -08:00
Cary R bb37607a30 Add island EOS cleanup code
This cleans up most of the memory allocated when building and
island and the branches that connect to it.
2009-02-09 13:41:54 -08:00
Cary R 284ba55764 Update the $sdf_annotate() compiletf and other fixes.
This patch updates the compiletf for $sdf_annotate() to better
check the arguments and to display the file and line location
when an error/warning does occur. It does the same for the
calltf messages. It also fixes a couple of subtle bugs.

First we need to look for a NULL string not a NULL value. The
result buffer should always be defined so will never be NULL.

Next if a scope has no modules we should return like the module
was not found (return 0) vs asserting.
2009-02-05 16:29:02 -08:00
Nick Gasson 2115e87f78 Fix VHDL naming collisions with modules
This fixes a bug where the renaming rules for modules
would generate entity names that collided with already
existing module names.
2009-02-05 14:40:47 -08:00
Cary R 0ea0bffd9a Make the addition of the local directory optional (include path).
In the past we automatically added the local directory to
the beginning of the include search path. This was found to
conflict with what other tools do so this functionality is
now only available when the -grelative-include option is
given to iverilog.
2009-02-05 08:37:33 -08:00
Cary R 87541ce335 vpi_free_object() is just a stub for vpiCallback objects.
The code was using vpi_free_object() to free a vpiCallback
object and that was creating a memory leak since this is a
do nothing routine. You need to explicitly use delete.
2009-02-05 08:23:12 -08:00
Stephen Williams 99a5d4ca9e Update mkinstalldirs to handle paths with spaces.
The newer mkinstalldirs can handle paths that have spaces in them.
While I'm at it, I also updated the Makefiles so that installation
can also work to DESTDIR directories that have spaces.
2009-02-04 08:44:22 -08:00
Cary R b959f473dc Cast away const to avoid a warning when cleaning up const data.
When cleaning up the vcd_list make sure to remove the const
qualifier before freeing the ident. This is created with strdup.
2009-02-03 14:14:25 -08:00
Cary R ec1ca8509d The cleanup of &A and &PV can nest and cleanup some VCD memory.
When cleaning up the &A<> and &PV<> we need to check if the handle
argument is a nested call to another &A<> or &PV<> if it is then
we need to also delete that construct.

We also need to cleanup the vcd_info information list.
2009-02-02 19:48:34 -08:00
Nick Gasson f89f3dcbaf More VHDL naming fixes
This handles the cases where:
    * Instance names contain leading/trailing underscores
    * Instance names contain consecutive underscores
    * Module names contain consecutive underscores
    * Module names contain leading/trailing underscores
	* Ports may be inconsistently renamed
2009-02-02 19:41:50 -08:00
Nick Gasson 501106dc92 Support named blocks with local variables in VHDL target
This patch adds code to generate process-local variables
for scopes of type IVL_SCT_BLOCK. This also handles using
the correct assignment operator (:=) for the local VHDL
variables.
2009-02-01 07:08:55 -08:00
Cary R 3f0b798ef6 More vvp EOS memory cleanup.
This patch cleans up callbacks for arrays, named events and
real variables. It also cleans up the decimal index constants
for net array words.
2009-02-01 07:05:41 -08:00
Cary R d2f4edbfbd Add a message when omitting a $Ssdf_annotate() call. 2009-02-01 07:01:49 -08:00
Cary R c8cb024cb2 Move the vvp private properties to vvp/vpi_priv.h
This patch moves the vvp private properties from vpi_user.h to
vvp/vpi_priv.h.
2009-02-01 06:55:51 -08:00
Cary R 7b1905b997 Add memory freeing and pool management for valgrind.
This patch adds code to free most of the memory when vvp
finishes. It also adds valgrind hooks to manage the various
memory pools. The functionality is enabled by passing
--with-valgrind to configure. It requires that the
valgrind/memcheck.h header from a recent version of
valgrind be available. It check for the existence of this
file, but not that it is new enough (version 3.1.3 is known
to not work and version 3.4.0 is known to work).

You can still use valgrind when this option is not given,
but you will have memory that is not released and the
memory pools show as a single block.

With this vvp is 100% clean for many of the tests in the
test suite. There are still a few things that need to be
cleaned up, but it should be much easier to find any real
leaks now.

Enabling this causes a negligible increase in run time and
memory. The memory could be a problem for very large
simulations. The increase in run time is only noticeable on
very short simulations where it should not matter.
2009-02-01 06:55:28 -08:00
Larry Doolittle 51307c0a3e Lint removal
elaborate.cc:2456: warning: suggest parentheses around comparison in operand of &
vpi/vcd_priv.c:210: warning: operation on 'idx' may be undefined

Probable behavior change.  Passes testsuite.
2009-01-29 17:35:28 -08:00
Cary R 761a15515d Cleanup allocated memory in the math functions and veriusertfs.
This patch cleans up the V-2005 and V-analog math functions to
free their allocated memory at the end of simulation. It also
modifies the veriusertfs code to do the same thing.

It also closes the VCD file at EOS.
2009-01-29 17:32:53 -08:00
Stephen Williams d4d7c14b36 Elide $sdf_anotate when specify is turned off.
Not only does this have a trivial performance benefit, it also will
prevent annotation warnings when the user turns of specify support.
2009-01-28 21:01:49 -08:00
Stephen Williams 03c31808e1 Make $sdf_annotate resilient to missing delay paths.
The $sdf_annotate function needs to handle the special (and probably
ver rare) case that there are no paths in the target module.
2009-01-28 20:44:15 -08:00
Stephen Williams cb1f4f781f Merge branch 'master' of ssh://[email protected]/~steve-icarus/git/verilog 2009-01-28 20:12:46 -08:00
Stephen Williams d7a67d6d17 Better error message about part selects on invalid objects.
Not all identifier types may have a part select, even when a bit
select is OK. Better handle that case.
2009-01-28 20:12:10 -08:00
Nick Gasson 3dadedf9b5 Fix VHDL bug where constant is assigned to input
This fixes a bug where the VHDL target would not
map ports in cases where the port was driven by
a constant.
2009-01-28 17:45:24 -08:00
Nick Gasson babc9c1352 Various signal naming fixes for VHDL target
This avoids generating invalid VHDL signal names in the
following cases:
	- The name begins or ends with an underscore
	- The name contains two consecutive underscores
	- The name is the same as a component declaration
	- The name differs from another only in case
2009-01-28 17:44:14 -08:00
Nick Gasson 497e095277 Avoid multiple declaration of VHDL temporaries
This fixes a bug where temporary variables could be declared
more than once.

It also takes out a debugging print statement I accidentally
left in the last patch.
2009-01-25 08:03:43 -08:00
Nick Gasson 308688f190 VHDL fix concatenation of std_logics
This fixes an assertion failure when taking a slice of
the result of concatenating several single-element vectors.
2009-01-25 07:59:06 -08:00
Nick Gasson 2107125545 Handle %m in VHDL $display code
Just prints a warning that it's not supported.
2009-01-25 07:55:20 -08:00
Nick Gasson ee5302cf33 Fix some more errors when reading from VHDL outputs
I forgot to modify the LPM generating code with the
last patch. This *should* now always ensure a signal
is readable before code is generated to read from it.
2009-01-25 07:50:03 -08:00
Nick Gasson 69e91e4065 Fix various problems with VHDL `buffer' port generation
This patch corrects several bugs with the generation of
VHDL `buffer' ports. The code generator should now
generate a buffer only if the port needs to be read inside
the architecture, otherwise it will stay `out'.

This also correct a bug where an output port is connected
directly to the output of an instantiated component. Generating
`buffer's would work here, but a more idiomatic VHDL approach is
to declare an intermediate signal which both outputs are connected
to. This is implemented in the patch (fixes the regression of
readout.v in the testsuite).
2009-01-25 07:49:54 -08:00
Martin Whitaker b8e350188e Fix for vvp assertion error on forward reference to array.
If an &A() operator contains a label for an array that has not
yet been declared, vvp fails with an assertion error. This
patch delays the calls to array_find() in the functions that
compile &A() operators, using the usual resolve list mechanism.
2009-01-25 07:46:36 -08:00
Cary R c419e77710 More end of simulation memory cleanup.
This patch adds some more memory freeing routines to vvp and
the vpi library. Much more to do before this is finished.
2009-01-25 07:40:28 -08:00
Nick Gasson e5ce88304e Fix mapping of VHDL expressions to function arguments
Noticed this as part of the test case for pr2516774b. Under some
circumstances the input arguments would be cast to the wrong type.
This patch ensures that all the arguments have the correct type.
2009-01-22 17:39:50 -08:00
Nick Gasson 3cc2018346 Emit VHDL hex constants for some unsigned bits strings
This patch changes the output of VHDL unsigned bit strings
which are 4, 8, 16, 32, or 64 bits to use VHDL hex string
constants.

So the following:
  "00000001"
Becomes
  X"01"

Which is much easier to read
2009-01-22 17:39:41 -08:00
Nick Gasson c787e1acd8 Fix VHDL bug where input may be driven by input
This is a fix for pr2527366 where draw_nexus would sometimes
generate code to drive an input from in an input (where they
should have been left unconnected)
2009-01-22 17:38:38 -08:00
Cary R ad3fcf3455 Fix a few memory leaks in vvp.
This patch fixes two memory leaks in the compile stage and one easy
fix in vpi/sys_display.c.
2009-01-21 19:35:47 -08:00
Nick Gasson ba8688c0d1 Fix regression of always3.1.8A with VHDL target
The patch for pr2516774 exposed a bug which caused
always3.1.8A to fail. This patch corrects that.

The test to decide when to use a sensitivity list
rather than an explicit wait statement wasn't tight enough.
2009-01-19 19:54:56 -08:00
Nick Gasson 78bc4b5d47 Fix assignment to VHDL function arguments
This patch is a fix for pr2516774.

The idea is to generate a local variable inside
a function whenever an argument is assigned to. The
variable has an initial value of the argument value
and is used in its place for the remainder of the
function. This patch also handles the case where the
argument is assigned to inside a while loop.
2009-01-19 19:50:48 -08:00
Nick Gasson e6846ea3a7 Improve memory management in VHDL target
Previously the VHDL code generator managed memory for
the AST objects by requiring that each AST element be
responsible for deleting its children. The disadvantages
of this are that it's quite easy to accidentally leak
memory by forgetting to delete a child, and no AST pointers
may be shared by multiple parents (or we'd end up with
double-deletes) -- this results in unnecessary copies of
objects being made.

There's no real need for fine-grained memory management of
AST objects since once they're allocated they tend to
persist until the code generator is about to terminate, when
they should all be freed.

This patch provides a custom new/delete operator for
vhdl_element which logs the vhdl_element objects allocated
in a std::vector (after calling the default operator new).
Once the code generator is finished a single free_all_objects
call deletes all the AST objects in one go. The custom delete
operator is required so that we can still explicitly deallocate
vhdl_element objects before the code generator completes.

There are also some allocation statistics printed at the end
when -pdebug=1 is specified.
2009-01-18 16:42:10 -08:00
Nick Gasson f9448b9dd7 Clean up VHDL debug messages
This won't produce so many useless messages, and the messages
produced should be more relevant.
2009-01-17 09:19:58 -08:00
Nick Gasson f1f9274bb9 Move VHDL global state management to a single file
The new state.cc/hh file now manages all the global
state that we maintain while generating VHDL. This
should make the code a bit tidier.
2009-01-17 09:19:58 -08:00
Nick Gasson 8043629231 Fix some cases where VHDL `buffer' ports were generated incorrectly
This actually removes generation of `buffer' for now.
2009-01-17 09:19:58 -08:00
Nick Gasson ede6acca77 Store only a single VHDL entity for each Verilog module 2009-01-17 09:19:57 -08:00
Nick Gasson 3c2080e502 Start improving performace of VHDL hierarchy generation
This should prune a large amount of the visits to scopes
in the hierarchy. In particular, only one instance of each
scope type should be visited.
2009-01-17 09:19:57 -08:00
Cary R 4b114ff783 Fix for add valid FD/MCD check to $fflush and $fclose.
This patch fixes some issues in the previous patch. Specifically
I need to use vpi_mcd_printf and some trickery was needed to
prevent the compiler from complaining about the format string.
2009-01-16 19:26:47 -08:00
Cary R c2d7ac61c2 Add valid FD/MCD checks to $fflush and $fclose.
This patch adds a check to verify the the FD/MCD is valid in these
two tasks. It displays a warning for invalid descriptors.
2009-01-16 19:26:38 -08:00
Cary R e8f91780e4 Factor out some common compiletf code in vpi/sys_display.c
This patch just factors out the common code for two of the
compiletf routines.
2009-01-16 19:20:21 -08:00
Cary R 71fdf0c849 Add/modify compiletf routines for $timeformat and $printtimescale.
Update/add compiletf routines for these two tasks. The
$printtimescale task was updated to work with more types
of objects.
2009-01-16 19:14:33 -08:00
Cary R 3e2c828778 Add missing vpiModule handle code.
Most named objects should have a vpiModule handle to get a handle
to the enclosing module. This patch adds code to get this for all
the elements that I could find that needed it.

It also adds a three more names to vpi_get_str(vpiType, ...) and
fixes a problem in the vpiLeftRange for PV signals.
2009-01-16 18:32:27 -08:00
Cary R 6f9ddea07f Keep parameters as a parameters reference for vpi calls.
For most cases just using the value of a parameter is fine, but
a vpi call can access more than the value so we want to use a
parameter reference instead of the value for vpi calls.

Strings were working correctly, integer values need some minor
code generator changes and real values needed to be pushed from
elaboration to the code generators. I also changed the default
real value comment from %g to %#g so that it is more obvious
that the value is a real value.
2009-01-16 18:21:50 -08:00
Cary R d2e7ea0b68 Convert $monitor to use string based formatting.
This completes the transition to the new string based formatting.
All the tasks now use the string formatting routines. Better
compile time checking and better messages were also added.

Also a couple of types were added to vpi_get_str(vpiType, ...)
and the calculation for vpiConstantSelect was fixed for both
the &A<> and &PV<> constructs. If the value is a plain variable
or if it is calculated in thread space we assume it is not a
constant.  This may not be true because of limitations/bugs in
the compiler (constant user functions are one known problem).
2009-01-15 19:42:42 -08:00
Cary R 22cc681073 Handle old style scope declarations correctly.
I forgot to modify the old style scope declarations so the
code was trying to free a constant string. Found in the vvp
test examples/hello.vvp.
2009-01-15 19:39:10 -08:00
Stephen Williams 8c07d3b51c Fix memory leak in vpi_put_value.
Certain paths through vpi_put_value cause a vpip_put_value_event to
be created with no path for deleting in. Add the capability in the
schedule_generic method, so that it can be delete as soon as it is
executed.
2009-01-14 20:15:50 -08:00
Cary R 185860a4f1 Make $strobe and $fstrobe use the string based formatting.
This patch modifies $strobe and $fstrobe to use the string
formatting routines. It also combines the $display/$write
and $fdisplay/$fwrite routines into one and removes the
old routines that are no longer needed.
2009-01-14 18:55:03 -08:00
Cary R 4b66ffd08c Use a static buffer when returning the vector value of a const. string.
This patch fixes vvp to use the standard static result buffer
when returning the vector value of a constant string. The
previous calloc method was creating a memory leak.
2009-01-14 18:51:36 -08:00
Cary R eddfa12569 Cleanup the lexor state information when done parsing.
This patch frees the lexor buffers when we are done parsing
the input file.
2009-01-14 18:48:44 -08:00
Larry Doolittle c6336d621e Allow building with gcc-4.4
With this small patch, building succeeds with Debian's current gcc-snapshot,
gcc (Debian 20090107-1) 4.4.0 20090107 (experimental) [trunk revision 143170]

That build shows no regressions in the test suite.  The patch does not
break building, or show test suite regressions, with gcc-4.3.

That new gcc version still emits a pile of new and arguably bogus warnings
 "dereferencing pointer '<anonymous>' does break strict-aliasing rules" for
   elaborate.cc:3422
   StringHeap.h:31
   vvp/vvp_net.h:687  (really vvp/vvp_net.h:825)
2009-01-14 18:47:06 -08:00
Cary R fb6e1c202a Update some copyright dates.
Update tgt-stub to have a 2009 copyright and a few individual files.
2009-01-14 18:45:40 -08:00
Cary R 2707a68d1b Fix more memory leaks in vvp and one in ivlpp.
This patch fixes some more memory leaks in vvp. Mostly related
to UDP compilation and one in find_scope() that was found when
testing the VPI code. The leak in ivlpp was that the define
temporary buffer not being freed when the lexor was finished.
2009-01-14 18:40:54 -08:00
Stephen Williams ea954a7ccc Merge branch 'master' of ssh://[email protected]/~steve-icarus/git/verilog 2009-01-13 17:46:49 -08:00
Stephen Williams b1aa4496ec Stub no longer references ivl_nexus_name.
The ivl_nexus_name function is deprecated.
2009-01-13 17:45:36 -08:00
Cary R c2605a5c9b Fix memory leaks in vvp and change vvp T_STRING token to be new based.
This patch fixes a bunch of memory leaks in vvp and converts the
T_STRING lexical token to be new based. There are still two
known leaks that I need to find a way to fix and likely some
unknown leaks that still need to be found and fixed.
2009-01-13 10:53:23 -08:00
Stephen Williams 8ca3ea2e83 Better handle right shift of unsized expressions.
When doing right shift of unsized expressions, pad the left operand
so that the right shift does not lose. This better accounts for the
lossless expectations of unsized arguments.
2009-01-12 19:19:00 -08:00
Larry Doolittle 5b9857fe76 Refactor two NetPins related methods
Seemingly does nothing, just refactors to create two new methods:
   bool NetPins::is_linked(void)
   void NetNet::initialize_value_and_dir(verinum::V init_value, Link::DIR dir)
and rearranges netlist.h.

This patch causes no regression in the testsuite.
It smooths the way for any attempt to address pr2023076.
2009-01-12 18:21:06 -08:00
Sreeraj.R bd5c48eccd Added gsystem-verilog gen flag and 4 additional keywords
For future system-verilog additions
2009-01-10 11:05:48 -08:00
Cary R 4f26c62207 Make the $fdisplay/$fwrite family use the string formatting.
This patch makes the $fdisplay() and $fwrite() family of task
use the string formatting code. It also adds a compiletf routine
for the tasks and a run time check that the FD or MCD is correct.
If not it fails instead of just dropping the output.

It also cleans up a couple of memory leaks and adds no argument
compiletf routines for the $monitoron/$monitoroff tasks.
2009-01-10 10:38:51 -08:00
Cary R edc4bc1923 Add the $abstime() system function from VASM-2.3.
This patch adds the $abstime() system function from VAM-2.3.
It returns the current time as a real value scaled to seconds.
2009-01-09 17:26:52 -08:00
Cary R 5cf7e26acf Finish real modulus in verireal.
Verireal had hooks for this, but had an assert(0). This patch
replaces the assert(0) with assert(gn_icarus_misc_flag) and
then used fmod() to calculate the modulus. It is the callers
responsibility to verify and report a message to the user
if the current state should not support real modulus.
2009-01-09 17:21:50 -08:00
Cary R cba8b42580 Make a plain $stime print in 10 digits (32 bits).
This patch makes $stime a unique call in display and returns
the lower 32 bits in a 10 digit field when it is called.
2009-01-09 16:58:13 -08:00
Cary R 5d7f8c9706 Update copyright in files changed in 2009
This patch updates the copyright notice in the files that
were modified in 2009. It also updates the normal programs
and the vvp target.
2009-01-08 20:03:34 -08:00
Cary R f993e78185 Make eval_tree mixed case div/mod work.
This patch makes constant mixed case division or modulus
optimize correctly. The modulus is only done if the
gn_icarus_misc_flag is set.
2009-01-08 19:56:28 -08:00
Cary R f2f7933708 Make lexical token STRING new based.
The STRING lexical token was malloc based, but then was passed
to routines that are expecting a new based result. This patch
standardizes on a new/delete based approach.
2009-01-08 19:40:50 -08:00
Cary R 7ccc9d4484 Fix some valgrind warnings and display a real parameter as a real.
This patch fixes some technically benign problems found by valgrind,
but we may as well give the values a default to make sure things
work correctly. I believe that the default I choose is the
appropriate value for the context.

The other problem is that real valued (local)parameters should be
printed as a real value like a real variable, etc. Trying to
do this as a decimal with the string formatting was causing a
memory problem. I could have fixed the routine to handle this,
but the better solution was to just display things the right way.
2009-01-08 19:34:10 -08:00
Stephen Williams a2aff77ca2 Avoid creating Nexus objects until they are really needed.
By not creating Nexus objects until necessary, we avoid creating a
lot of spurious objects. In fact, it is true that almost every
link that is created and connected to another link will create a
spurious Nexus object without this patch.
2009-01-07 22:07:08 -08:00
Cary R 2353f91693 Make the CREATE_VERSION script create the correct file.
The version tag is now stored in the version_tag.h file
and is then copied along with the VERSION into the master
version.h file by the Makefile.
2009-01-06 20:48:54 -08:00
Nick Gasson 50f11390b2 Fix VHDL value of undriven net
This ensures an undriven net has the correct value in
the generated VHDL (either '1', '0', or 'Z').

This is a fix for pr2489116.
2009-01-06 20:36:33 -08:00
Nick Gasson 02b58f6ae8 Remove some redundant code from draw_synthesisable_wait
The default draw_wait now produces code for FFs with sync
waits that should synthesise OK.
2009-01-06 20:33:34 -08:00
Nick Gasson 6047eab005 Try to generate VHDL sensitivity lists whereever possible
This patch generates VHDL sensitivity lists for sequential
as well as combinatorial processes which do not contain
a wait statement. Otherwise it falls back on the original
wait-on/until behaviour.

This should make the generated VHDL more acceptable to
synthesisers.
2009-01-06 20:33:21 -08:00
Nick Gasson 19720a0f9d Prefer sensitivity list for VHDL combinatorial processes
This patch generates a sensitivity list for combinatorial
VHDL processes if they don't contain a wait statement, and
a wait-on statement if they do contain another wait statement.

This should help synthesisers correctly identifier
level-sensitive latches.
2009-01-06 20:33:08 -08:00
Nick Gasson a0489e9208 Generate more idiomatic VHDL for some Verilog templates
In particular this improves the code generated for flip-flops
so the output can be synthesised with certain tools (e.g. Synopsis).

See the comments above draw_synthesisable_wait for more details.
2009-01-06 20:32:54 -08:00
Cary R 80e596b212 Add leading 0 support to $swrite/$sformat and $display uses this code.
This patch does a number of things.

It adds file and line number information to the strobe_cb_info
structure. This allows the $swrite and $sformat calls to reference
their location in warning/error messages.

Their compiletf and calltf routines also display file and line
number information in messages.

The $display routine was converted to use the string formatting
routine. This can be reverted by defining USE_OLD_DISPLAY. The
old code will be removed once there has been more testing.

A number of bugs were fixed that were discovered with the
$display code.

The output of some conversions, variables and system functions
were changed to match the original display code or to better
match expectation.

Leading zero support was added to the %b/%b, %o/%O, %h/%H, %x/%X,
%c/%C and %d/%D. The floating point conversions already supported
adding a leading zero.

This is the start of converting all the various display tasks to use
the string formatting code and a cleanup/update of the sys_display.c
file in general.
2009-01-06 20:23:17 -08:00
Cary R 24f2b08d08 Add verion_tag.h to the .gitignore file 2009-01-06 20:19:30 -08:00
Stephen Williams 90a4ddebba Keep source code version information in version files.
Rather then spread VERSION= defines throughout all the makefiles, put
the base version in version_base.in. Use that to generate a version.h
that includes the base version as well as the detailed version.
2009-01-05 21:43:21 -08:00
Stephen Williams eaea529c28 Delay statement times are 64bit.
In certain special cases, the compiler did not properly work with
long64 while handling delay statement times.
2009-01-05 20:22:54 -08:00
Stephen Williams 707a3ebe27 Handle ternary expressions with mixed argument types.
If the true and false alternatives are mixed types, then vectored
arguments are treated as if in a self-determined context then cast
to REAL.
2009-01-05 19:44:52 -08:00
Cary R 8eb7e4b3d4 Set real nets with no driver to 0.0.
In VAMS 2.3 real nets with no driver are defined to have a value of 0.0.
Setting them to High-Z was crashing the run time.
2009-01-02 20:56:30 -08:00
Michael Strelnikov d56bf3a5eb Added type setting of "lval" unary expressions (fix for 2459681)
Unary expressions used in left side should
   have type other IVL_VT_NO_TYPE.
   This patch solves mem[~indx] = 1'b1;
2009-01-02 20:51:12 -08:00
Stephen Williams 0b3bc81b76 Remove .cvsignore files.
We are in git now, get rid of this CVS cruft.
2009-01-02 16:06:19 -08:00
Stephen Williams b45834f074 Handle part selects with bad (xz) bits.
Part selects need to be fully defined. If not, then the resulting
expression is 'bx no matter what. The same for bit selects, when
the bit select expression is constant.
2009-01-01 16:20:41 -08:00
Stephen Williams ea938b7907 Revert "Enable -Wshadow by default"
This reverts commit 31d67fcd3e.
The concensus has been that this causes too many build problems in
the general case and what is needed instead is a way to turn on the
extra warnings for developers only.
2009-01-01 08:33:26 -08:00
Cary R f1b0a77e0f In the MinGW iverilog-vpi driver use $CFLAGS instead of CXXFLAGS.
CFLAGS has the appropriate -W flags defined while CXXFLAGS is
just the default. The script iverilog-vpi uses CXXFLAGS because
it is defined in the Makefile to have the -W flags. This
directory is C based so does not define CXXFLAGS.
2009-01-01 08:29:03 -08:00
Michael Strelnikov 1fe6c1941b Improved $display task
Added a proper zero padding to formats like %04d
2009-01-01 08:05:24 -08:00
Cary R 5b840bcd96 Add ivl_lpm_trigger to ivl.def
This is needed to allow Cygwin and MinGW to compile.
2008-12-30 09:12:22 -08:00
Cary R 24f98905aa Support a delay without a statement in nex_input().
Add code to check for a plain delay statement (just a delay).
When one is found generate a null statement and do not add it
(the null statement) to result.
2008-12-29 16:32:33 -08:00
Martin Whitaker 21f33085f0 Fix for pr2123173.
Functions that appear in continuous assignment expressions and that
have hidden dependencies or side effects need to be re-evaluated
whenever any input to the expression changes. This patch adds support
in the compiler and vvp runtime to enable this. This is currently
activated for any system function call that has no arguments. The
user may also force it to be used for any user function by passing
the option -gstrict-ca-eval to the compiler driver.

This patch also removes the -dautomatic option which was used for
gaining confidence in the code that supports automatic tasks and
functions. It is believed that the testsuite provides reasonable
fault coverage, and further tests can be added if bugs are found.
2008-12-29 16:09:33 -08:00
Larry Doolittle 31d67fcd3e Enable -Wshadow by default
The code base is almost shadow-free now, so this won't add much noise to the compiles.
Problems I know about:
 lxt{,2}_write.c:  patch sent upstream
 cflexor.c:  exposes gray area of name space boundary
2008-12-29 16:03:16 -08:00
Larry Doolittle b76c14e452 Shadow reduction part 6
Finish cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality.  Patch looks right, and is tested
to compile and run on my machine.  No regressions in the test suite.

This is the end of the simple, coordination-free patches.
The remaining shadows are special cases that will need extra attention.
2008-12-29 16:00:03 -08:00
Stephen Williams adbaaa9352 Add some more human readable strings for operand codes. 2008-12-19 17:17:39 -08:00
Stephen Williams 17c2d304b9 Merge branch 'master' into elaborate_pexor_rework 2008-12-19 16:34:11 -08:00
Stephen Williams 33044876dd Handle errors in parameter handling.
Don't crash if the user typed in an invalid parameter.
2008-12-19 16:32:44 -08:00
Cary R 9da9ed243a Make parameter up index use the real value not a pointer to the value.
When the parameter up index was being reworked someone mistakenly
used the pointer value instead of the actual value in the MSB/LSB
comparison. This obviously could give incorrect results.
2008-12-19 15:17:36 -08:00
Stephen Williams d1ce6d2535 Fix the signed-ness calculations of +- in parameter expressions.
This fixes up the elaboration of binary expressions found in
parameter expressions. Parameter expressions are special because
they elaborate early, before all the other parameters are necessarily
completed.
2008-12-18 21:33:31 -08:00
Stephen Williams cadfb2e4eb Create .gitignore file with the contents of info/exclude.
Having our users manually edit their .git/info/exclude is
tedious and this information belongs in the code repository.
So this patch creates a file .gitignore that contains the
appropriate information to exclude all the normal files
that should never be tracked in git..
2008-12-18 18:51:31 -08:00
Cary R 2288694217 Fix MinGW compilation of driver-vpi.
The Makefile.in was incorrectly changed and this broke compilation
on MinGW.  This patch basically reverts the previous changes and
uses a few more $(srcdir) paths.
2008-12-18 18:37:36 -08:00
Larry Doolittle 9ff319b39b Shadow reduction part 5
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality.  Patch looks right, and is tested
to compile and run on my machine.  No regressions in test suite.

This patch set covers C code, with the notable exception of
vpi/lxt_write{,2}.c.
2008-12-18 16:42:55 -08:00
Cary R a3a3485c85 Make casex/z conditional x/z aware.
Previously only the X/Z state of the label expression was
considered to be a don't care. This patch adds that
functionality to the conditional expression as well.
2008-12-18 16:32:08 -08:00
Cary R 09c7578d1e Clean up Makefile.in make check targets.
Some of the Makefile.in files were missing a check target.
This patch adds them where needed.
2008-12-16 19:44:29 -08:00
Cary R 26ee14c7dd Clean up Makefile.in files.
This patch cleans up the Makefile.in files.

We only need to delete config.log in the lower directories.

We reference the *.in files at $(srcdir)/

We need to make distclean for the tgt-(fpga,pal,verilog) directories.
This is to cleanup the Makefile.

Add some missing "rm -r f dep"
2008-12-16 19:42:53 -08:00
Cary R 45d46da443 Move driver/main.d to dep directory.
The driver/main.o target was missing the command to move the
depend file to the dep directory.
2008-12-16 19:41:18 -08:00
Cary R 10490029e3 Fix datarootdir and Makefile in tgt-fpga
I know we are not currently using this, but configure is building
the Makefile so it would be best if it didn't complain. This patch
adds a datarootdir target and fixes the Makefile and distclean
targets.
2008-12-16 19:40:21 -08:00
Cary R 2ce2fab1d6 cadpli.c needs to include config.h to get one of the DL defs.
cadpli will not compile correctly unless it knows which DL
interface to use. This patch makes it include config.h to get
this definition. It also cleans up the Makefile.in.
2008-12-16 19:38:38 -08:00
Cary R eea7693539 VHDL: Add initial support for non-constant casex/z label expressions.
This patch adds support for concatenation/repetition, signals and
part and bit select of signals for casez/x expression labels.
These along with the original constants can be mixed in almost any
order. Only constant selects are currently supported.
2008-12-16 19:20:04 -08:00
Cary R 8cd50c163b Make the procedural shifts work with undefined shift values.
This patch adds code to check for an undefined shift value in
the procedural opcodes. When an undefined value is found 'bx
is returned.
2008-12-16 09:11:37 -08:00
Nick Gasson 4f4191ecdd Add VHDL flag to specify maximum module depth
Specifying -pdepth=N only outputs entities that correspond
to Verilog modules found at depth < N in the hierarchy.

Setting -pdepth=0 (the default) outputs all entities.

This is for feature request 2391457
2008-12-16 09:05:33 -08:00
Stephen Williams 8e8b36ee36 Add automatic dependencies to subdirs that lack them.
The driver/ and driver-vpi/ directories lacked the -MD method of
automatic dependencies. Add it to them.
2008-12-16 09:05:17 -08:00
Stephen Williams 6b45f8899e Flatten the tree of configure scripts.
Collapse all the configure checks to a single configure script in
the root of the source tree. This makes the configure process run
a lot faster, expecially on Windows systems that are slower in general.
2008-12-13 21:42:55 -08:00
Cary R 7796a839aa Rewrite the check for windows and MinGW.
It is recommended that AC_CYGWIN not be used and under MinGW
the previous test was complaining about multiple calls to
AC_CANONICAL_HOST. The new test performs the same function
and also displays the MinGW status if we are compiling on
windows.

Also removed a AX_CCP_IDENT call in the vpi directory and
tgt-null is built by the top configure so there is no need
to try to run configure in that directory.
2008-12-12 21:10:50 -08:00
Cary R 65d5620086 Fix MinGW shared, PIC and rdynamic flags.
A native MinGW compile was not setting these to the correct
value. This patch makes them match what Cygwin uses. Adding
the -Wl,--enable-auto-image-base should make vvp load
slightly faster since it loads multiple DLL files.
2008-12-12 21:09:38 -08:00
Cary R f1e2f373ae Fix MinGW make distclean and add <file>.in dependencies.
This patch fixes the crash in MinGW make distclean. The problem
was that vpi/ and driver-vpi/ were being called twice and the
MinGW make was failing on the second call since the Makefile
was already removed.

Add a dependency on config.h and _pli_types.h in the make all
target. It is likely that only _pli_types.h was needed, but
this makes it clear that they need to be rebuilt if the .in
files change.

The lower directories that depend on the top level config.status
now have a target to rebuild the local Makefile file it the
corresponding Makefile.in changes.
2008-12-12 20:58:50 -08:00
Nick Gasson b6c4560fdc Avoid assertion failure in VHDL translate_select
This avoids triggering an assertion failure by trying to
select bits from a std_logic (which isn't a vector type).
2008-12-12 20:52:50 -08:00
Stephen Williams f7ee3fe173 Fix elaboration of part-select ports.
Verilog-1995 allows ports to be part selects of signals in the module.
Handle those cases with part select or TranVP as needed.
2008-12-11 21:35:28 -08:00
Stephen Williams dbe45159ab Merge branch 'master' into verilog-ams 2008-12-10 19:45:35 -08:00
Cary R f3c2916e1a Make a copy of the local include directory so that it doesn't get lost.
Some compilers when optimizing can overwrite the path before it is
read so make a copy of the local include directory and free it when
we are done.
2008-12-10 19:17:48 -08:00
Cary R 87972adb04 Check system() return when getting version information.
We were not checking the return of the two system calls used
to get the version information from ivlpp and ivl. This patch
adds checks and prints an appropriate message if they fail.
2008-12-10 19:12:55 -08:00
Stephen Williams d4c62309eb Treat assignment into a task port exactly like blocking assignment.
Reuse the code that the blocking assignment uses. This fixes makes
the task port input assignment work better.
2008-12-09 21:52:15 -08:00
Cary R e8b4c5be85 Check for too few buf/not port expressions.
This patch adds code to check that buf and not primitives have
at least two port expressions. An error message is printed for
this case.
2008-12-08 21:04:30 -08:00
Nick Gasson 651d208451 Remove some uneccessary zero-time waits from VHDL outputs
This patch optimises away straight line sequences like:

wait for 0 ns;
wait for X ns;

to:

wait for X ns;

This tidies up the output a bit.

It also has the effect of removing all code from initial
processes where the assignments have been extracted as
VHDL signal intialisers. (c.f. pr2391337)
2008-12-07 16:53:47 -08:00
Nick Gasson 712e08ebe8 Emit useful error message for pr2362211
This prints out an error message rather than crashing out with
an assertion failure when a function assigns to a non-local
variable, which cannot be done in VHDL.
2008-12-07 16:50:07 -08:00
Nick Gasson d689c93879 Rework VHDL assignment statement generation
This changes the assignment statement generator so that
each VHDL declaration "knows" which type of assignment
statement can/should be used on (i.e. signals must be
assigned with <=). This will help us catch cases when
we try to use, for example, := with signals. This occurs
in pr2362211 where we try to assign to a signal within
a function (where only := can be used).
2008-12-07 16:49:57 -08:00
Nick Gasson c06c49c992 Fix assignment of constant to input
If a module's input was connected to a nexus that contained
a constant driver. That constant would be incorrectly generated
as an assignment to the input *inside* the child module (instead
of an assignment inside the instantiating module).
2008-12-07 16:45:05 -08:00
Stephen Williams bcaf7355ca Remove most of the lingering CVS droppings.
Remove the #ident and $Log$ strings from all the header files and
almost all of the C/C++ source files. I think it is better to get
this done all at once, then to wait for each of the files to be
touched and edited in unrelated patches.
2008-12-05 21:48:28 -08:00
Larry Doolittle 4948875230 Allow building with gcc-4.4
With this small patch, building succeeds with Debian's current gcc-snapshot,
gcc (Debian 20081130-1) 4.4.0 20081130 (experimental) [trunk revision 142292]

That gcc also warns about the remaining #idents in
  vvp/concat.cc
  vvp/dff.h

The resulting build shows some regressions in the test suite, that
I am still investigating.  The patch does not break building, or show
test suite regressions, with gcc-4.3.
2008-12-05 20:48:25 -08:00
Cary R 0abefc61fb Fix out of range indexed part selects and negative verinum width calc.
This patch fixes fully out of range constant indexed part selects
to just return 'bx. It also adds support for constant undefined
base values which also just return 'bx.

A bug in the bit width calculation when building an unsized, signed
negative integer value was also fixed (-3 needs 3 bits not 2, etc.)
2008-12-01 21:11:33 -08:00
Cary R a84682e07d Add two missing function definitions.
This patch adds the function definitions for ivl_expr_branch and
ivl_expr_nature to the ivl.def file. This is needed to get Cygwin
and MinGW to compile correctly.
2008-12-01 21:06:18 -08:00
Stephen Williams d272a93a40 Case statements need their expresions probed.
Probe the widths of the case statement expressions. The expressions
are self-determined in that context, but the probe is needed to
setup the expression types.
2008-11-29 20:38:40 -08:00
Nick Gasson 1cc5586c4d Add debugging output to VHDL target
Prints progress when -pdebug=1 specified.

Adds a new debug_msg function to print progress messages.
2008-11-29 20:16:09 -08:00
Stephen Williams d5f1d0e9eb Seperate islands from tran/switch islands
Tran islands are a kinds of island, so seperate the tran handling
from the core island concept. This will allow for creating new
kinds of islands. (Think analog.)
2008-11-29 10:05:31 -08:00
Stephen Williams fc00bd9a5b probe expression widths of analog contribution expressions.
The expressions of a contribution statement are real valued by
definition, but we need to do the width probing anyhow in order
to resolve types and the widths of subexpressions.
2008-11-28 18:40:47 -08:00
Stephen Williams 17b937740a Merge branch 'master' into verilog-ams 2008-11-28 16:29:50 -08:00
Stephen Williams 82143edf2c Rework shift and power PExpr nodes for their special needs.
The power (**) and shift operators are different from other binary
operators because their expression width calculations rely only on
their left operand, with their right operand self-determined. Get
the handling of these operators out of the PEBinary base class to
prevent confusion.
2008-11-28 14:40:25 -08:00
Stephen Williams 69726a56b0 More self-determined expressions need width probed.
Find and fix some more expressions that are self-determined, that
nevertheless need their widths probled.
2008-11-28 11:24:42 -08:00
Cary R 2ce9841354 A power needs to use the signed (real pow) if either argument is signed.
The power operator is different in that it uses the signed version
if either of it's arguments are signed. This patch fixes the code
generator to do this correctly.
2008-11-28 10:44:31 -08:00
Cary R 6b76f76a3a Add the procedural signed power function.
This patch adds the procedural power function %pow/s for signed
values. This has bit based inputs and outputs, but uses the double
pow() function to calculate the value.
2008-11-28 10:33:45 -08:00
Stephen Williams 38abe7185d Fix calculation of verinum==verinum
This test was way to picky about the widths of the arguments. In real
tests, the arguments may have different widths. This especially matter
when comparing unsized values.
2008-11-27 20:14:27 -08:00
Stephen Williams bd754b24f4 Support direct nesting of conditional generate schemes.
Verilog generate schemes support a special case where conditional
generate schemes that contain only a nested conditional generate
scheme do not create a new scope. Instead, it relies on the nested
generate scheme to generate the scope.
2008-11-27 19:45:22 -08:00
Stephen Williams 90bfebd578 During test_width is not the time to assert on no_type
unary expressions that have problems should not assert in the
test_width method. Instead, let the error propagate back and be
handled during expression elaboration. This found a few places
where expression widths/types weren't probed before elaboration.
2008-11-26 15:37:38 -08:00
Nick Gasson 4263f791f6 Fix part select of width-1 vector
Signals of width 1 are declared in VHDL as std_logic, as this
is the usual way to represent them. Unfortunately, we cannot
distinguish between

reg [0:0] a;

and

reg a;

This patch avoids trying to slice a std_logic so a[0] is equivalent to a.
2008-11-26 13:14:27 -08:00
Stephen Williams 21552447a1 The iverilog-vpi script depends on the Makefile
Building the iverilog-vpi script involves editing commands in the
Makefile, so it makes sense for iverilog-vpi to depend on it.
2008-11-25 18:55:36 -08:00
Cary R 4c28af4c36 Update Makefile.in to have current version by default.
This patch removes the CVS ident information from the Makefile.in
files it also puts in the current version 0.9.devel for the default
VERSION definition. This is normally passed down, but a local make
will use the value from the local Makefile. This will eventually be
replaced with a file based version to give us just one place to
reliably modify the version.
2008-11-25 16:42:32 -08:00
Stephen Williams 34eb3e55cd Merge branch 'master' of ssh://[email protected]/home/u/icarus/steve/git/verilog 2008-11-25 16:38:44 -08:00
Stephen Williams 5660e0ed8b Install header files in includedir/iverilog
Move the header files from includedir/verilog to .../iverilog
because the verilog name is a little too generic. The iverilog-vpi
command should handle the changes.
2008-11-25 16:38:09 -08:00
Cary R 8c4a080754 Put a version in the vvp file and have vvp verify compatibility.
This patch makes the code generator put the compiler version
information in the vvp output file. It also adds checks in vvp
to verify that this version is compatible with the run time.
I am assuming that a base release 0.9.0, etc. will have a
blank VERSION_TAG. Any change relative to the release will have
a VERSION_TAG.
2008-11-25 08:01:06 -08:00
Larry Doolittle fcd39fd0a1 Restore pristine builds
Commit 24827c4b42 broke
pristine builds.  Touch up CPPFLAGS so tgt-vvp/vvp.c
and tgt-vhdl/vhdl.c can find version.h when building
out-of-tree.
2008-11-24 22:07:51 -08:00
Stephen Williams 16e5197325 Branches are parts of islands.
Expose the island information for branches to the ivl_target API.
2008-11-24 22:00:33 -08:00
Stephen Williams 87177087c4 ivl_target.h access branch terminals
Fill in the functions to add branch terminals, and add code in the
stub to check that the terminals are present and reasonable.
2008-11-23 22:38:33 -08:00
Stephen Williams d8ec6fc42a Add functions for targets to scan disciplines.
The disciplines are, from the perspective of the ivl target, collected
into the design. Add functions for the target to scan the disciplines
in the design.

In the process, also clean up the handlng of design constants.
2008-11-23 21:29:54 -08:00
Stephen Williams 6185556ef5 Merge branch 'master' into verilog-ams 2008-11-23 08:24:34 -08:00
Stephen Williams 4de891d096 Support drawing some select expressions in place.
Select of signals is natural for evaluating in place, if possible.
Doing so can save instructions for certain expressions.
2008-11-22 21:17:05 -08:00
Stephen Williams 83a7497912 Lor takes advantave of STUFF_OK_47
It is ot uncommon for the arguments to logical or to leave stuff
in bit registers 4-7. Allow the lor itself to take advantage of
that to save some %mov instructions.
2008-11-22 10:45:15 -08:00
Stephen Williams bc8b97dbcd Pad expression in place
When padding expressions, pre-allocate the target space and calculate
the sub-expression directly into the target. Then pad from there. This
saves a move into the result space.
2008-11-21 21:12:40 -08:00
Stephen Williams f502d4c8ad Specify support off by default.
The specify support has some interesting bugs, and anyhow is rarely
used. Leave it OFF by default.
2008-11-20 21:01:33 -08:00
Cary R 45f2d68d33 Add verilog<suffix> to MinGW iverilog-vpi tool
When changing where the include files were located the MinGW
iverilog-vpi tool was missed.
2008-11-20 19:59:05 -08:00
Cary R 6f1887bf1c Remover @ident_support@ fro tgt-null/Makefile.in
This was missed in the previous patch.
2008-11-20 09:51:43 -08:00
Stephen Williams 27f4ba2e38 Remove the unused CVS ident support in the configure scripts. 2008-11-19 21:07:34 -08:00
Cary R 4fa2223832 Fix NULL and STUB -V output.
Fix the NULL and STUB target -V output to match the other targets.
2008-11-19 20:45:42 -08:00
Cary R e416fb6486 Add converter info to VHDL output.
This patch adds some converter information to the VHDL output.
2008-11-19 20:44:34 -08:00
Cary R 24827c4b42 Add a -V flag to the runtime and update the manual pages.
This patch adds a -V flag to the runtime to print version information.
It also updates the manual page to document this and makes some minor
changes to the iverilog an iverilog-vpi manual pages.
2008-11-19 20:40:30 -08:00
Cary R c9077bd0be For scheduled put values save the string and free it after the put.
Users expect that vpi_put_value() will keep a copy of the string
that is passed to it. This patch implements this buy copying the
string and then freeing it after the actual put_value call.
2008-11-19 20:21:03 -08:00
Stephen Williams a288b0180c Fix concatenations losing track of its repeat values.
In some cases, it was possible for the NetEConcat expression to
lose track of the repeat expression, causing the output result to
have a broken concatenation expression.

This also adds some internal checks that the concatenation widths
add up properly.
2008-11-19 13:28:50 -08:00
Cary R 5eaea58209 Update GNU address in -V output and add -V stub to VHDL target.
This patch updates the GNU address in the -V output, adds the
VERSION_TAG info to the tgt-vvp back end and adds the whole -V
hook to the tgt-vhdl back end.
2008-11-18 20:33:22 -08:00
Cary R cedbdb63fa VHDL make comment for temporaries unique.
Make the comment for local signals (temporaries) unique from
normal signals.
2008-11-18 20:28:28 -08:00
Cary R 3c4b9692a6 Pads and local signal file/line should be related to creation location.
When padding a signal or when creating a local signal the file and
line information should be related to where the new object was
created not the signal value it is being created from.

This patch modifies the NetE* pad_to_width() routines to take a
LineInfo object to set the location to the correct value.

It fixes some set_line() calls to use the correct location.

It fixes ports to not set the file/line information if it is
already defined. Doing this was causing the definition of
signals to become the instantiation instead of the real
module declaration.
2008-11-18 20:24:19 -08:00
Stephen Williams 1630c41d5f Merge branch 'master' of ssh://[email protected]/~steve-icarus/git/verilog 2008-11-18 20:10:43 -08:00
Stephen Williams 5e174f54ee Elaborate signals in generated named blocks.
Named blocks create scopes, and generated named blocks' scopes can
have signals declared in them. So the elaborate_sig for the generate
scheme needs to call the elaborate_sig for the processes as well as
the obvious gates and tasks/functions.
2008-11-18 20:10:10 -08:00
Stephen Williams 7ec86757c5 Elaborate concatenation expression put tested widths to use.
Concatenation expressions need to use the tested widths of its
argument expressions during elaboration.
2008-11-18 16:52:05 -08:00
Stephen Williams dafe61b0f9 Update for s20081118 snapshot 2008-11-18 15:37:42 -08:00
Nick Gasson 7529034c7a Fix incorrect temporary size with padding
Fix for pr2224949

The compiler generates a concatenation LPM to zero-pad ports when the
signal widths don't match up. However, when the VHDL generator generated
the input signals to this LPM it incorrectly sized them to be the width
of the result.
2008-11-18 15:00:00 -08:00
Cary R ec0e718151 VHDL: make casez support 'x' and handle a full don't care case.
The VHDL converter erroneously treated a casez and casex exactly
the same. In reality a casez compares a 'x' value (it is not a
don't care). It also adds support for a full don't care case by
just returning True for the condition.
2008-11-18 14:42:36 -08:00
Stephen Williams 35e0a98732 Improve error message about signal type conflict.
When the parser detects a signal type conflict, print a more useful
error message. In the process, be more careful with what line number
is actually attributed to the declaration.
2008-11-18 14:34:34 -08:00
Cary R 3190066013 Remove old real array word debug message.
This message appears to be left over from the original implementation
of real array words.
2008-11-18 13:28:08 -08:00
Cary R 95065819f1 Evaluate constant negated reductions.
This patch adds support for calculating the negated reductions
(~&, ~| and ~^) in the compiler when given a constant argument.
2008-11-17 19:55:41 -08:00
Cary R e191fcdd28 A non-negated reduction needs to change a 1'bz into a 1'bx.
In a procedural single bit non-negated reduction (&, | or ^)
we need to translate a 1'bz to a 1'bx. The easiest way to do
that is with two %inv opcodes. This patch modifies the code
generator to do this for this very special case.
2008-11-17 19:55:25 -08:00
Cary R a8a8d3ce5b Fix MinGW suffix configuration.
In the driver-vpi file we need to use g for the suffix replacement
so that both libraries get changed.

Also added an end line to the config.h.in file.
2008-11-17 19:45:21 -08:00
Stephen Williams 4bc90f7cfd Create support for the --enable-suffix configuration option.
This configure option causes the installed commands to have
a suffix string that makes them distinct from other versions
that also have a suffix string. This allows for multiple
installed versions of Icarus Verilog.

Also, move installed C/C++ header files into a subdirectory of
their own under the target include directory, to make clearer
the purpose and source of those files.
2008-11-17 07:22:46 -08:00
Stephen Williams e98f29e96f Merge branch 'master' into verilog-ams 2008-11-16 18:42:06 -08:00
Larry Doolittle e0a1b41b37 Correct and enhance some debug_elaborate messages
Make port number self-consistent, starting at 1.
Add messages marking the start and stop of recursive elaboration.
2008-11-16 18:01:23 -08:00
Larry Doolittle fe38f7a9a9 Quiet compiler warnings
Eliminate three "warning: suggest parentheses around assignment used as truth value"
Obviously not needed, but it's easier to add the superfluous parentheses
than remember that these warnings are benign.
2008-11-16 17:57:50 -08:00
Stephen Williams 4892e93a09 Fix special case that one of the arguments of a compare is a real expression.
If one of the arguments of a comparison expression has a real value, then
the expression with is 1 no matter the width of the other argument. This
means that the arguments may have different widths in this special case.
Patch is from pr2251119, suggested by Martin Whitaker.
2008-11-15 21:42:02 -08:00
Martin Whitaker a42eb5cf94 Improved automatic variable error reporting.
This patch moves the checks for automatic variables being passed to
the $monitor or $strobe system tasks from the calltf routine to a
new compiletf routine. It also adds the file name and line number
of an offending call to the error message.
2008-11-15 20:48:41 -08:00
Nick Gasson 1d4ade80b2 Fix select from non-variable-reference error (pr2281519)
VHDL can't select bits from arbitrary expression so sometimes
translating IVL_EX_SELECT would fail. This is easily fixed by
replacing the select with a shift in this instance (and the
resizing)
2008-11-15 20:39:00 -08:00
Martin Whitaker fe199a7593 Fix for pr2276163.
The VVP %join function was incorrectly treating the return from a
non-automatic function as a return from an automatic function in
the case that the non-automatic function result was being used as
a parameter to an automatic function. This patch fixes this error.
2008-11-15 11:04:51 -08:00
Cary R 407ce5e152 Add support for the 1364-2001 generate of a named block.
This is obsolete in 1364-2005, but is supported 1364-2001.
Icarus already supported generate with unnamed block.
2008-11-15 08:08:29 -08:00
Larry Doolittle 1d41037009 Avoid crash with typo in varaible name
A simple typo in the rhs of an expression would crash the compiler.
Example:

module crash3;
reg clk;
integer cnt1=0;
always @(posedge clk) begin
        cnt1 <= (cnt==81) ? 0 : (cnt1+1);
end
endmodule
2008-11-14 22:29:09 -08:00
Stephen Williams 574c8a870d Merge branch 'master' of ssh://[email protected]/~steve-icarus/git/verilog 2008-11-14 22:18:20 -08:00
Cary R c278b4e41f Add support for arrayed instances with inout ports.
A NetTran (TRAN_VP) can be used to connect arrayed instance inout
ports. This allows bi-directionality and conflict resolution.
2008-11-14 22:13:41 -08:00
Stephen Williams 91972cd9a1 Merge branch 'master' of ssh://[email protected]/~steve-icarus/git/verilog 2008-11-14 21:53:01 -08:00
Cary R dc6a9e03c9 Shifting a signed constant should just return the L-value.
We already covered the case of shifting zero, but the case of
shifting a signed constant was missed.
2008-11-14 21:48:09 -08:00
Cary R 221b83b932 Rework $plusarg routines.
This patch addresses a number of issues:

Rewrote the $test$plusargs and $value$plusargs routines to have
better error/warning messages, to support runtime strings, to
correctly load bit based values (truncating, padding, negative
value), added support for the real formats using strtod() and
added "x/X" as an alias for "h/H" to match the other part of
Icarus.

Rewrite the vpip_{bin,oct,hex}_str_to_vec4 routines to ignore
embedded "_" characters. Add support for a negative value and
set the entire value to 'bx if an invalid digit is found. A
warning is printed for this case.

Rewrite vpip_dec_str_to_vec4 to ignore embedded "_" characters,
to support a single "x" or "z" constant and to return 'bx if an
invalid digit is found. A warning is printed for this case.

It simplifies the system task/functions error/warning messages.

It removes the signed flag for the bin and dec string conversions.
This was not being used (was always false) and the new negative
value support makes this obsolete.

Add support for a real variable to handle Bin, Oct, Dec and Hex
strings. They are converted into a vvp_vector4_t which is then
converted to a real value.

Add support for setting a bit based value using a real value.

Removed an unneeded rfp signal in vpip_make_reg()
2008-11-13 15:56:29 -08:00
Martin Whitaker 69428bb050 Fix for pr2271367.
This patch fixes a bug introduced by one of the checks for illegal
use of automatically allocated variables.
2008-11-13 15:52:17 -08:00
Nick Gasson 256454960c Add complete list of VHDL reserved words
make_safe_name now makes sure a VHDL signal is never given a
name that conflicts with any reserved words. If it does, we
just prepend VL_.

(This code was already present, but the full list of reserved
words wasn't.)
2008-11-13 15:45:41 -08:00
Stephen Williams d06092d7d7 Merge branch 'vhdl' 2008-11-13 15:45:37 -08:00
Martin Whitaker 416bd35f2e Fix for leak in thread vector allocation.
In the vvp code generator, when zero/sign extending a sub-expression,
the sub-expression is first evaluated and stored in one location in
the thread vector store, then is copied and extended into a second
location. The storage used for the initial sub-expression evaluation
is never deallocated.
2008-11-12 22:12:00 -08:00
Stephen Williams 87654f8661 Fix bug generating code for shift of constant zero.
The code generator detects this case, but instead of returning the
constant zero, it breaks out and writes partial code for the shift.
2008-11-12 21:46:23 -08:00
Stephen Williams 9f2b5cd9b7 Make the associative sum constant elimination more resilient to size details.
The NetEBAdd::eval_tree method is able to use the associative property
of addition to reduce some constants, but it is picky about widths.
Make it a little bit more resilient to expression widths.
2008-11-12 20:59:10 -08:00
Nick Gasson 5fd32937f2 Fix overly restrictive check for slices
Fixes some instances of "can only select from a variable reference"
2008-11-12 22:26:44 +00:00
Nick Gasson f1a2e71aab Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl 2008-11-12 22:15:57 +00:00
Stephen Williams 7c50c9aedf Scan concat arguments with test_width.
Even though we cannot immediately give a width for a concatenation
that has a repeat expression (the expression must be evaluated first)
we still must scan the test_width of the arguments so that they can
resolve their types.
2008-11-11 21:09:19 -08:00
Martin Whitaker 04377151bc Checks for illegal use of automatically allocated variables.
This patch adds a number of compile and run-time checks for illegal
uses of variables declared in automatic tasks and functions. It
also adds a check for event expressions in automatic tasks that use
features not yet supported in VVP.
2008-11-11 20:45:19 -08:00
Stephen Williams da85c4fe00 Give the branch access expression type some meat.
In the ivl_target API, the IVL_EX_BACCESS expression type gets some meat,
specifically references to the branch it accesses and the the nature to
be accessed on that branch.
2008-11-11 20:41:14 -08:00
Stephen Williams 35a8d42741 Merge implicit branches.
Implicit branches all really are the same branch, so be careful to not
create a new branch if it already exists.
2008-11-10 21:19:30 -08:00
Stephen Williams 00df651c5f Branch references all the way down to the stub generator.
This includes enough API to get the branch nexus bits and signals
and show them in the dump. This also includes creating the reference
ground for branch access functions that use the implicit ground.
2008-11-09 21:42:12 -08:00
Stephen Williams 25201954d3 Bring branches forward as far as the emit method and target_t. 2008-11-09 17:11:04 -08:00
Stephen Williams 0da27a2f45 Collect analog branches into islands.
Discipline islands all along were intended to carry collections of
analog branches, as well as the current switch modeling support.
2008-11-09 15:32:50 -08:00
Stephen Williams 988fc70368 Merge branch 'master' into verilog-ams 2008-11-07 20:14:43 -08:00
Cary R bbdf622ea5 Fix numerous problems with the divide and modulus operators.
This patch fixes a number of problems related to the divide and
modulus operators.

The net version (CA) of modulus did not support a signed version.

Division or modulus of a value wider than the machine word did
not correctly check for division by zero and return 'bx.

Fixed a problem in procedural modulus. The sign of the result is
only dependent on the L-value.

Division or modulus of a signed value that was the same width as
the machine word was creating an incorrect sign mask.

Division of a signed value that would fit into a single machine
word was not checking for division by zero.

Division or modulus of a wide value was always being done as
unsigned.

Added a negative operator for vvp_vector2_t. This made
implementing the signed wide division and modulus easier.
2008-11-07 19:58:00 -08:00
Stephen Williams 4879b98b3a Merge branch 'master' into verilog-ams 2008-11-07 19:49:52 -08:00
Stephen Williams 13aaaab783 Bring analog contribution statements to the ivl_target API.
Add support for analog processes with analog contributation statements
all the way down to the ivl_target code generator API.
2008-11-06 21:31:34 -08:00
Cary R 1e06a2ddef ivlpp - clear lexor dynamic state information for flex >= 2.5.9
For flex version 2.5.9 and later there is a function
"yylex_destroy()" that clears any space dynamically
allocated by the scanner.
2008-11-04 16:01:47 -08:00
Cary R 049290d0fc Fix a memory leak and release all dynamically allocated memory (ivlpp)
This patch fixes a minor memory leak in ivlpp and releases all
dynamically allocated memory before the program exits. Other than
the dynamically allocated push state buffer in flex, ivlpp has no
valgrind memory errors or warnings.
2008-11-04 11:58:49 -08:00
Cary R 4c67bd0b35 Fix memory leak and free temp. file names to make valgrind happy.
There was a memory leak in the preprocess_only code (cmd was not
being freed when the command completed successfully.  Valgrind
was also marking the temporary file names as still reachable, so
they are not memory leaks, but freeing them makes valgrind happier.
2008-11-04 11:41:31 -08:00
Stephen Williams 4f7457fcec Merge branch 'verilog-ams' 2008-11-04 11:37:58 -08:00
Cary R 95ea159e75 Print `include comment after included text.
The inline comment text that appears after an `include directive
should appear after the included text not before.
2008-11-04 11:26:27 -08:00
Stephen Williams 0d88d3a798 Enforce that l-value of contribution is an access function. 2008-11-03 21:58:16 -08:00
Stephen Williams eb240ddb73 Bring discipline natures all the way to the ivl_target API.
The natures of disciplines were already available, this just brings
the information forward to the ivl_target.h API and exposes them via
access functions.
2008-11-03 21:10:10 -08:00
Stephen Williams c73199942b Proper test_width implementation for nature access functions.
Nature access functions have fixed output width and type. Implement
the test_width handling for access functions to reflect this.
2008-11-02 21:46:27 -08:00
Stephen Williams ddb2c60701 Remove svector class from Module.h
The goal is to completely remove the svector class because the standard
vector class works perfectly well. This removes the uses in the Module.h
header file.
2008-11-02 20:08:38 -08:00
Stephen Williams 77eb68d314 Minor documentation improvements. 2008-11-02 16:56:25 -08:00
Stephen Williams f4687757f1 Bring signal discipline all the way to the ivl_target API.
Signals may have VMA disciplines attached. Make the attached discipline
visible through the ivl_target.h API. Also, re-arrange the internal
handling of the discipline structure so that we can expose disciplines
through the ivl_target C API without creating new structures. The
t-dll-api implementations of the discipline access functions can look
at the elaborated discipline structure directly. This is possible since
the discipline parse and elaboration are very simple.
2008-11-02 08:10:41 -08:00
Stephen Williams b20019d8b6 Merge branch 'master' into verilog-ams 2008-11-01 21:09:29 -07:00
Stephen Williams 6cac1d2cab Add support for real/realtime arrays.
Support arrays of realtime variable arrays and net arrays. This
involved a simple fix to the ivl core parser, proper support in
the code generator, and rework the runtime support in vvp.
2008-11-01 20:44:03 -07:00
Larry Doolittle 520d9b9dd0 Touch up new developer quick start
Spelling and other minor touch-up for the new and
much-appreciated developer-quick-start.txt
2008-10-31 20:44:54 -07:00
Stephen Williams 403a1e9415 Add a dup_expr method to NetEUBits.
The NetEUBits needs to create a NetEUBits when the dup_expr method is
called, so it needs its own dup_expr method.
2008-10-30 22:11:05 -07:00
Larry Doolittle 9b640f3114 Shadow reduction part 4
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality.  This patch set covers the tgt-vhdl
directory, and was tested by Nick.
2008-10-30 21:46:44 -07:00
Cary R 7ac35e478b The scope of real values needs to be calculated.
Finding the scope of a real value is no longer simple, so it must
be calculated.
2008-10-30 21:41:36 -07:00
Cary R 2c7fe8aa2a Fixes for real VPI interface, etc.
This patch fixes some problems found when trying to dump words
from a real wire array. There are still a few more things that
look suspicious and need testing.
2008-10-30 21:41:28 -07:00
Stephen Williams 1ec09327e9 Elaborate divide expressions to the proper width.
If the operands of a divide expression are fixed width, pad them out
to the width of the expression so that the calculations come out right.
2008-10-30 21:19:56 -07:00
Nick Gasson ea9bbf804c Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl 2008-10-30 20:00:53 +00:00
Stephen Williams 1922a0df9e Fix C++ compiler warning.
classes with virtual methods must have virtual destructors. Otherwise,
destruction may not work corectly.
2008-10-29 21:03:44 -07:00
Martin Whitaker 18edf2f15f Rework of automatic task/function support.
This patch splits any VVP net functor that needs to access both
statically and automatically allocated state into two sub-classes,
one for handling operations on statically allocated state, the
other for handling operations on automatically allocated state.
This undoes the increase in run-time memory use introduced when
automatic task/function support was first introduced.

This patch also fixes various issues with event handling in automatic
scopes. Event expressions in automatic scopes may now reference either
statically or automatically allocated variables or arrays, or part
selects or word selects thereof. More complex expressions (e.g.
containing arithmetic or logical operators, function calls, etc.) are
not currently supported.

This patch introduces some error checking for language constructs
that may not reference automatically allocated variables. Further
error checking will follow in a subsequent patch.
2008-10-29 20:43:00 -07:00
Stephen Williams ea057a7574 Elaborate logical and/or to account for special properties.
The arguments of logical and/or are self determined, and the width is
fixed as 1 bit. Account for this special behavior by creating the
PEBLogic class.
2008-10-29 20:31:26 -07:00
Stephen Williams b7d3276e4d Enforce bit width of operands of comparisons operators.
The comparison operator operands are self determined, but are forced
to be the width of the wider operand. This means that the operands must
be evaluated with their widths truncated. In spite of all this, note
that comparisons expression results are 1 bit wide.
2008-10-29 19:34:44 -07:00
Cary R 22ddb26389 Add support for arrays of real nets.
This patch adds support for arrays of real values nets (wire real).
2008-10-27 21:45:02 -07:00
Stephen Williams 9b89ca49bb Merge branch 'master' of ssh://[email protected]/~steve-icarus/git/verilog 2008-10-27 21:39:47 -07:00
Stephen Williams 94e7d71b97 Make sure divide expressions are evaluated using the expression width.
The operands of divide need to be at least the width of the expression
when calculating a constant divide. The only matters for the special
case where the result is x, because the verinum implementation of
divide will get the result width from the left expression width.
2008-10-27 21:39:07 -07:00
Stephen Williams 810686d88e Merge branch 'master' into verilog-ams 2008-10-27 09:23:13 -07:00
Stephen Williams 0bd1739225 Merge branch 'vhdl' 2008-10-27 09:19:13 -07:00
Stephen Williams 038b024e71 Merge branch 'master' into verilog-ams 2008-10-26 21:59:53 -07:00
Stephen Williams 27410f5d88 Remove the now obsolete NetNet list in NetScopes.
Now that NetNet objects in NetScopes are kept in a map, remove the
linked list for scanning them. This improves the lookup process from
an O(e**N) process to more like O(log(N)). This matters for very
large designs.
2008-10-26 20:42:11 -07:00
Stephen Williams 0af896a7ff Keep a map of NetNets for fast access.
It turns out that netnets in scopes are accessed a lot, and mapping
them may help with performance.
2008-10-26 16:50:46 -07:00
Stephen Williams 81a0007f22 Add developer quict start.
Some basic documentation to help new developers get oriented.
2008-10-26 16:34:21 -07:00
Stephen Williams 2a5ea9e874 Remove the vpip contents.
These files are (were) related to the old vvm backend that is no longer
in use. Thus, these files are dead code.
2008-10-26 14:29:09 -07:00
Stephen Williams b9272f750d Update the BUG submission guidlines. 2008-10-26 13:43:35 -07:00
Nick Gasson f49a4e4336 Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl 2008-10-26 12:48:22 +00:00
Cary R 26e1693b2f generate case items can have an optional statement.
generate case supports optional statements by putting
 a ';' in place of the statement. This patch adds
this functionality for all generate case items.
2008-10-25 23:27:00 -07:00
Stephen Williams 68fbb94b3a Basic elaboration of analog contribution statements.
Get at least basic elaboration of analog processes and contribution
statements. Bring the statements and analog statements together and
net future elaboration work sort out which statements are valid in
a given context. This makes sense because there really is a lot of
syntactic overlap, and analog behavioral code is processed somewhat
sequentially.
2008-10-22 21:56:00 -07:00
Stephen Williams 5aa810dde7 Infrastructure for elaborating analog statements.
Put together the infrastructure for elaborating analog statements,
including create the NetAnalogTop objects that hold analog statements
and are in turn held by the design.

While doing this, clean up the various unique initial/always enumerations
to use the ivl_process_type_t type.
2008-10-21 22:15:49 -07:00
Larry Doolittle 365960df9d Spelling fixes
No code changes.
2008-10-21 19:55:19 -07:00
Cary R 644465ccc1 Remove one input is const. Z mux optimization.
The optimization that allowed a mux that had one input always
connected to high-Z produces code that is actually slower than
the original mux, so for now we are removing that optimization.
2008-10-21 19:51:07 -07:00
Larry Doolittle 904e76f176 Shadow reduction part 3
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality.  Patch looks right, and is tested
to compile and run on my machine.  No regressions in test suite.
2008-10-20 21:43:02 -07:00
Cary R de2b10b445 An optimized mux should use MOS devices not bufif devices.
The bufif devices do not correctly propagate the Z value as
required by the standard. The MOS devices do propagate a Z
value, but they do not correctly handle the case where both
inputs are Z and the select is undefined/Z. The standard
specifies that this should be X, but we produce Z. The full
MUX and %blend operator also function this way, so Icarus
may not match the standard, but it is consistent. I would
also argue that the standard is incorrect. If both inputs
are Z then the output should be Z no matter what select is.
2008-10-20 21:34:00 -07:00
Stephen Williams a654bdc169 Clean up some handling of test_width for ternary expressions.
The condition expression needs its width tested, even if the width
is not used. Also clean up some handling of widths/types for other
expression types.
2008-10-18 22:00:22 -07:00
Martin Whitaker cb2ed9210c Fix for pr2169870.
This patch fixes a bug which prevented storage being allocated for
automatic tasks that had no input or output parameters.
2008-10-16 21:06:38 -07:00
Cary R 50550ca79e Fix %ix/getv and %ix/getv/s documentation.
These two operators had their arguments wrong.
2008-10-16 21:03:00 -07:00
Larry Doolittle f3cb18343a Conditional test width
Add the test_width call for PCondit expr_
Very similar to commit 5fdd9d8339
2008-10-16 21:00:36 -07:00
Cary R c6a5a43620 Fix port signedness calculation.
This fixes the sign calculation for port padding. It also reports if
the padding will be signed or not in the warning message. The inout
calculation may not be correct. It requires both the signal and the
port to be signed, but inout is not currently padded anyway.
2008-10-16 20:55:09 -07:00
Cary R b0e57a1a67 Ignore PS that are outside the signal and allow PS to extend past the signal.
If a part select (either a constant or constant indexed part select)
of a L-value is fully outside the signal the part select will be
omitted after printing a warning. If a part select straddles the
upper portion of a signal a warning will be printed. The run time
will use only the appropriate part of the select. Straddling the
lower part of the signal is not currently supported and a message
is printed for this case.
2008-10-14 19:47:55 -07:00
Stephen Williams 5fdd9d8339 Test the width of expression for shift amounts.
The right-operand of shift expressions is self-determined, but we still
need to run a test_width to get the PExpr decorated with types and
expression widths.
2008-10-14 19:36:48 -07:00
Nick Gasson 8a3309d79d Add a comment to the output about casex/z translation 2008-10-14 20:21:19 +01:00
Nick Gasson a47b7352b4 Add casex/z support
A casex statement cannot be directly translated to a VHDL case
statement as VHDL does not treat the don't-care bit as special.
The solution here is to generate an if statement from the casex
which compares only the non-don't-care bit positions.
2008-10-14 20:16:10 +01:00
Stephen Williams fff5e494ed Do not truncate subtraction expressions based on l-value.
The l-value doesn't really constrain the size of unsized expressions
because there are possible sub-expressions that may pull high bits
down to the low bits. (Divide, for example.)
2008-10-13 22:06:03 -07:00
Stephen Williams 1c90997499 concatentations that reduce to constants need proper signed-ness
It is possible, via the use of the $signed() function, for concatenation
expressions to be signed. Make sure the evaluated constant had the
proper sign by checking explicitly.
2008-10-13 20:50:56 -07:00
Stephen Williams 1a3e655285 Merge test_width rework
This collection of patches fixes a variety of bugs with the handling
of signed-ness in exprsesions.
2008-10-13 20:23:50 -07:00
Larry Doolittle 3adcbb5611 Shadow reduction part 2
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality.  Patch looks right, and is tested
to compile and run on my machine.  No regressions in test suite.
2008-10-13 20:12:47 -07:00
Martin Whitaker 647b3e5bda Bias storage of events towards static scopes.
This patch modifies the code that finds and combines similar events
such that if similar events are found in both static and automatic
scopes, the retained event will be in a static scope. This is a
performance enhancement, as VVP has more run-time overhead when
handling events declared in an automatic scope.
2008-10-13 20:10:22 -07:00
Cary R c41fb50929 Copy from the existing function when duping a system function.
This code was likely never checked properly since it makes no
sense to copy the expression from the new temporary system
function. You must copy the value from the current function.
2008-10-13 20:06:41 -07:00
Stephen Williams c5d4d9eec1 Merge branch 'master' of ssh://[email protected]/~steve-icarus/git/verilog 2008-10-13 20:00:49 -07:00
Cary R 9cb62a4d64 Check that numbers fit into the correct immediate width (32 bits).
Even on 64 bit machines immediate values should be limited to
32 bits so that the a.out file will run correctly on a 32 bit
machine. This patch fixes a number of places where the code
generator was not checking for/observing this.
2008-10-13 19:56:46 -07:00
Stephen Williams 25f6282a54 Generate signed comparisons independent of the signedness of the expression
The signedness of comparison expressions is typically unsigned, even if
the comparison to be performed is signed. The comparison (and particularly
the expr_synth of the comparison) needs to account for this explicitly.
2008-10-13 19:43:02 -07:00
Stephen Williams 55b8ff4441 Pad the subexpression of unary not.
The operand of unary not needs to be padded to the expression width
before the operator itself. Otherwise, the high (pad) bits will come
out wrong.
2008-10-12 21:38:07 -07:00
Stephen Williams 62f518c205 The signedness of a ternary expression comes from its operands.
If either of the operands of a ternary expression are unsigned, then
both are treated as unsigned. It works just like a binary expression
in that regard.
2008-10-11 21:52:41 -07:00
Stephen Williams 864a86f7ee Multiply nodes are always unsigned.
It is up to the elaborator to sign-extend the inputs if the multiply
is signed in the Verilog source. The run time always processes the
multiply as unsigned.
2008-10-11 21:08:14 -07:00
Stephen Williams 995fc380e8 Get padding of signed comparison operands.
The results of comparisons are unsigned, but the arguments may be signed
and the calculation performed may be signed. Handle the padding properly
for comparisons so that the math is properly signed.
2008-10-11 09:20:49 -07:00
Stephen Williams bd71b7fbb2 Real valued multiply are always signed.
By definition.
2008-10-11 09:19:11 -07:00
Stephen Williams 3a99a5e800 Suppress operand has_sign if expression is unsigned.
Fix processing of arguments of +- and * when only one of the operands
is signed.
2008-10-11 08:39:06 -07:00
Stephen Williams a9497e9c6a Less agressive padding of unsized lossless addition.
When doing lossless addition to an unsized constant, we make the size
be width of an integer, only to be consistent with other tools. In fact,
don't go overboard if we don't have to.
2008-10-10 20:45:11 -07:00
Stephen Williams c85eff93f2 The test_width methods scan and mark expressions with type and size.
Later passes need the intermediate results for width and size so that
some special cases, were self-determined arguments occur, can be
processed properly during elaboration. This can be especially tricky
and interesting for ternary expressions.
2008-10-10 20:42:07 -07:00
Larry Doolittle c010145eaf Shadow reduction part 1
Start cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality.  Patch looks right, and is tested
to compile and run on my machine.  YMMV.
2008-10-09 11:55:26 -07:00
Martin Whitaker b5ad161f90 Fix for pr2148500.
This patch fixes the expression width calculation for a multiply
operation with an unsized operation. The expression width needs
to be at least the minimum of the maximum multiply result width
and the width of an integer.
2008-10-09 11:52:40 -07:00
Martin Whitaker 610dedc2b8 Fix for pr2146824.
Currently, a bitwise boolean operator will cause the expression
width to be reduced to the size of the result. This can give
rise to incorrect results. This patch changes the behaviour to
take into account the required precision for calculating the
two operands.
2008-10-09 11:33:14 -07:00
Martin Whitaker 082e06edb0 Remove checks for constant expressions from the parser.
This patch removes all the checks for constant expressions performed
during the parsing phase, as these checks are (mostly) repeated during
elaboration. It adds the missing check in the elaboration phase (the
RHS of a register initialisation), and improves the error reporting
and error recovery in other checks.

This patch fixes pr2132552, which was caused by a fault in the parser
constant expression checking.
2008-10-09 11:11:32 -07:00
Nick Gasson fd4018cb33 Fix IVL_LPM_MUX where inputs are different signedness to outputs 2008-10-05 17:08:19 +01:00
Nick Gasson b40de5ccb0 Implement IVL_LPM_CMP_NE(E)
Looks like I forgot this one
2008-10-05 17:04:19 +01:00
Nick Gasson a7cbb38248 Fix resizing of constant bit vectors
Emitting a VHDL expression like Resize("01", 32) is ambiguous
between interpreting "01" as a Signed or an Unsigned. There's
no point actually outputting this as we can sign-extend the
constant value in the code generator, which is what this
patch does.
2008-10-05 13:49:07 +01:00
Nick Gasson 4394aff909 Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl
Conflicts:

	tgt-vhdl/stmt.cc
2008-10-05 12:44:30 +01:00
Stephen Williams 5cfe47da2b Don't try to shrink a valid r-vlaue width.
In assignments, the expression width may be defined by the width of
operands, and not that of the l-value. Choose whichever is creater and
set (or pad) the expression to that width.
2008-10-04 21:44:10 -07:00
Stephen Williams cc9e3d1536 Comments should be tossed by the lexor.
It is silly to use yymore() to collect even more of the comment so that
it can be tossed at the tail end of the comment processing. So don't.
2008-10-04 20:35:22 -07:00
Stephen Williams 03fd124d5a Handle multiply with constant zero.
Multiply of any expression with constant 0 will always return zero.
We can handle this early, during elaboration, and save a lot of code
downstream the trouble.

Also, while we are at it, fix up test_width to re-test the left
expression width if the right expression width is unsized. This allows
for the left expression code to adapt to the unsized-ness of the
expression context.
2008-10-04 20:01:19 -07:00
Stephen Williams 18de6980ff Fix associative add tree to get result width correct.
When evaluating A+1+2 in eval_tree, the (1+2) needs to have the correct
result width, or the elaborated expression with will be lost.
2008-10-03 19:52:26 -07:00
Cary R 5fd3be570e Pad input and output ports correctly.
This patch pads inputs and output ports correctly when the port
and the port expression have different widths. It does not fix
inout ports.

It also sets the file and line number information in the unsigned
pad_to_width() routine.
2008-10-03 17:40:05 -07:00
Cary R bd504ea14e Do not evaluate parameters too early.
This patch pushes the evaluation of constant system functions into
normal elaboration vs doing them in the preliminary parameter
elaboration.

It also fixes the compiler version of clog2 to return integer_width
vs a fixed 32 bits.
2008-10-03 17:29:10 -07:00
Stephen Williams aebd9c2bc7 Sign extend r-values that refuse to pad themselves.
There are cases where the r-value doesn't pad itself to the width
that is requested by the call to elaborate_expr. This impacts the
elaboration of PGAssign. Pad/sign extend as appropreate.
2008-10-02 22:02:35 -07:00
Stephen Williams 7b4fda8785 Process arguments to bitwise operator using singned/unsigned rules.
The arguments to bitwise operators are padded if *either* of the operands
is unsigned. This is according to the sign/unsigned expression rules
of Verilog, and also matches the behavior of the "Big-3."
2008-10-01 22:38:53 -07:00
Jared Casper feba5d9470 Compatibility with gcc-4.3
The addition of UINT_MAX in netlist.cc requires #include <climits> when compiling with gcc-4.3.2.

I also noticed that commit 8704e3e used c style includes in c++ sources contrary to the style used in the rest of the c++ code and fixed those.
2008-09-30 21:57:25 -07:00
Cary R 6b62cce14a Produce a better message for ! and real values.
In the transition to the new expression code we forgot how to
handle the logical not (!) of a real value. This patch adds a
more appropriate error message until we get this reimplemented.
2008-09-30 21:53:25 -07:00
Cary R 3bce8bb995 GetProcAddress expects no underscore (MinGW)
MinGW uses the GetProcAddress() function to find the address of
the vlog_startup_routines() procedure in a .vpi file. This routine
requires that the leading underscore be omitted from the name even
though the underlying routine really has one.
2008-09-30 21:51:28 -07:00
Cary R 716853699f Initialize real value in automatic functions.
alloc_instance for real values was just passing a new double
to be added to the context items. The new constructor does
not set the default value so we need to do that manually.
2008-09-30 21:48:13 -07:00
Stephen Williams 55a15d604d Pad operands of bitwise operators.
When elaborating bitwise operators width context determined width,
pad the operands.
2008-09-30 21:35:09 -07:00
Stephen Williams b548dec070 Width of identifier accounts for expression minimum
When the test_width method is called with a expression min width,
then the PEIdent::test_width needs to honor that minimum.
2008-09-29 22:04:28 -07:00
Stephen Williams 2da50e1788 Cast to real when add arguments have mixed type.
When synthesizing, be careful (especiall for addition) that if the
arguments are mixed, then cast the non-IVL_VT_REAL arguments to
IVL_VT_REAL.
2008-09-29 21:02:37 -07:00
Stephen Williams 3aaea46144 Content-free portability fixes.
These are patches from ITOH Yasufumi and Larry Doolittle of pr2120948.
They change nothing, but make the code compile with older compilers.
2008-09-29 18:06:47 -07:00
Stephen Williams 2251844124 Merge branch 'master' into expression-width-rework 2008-09-28 21:21:41 -07:00
Stephen Williams 729771e562 Check expression width for sanity
Assertion to check for insane expression widths that are likely caused
by compiler bugs.
2008-09-28 08:58:08 -07:00
Stephen Williams 0bb1f9740b Fix width of short circuit FALSE clase of Ternary / Fix expr type if system functions
Simple error setting the expression width of the FALSE clause of a
ternary expression when the expression is short cuirted to false.

Fix a simple error where the type of a system function is not returned
through the test_width function.
2008-09-28 08:57:25 -07:00
Martin Whitaker 7ebcc6b357 Support for automatic tasks and functions.
This patch adds support for automatic tasks and functions.
Refer to the overview in vvp/README.txt for details.
2008-09-27 15:51:16 -07:00
Stephen Williams 3296b1dee3 Include a calculation of the expression type in test_width methods.
The type of the sub-expression is sometimes needed by clients of the
test_width methods, so add that as an output.
2008-09-26 22:20:11 -07:00
Stephen Williams 42d412c626 Unify all the r-value elaboration.
R-value expression elaboration happens in several places. Factor out
the common code so that they are all handled correctly and uniformly.
2008-09-25 21:22:21 -07:00
Stephen Williams 4919b70da6 Give l-value nets their proper type.
L-value nets (i.e. in continuous assignments) that were words in
arrays need to have the data type of their parent array.
2008-09-25 21:21:00 -07:00
Stephen Williams d3f17f27c1 Handle widths of real value arguments to user functions.
The arguments to user defined functions are self-determined. And if
the result is real valued, we can call them lossless self-determined.
Treat these arguments like r-value elaboration for assignments.

Also clean up the binary divide elaboration a little bit.

Also, floating point literals are unsized with width==1.
2008-09-25 20:37:18 -07:00
Stephen Williams 873ed60ff8 Multiply of real values has width of 1.
When a multiply expression is IVL_VT_REAL, then the default width is
the width of the operands, and not the sum of the operands. In fact, it
should turn out to be 1.

Also, the width of the multiply expression when we get to the ivl_target
API, need not be the sum of the widths of its arguments. In fact, if the
arguments are signed, that would be completely wrong. So adjust the
stub target to properly test this constraint.
2008-09-25 20:33:29 -07:00
Stephen Williams ce7dd6b4ff Account for real type l-values when working with widths.
Widths of real values are always 1. When paired with vectorable types
in expressions, the vectorable type is processed as losslessly self-
determined. ("unsized" in the test_width methods.)
2008-09-22 21:09:06 -07:00
Stephen Williams 2381fc72b0 Constants may take on the width of the l-value.
Don't force the expression with to be different from the l-value if the
l-value is the immediate destination. This saves the effort of handling
overly wide constant values in simple cases.

Also, in determined contexts, signed unary minus does not need to pad the
width of the expression.
2008-09-21 18:14:26 -07:00
Stephen Williams 6e12c1f236 Elaborate of PGAssign always passes calculated width.
the PGAssign elaborate method used the test_width to get the width
of the r-value expression. This should be completely sufficient to
get the width of the expression, so always use a defined width to
elaborate the expression.
2008-09-20 19:23:54 -07:00
Stephen Williams dc313436c1 Self-determined ternary expressions use better width tester.
When ternary expressions are self-determined, use the test_width
method to get a proper reading of the expression width. Also improve
the test_width method to handle unsized operands.
2008-09-20 18:17:17 -07:00
Stephen Williams 46bf03bba4 Pad signed arguments to multiply
Arguments to multiply that are signed must be the width of the output
for the 2s complement multiply to work correctly.
2008-09-19 22:00:29 -07:00
Cary R 103b351641 Document the %assign/av/e opcode. 2008-09-19 21:13:01 -07:00
Cary R f7d3c7c711 Add non-blocking EC for arrays and other fixes.
This patch adds non-blocking event control for array words.
It also fixes a problem where the word used to put the
calculated delay for a non-blocking array assignment was
not being released. It also fixes the non-blocking array
assignments to correctly handle off the end/beginning part
selects.
2008-09-19 21:08:03 -07:00
Cary R a39b9d4ef1 Elaboration debug messages should depend on debug flag.
The debug messages for the ternary were missing a conditional
on the debug flag.
2008-09-19 20:49:02 -07:00
Martin Whitaker a4973c217d Support parameter, localparam, and event declarations in any scope.
Currently, parameters and localparams declared in tasks, functions,
generate blocks, and named blocks are placed in the parent module
scope. Event declarations in these scopes are not permitted (a
syntax error is reported). This patch corrects this behaviour, so
that all the above declarations are accepted and are placed in the
scope in which they are declared.

Note that the IEEE standard does not permit parameter declarations
in generate blocks. This patch causes the parser to reject such
declarations.
2008-09-19 20:23:14 -07:00
Cary R 626394d198 Some event control assigns can be skipped so add an event clear.
Since some event control assignments can be skipped we need an
event control clear so that future %evctl statements do not fail
their assert. This patch adds %evctl/c and uses it in the compiler
as appropriate to keep the event control information in sync.
2008-09-19 20:04:51 -07:00
Cary R 8ffec473ef Add event control for vectors and parts of a vectors.
This patch adds full event control for vectors and parts of a
vector. It also fixes the other non-blocking part select code
to correctly handle a negative offset ([1:-2] of a [4:0] will
have an offset of -2).
2008-09-19 19:46:33 -07:00
Stephen Williams 38e62bb1d2 Fix conversion of negative integer to real.
When an integer/bool value is constant and negative,
and is used in a real-valued context, fix the
code generator calculation of the negative value.
2008-09-19 17:04:40 -07:00
Cary R 2d1e0b3ade When evaluating a constant into an index make sure to clear bit 4.
When evaluating an expression into an index register bit 4 is used
to determine if the expression had any X/Z bits. In the case of a
constant immediate value this can not happen so make sure the bit
is cleared.
2008-09-18 21:52:00 -07:00
Cary R 3ba9e945d7 Fix MinGW to us _snprintf in tgt-vvp/vvp_process.c
We need consistent pointer output (%p) and under MinGW we need to
us _snprintf instead of snprintf to get this. The recent event
control addition missed this. This has been reported to the MinGW
developers and they are working on a solution.
2008-09-18 14:53:42 -07:00
Larry Doolittle 2a1608c075 Configure UL_AND_TIME without warnings
The previous patch (commit 8b0ca902a6)
dealing with the possibilities of (unsigned long) and (vvp_time64_t)
being either the same or different managed to redefine UL_AND_TIME64_DIFF
in the 64-bit case.  This does, of course, trigger a compiler warning.
That warning is repeated on every .cc file with a #include "config.h",
which is to say, just about every file.

This patch inverts the sense of the preprocessor conditional, calling
it UL_AND_TIME64_SAME.  No more warnings!
2008-09-18 14:49:11 -07:00
Stephen Williams 411ee517ee Instance arrays with multiple outputs and not vectorized.
It takes a carefully crafted source file to cause elabortion to make
an arrayed multiple-output gate that is not vectorized into a single
wide gate. But that special case does need to be handled.
2008-09-16 21:03:26 -07:00
Cary R 8b0ca902a6 We don't need a special vector4_to_value if vvp_time64_t == unsigned long.
When vvp_time64_t is equivalent to an unsigned long we do not want
(cannot have) both an unsigned long and vvp_time64_t version of
vector4_to_value().
2008-09-16 20:00:58 -07:00
Cary R 6f46930c23 Make it an error to have a `timescale inside a module definition.
While the standard is not completely clear about this, we are making
it an error for a `timescale directive to be inside a (macro)module
definition. This means that all modules and any statements contained
within have a single well defined time unit and precision.
2008-09-15 21:25:41 -07:00
Stephen Williams 0e699ca226 Handle logic gates with multiple outputs.
Logic gates usually have one output and several inputs, but a few
have multiple outputs and one input. Since the NetNode objects have
only a single output, handle the case by creating multiple NetNode
objects, one for each output.
2008-09-14 21:04:03 -07:00
Cary R 5463e5e66b More refinements on negative real variable delays.
This should do the rounding correctly on real negative delay
values.
2008-09-14 09:13:03 -07:00
Cary R 441f173ced Variable delays for .delay must be scaled correctly.
A variable that is used to set the delay of a .delay statement
must be scaled to match the local units and for real values
rounded using the precision. This value is then converted to
the simulation precision.
2008-09-14 09:12:53 -07:00
Stephen Williams d3d54144ff Be more explicit with the type matching rules.
Signals of a nexus must have types that exactly match, but the drivers
of a signal nexus have slightly more subtle rules for the case where
the signal is IVL_VT_LOGIC. Express those rules in the function
check_signal_drive_type, and use it to check the type of constants
driving a signal.
2008-09-13 20:22:48 -07:00
Stephen Williams e4c9ad2b17 Remove redundant NetPins node pointer.
Remove redundant pointer to the containing NetPins object by keeping
the pointer only in the first Link (pin 0) of an array of links. In
this link, replace the pin number with the NetPins pointer, and set
a pins_zero_ flag to indicate that this has happened. This way, only
the first pin in a Link array will have the pointer to the NetPins
that contains the array, and the pointer takes up practically no space
at all.
2008-09-13 19:49:38 -07:00
Stephen Williams 0339e9eb1e Cleanup unused junk in NetAddSub class.
This class was old, and its original design pulled literally from
the LPM reference. But of nine pins declared, only 4 were used.
Remove all the excess junk and clean up the designed dump handling
of the device.
2008-09-13 18:28:43 -07:00
Stephen Williams 7d6b391572 In continuous assignment, r-value is sized or lossless, never self determined.
The r-value expression takes on at least the width of the l-value. If
there is a sized width greater then the l-value width, take that on
instead. But if the r-value is unsized, there are unsized sub-expressions
that cause the expression as a whole to be unlimited width, so elaborate
and evalulate the r-value as lossless.
2008-09-13 17:40:19 -07:00
Stephen Williams 804f5a94d5 Manage expression types for ternary a little better.
The true and false expression clauses must have compatible types,
which are not necesarily identical. In particular, VT_BOOL and
VT_LOGIC are compatible for the purposes of ternary arguments. The
test in NetETernary::synthesize was incorrect.

In the process, fix the type handling of NetConst objects to allow
for IVL_VT_BOOL constants. This is information that the downstream
may find useful, so should be handled correctly.
2008-09-13 16:43:39 -07:00
Cary R 3d5998cd63 Allow variable delay in continuous assignments.
Add the ability to delay continuous assignments using a
variable delay.
2008-09-13 15:01:23 -07:00
Nick Gasson eda1df5df2 Avoid processing tgt-vhdl/Makefile.in twice
It's processed once by AC_OUTPUT in configure.in and then again
by AC_OUTPUT in tgt-vhdl/configure.in. This is a bug from when I
first started on the VHDL target, and was basing it on the tgt-vvp
code. The call to configure in the tgt-vhdl directory is not
actually necessary either, since it doesn't do any checks not
performed elsewhere, so that should proably be removed later.
2008-09-13 14:57:33 -07:00
Stephen Williams 3d86cc1a15 Reduce the size of Link class objects.
Put the enumerated members of the Link class into bit fields to keep
the size down to a minimum.
2008-09-13 14:51:42 -07:00
Nick Gasson c5263268ed Tidy up reduction functions in support.cc
This removes some unnecessary code duplication as the functions
only differ (or need to differ) in two places.
2008-09-13 18:20:12 +01:00
Nick Gasson e5abe182c1 Add reduction XOR/XNOR in expressions 2008-09-13 18:09:11 +01:00
Nick Gasson e5343ef73f Implement arithmetic right shift >>>
This is currently implemented using the numeric_std
shift_right function as the sra operator is not defined on
signed/unsigned types before VHDL-2006.
2008-09-13 15:23:42 +01:00
Cary R 1f9f73a4be Modify $realtime to use vpiScaledRealTime
$realtime should use vpiScaledRealTime instead of scaling the
time itself. This also allows it to work for time over 32 bits.
2008-09-12 20:36:08 -07:00
Cary R 1e60754ff0 Partial non-blocking event control implementation
This patch pushes the non-blocking event control information to
the code generator. It adds the %evctl statements that are used
to put the event control information into the special thread
event control registers. The signed version (%evctl/s) required
the implementation of %ix/getv/s to load a signed value into
an index register. It then adds %assign/wr/e event control based
non-blocking assignment for real values. It also fixes the other
non-blocking real assignments to use Transport instead of inertial
delays.
2008-09-12 20:00:28 -07:00
Larry Doolittle cdfb2315cf One more signed vs unsigned comparison fix
Introduced in a8ad505af7
Various improgements to expression ::synthesize methods
2008-09-12 19:39:15 -07:00
Nick Gasson 2516d63805 A basic translation of the Verilog power operator to VHDL
The exponentiation operator in VHDL is not defined for numeric_std
types. We can get around this by converting the operands to integers,
performing the operation, then converting the result back to the
original type. This will work OK in simulation but certainly will not
synthesise unless the operands are constant.

However, even this does not work quite correctly. The Integer type in
VHDL is signed and usually only 32 bits, therefore any result larger
than this will overflow and raise an exception. I can't see a way
around this at the moment.
2008-09-12 20:19:22 +01:00
Stephen Williams 3abf51dcad Get rid of names attached to Links.
This is simply no need for the names on links,
other then for debug messages, and there are
better ways to handle that.
2008-09-10 19:34:28 -07:00
Stephen Williams 5dfecb3789 Remove useless Link instance number. 2008-09-10 07:29:23 -07:00
Cary R 088c7f3feb Add calculated delay, real valued, non-blocking assignments.
This patch add the ability to do a non-blocking assignment
for real values using a non-constant (calculated) delay.
2008-09-09 20:09:49 -07:00
Cary R 3982781e97 Add cast to remove warning. 2008-09-09 19:24:14 -07:00
Larry Doolittle f233793061 Spelling fixes
No code changes.
2008-09-09 19:21:42 -07:00
Larry Doolittle 8704e3e34f Compatibility with gcc-4.3
Add "include"s to fix errors flagged by gcc-4.3.2
2008-09-09 19:19:51 -07:00
Nick Gasson ec2511da64 Use British spelling and fix a few typos 2008-09-09 19:57:32 +01:00
Stephen Williams 05f129211e Remove the elaborate_net methods.
These methods are no longer in use, their functionality taked over
by a compination of elab_and_eval and NetExpr::synthesize methods.
2008-09-08 21:26:26 -07:00
Stephen Williams eb9d037bf0 Remove elaborate_net from all elaborations.
Use elaborate_expr and synthesize() methods in place of the
elaborate_net methods, so that elaboration is more consistent.
2008-09-08 19:13:49 -07:00
Stephen Williams 90f55a1d00 Merge branch 'elaborate-net-rework' 2008-09-08 18:02:51 -07:00
Stephen Williams 527f5c4849 The -V flag gets version information from all parts.
When the -V flag is passed to the iverilog command, we can easily
print the version information for the driver itself, but it is also
valuable to probe all the components that would have been used for
a real compile. So the driver executes the preprocessor and the ivl
core to have them print version information.

The ivl core program also tries to load the target code generator
and get version information to print. For this to work, create a new
optional entry point "target_query" that takes a query key string as
an argument and returns a const string as the result. Use this with
the key "version" to get version information out of the target.
2008-09-07 21:54:46 -07:00
Stephen Williams 4898cd04c6 Remove redundant back-end selections.
Target selection is done by the DLL target code generator, so there
is no value having a layer of target selection ahead of it. Remove
all that redundant code and simplify the target config files to reflect
this.
2008-09-07 16:43:54 -07:00
Stephen Williams 6411e96193 Generate delay devices for sign-extend devices.
It is possible for signe-extend to have a delay attached to it. (Same
for repeat.) Handle it like other LPM devices, by stuffing a .delay
device into the output path of the device, if appropriate.
2008-09-06 18:05:18 -07:00
Stephen Williams dd47599d55 Merge branch 'master' into elaborate-net-rework 2008-09-06 17:20:14 -07:00
Nick Gasson 8fc35fa32a Avoid emitting empty string at end of $display translation
This happened if the last part of a format string was a % code.
2008-09-06 13:23:55 +01:00
Nick Gasson 6fe7583784 Cary R.'s additional system functions, real value error messages, etc.
I've changed the find_entity() error messages to asserts since
this should be fixed by the previous patch.
2008-09-06 12:06:01 +01:00
Nick Gasson a34348bb35 Add (temporary) error for ICT_SCOPE_GENERATE
Generate scopes were previously ignored, and this would cause a segfault
later on. This patch gives an error whenever it encounters a generate
scope. This should be removed once generate statements are implemented.
2008-09-06 11:38:37 +01:00
Stephen Williams 8717a85f7f Prepare for snapshot 20080905 2008-09-05 17:44:41 -07:00
Cary R 5bf55485d5 Pass file and line number information for expression constants.
This patch passes the file and line number information for
constants that are used in expressions.
2008-09-05 17:33:45 -07:00
Stephen Williams 38970fea65 Merge branch 'vhdl' 2008-09-05 14:40:48 -07:00
Cary R 90fbac6e33 Add callbacks to vpiMemory objects.
This patch adds the ability to set a global array callback.
These type of callbacks will be called when any element of
the array changes.
2008-09-04 21:37:50 -07:00
Larry Doolittle 66949122cf Non-controversial whitespace cleanup
Nothing to do with tab width!  Eliminates useless
trailing spaces and tabs, and nearly all <space><tab>
pairings.  No change to derived files (e.g., .vvp),
non-master files (e.g., lxt2_write.c) or the new tgt-vhdl
directory.

Low priority, simple entropy reduction.  Please apply
unless it deletes some steganographic content you want
to keep.
2008-09-04 21:31:30 -07:00
Stephen Williams 6f002935d7 Parse attributes on statements within event statements.
Statements can have attributes attached to them. Handle a few cases in
the parser where attributes may be attached to statements, and get them
as far as the pform.
2008-09-04 21:27:21 -07:00
Stephen Williams 5f0b723534 Merge branch 'master' into elaborate-net-rework 2008-09-03 19:59:31 -07:00
Cary R 7beb059d90 Add blocking repeat event control, make repeat sign aware
This patch adds blocking repeat event controls and also makes the
base repeat statement sign aware. If the argument to repeat is
negative (it must be a signed variable) then this is treated just
like an argument of 0 (there is no looping). Doing this allows us
to model the repeat event control as follows.

  lhs = repeat(count) @(event) rhs;

is translated to:

  begin
    temp = rhs;
    repeat (count) @(event);
    lhs = temp;
  end

This patch also pushes the non-blocking event control
information to the elaboration phase where it will report they
are not currently supported.
2008-09-03 19:35:54 -07:00
Stephen Williams 60169f6353 Get generate block scope from generate case.
The generate block is a placeholder for the generate items, and it
is the items themselves that can specify the name of the generate
block that is created.
2008-09-03 17:59:39 -07:00
Stephen Williams e4411777ed Remove unused net_force.cc source file. 2008-09-02 18:38:04 -07:00
Stephen Williams 456fffa7ed Remove last vestiges of XNF.
XNF hasn't been supported in a while. Xilinx doesn't put any effort
into it either, for that matter.
2008-09-02 18:23:48 -07:00
Nick Gasson 4cb2090978 Fix vhdl_expr::cast when expression has no assigned type
This avoids a couple of segfaults
2008-09-02 20:22:50 +01:00
Nick Gasson ff766899b0 Add IVL_LPM_CMP_GT 2008-09-02 19:07:38 +01:00
Nick Gasson 122890fef4 Make sure LPM expression is cast to the output type
This fixes some signed/unsigned bugs identified by the signedX tests.
2008-09-02 19:02:54 +01:00
Cary R 1944f372c5 Fix a couple uninitialized value problems found with tgt-vhdl.
This patch fixes two uninitialized variable problems found
with valgrind when testing the VHDL code generator.
2008-09-01 21:23:58 -07:00
Cary R 8fbfdffe91 Allow .array/port input access generate statement.
For nested array accesses the .array/port statement must
evaluate its input argument before it starts printing the
actual .array/port statement.
2008-09-01 14:04:51 -07:00
Larry Doolittle 23127852c7 Compatibility with gcc-4.3
Add "include" to fix error with abort() in dup_expr.cc
Add "include" to AStatement.h so usage of struct PExpr works
Get rid of eval_tree.cc:577: warning: suggest parentheses around comparison in operand of ^
2008-09-01 13:55:57 -07:00
Stephen Williams c150223a3a Fix problem with vvp_vector2_t right shift
that trips only when starting with perfectly
aligned inputs.
2008-09-01 13:55:42 -07:00
Stephen Williams c0a4b7c670 Fix a bug in vector evaluation of abs().
The calculation of the abs of a signed value
was inverting the value if it was signed,
and not if it was negative.
2008-08-30 17:35:57 -07:00
Stephen Williams 319b886118 Build files compatible with snapshot 20080830 2008-08-30 17:09:51 -07:00
Stephen Williams fc476aa281 Fix right shift of vvp_vector2_t.
The right shift of vvp_vector2_t needs to
account for and mask off shifted bits. Otherwise
there will be unexpected results after
a vvp_vector2_t::trim method.
2008-08-30 15:30:22 -07:00
Stephen Williams 49c4f2d106 Fix crash on uninitialized data. 2008-08-30 15:28:31 -07:00
Stephen Williams bc3411e28e Merge branch 'master' into elaborate-net-rework 2008-08-29 22:13:07 -07:00
Cary R 97e662d667 Remove unneeded real compare code.
The code removed is unneeded since real values are already
handled by the real specific comparison that is called at
the beginning of each function.
2008-08-29 21:16:59 -07:00
Stephen Williams f900b6d541 Add the Verilog-2005 and Verilog-AMS constant system functions.
This patch adds the constant system functions for Verilog-2005
and Verilog-AMS. These are evaluated at compile time. $abs(),
$min() and $max() support their polymorphic behavior in the
compiler where it really matters. They are always evaluated
as reals in the run time and the result/argument(s) will be
converted as needed.

The Verilog-2005 functions are available if using the 2005
generation (default) and if either the icarus-misc (also on
by default) or verilog-ams flags are set.

The Verilog-AMS functions are available if either the
icarus-misc or verilog-ams flags are set.
2008-08-29 21:11:44 -07:00
Cary R 0804eccfec Evaluate constant real EQ and NE constructs.
This patch adds code to evaluate constant == and != with real values.
2008-08-29 20:41:10 -07:00
Cary R 2e97b28185 More NaN constant fixes.
This patch cleans up %loadi/wr regarding NaN values. It also
fixes the code generator to correctly output a NaN value as
a Cr<> constant.
2008-08-29 19:32:00 -07:00
Cary R 2d3cd7cb9a Handle NaN constant in the code generator and fix loadi/wr NaN bug.
This patch fixes a bug in %loadi/wr regarding NaN values. It also
fixes the code generator to correctly output a NaN value.
2008-08-29 19:31:50 -07:00
Stephen Williams c9efe87146 Merge branch 'master' into elaborate-net-rework 2008-08-29 19:10:48 -07:00
Stephen Williams 1ca8241b88 Merge branch 'master' into verilog-ams 2008-08-29 19:03:34 -07:00
Stephen Williams 8d21c0390e Remove dead EEQ code.
The EEQ function is handled by vvp_cmp_eeq, an arithmetic expression
processor and the logic version of EEQ is never used.
2008-08-29 18:45:19 -07:00
Stephen Williams 3b778b1a06 Minor improvements to expression debug prints. 2008-08-29 18:44:45 -07:00
Stephen Williams e322cce650 Clean up $clog2() measurement of unsized numbers.
If the argument to $clog2() is unsized constant, then trim it to the
smallest representation that doesn't lose the sign, then do the $clog2
on that.

Also, use integer_width instead of 32 for the minimum $clog2() result
for a negative value.
2008-08-29 18:42:22 -07:00
Nick Gasson ed929a37bb Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl 2008-08-29 18:38:49 +01:00
Stephen Williams 4c7144afc0 Remove dead EEQ code.
The EEQ function is handled by vvp_cmp_eeq, an arithmetic expression
processor and the logic version of EEQ is never used.
2008-08-28 22:08:46 -07:00
Stephen Williams 5d5228b6b8 Minor improvements to expression debug prints. 2008-08-28 21:16:44 -07:00
Stephen Williams e6c2637367 Clean up $clog2() measurement of unsized numbers.
If the argument to $clog2() is unsized constant, then trim it to the
smallest representation that doesn't lose the sign, then do the $clog2
on that.

Also, use integer_width instead of 32 for the minimum $clog2() result
for a negative value.
2008-08-28 21:15:43 -07:00
Stephen Williams 468f45b4db Merge branch 'master' into elaborate-net-rework 2008-08-28 18:17:24 -07:00
Cary R 8c38872b4b Fix the always zero delay check to happen after elaboration.
This patch moves the always zero or possibly zero delay checks
to a point after the circuit is full elaborated. Before it
could try to check tasks that had not already been evaluated
resulting in a crash.
2008-08-28 17:49:41 -07:00
Cary R d15e2a2f73 Work around a flex limitation with yyrestart()
See the comments added with this patch for more information.
2008-08-28 17:41:13 -07:00
Cary R 150d51c19b Optimize block delay type check
When looking for a delay_type() in a block stop when we have a
DEFINITE_DELAY. Doing this could reduce the number of statements
that need to be checked.
2008-08-28 17:38:02 -07:00
Larry Doolittle b455f3af5d Spelling fixes
Comments only, no code changes
2008-08-28 17:36:32 -07:00
Nick Gasson 0e458501b3 Ensure binary operands have correct signedness
Previously only signedness was only corrected for the
result. This patch ensures the VHDL operands have the
same signedness as their Verilog counterparts.

This fixes a few of the signedX tests.
2008-08-28 21:53:12 +01:00
Cary R 3b8dc81a97 By default convert a recv_vec8_pv to a recv_vec4_pv
Assume that anything that is strength aware already handles a
recv_vec8_pv and make the default function convert the bits
to a vec4 and then call recv_vec4_pv with this new value.
2008-08-27 21:22:18 -07:00
Cary R 0ae8f744c4 Variable arrays need to keep their signedness.
Since variable arrays create their elements dynamically the base array
structure for them needs to keep the signedness information.
2008-08-27 21:16:25 -07:00
Cary R 370ff9719f Make &A and &PV nestable.
This patch makes it so that &A and &PV can nest for the symbol
argument. This allows nested array selects, etc.
2008-08-27 21:09:41 -07:00
Stephen Williams 3ed0c4e809 Don't crash looking for delay_type of empty task.
It is legal for a task to have no definition. In that case, the
delay_type calculations (used to detect infinite loops) can assume
that an empty definition is a no-op and return NO_DELAY.
2008-08-27 18:42:05 -07:00
Stephen Williams 0121c41942 Better optimization of constants in expressions
Be more sophisticated with the code generated for constant values.
When values are large, use an optimal mix of %movi and %mov
instructions to get the desired value, no matter what the content.
2008-08-27 18:22:23 -07:00
Stephen Williams 091a546387 Broken run-time wide divide.
The wide-divide function was broke. It generated bad results.
2008-08-27 18:20:35 -07:00
Nick Gasson 8323d5d01d Finish cast.cc cleanup
Replace big if statement with switch statemetn
2008-08-27 16:59:05 +01:00
Nick Gasson b5e65ac9ed Refactor and clean up cast.cc
This splits up the monolithic and confusing vhdl_expr::cast function into
several smaller to_XXX functions which each generate code to cast an 
expression to type XXX. This makes it much easier to understand and maintain.
2008-08-27 16:47:07 +01:00
Stephen Williams 63e200726f Merge branch 'master' into elaborate-net-rework 2008-08-26 21:53:44 -07:00
Stephen Williams b2b0f45473 Use the expression with to calculate expression width in assignments.
In continuous assignment, the width of the expression needs to come
from the expression itself, and not just from the width of the l-value.
Use the PExpr::test_width method to get the width of the expression
to pass to the elaborate.
2008-08-26 21:33:24 -07:00
Cary R bccb762e9f Correctly cast strlen() for %*s width argument.
We had fixed many of these warning before, but I missed this
one since this file was not part of the distribution when we
fixed the other cases.
2008-08-26 16:09:00 -07:00
Stephen Williams c26ee8534d Improved comments. 2008-08-25 21:52:40 -07:00
Nick Gasson 924ddb787a Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl 2008-08-25 20:07:49 +01:00
Stephen Williams 0341679360 Handle real-valued unary subtract.
the sub_net_from function is used by the ::synthesize method of the
NetEUnary class to make the expression 0-N. By making that function
handle a real-valued net, the NetEUnary suddenly supports real-valued
nets, and this probably helps in other places as well.
2008-08-23 18:11:11 -07:00
Stephen Williams 65c3bc91de Short-circuit elaboration of ternary expressions.
When the condition expression of a ternary is constant 1 or 0, we can
short-circuit the elaboration by only processing the clause (true or
false) that we need. This saves compile time and execution time.
2008-08-23 10:50:24 -07:00
Cary R be3d7b435d Print a better message for instance port expression errors.
This patch adds code to print an error message when there is
a syntax error in the port expression list.
2008-08-23 09:34:12 -07:00
Cary R 92dd13a225 Error message for missing system tasks/functions.
This patch adds an error message for the standard system
tasks and functions that are not currently implemented.
These are currently $fmonitor*, $ferror, $fread, the
queue and PLA tasks.
2008-08-23 09:20:30 -07:00
Nick Gasson 8e023d1227 Remove redundant function 2008-08-22 21:27:24 +01:00
Nick Gasson d21b3258e3 Support conversion of (un)signed to std_logic
Take the least-significant bit. This fixes a couple of broken
test cases.
2008-08-22 20:59:14 +01:00
Nick Gasson 331a51e842 Add more warnings about untranslatable constructs 2008-08-22 20:25:58 +01:00
Nick Gasson 63a1e25129 Catch case where component name and instance differ only in case
This causes an error in VHDL (which is case-insensitive). This 
patch simply appends _Inst to the instance name if it detects this.
2008-08-22 20:20:17 +01:00
Nick Gasson fae7ab2418 Use case-insensitive string comparison for get_decl
This will allow us to detect cases where identifiers differ only by case
2008-08-22 20:15:45 +01:00
Stephen Williams 65a4f36de5 Watch out for left operand of left shift that is not known early.
It is possible for the left operand of a left shift to be not known
early during elaborate expression. In that case, make a punt expression
and expect it to be resolved later.
2008-08-21 18:58:38 -07:00
Stephen Williams 04d49fcf35 Merge branch 'master' into elaborate-net-rework 2008-08-21 18:11:21 -07:00
Nick Gasson 535ef6be38 Change function return value from Verilog_Result to <funcname>_Result 2008-08-21 19:44:12 +01:00
Nick Gasson d3b7d7a13d Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl 2008-08-21 18:35:54 +01:00
Nick Gasson b92b62a8fb Include cstring required for GCC 4.3
GCC 4.3 has tightened up header dependencies so that
`strcmp' is no longer declared if <cstdlib> is included
(which it was in prior versions). This causes the changes
in 5e512e6570 to fail to
build with 4.3.

This patch includes <cstring> in the files that are failing.
2008-08-21 09:36:03 -07:00
Cary R 7eb34013dd Add vpip_calc_clog2 to vvp.def file
This is needed to get cygwin to compile correctly.
2008-08-21 09:34:33 -07:00
Stephen Williams e18eb32d8b Process shift by constant amounts early in expression elaboration.
The expr:::synthesize methods need not deal with saturating left or
right shifts if they are dealt with early, in elaborate_expr methods.
So the elaborate_expr for shift takes on much more responsibility.
2008-08-20 21:47:07 -07:00
Nick Gasson 4ebe09bb72 Various fixes to support automatic functions
Mostly this ensures that a recursive call to a function
is made with the correct types (this may involve generating
code to cast expressions to the correct type).
2008-08-20 22:54:53 +01:00
Nick Gasson a07dc968e7 Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl 2008-08-20 18:58:46 +01:00
Stephen Williams 28991d30f4 Fix some ambiguous casts. 2008-08-20 09:40:16 -07:00
Cary R 11109f519c Push the automatic property for tasks and functions to the code gen.
This patch pushes the automatic property for both tasks and
functions to the code generators. The vvp back end does not
currently support this so it will error out during code
generation. The VHDL back end should be able to use this
property and tgt-stub prints the property. Having this will
also make it easier when we do adding this to the runtime.
2008-08-20 09:23:14 -07:00
Cary R 5e512e6570 Finish $clog2 function.
This patch fixes problems in the initial $clog2 implementation
and adds correct functionality to the runtime.
2008-08-20 09:01:21 -07:00
Cary R c032d28aaa Convert the infinities to 'bx
This patch modifies the double to vector conversions to return
'bx for either +/- infinity.
2008-08-20 09:01:09 -07:00
Cary R 768633e464 Add $clog2 function.
This patch adds the $clog2 system function. It also makes this
function work as a constant function. The runtime version still
needs to be updated to use an integer based version instead of
the current double based method. The double method suffers from
rounding errors.
2008-08-20 08:59:36 -07:00
Cary R e501bbdd27 Fix problems in VPI callback time and value formats.
This patch adds support for vpiScaledRealTime and vpiSuppressTime
to VPI callbacks. It also fixes a bug where the callback data
object was not being copied correctly and adds support for
vpiSuppressVal. This requires adding vpiSuppressVal to a few
other routines. It adds the ability for a callback to return
more than vpiScalarVal (all values supported by the
vpip_vec4_get_value() procedure). It also fixes a bug where
vpip_vec4_get_value() would incorrectly return vpiZ for a BIT4_X
scalar value. It also comments the potentially dangerous
vpiScalarVal calculation in the vvp_fun_signal::get_value()
procedure.
2008-08-20 08:52:09 -07:00
Nick Gasson cb1d4fd278 Amend inaccurate comment 2008-08-18 16:15:05 +01:00
Nick Gasson e1deba51ab Handle BUFIF logic when vector inputs 2008-08-18 15:48:07 +01:00
Nick Gasson d53014a07f Fix leading comma it expression only has "others" part
Stop syntax errors caused by things like this:
  (, others => '1')
2008-08-18 15:36:11 +01:00
Nick Gasson 7865264de0 Implement IVL_LPM_REPEAT 2008-08-18 15:34:58 +01:00
Nick Gasson 86661c1538 Add a few more `unsupported' messages 2008-08-18 15:29:30 +01:00
Nick Gasson e2dd7425bd Add error messages for unsupported statement types 2008-08-18 15:24:38 +01:00
Nick Gasson e01b16e586 Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl 2008-08-18 15:16:02 +01:00
Nick Gasson 6adc3c9f13 Add short section on VHDL to man page 2008-08-17 19:42:07 +01:00
Stephen Williams 0de2dcb211 Allow elaborate_expr to handle implicit nets.
When the elaborate_expr code is used for expressions of continuous
assignments, it needs to be able to create implicit nets.
2008-08-17 08:22:42 -07:00
Stephen Williams a8ad505af7 Various improgements to expression ::synthesize methods
Since NetExpr::synthesize methods were rarely used, then had a lot
of bugs. Now that continuous assign uses these methods, these bugs
must be fixed.

Binary and Unary minus properly pad/extens its arguments,
Case compare generates correct code,
Divide properly takes on signed flag,
Signed right shift sign-extends its argument to prevent loss of sign bits
and uses the NetSignExtend instead of simple padding,
Use the correct target node for reduction NAND,
Properly handle constant arguments of NetESelect

Handle some exressions that were not handled before, include abs()
and POW.
2008-08-17 08:21:24 -07:00
Stephen Williams e8804500b0 Replace an assert in vvp/arith.cc with a detailed message.
... and an assert.
2008-08-16 19:02:09 -07:00
Stephen Williams 66bed241f1 Prevent silent overflow of mantissa
When converting a binary constant to a real value in the vvp code
generator, make sure the mantissa does not overflow. If it does,
panic in some way.
2008-08-16 18:30:07 -07:00
Stephen Williams f8bd8e1bd6 Unary minus and signed right shift need to extend their arguments.
In signed contextx, the right shift and unary minus expressions need
to be sign extended before they operate, otherwise there may be bad
results in the high bits in the greater context.
2008-08-16 17:30:32 -07:00
Stephen Williams d2eba7eefe Modulus value bit width should match input dividend width. 2008-08-16 16:25:56 -07:00
Stephen Williams 5ddf34d39b Signed operands do not make power (**) real. 2008-08-16 15:36:14 -07:00
Martin Whitaker 2c1426a44d Patch to ensure functions are evaluated immediately.
This patch causes a thread that is created to evaluate a function
to be executed immediately. The parent thread is resumed when the
function thread terminates.
2008-08-16 14:42:17 -07:00
Stephen Williams 30e6cfce41 Real valued nets are signed, and pform unary expression have width.
Real valued nets should ne treated as signed no matter what.
Also, PEUnary nary expressions need a useful test_width method.
2008-08-15 22:03:19 -07:00
Stephen Williams 1ae2c0c9e0 Extra diagnostic details in elaboration of continuous assignment. 2008-08-15 21:19:04 -07:00
Cary R 1f5b11246e Correctly pass a concatenation elaboration error.
Because Icarus tries to elaborate as much as it can even after
an error has occurred we need to check for these errors during
elaboration. This patch prevent an undefined identifier from
crashing the compiler.
2008-08-15 17:26:08 -07:00
Cary R d3caa547ba Print an error for automatic tasks or functions.
This patch adds code to recognize and report that automatic
task or functions are not currently supported.
2008-08-15 17:10:59 -07:00
Nick Gasson 026d941734 Avoid printing field widths in $display/$write output
This removes some unwanted artifacts from the output.
2008-08-15 19:43:16 +01:00
Stephen Williams 61b9c5e069 Pad signed expressions in continuous asignments
When the continuous assignment is signed, then sign-extend the r-value
in the few cases where the expression is stubbornly smaller then the
desired width.
2008-08-14 20:38:34 -07:00
Stephen Williams 4b646aca90 Account for signed multiply
When multiply is done in native words, the conversion to words from the
vp_vector4_t vectors must be done signed. This only matters if the
input operands are different sizes (and themselves signed) but will
not hurt even if we want an  unsigned result.
2008-08-14 20:37:04 -07:00
Stephen Williams 50c1533fdd Fix evaluation of logical equality with x bits.
Logical (in)equality needs to look at all the bits of both operands,
and cannot short circuit the test unless defined bits differ. If there
are undefined bits, the equality is undefined at that point, but return
x only if there are not other bits that make the results clearly
unequal.
2008-08-13 22:22:59 -07:00
Nick Gasson a577ee447b Generate process for sequential UDPs 2008-08-13 17:03:03 +01:00
Nick Gasson d7b85c42a0 Split sequential and combinatorial UDPs into separate functions 2008-08-13 11:57:05 +01:00
Stephen Williams 3def0e0dec Fix some expression elaborate vector width problems. 2008-08-12 21:32:21 -07:00
Stephen Williams dc6d3f4afb Fix a spurious non-local net.
During elaboration of continuous assignment that connected the rval
to the lval with a part select forgot to mark the signal it created
as temporary.
2008-08-12 21:31:39 -07:00
Stephen Williams 3d1f363be8 Handle special case of net assigned to net.
When nets are assigned directly to a net, we need to create a driver
to carry the strength. Normally, the implied drive of a continuous
assignment is carried by whatever gate the r-value expression ends
with, but with simble net-to-net assignment, there is no net so we
need to install a BUFZ to carry the assignment.
2008-08-12 21:03:38 -07:00
Nick Gasson dea54df71b Catch possibly NULL return value
This is caused by using a hierarchical reference (which can't
be translated to VHDL). The result of get_decl is NULL since
the signal has been declared in a different VHDL architecture.
Adding the assert is cleaner than having it segfault, for the
moment, until a nicer error message can be added.
2008-08-12 09:47:03 +01:00
Stephen Williams 6051150c14 Continuous assign no longer uses elaborate_net.
convert the continuous assign elaboration to use elaborate_expr
and synthesize methods instead of the elaborate_net methods of
PExpr. This exposes problems with the synthesize methods, but it
is a better way to do it.
2008-08-11 21:21:33 -07:00
Nick Gasson a3929330b0 Fix regression caused by UDP delay patch
translate_time_expr cannot be passed a NULL ivl_expr_t.
2008-08-11 20:53:13 +01:00
Nick Gasson c404b761b7 Change out' ports to buffer' when the signal is read
Previously this was handled by creating an internal
signal that was connected to the output and could also
be read inside the entity. The correct solution is to
make the output `buffer' rather than `out'. However, this
does not work in the case when an output is connected to
an output of a child entity, and that values is read
in the parent. In this case *both* the outputs of the child
and the parent need to be made `buffer'.
2008-08-11 20:48:28 +01:00
Nick Gasson 9b1f2d5971 Remove UDP debug messages from output 2008-08-11 20:37:10 +01:00
Nick Gasson 9d7e4ac15f Allow delays in combinatorial UDPs
Add a `after' clause to the `with .. select' statement.
2008-08-11 20:36:09 +01:00
Nick Gasson d55a3a073a Handle '?' in vl_to_vhdl_bit
The rough translation is '-', although the semantics are incompatible
in some cases (e.g. '-' = '1' is false)
2008-08-11 13:53:42 +01:00
Nick Gasson 01bf741983 Implement combinatorial UDPs
Using a `with .. select' statement
2008-08-11 13:23:50 +01:00
Nick Gasson bf3734110e Add VHDL syntax element for `with .. select' statement
This will be used to implement combinatorial UDPs
2008-08-11 13:09:52 +01:00
Nick Gasson 6dcf936807 Generate combined input for UDP devices
Combinatorial UDPs will be implemented with a `with ... select'
statemetnt. However the input to this must be "locally static".
This patch joins the inputs into a vector which can be used as
the select expression.
2008-08-11 12:58:46 +01:00
Stephen Williams 1d884cb0e9 Shuffle the argument list for the synthesize method.
In preparation for using the synthesize method to replace the
elaborate_net method of PExpr, rework the interface to the
synthesize() method. This changes no fnctionality, but does set
up the infrastructure for the next step.
2008-08-10 18:22:34 -07:00
Nick Gasson 8e0bf3ebff Add conversion from std_logic to (un)signed types
Implemented using the expression (0 => X, others => '0')
2008-08-10 11:22:23 +01:00
Nick Gasson 380e3a8121 Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl 2008-08-10 09:51:20 +01:00
Cary R 1f8ff7ff8d Pass a NULL expression when parameter expression elaboration fails
When elaborating a parameter expression fails we need to set the
expression to 0 since it has already been partially allocated.
Doing this allows us to not evaluate the dummy expression later.
2008-08-09 19:27:14 -07:00
Cary R b1f1c11441 User task and function arguments can be time or realtime
This patch adds the time and realtime properties for user
task and function arguments. It also make a common rule
for real and realtime since they are the same.
2008-08-09 19:10:09 -07:00
Cary R c918cf4a46 User task and function arguments can take an optional reg.
User task and function arguments can take an optional reg
property. This property is completely ignored by Icarus.
2008-08-09 19:04:17 -07:00
Cary R f835c7569e Check for a possible corrupt function definition and return.
If a function definition has no ports and no return type it is
assumed to be a bad definition so we don't check it further.
2008-08-09 18:46:18 -07:00
Martin Whitaker 5aecd044c5 Patch to fix pr2043585.
This patch fixes a bug in the VVP code generator that causes syntactically
incorrect code to be generated if an event expression contains a memory or
array port.
2008-08-09 18:22:46 -07:00
Cary R 2a389a9abe Display signal array size when using -delaborate.
This patch modifies one of the debug_elaborate messages to display
the array information when needed.
2008-08-09 18:10:59 -07:00
Nick Gasson 6527262348 Add correct file/line information to signals
This patch adds a FILE_NAME function for signals to extract
the file/line information from the net's LineInfo, replacing
the dummy values.
2008-08-09 16:57:26 -07:00
Stephen Williams 79e1273814 Do not consome pform defparams in module definition.
The list of defparams in the pform module definitions (in class Module)
should not be consumed when they are used. The module may be instantiated
moltiple times, so consuming the defparams during elaboration will cause
subsequent instantiations to not have the defparams. That's wrong.
2008-08-09 16:45:20 -07:00
Nick Gasson 709c850e69 Add correct file/line information to signals
This patch adds a FILE_NAME function for signals to extract
the file/line information from the net's LineInfo, replacing
the dummy values.
2008-08-08 20:35:27 +01:00
Nick Gasson 7ed8c0915d Add file/line comments to signal declarations 2008-08-08 20:28:16 +01:00
Nick Gasson eef1c968dc Add message that casex cannot be translated
...with the correct behavior. It would be possible to
just translate it as a regular VHDL case statement (as
it was before this patch). But the behavior is not
correct as VHDL only does the equivalent of case-equality
in case statements and this can be confusing when debugging
the output. An alternative might be to emit a warning rather
than an error.
2008-08-08 20:09:40 +01:00
Nick Gasson 0985158090 Handle %% in $display 2008-08-08 20:07:22 +01:00
Nick Gasson 090ae5fa56 Catch case where signal with same name in task and module
This fixes task3.14C
2008-08-08 19:47:20 +01:00
Nick Gasson 13cb81f4bb Add task signals to containing architecture
This is necessary to support the in-line expansion of tasks
2008-08-08 19:31:45 +01:00
Cary R ef66ca6498 Do a part select of the array selection result not the base array.
When doing the part select of an array selection you need to use
the result from the array selection to do the part select not the
base array signal.
2008-08-07 20:45:58 -07:00
Cary R d43452f88d Check all generate expressions for failure.
This patch adds code to check that the various generate expressions
evaluate correctly.
2008-08-07 20:41:24 -07:00
Cary R e719dc250a %load/av now matches %load/v for truncating/extension.
This patch adds code to make %load/av extend or truncate
a value like %load/v.
2008-08-07 20:34:20 -07:00
Nick Gasson bb0efda526 Make make_safe_name case insensitive 2008-08-07 17:58:42 +01:00
Nick Gasson e4d0a92d7c Division and modulus operators 2008-08-07 14:18:26 +01:00
Nick Gasson 28d782e13c Remove redundant verilog_support.vhd file 2008-08-07 13:10:53 +01:00
Nick Gasson 6f5f700cb9 Very minimal implementation of tasks
This expands the task in-line inside the process to avoid
problems with global variables (VHDL processes cannot
reference globals)
2008-08-07 10:54:39 +01:00
Nick Gasson a17924f819 Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl 2008-08-07 09:19:13 +01:00
Stephen Williams 893aae2ca4 Add BUFZ to input ports when necessary.
When driving an input port to a module, watch out for the case where
the net is also driven within the instance. If this is the case, take
pains to make sure what goes on in the instance doesn't leak out
through the input port. Add a BUFZ (continuous assignment) to isolate
the context from internal driving.
2008-08-06 21:04:52 -07:00
Nick Gasson 4cbec1c817 Add XNOR binary operand 2008-08-06 11:18:01 +01:00
Holger Wächtler d84771428a need to decrement string len if we have a '-' sign 2008-08-05 15:26:29 -07:00
Holger Wächtler 484d3ea36b this patch adds support for conversion of negative vpiDecStrVal in vpip_dec_str_to_vec4() 2008-08-05 15:26:22 -07:00
Holger Wächtler c71e930ffa $fscanf("%s"): accept '-' and '_' chars. 2008-08-05 15:26:16 -07:00
Holger Wächtler 15584a4f81 fix $fscan("%d") for values > 32 bit
The old code returns a vpiIntVal for $fscanf("%d") format strings. This
limits the maximum input range arbitrarily to 32 bit.

This patch implements %d parsing similiar to %b and %x.

'?' and 'X' chars are not accepted for %d format.
2008-08-05 15:26:09 -07:00
Nick Gasson f86f454956 Apply the last patch to if/case statements too
This further cleans up the output by removing more
useless `wait for 0ns' statements.
2008-08-05 11:09:51 +01:00
Nick Gasson e01e038cf9 Avoid generating useless `wait for 0ns' statements
If the final statement in a process is a non-blocking
assignment then there is no point adding a `wait for 0ns'
after it since it will be immediately followed by another
wait. This case is suprisingly common, so this patch helps
generate much cleaner output without breaking the cases
where the 0ns wait is actually required (e.g. to implement
non-blocking assignment properly).
2008-08-05 11:02:36 +01:00
Nick Gasson c849dfeec4 Add XNOR logic device 2008-08-05 10:45:01 +01:00
Nick Gasson 8d7b03576c Correctly implement unary XNOR
Forgot to negate the output.
2008-08-05 10:38:43 +01:00
Stephen Williams b292a5fc05 Create a branch object to be the argument to the access function.
The NetBranch object is connected, but not like an object, so the
NetPins object base class is factored out from NetObj to handle the
connectivity, and the NetBranch class uses the NetPins to connect a
branch.

Also, account for the fact that nets with a discipline are by default
real-valued.
2008-08-04 20:54:05 -07:00
Nick Gasson 72019959a8 Translate some ternary expressions to if statements
This re-implements some earlier functionality where
ternary expressions on an assignment RHS are translated
to an if statement.
2008-08-03 15:47:32 +01:00
Nick Gasson 9565ea1034 Add some whitespace above component instantiations 2008-08-03 14:50:13 +01:00
Nick Gasson 49a2693357 Add file / line number information to functions 2008-08-03 14:46:57 +01:00
Nick Gasson 10a5ca199d Add file / line number comments to instantiations 2008-08-03 14:38:08 +01:00
Nick Gasson c2f622327f Use ivl_scope_def_* for definition file/line numbers 2008-08-03 14:34:41 +01:00
Nick Gasson 0e2628a3fb Minimal implementation of IVL_LPM_MUX
This handles the (common) case of the select being only
1 bit wide. Implemented as a concurrent assignment with
a `when' clause.
2008-08-03 12:46:50 +01:00
Nick Gasson 45dfa28dba Remember signal pin a nexus was attached to
Also modify nexus_to_var_ref to set the correct array
offset when the signal is an array (the offset comes
from the pin).
2008-08-03 11:41:26 +01:00
Nick Gasson c8cbac58f5 Add forward declarations for functions
This patch adds a forward declaration for every user funciton.
This fixes VHDL compile problems if a function calls another
before it has been declared.
2008-08-03 10:50:31 +01:00
Nick Gasson c1b5424ca6 Implement assignment with multiple lvals
Multiple lvals are implemented by first assigning the complete
RHS to a temporary, and then assigning each lval in turn as
bit-selects of the temporary
2008-08-02 18:40:24 +01:00
Nick Gasson c706c94e38 Generate a vhdl_var_ref for every assignment lval
This completes the refactoring of make_assignment
necessary to implement multiple lvals.
2008-08-02 18:20:18 +01:00
Nick Gasson fad8abee34 Start refactoring make_assignment for multiple lvals
This patch lifts the RHS generating code out of the
lval-specific code and sticks a loop around the lvals.
2008-08-02 16:38:44 +01:00
Nick Gasson 9448c5939c Always user Ternary_* support functions for ternary assignments
Previously the code generator expanded ternary assignments to
and `if' statement. This patch replaces that with a single assignment
and a call to a Ternary_* support function. This will make it
much easier to support multiple lvals later.
2008-08-02 15:46:36 +01:00
Nick Gasson 752a90dc2f Insert blank line before VHDL process in output 2008-08-02 10:45:38 +01:00
Nick Gasson a60216ec15 Use ivl_process_* functions for file/line number information 2008-08-02 10:44:03 +01:00
Nick Gasson 5d0df8d880 Change format of line file/line numbers 2008-08-02 10:42:00 +01:00
Nick Gasson 1cd13ecdbd Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl 2008-08-02 10:37:22 +01:00
Stephen Williams c14987aa18 Merge branch 'master' into verilog-ams 2008-08-01 21:15:11 -07:00
Cary R aeec93a322 $time, $stime and $simtime return an integer rounded value for %f
The $time, $stime, $simtime (integer time) system functions should
return a rounded integer value in a real context.
2008-08-01 20:37:41 -07:00
Cary R 61930c3b6e Add file and line information to processes.
This patch adds file and line information to processes
(initial and always).
2008-08-01 20:13:29 -07:00
Cary R 296f1bacc1 vvp_vector4_t words are unsigned long.
The double to vvp_vector4_t constructor was not using the correct
declaration for the bit words. This worked as long as unsigned and
unsigned long were the same size (usually).
2008-08-01 20:10:52 -07:00
Nick Gasson bb80b432e6 Add comments file/line number comments
Added to entities, architectures, and processes
2008-08-01 21:21:42 +01:00
Stephen Williams be551a6b68 Add a stub vvp_net_t::delete method
Some compilers reference the delete method for the vvp_net_t object
even though it is never used. So provide a stub with an assert.
2008-08-01 09:48:59 -07:00
Nick Gasson e0834f7f38 Add NAND and NOR logic devices 2008-08-01 17:46:04 +01:00
Nick Gasson a26d91557b Add binary NAND and NOR operators 2008-08-01 17:42:26 +01:00
Nick Gasson 3f73c9bb54 Make sure argument to unary - is signed 2008-08-01 16:35:47 +01:00
Nick Gasson 09f3eb4a36 Don't bother calling reduction function if argument is std_logic 2008-08-01 16:27:55 +01:00
Nick Gasson 33885ed891 Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl 2008-08-01 08:25:38 +01:00
Nick Gasson d21277f1b9 Tidy up whitespace in output 2008-07-31 21:17:49 +01:00
Nick Gasson 7b0f675785 Add check for sequential UDPs 2008-07-31 21:08:59 +01:00
Nick Gasson db339b8fc3 Stub for UDP logic devices 2008-07-31 20:59:20 +01:00
Stephen Williams eca8a46b40 Merge branch 'master' into verilog-ams 2008-07-30 18:18:40 -07:00
Stephen Williams 4ca7f2a9bd Merge branch 'master' of ssh://[email protected]/~steve-icarus/git/verilog 2008-07-30 18:05:43 -07:00
Stephen Williams 221c63b766 Add some simple error checking. 2008-07-30 18:02:07 -07:00
Stephen Williams 9f04641fc7 Detect and elaborate AMS access functions.
Detect function call expressions that turn out to be calls to the
access function of a nature. Elaborate the access function and stub
the emit code. This gets the access function just short of the code
generator.
2008-07-30 18:01:41 -07:00
Cary R 3191b3efcb An included file should start at line 1.
The preprocessor was incorrectly setting the line when starting
an include file to the line it was called from instead of 1.
This would give incorrect line numbers for errors/warnings in
the included file.
2008-07-30 15:04:19 -07:00
Cary R 1a41ac3145 Update real to int conversion: -inf is 'b0 not 'b1 like +inf.
The new real to int conversion was incorrectly setting the
bits for minus infinity to all ones. This is incorrect in a
two's complement encoding where the largest negative number
would be a leading 1 followed by an infinite number of zeros.
2008-07-30 14:59:13 -07:00
nog 6d4dd5ae3b Fix macro argument replacements
When searching for macro arguments to replace, make sure that the
argument is not the begining of another identifier.
2008-07-30 14:52:04 -07:00
Cary R 6cb3d86d15 Update %cvt/vr to use new double to vector conversion (constructor).
This patch updates the %cvt/vr command to use the new double to vector
constructor. This allows the resulting bit pattern to be larger than
a long. The old method was producing incorrect results without a
warning for large bit values.
2008-07-30 14:40:14 -07:00
Cary R 7a4f85d382 Make .part/pv strength aware and resolv vec8_pv aware.
This patch makes .part/pv strength aware, resolv vec8_pv
aware. vvp_net_fun_t adds vec8_pv as a virtual function
with an appropriate error default. vvp_fun_signal should
full support vec8_pv (not tested and may not be needed).
2008-07-30 14:31:33 -07:00
Cary R 5207be0778 Use ivl_signal_dimensions to find arrays not ivl_signal_array_count
ivl_signal_dimensions() is the correct call to use to determine
if a signal is part of an array. If it is greater than zero the
signal is an array.
2008-07-30 14:25:29 -07:00
Cary R 2ceb0539af IVL_VT_LOGIC is default localparam type not IVL_VT_NO_TYPE
This patch fixes a bug where a local parameter with only a range
was incorrectly setting the default parameter type to IVL_VT_NO_TYPE.
This would create a compile time assert for any untyped
parameter/localparam immediately following it.
2008-07-30 14:16:18 -07:00
Cary R f9c67e21b2 Some variable part select arguments must be drawn before the part select.
Some variable part selects need to draw the select argument before the
variable part select is printed e.g.(.array/port).
2008-07-30 14:07:03 -07:00
Nick Gasson baa2363e85 Split logic device code into separate file 2008-07-30 10:13:08 +01:00
Nick Gasson e5b8abfb23 Remove debugging output 2008-07-29 21:15:51 +01:00
Nick Gasson 9f6f711f8d Remove unused variable 2008-07-29 21:08:50 +01:00
Nick Gasson 9a5b7bb0b0 Connect signals together if joined in a nexus 2008-07-29 21:03:00 +01:00
Nick Gasson eaf1cc9120 Fix assertion failure with arrayed signals 2008-07-29 19:47:17 +01:00
Nick Gasson 3bcd42dc8f Fix case where logic device has no valid output 2008-07-29 19:39:20 +01:00
Nick Gasson 744fbed783 Finish re-writing nexus code 2008-07-29 19:33:40 +01:00
Nick Gasson c9454b346e Fix module3.12B 2008-07-29 19:04:41 +01:00
Nick Gasson 5ec2c37e7e Get functions working again 2008-07-29 15:29:49 +01:00
Nick Gasson 25602e487d Comment 2008-07-29 15:12:51 +01:00
Nick Gasson e037ffd952 Create temporaries for LPM outputs 2008-07-29 15:09:58 +01:00
Nick Gasson 48c1a7982c Make seen_nexus private 2008-07-29 14:24:04 +01:00
Nick Gasson a842b327c7 Generate constant drivers as concurrent assignments 2008-07-29 14:02:05 +01:00
Nick Gasson f8034d69ef Fix constants in nexuses 2008-07-29 13:30:54 +01:00
Nick Gasson d94dac28a8 Remove redundant lpm_output 2008-07-29 13:08:13 +01:00
Nick Gasson 680c6f0503 Make sure LPMs have valid inputs/outputs 2008-07-29 13:06:21 +01:00
Nick Gasson 39717989a8 Call set_active_entity in the right places 2008-07-29 13:04:29 +01:00
Nick Gasson c26b7ce675 Port maps 2008-07-29 13:02:55 +01:00
Nick Gasson c6f6ea7358 Instantiation working again 2008-07-29 12:21:19 +01:00
Nick Gasson c0c838f1bc Logic devices now working again 2008-07-29 12:11:44 +01:00
Nick Gasson 1a45e9164f Find signal a logic device is connected to 2008-07-29 12:04:40 +01:00
Nick Gasson 8a5f129e56 Draw nexus in multiple passes 2008-07-29 12:00:26 +01:00
Nick Gasson 65c2ceb89d Build entity hierarchy in separate stages 2008-07-29 11:01:02 +01:00
Nick Gasson 7a2e9c02cd Simplify support function emitting code 2008-07-28 22:48:21 +01:00
Nick Gasson f88415b1d7 Conversion of std_logic to integer 2008-07-28 22:46:39 +01:00
Nick Gasson 1250010696 Merge branch 'vhdl' of [email protected]:nickg/iverilog into vhdl
Conflicts:

	tgt-vhdl/support.cc
2008-07-28 21:47:37 +01:00
Nick Gasson 506a0ba7d6 Support repeat in concatenation 2008-07-28 21:46:19 +01:00
Nick Gasson 1d4914c590 Undo last commit 2008-07-28 13:04:30 +01:00
Nick Gasson 3e28a10676 Compress support function names a bit 2008-07-28 13:02:04 +01:00
Nick Gasson 78028a3310 Fully support ternary expressions 2008-07-28 12:59:10 +01:00
Stephen Williams 25a27f9dd9 Parse contribution statements as far as pform.
Contribution statements have an l-value and r-value. Parse those
expressions into pform so that elaboration has something to work with.

In this process, this patch also changes the PECallFunction class to
use the vector template instead of the svector template. The latter
doesn't add anything over the STL vector template, so this is a start
of working the svector out.
2008-07-27 17:22:19 -04:00
Stephen Williams 03e306c805 Infrastructure for parsing analog process statements.
Organize the parsing infrastructure for parsing analog processes,
including holding them in scopes, and collecting analog statements.
2008-07-27 15:02:09 -04:00
Nick Gasson b9cecbef64 Make sure LPM comparison result is std_logic not Boolean 2008-07-27 19:05:49 +01:00
Nick Gasson 8b32096e2a Convert std_logic to Boolean in loop tests 2008-07-27 18:39:16 +01:00
Nick Gasson ba462eb8b7 Merge branch 'vhdl' of [email protected]:nickg/iverilog into vhdl 2008-07-25 20:00:26 +01:00
Nick Gasson 5a09819729 Catch case of select expression on non-variable 2008-07-24 16:00:12 +01:00
Nick Gasson d3296d4895 Refactor while/for loop code to use common base 2008-07-24 15:22:25 +01:00
Nick Gasson 39c9c54760 Add repeat statement 2008-07-24 14:52:06 +01:00
Nick Gasson 8bee5b1108 Add `forever' statement type 2008-07-24 14:30:10 +01:00
Nick Gasson e4c2400eb2 Refactor the expression->time code into a single function 2008-07-23 16:18:49 +01:00
Nick Gasson 1409207def Correctly indent case statements 2008-07-23 14:31:41 +01:00
Nick Gasson 30fdadc525 Support delays in logic devices 2008-07-23 13:40:42 +01:00
Nick Gasson a5db0297b0 Unary minus 2008-07-22 15:44:29 +01:00
Nick Gasson e25f946ac0 Merge branch 'vhdl' of file:///media/disk/data/iverilog/ into vhdl 2008-07-21 15:20:42 +01:00
Nick Gasson 2f4f075005 Typo 2008-07-21 15:20:40 +01:00
Nick Gasson 3ca85491ee Unary AND and XOR 2008-07-20 16:41:57 +01:00
Nick Gasson d8351ec1b2 Fix reduction OR in procedural code 2008-07-20 15:13:20 +01:00
Nick Gasson 77508b9afa Reduction OR operator 2008-07-20 15:10:00 +01:00
Nick Gasson 38de6ebf3a Compress support function definitions a bit 2008-07-19 21:04:52 +01:00
Nick Gasson af3ee49f57 Refactor support function code a bit 2008-07-19 20:49:55 +01:00
Nick Gasson 0cb6ea34d7 Move type conversion code into a separate file 2008-07-19 15:23:47 +01:00
Nick Gasson b6df73d3b9 Support functions for converting (un)signed -> boolean 2008-07-19 15:15:16 +01:00
Nick Gasson 2d79e1a2e0 Store the currently active entity 2008-07-19 14:45:00 +01:00
Nick Gasson 7b311b6adb Translate internal delays in assignments 2008-07-18 14:47:35 +01:00
Nick Gasson df4a380e42 Fix implementation of IVL_LPM_UFUNC
Function name was not correct.
2008-07-18 14:31:12 +01:00
Nick Gasson 6ff80e80a4 Catch case where (un)signed is converted to boolean 2008-07-18 12:30:24 +01:00
Nick Gasson 8b6b111541 Add IVL_LPM_CMP_EQ 2008-07-18 11:58:26 +01:00
Nick Gasson fd8f01e317 Add IVL_LPM_CMP_GE 2008-07-18 11:56:00 +01:00
Nick Gasson 00317dd47f Dummy implementation of $time 2008-07-18 11:50:05 +01:00
Nick Gasson e9637f6d11 Generate synthesisable code for sequential processes
Whilst adding `wait until ...' at the end of every
process is a valid translation of the input, it is not
actually synthesisable in at least one commercial
synthesiser (XST). According to the XST manual the
correct template is to use `wait until ...' at the
start of sequential processes and `wait on ...'
(equivalent to `wait until ...' with 'Event on all
the signals) at the end of combinatorial processes.
This patch implements that.
2008-07-17 17:36:42 +01:00
Nick Gasson 1f9ed2c5ec VHDL AST element for `wait on' statement 2008-07-17 17:23:21 +01:00
Nick Gasson 7677b59650 Make sure offset of IVL_LPM_ARRAY is integer 2008-07-17 16:41:34 +01:00
Nick Gasson 9cf4792d53 Translate array references in expressions 2008-07-17 14:47:10 +01:00
Nick Gasson 4d9f029000 Generate correct array bounds 2008-07-17 14:38:07 +01:00
Nick Gasson 9916686c24 Convert constant bits to integers 2008-07-17 14:29:56 +01:00
Nick Gasson c86377790f Automatically convert constant bit strings to integers 2008-07-17 14:26:35 +01:00
Nick Gasson 2a791bfb38 Assignment to arrays 2008-07-17 13:41:44 +01:00
Nick Gasson 1d3ac6bc1f Generate VHDL array type declarations of Verilog arrays 2008-07-17 13:08:55 +01:00
Nick Gasson 3fa5a04947 Merge branch 'vhdl' into array 2008-07-17 12:01:09 +01:00
Nick Gasson 7c5b0f737c Class for VHDL type declarations 2008-07-17 11:59:02 +01:00
Nick Gasson c116808fdb Remove duplicated code 2008-07-17 11:46:36 +01:00
Nick Gasson 553f3d77a9 Code for VHDL array type 2008-07-17 11:43:59 +01:00
Nick Gasson 642fbe9fc5 Correct check for arrays 2008-07-17 11:31:06 +01:00
Nick Gasson 395a2248d8 Make sure 1-bit constants are std_logic not (un)signed 2008-07-16 16:52:15 +01:00
Nick Gasson be67cae29f Add translation for IVL_ST_CASEX 2008-07-16 16:42:44 +01:00
Nick Gasson f62a00bedb Fix LPM binop with different signedness
Need to explicitly cast between signed/unsigned to
make sure both arguments have the same type or the
VHDL won't compile.
2008-07-16 16:20:08 +01:00
Nick Gasson 646a6056a2 Add IVL_LPM_CMP_EEQ support 2008-07-16 12:50:55 +01:00
Nick Gasson 4504c2bceb Fix initialisation order bug with `if' statements
If an assignment appears inside an if statement branch
it could be incorrectly used as the signal's initial
value.
2008-07-16 12:11:00 +01:00
Nick Gasson d343db34fd Fix initialisation order
Initial processes set a magic flag in the code generator
which allows it to push constant assignments into the
VHDL signal initialisation and omit the assignment.
However, it should only do this if the signal has not
already been read (otherwise the previous read would
not get the undefined value as expected)
2008-07-16 12:00:11 +01:00
Nick Gasson b5e12077b2 Fix assignment to lval slice
It was broken in yeserday's refactoring
2008-07-15 18:40:30 +01:00
Nick Gasson f3753ea9ad Add warning that arrays are not yet implemented 2008-07-15 18:09:18 +01:00
Nick Gasson 45e289d32d Implement IVL_LPM_SHIFTL/R 2008-07-15 18:01:37 +01:00
Nick Gasson 40cabff44f Leave blank line at end of function 2008-07-15 16:30:50 +01:00
Nick Gasson a9c98ad5f2 Handle `if' with empty cond_true part
Fixes assertion failure with following statement:

if (foo)
  begin
  end
else
  ...
2008-07-15 14:26:19 +01:00
Nick Gasson b8e758edf0 Refactor LPM code 2008-07-15 14:09:24 +01:00
Nick Gasson 0b48f69b4e Tidy up blocking assignment code 2008-07-15 10:44:48 +01:00
Nick Gasson d1e7e325b7 Remove redundant edge_detector function 2008-07-14 21:34:48 +01:00
Nick Gasson 75b1db0add Fix assignment with ternary RHS
This was also broken in the last commit
2008-07-14 21:27:21 +01:00
Nick Gasson 6e965523a1 Fix PV assignment (was broken in last commit) 2008-07-14 21:09:19 +01:00
Nick Gasson 8589c0691b Refactor assignment code 2008-07-14 21:04:09 +01:00
Nick Gasson 99ef8ec4f1 Simplify edge detector code
Now generates a `wait until' statement rather than a
sensitivity list.
2008-07-14 20:29:49 +01:00
Nick Gasson d22c9a8b05 Simplify blocking assignment
Now generates 'wait for 0 ns' after non-blocking assignment
2008-07-14 19:54:45 +01:00
Nick Gasson f84f50842c Support bufif for tri1 nets 2008-07-14 19:13:11 +01:00
Nick Gasson 65720f49fe Simple bufif cases 2008-07-14 19:00:58 +01:00
Nick Gasson 6243736481 Pull-up/pull-down logic devices 2008-07-14 12:04:20 +01:00
Nick Gasson e331e4831b Fix nexus_to_expr where nexus has IVL_LPM_SELECT_PV 2008-07-14 11:53:38 +01:00
Nick Gasson 78ee61558d Remove redundant test
Signal is guaranteed to appear in arch_scope or its parent
by the surrounding `if' statement.
2008-07-13 15:27:07 +01:00
Nick Gasson 07c4ff7ea7 Add assertion about result of lpm_to_expr 2008-07-13 15:26:03 +01:00
Nick Gasson e5422dddd2 Remove useless `ignore' param to nexus_to_expr 2008-07-13 15:24:35 +01:00
Nick Gasson 6af201ea03 Refactor nexus expansion functions.
Now a single function nexus_to_expr
2008-07-13 15:17:14 +01:00
Nick Gasson 27a40cfdcd Constant assignments to outputs
If the Verilog source contained a continuous assignment
of a constant to an output, it would not be present in
the VHDL output. This patch generates a VHDL continous
assignment in these cases.
2008-07-13 13:02:17 +01:00
Nick Gasson 3bd480a375 Allow ouput to be read if connected to child output
If output P of A is connected to output Q of B (and A is
instantiated inside B) then VHDL does not allow B to read
the value of Q (also P), but Verilog does. To get around
this the output Q is mapped to P_Sig which is then connected
to P, this allows B to read the value of P/Q via P_Sig.
2008-07-13 12:41:02 +01:00
Nick Gasson aa951af2b7 Change 'signdness' to 'signdness' 2008-07-10 19:27:17 +01:00
Nick Gasson 55747bf79d Refactor signdness changing code into a single function
This is the code that generated calls to signed/unsigned in
the VHDL output.
2008-07-08 13:07:11 +01:00
Nick Gasson 1cd7689d03 Fix casting with signed/unsigned expressions
Previously the code generator tried to infer the VHDL types. Now it
takes a much more dumb approach and forces the VHDL type to be
the same as the ivl type (derived from ivl_expr_signed and
ivl_expr_width) in the expression tree. This works much better :-)
2008-07-08 12:58:50 +01:00
Nick Gasson bd5cc96956 Correct vector sizes for bit select 2008-07-08 00:20:31 +01:00
Nick Gasson a0dbb1aa5d Fix more bugs in part selects 2008-07-07 21:45:27 +01:00
Nick Gasson 4777966b4c Bit select bug fixes 2008-07-07 21:19:59 +01:00
Nick Gasson 860a74ddd8 Allow LPMs in port maps 2008-07-07 20:41:29 +01:00
Nick Gasson 2bb645e0bc Refactor LPM code to allow lpm->expr function 2008-07-07 19:46:18 +01:00
Nick Gasson 47db80315c Add sign extension LPM 2008-07-07 19:27:52 +01:00
Nick Gasson 0348664512 Correctly determine VHDL type of LHS of part select 2008-07-07 16:35:39 +01:00
Nick Gasson 3987e0753d Fix case where booleans are compared against vectors 2008-07-07 16:31:27 +01:00
Nick Gasson 6b73cc39a5 Add Active_High support func and fix LPM part select 2008-07-07 16:17:54 +01:00
Nick Gasson b0de1a8d7e Implement part select for LHS of assignment 2008-07-07 16:11:45 +01:00
Nick Gasson 37fe6e4219 Dummy implementation of IVL_LO_BUF* 2008-07-07 15:49:51 +01:00
Nick Gasson 89cdbf63be Reduction LPM types 2008-07-07 15:45:20 +01:00
Nick Gasson 7f955cc070 Move the VHDL support package 2008-07-07 15:36:13 +01:00
Nick Gasson 4db5b9d7ed Add unary OR/NOR
These are currently implemented with reference to an external
Reduce_OR function
2008-07-07 15:23:57 +01:00
Nick Gasson dadd145d09 Add message for unsupported LPM nexus pointer 2008-07-07 15:04:28 +01:00
Nick Gasson bdf5ee7ab7 Concat LPM 2008-07-07 14:48:57 +01:00
Nick Gasson ebaa4c7d5d Implement assignment to part select properly
Previously the base of the lval was ignored, this ensures
the correct assignment is generated.
2008-07-07 11:00:27 +01:00
Nick Gasson c33600bcc3 Add concatenation operator 2008-07-06 18:21:34 +01:00
Nick Gasson 85d2cc78d6 Finish ternary operator expansion 2008-07-06 17:56:48 +01:00
Nick Gasson 18071562ba Partially implement ternary expressions
This handles the case where the expression appears as the
right hand side of an assignment. The expression is converted
into a regular if statement.
2008-07-04 21:55:51 +01:00
Nick Gasson 5aeff6d47d Merge blocking and non-blocking assignment code 2008-07-04 20:07:38 +01:00
Nick Gasson a298b03735 Add bitwise OR 2008-07-04 12:05:49 +01:00
Nick Gasson 3d0a2b55ce Avoid declaring same function multiple times
If it appears in multiple places in the hierarchy
2008-07-04 12:03:37 +01:00
Nick Gasson 19871efd5a Fix bug where sensitivity might reference undefined signals 2008-07-04 11:58:33 +01:00
Nick Gasson 1410c339de Make sure any calls to numeric_std Resize have correct type
The signed/unsigned-ness of an expression needs to be
preserved over any call to Resize. Also add a sanity
check to make sure non-vector types are not resized.
2008-07-04 11:36:11 +01:00
Nick Gasson 96d32b29c9 Translate logical expressions correctly.
For logical AND/OR in VHDL both operands must be of the
same type (Boolean)
2008-07-04 11:23:32 +01:00
Nick Gasson 88816e150a Properly parenthesise unary operators 2008-07-04 11:17:24 +01:00
Nick Gasson 409fc4dc19 Check if case expression variable is already defined
Verilog_Case_Ex is used as a temporary to store the result of
any non-static case expression. This fixes a bug where it would
be declared multiple times if there were multiple case statements
in a block.
2008-07-04 11:15:34 +01:00
Nick Gasson c54b36c902 Add logical AND operator 2008-07-04 11:10:20 +01:00
Nick Gasson 19cbab78b2 Tidy up code to generate default branch of case 2008-07-03 20:04:47 +01:00
Nick Gasson 1736cd9bc8 Fix uneccessarily complicated generated case statement
No need to generate separate case test variable if the
test in the VL source is a simple variable reference.
2008-07-03 16:27:36 +01:00
Nick Gasson a5264e9995 Make sure all choices are covered in case statement 2008-07-03 16:17:56 +01:00
Nick Gasson 6868127ba3 Make sure case expression has the correct type 2008-07-03 16:14:17 +01:00
Nick Gasson dbbadbc309 Make sure the renamed signal is used in the sensitivity list 2008-07-03 16:13:02 +01:00
Nick Gasson fb08164cbc List some more illegal VHDL names 2008-07-03 15:20:43 +01:00
Nick Gasson 7e999c5496 Fix continuous assignment of constants
E.g. in assign p = 1 the RHS signal in the generated LPM now
has a correct intial value (and it will never be written to
elsewhere)
2008-07-03 15:13:12 +01:00
Nick Gasson 4fac825457 Add PV part select type 2008-07-03 14:45:54 +01:00
Nick Gasson 35c66744db Cleanup and remove debug output 2008-07-01 11:31:00 +01:00
Nick Gasson 930e04f6c7 Ensure port map expressions are globally static 2008-07-01 11:28:02 +01:00
Nick Gasson 37756b8d06 Avoid mapping a signal to itself 2008-07-01 11:13:02 +01:00
Nick Gasson 596c93ce7e Rename instance if it has the same name as the type 2008-07-01 11:05:24 +01:00
Nick Gasson edfae1abfb PV LPM part select type 2008-07-01 11:02:49 +01:00
Nick Gasson 624943b3ca Simplify port map generation code 2008-07-01 10:59:31 +01:00
Nick Gasson ef89a760d6 Add vhdl_element::print method for debugging 2008-07-01 10:44:20 +01:00
Nick Gasson 050aa277ae Make vhdl_element::emit a little more generic 2008-07-01 10:37:22 +01:00
Nick Gasson f03dfb50ad Refactor nexus_to_var_ref 2008-07-01 10:33:46 +01:00
Nick Gasson 6e8474f584 Fix bug where func had to be declared before use 2008-06-30 17:58:15 +01:00
Nick Gasson 4e73b1b133 Fix bug when resolving nexus to VHDL signal 2008-06-30 17:47:45 +01:00
Nick Gasson e08e29c8b4 Add UFUNC LPM type 2008-06-30 16:35:29 +01:00
Nick Gasson b82ca28190 Add XOR logic type and fix part select 2008-06-30 16:18:55 +01:00
Stephen Williams e02d186946 Handle multiple passes of scope and defparam elaboration.
When generate schems and instance arrays are nested, it takes
multiple iterations of elaborate scope, defparams and evaluate
parameters before everything is worked out. Rework the work item
processing so that the loop elaborates scopes and runs defparams
in phases. The phases are needed so that we can tell when the
remaining defparams are orphaned.
2008-06-30 03:46:46 +02:00
Stephen Williams d9b02657a7 Modules within generate schemes are not default roots.
Modules mentioned within generate schemes are not candidates for
defaults guesses at root modules. They are, obviously, used within
the generate schem.
2008-06-28 13:34:46 -05:00
Stephen Williams d761a2273c Run generate schemes after defparams.
We must run generate schemes after running defparams because the
defparams may define the results of the generate schemes. So put
the generate schemes for a module scope into elaborator work items.
2008-06-28 13:06:14 -05:00
Stephen Williams e3d9cc30a8 Checkin some developer convenience scripts. 2008-06-28 09:51:42 -07:00
Stephen Williams 1ef7994ae2 Handle indexed defparams.
The l-value of a defparam assignment is a hierarchical name that may
include array selects to select scopes from module arrays. Therefore
it makes no sense to store parsed defparams in a map. Instead, they
should go into an ordered list. This also maked more sense because later
defparams *may* have the same name as a previous defparam, and will
override the previous defparam. So replace the map of parsed defparams
with a list of parsed defparams.

Also, as soon as the defparam expression is elaborated, the list entry
is no longer needed, so delete it. Save memory.
2008-06-28 09:30:09 -07:00
Nick Gasson 081f397460 Implement LPM part select 2008-06-27 14:58:03 +01:00
Nick Gasson f800298d01 Fix memory leak 2008-06-27 12:29:50 +01:00
Nick Gasson 301a25303f Remove useless assertion 2008-06-27 12:21:53 +01:00
Nick Gasson b24eb6ce88 Handle local variables in functions 2008-06-27 12:21:27 +01:00
Nick Gasson fd60bfd3d2 Rewrite function parameter finding code 2008-06-27 12:18:39 +01:00
Stephen Williams da2c4b0fa1 Multiple passes for run_defparams.
It is possible for defparams to not find their target the first time
around, because the elaboration of the target scope is not yet done.
So retry the defparams once for each scope by putting it on a work
item in the elaborator_work_items list.
2008-06-25 22:02:22 -07:00
Stephen Williams 4251979e8b Merge branch 'master' into defparam-rework 2008-06-25 20:26:01 -07:00
Cary R 12783674cb Clean up compiler warning. 2008-06-25 16:34:54 -07:00
Cary R c17ffcae2c Rework previous patch to use the correct method. 2008-06-25 15:42:41 -07:00
Cary R 897f14e60a Fix memory leak in recent patch. 2008-06-25 15:42:34 -07:00
Cary R 4163eb28d0 Copy file and line info during a macro expansion.
The file and line number information needs to be copied when
doing a macro expansion. This prevents a macro that expands to
an `ifdef of other construct that needs to push the stack
from core dumping.
2008-06-25 15:42:29 -07:00
Nick Gasson 500442e5c5 Working function calls 2008-06-25 22:15:57 +01:00
Stephen Williams 8c54803094 vpi_get_value of integer values replaces x/z bits with 0.
In arithmetic expressions, vectors with x/z are replaced with 0,
but vpi_get_value replaces x/z bits with 0 bits without replacing
the whole vector.
2008-06-25 13:59:39 -07:00
Nick Gasson 2baf31dff8 Fix bug with $display and integer literals 2008-06-25 21:54:11 +01:00
Nick Gasson d997397c38 Generate function calls with parameters 2008-06-25 21:49:22 +01:00
Nick Gasson 7773000c36 Generate function declarations 2008-06-25 21:40:35 +01:00
Nick Gasson 042f7ccbcd Generate a return type for functions 2008-06-25 18:43:50 +01:00
Nick Gasson 44aa8a6b91 Associate signals with scopes rather than entities 2008-06-25 18:12:57 +01:00
Nick Gasson 43c671cb5c Emit VHDL for function declarations 2008-06-25 18:00:48 +01:00
Nick Gasson a3df37b851 Initial code to generate function calls
Also catch a few null-pointer issues
2008-06-25 17:29:09 +01:00
Nick Gasson c01c2bd742 Dummy code for handling function scopes 2008-06-25 12:48:46 +01:00
Stephen Williams 533ee87bb1 Delay elaborate of instance array scopes to allow defparams to propagate.
When we detect that a module instance is an array of instances, delay
the elaboration of the array until after the first defparam processing
is complete. This allows for defparam statements to control the
instantiation of module instance arrays.
2008-06-24 22:03:28 -07:00
Stephen Williams c810406195 run scope elaboration as queued work items.
Putting scope elaboration into work queue items allows for handling
more complex processing order. The elaboration_work_list queue drives
the processing of elaborate_scope and parameter evaluation.
2008-06-24 20:28:08 -07:00
Larry Doolittle 3ec8a867db Spelling fixes
comments, documentation, a variable name, and a couple of messages
2008-06-24 17:01:45 -07:00
Nick Gasson 899a70908e Fix small bug with initialisation and ammend comments 2008-06-24 20:13:18 +01:00
Nick Gasson bf95d77562 Finish replacing vhdl_process with vhdl_procedural 2008-06-24 20:01:06 +01:00
Nick Gasson db992e808f Start using vhdl_procedural instead of vhdl_process 2008-06-24 19:54:22 +01:00
Nick Gasson f2aca68b82 Add new vhdl_procedural superclass for process/task/func 2008-06-24 19:50:57 +01:00
Nick Gasson 12b448ef01 Merge branch 'vhdl' of [email protected]:nickg/iverilog into vhdl
Conflicts:

	tgt-vhdl/vhdl_syntax.cc
2008-06-24 19:42:35 +01:00
Nick Gasson e77bb0157e Remove redundant methods from vhdl_arch 2008-06-24 19:39:05 +01:00
Nick Gasson 75631bd8f1 Move is_inital code out of vhdl_process into vhdl_scope
Part of tidy up before implementing functions
2008-06-24 19:06:06 +01:00
Nick Gasson 63b1887ff2 Refactor code to use the new vhdl_scope class 2008-06-24 18:52:25 +01:00
Nick Gasson ba36e47575 Add new vhdl_scope class and refactor 2008-06-24 18:12:00 +01:00
Nick Gasson 3866c4526e Simplify code to emit operators 2008-06-24 14:58:58 +01:00
Nick Gasson cb08f02de1 Resize signed/unsigned bit vectors correctly 2008-06-24 10:58:21 +01:00
Nick Gasson 4188fbecee Add XOR operator and catch default case branch 2008-06-24 10:55:45 +01:00
Nick Gasson f261bf7e97 Fix bug where variables could be declared twice 2008-06-23 15:13:10 +01:00
Nick Gasson 88dc9b6b63 Remove debugging information from the output 2008-06-23 15:02:26 +01:00
Nick Gasson 632a265e14 Fix casting/resizing order bug 2008-06-23 15:00:55 +01:00
Nick Gasson 449cd0a76e Correctly generate signed/unsigned types 2008-06-23 14:28:27 +01:00
Nick Gasson 181a53d3ed Merge branch 'master' of git://github.com/steveicarus/iverilog into vhdl 2008-06-23 13:48:56 +01:00
Nick Gasson 44958409f5 A slightly smarter $display 2008-06-23 13:45:24 +01:00
Nick Gasson f81129aa68 Fix some bugs with blocking assignment 2008-06-23 13:36:28 +01:00
Nick Gasson e5ef0d97bd Fix signed/unsigned resizing 2008-06-23 13:04:28 +01:00
Nick Gasson 469036990a Output blocking assignments in the right place 2008-06-23 12:30:48 +01:00
Nick Gasson d06f5c7c54 Emit loop statements with the correct indent 2008-06-23 12:27:30 +01:00
Nick Gasson 9911939576 Simplify casting code 2008-06-23 12:21:10 +01:00
Nick Gasson c9ace14c40 Shift operators working correctly 2008-06-23 12:14:12 +01:00
Nick Gasson d5cdb91d55 Handle complex expressions in case statement 2008-06-23 11:36:12 +01:00
Stephen Williams 360be597a8 Minor cleanup and comments.
The initial elaboration needs better comments/documentation.
2008-06-21 18:36:46 -07:00
Nick Gasson 75f7c9ae0c Only move constant assignments into initialisation 2008-06-21 16:40:18 +01:00
Nick Gasson c926454a41 Statements might be emitted in wrong order 2008-06-21 16:33:05 +01:00
Nick Gasson 5cfe7ea0aa Tidy up output 2008-06-21 16:28:07 +01:00
Nick Gasson c70fb4ba08 Simple implementation of IVL_EX_SELECT 2008-06-21 16:17:44 +01:00
Nick Gasson 7cba9f3cb2 Shift left/right 2008-06-21 15:19:33 +01:00
Nick Gasson d6acb8d059 Less than / greater than 2008-06-21 15:16:22 +01:00
Nick Gasson ec23b70bb7 While loops 2008-06-21 15:13:44 +01:00
Nick Gasson 58f2f5007d Bitwise AND 2008-06-21 15:05:48 +01:00
Nick Gasson 0caf4fd9d0 Add case statement 2008-06-21 15:03:36 +01:00
Nick Gasson 037ce08f72 Fix tiny bug in $display code 2008-06-21 14:42:54 +01:00
Cary R 27cdd27889 Add .cast/int and update .cast/real.
This patch adds .cast/int and updates .cast/real to act as a local
(temporary) net and to support either a signed or unsigned input.
The vvp_vector4_t class not can convert an arbitrarily sized double
to a vector value. This removes the restriction of lround().

Also document the new statements.
2008-06-20 19:45:18 -07:00
Larry Doolittle f60a6561bb Cast strlen to int for printf field width
strlen is a size_t, and the * field width takes an int.
Make this an explicit cast.  It's good for 64-bit machines
and squelches warnings from gcc-4.3.
2008-06-20 15:54:32 -07:00
Nick Gasson 204862ac3c Implement $write 2008-06-20 19:00:07 +01:00
Nick Gasson 0f50849fbb Add call to To_Integer when printing signed/unsigned 2008-06-20 18:26:39 +01:00
Nick Gasson 404c22ac86 Improved implementation of $display 2008-06-20 11:51:13 +01:00
Stephen Williams fe555e4539 Merge branch 'master' of ssh://[email protected]/~steve-icarus/git/verilog 2008-06-19 21:32:18 -07:00
Stephen Williams c87e629150 Better handle nesting of scopes inside generate blocks.
Within generate schemes it is possible to have nested scopes, even
more liberally then outside generate blocks. So see to it that the
scopes properly stack with the generate blocks, and that wires and
behaviors are put in the right scopes.
2008-06-19 21:31:53 -07:00
Stephen Williams b9d6c816f1 Properly evaluate a unary ! with logic argument and real result. 2008-06-19 19:14:19 -07:00
Stephen Williams 0153a25061 Elaborate nets with real-valued parameters. 2008-06-19 19:13:50 -07:00
Cary R 476a4c7bc4 Add a script to manually build the version.h file.
This script is used to manually build a version.h file.
It is needed when building with MinGW using a cygwin
hosted repository.
2008-06-19 16:59:22 -07:00
Nick Gasson 08d80b35cb Rename signals that would be illegal VHDL names 2008-06-19 16:15:47 +01:00
Nick Gasson 6622b5fe3a Compare logic values for === and !== 2008-06-19 16:08:33 +01:00
Nick Gasson d7bb5658f2 Translate IVL_ST_DELAYX statements 2008-06-19 12:16:19 +01:00
Stephen Williams 2f3627cd6d Allow generate schemes to generate task/function definitions.
Generating task/function definitions involves getting the functions
to put themselves into the generate scheme instead of the module,
and getting elaboration to elaborate those definitions in the
generate scheme.
2008-06-18 21:54:58 -07:00
Stephen Williams ce9fd0147f Detect and warn about anachronistic use of begin/end in generate.
Verilog-2001 only allows a single generate item within a generate-
endgenerate region, but allowed one to collect generate schemes with
begin/end blocks. Verilog-2005 cleaned up that mess, and it is the
2005 syntax that Icarus Verilog implements. This patch detects the
anachronistic use of begin/end within the generate region, ignores
the begin/end words, and prints a warning that the user is using an
obsolete syntax.
2008-06-18 20:33:30 -07:00
Nick Gasson be12f56856 Document blocking assignment behaviour 2008-06-18 14:04:16 +01:00
Nick Gasson e0f41198d6 Blocking assignment working correctly 2008-06-18 13:49:03 +01:00
Nick Gasson fb31a88c51 Blocking assignment nearly working 2008-06-18 13:30:19 +01:00
Nick Gasson 254ccb9ccb First passing at blocking assignment 2008-06-18 13:06:27 +01:00
Nick Gasson d2bebee9d9 Refactor before adding blocking assignment 2008-06-18 12:51:11 +01:00
Stephen Williams b2c9352bb5 Merge branch 'master' of ssh://[email protected]/~steve-icarus/git/verilog 2008-06-17 21:45:58 -07:00
Stephen Williams 15481a9520 Elaborate block scopes burried in generate schemes.
Named begin/end blocks burried within generate schemes need to be
elaborated. Handle this by remembering to elaborate_scope on the
statements within the generate scheme.

In the process, clean up/regularize some of the member names and
methods.
2008-06-17 21:45:37 -07:00
Stephen Williams 37723698dc Handle non-real operands to real division.
This handles the general case of a non-real operand to a real-valued
division. This can turn up if only 1 operand of a divide is real. In
this case the division as a whole is real and the other operand must
be cast to real.

This method creates an extra node, but it should be a very compact
node and this node does no evaluation tricks so in the run time should
be no more expensive then folding the cast into the .arith/div.r itself.
2008-06-17 17:07:19 -07:00
Nick Gasson af8c08e6a7 Allow optional VHPI $finish implementation 2008-06-17 20:16:16 +01:00
Nick Gasson 01249000c3 Temporarily treat blocking assignment as non-blocking 2008-06-17 14:07:36 +01:00
Cary R f6edd098a9 More file name and mode checks for $fopen{a,r,w}?.
This patch adds checks that $fopen is only called with a valid
mode argument. It also checks that the file name for $fopen{a,r,w}?
is a valid looking file name (all characters satisfy isprint()).
The later should prevent creating weird file names because of
Verilog bugs.
2008-06-16 18:00:31 -07:00
Cary R 6321fb6a92 Pad Octal string value correctly.
This patch changes the base oct to string converter to correctly
pad the top digit. x or xx should display as a single lower case
x when they are located in the top bits. Before these were being
interpreted as 00x or 0xx and displayed X. Also modified the hex
conversion to use this same scheme instead of a loop.
2008-06-16 17:58:16 -07:00
Stephen Williams 69ba009439 Cleanup the resolver function.
First, handle the trivial (but possibly common) resolution cases in
inlined code, and only call the complete function for the complicated
cases. Then clean up the complex function for readability, and account
for the constraints that the front-end function established.
2008-06-16 17:45:08 -07:00
Stephen Williams 86e5762b1c Compact of vvp_vector4_t in arrays.
Arrays of vvp_vector4_t values redundantly store some fields in every
word. Create a special type that stores vvp_vector4_t values in a form
that does not duplicate the width of all the items. This can save a lot
of space when big memories are simulated.
2008-06-16 15:02:07 -07:00
Stephen Williams 49363c660c Remove the duplicate schedule_assign_vector.
The schedule_assign_plucked_vector is a better way to implement the
schedule_assign_vector, or at least no worse, so remove the now
redundent schedule_assign_vector.
2008-06-16 13:40:20 -07:00
Nick Gasson 1debbc3100 Simplify edge_detector() a bit 2008-06-16 20:06:06 +01:00
Nick Gasson ae0b09dd3a Don't bother emitting else part if it's empty 2008-06-16 19:53:42 +01:00
Nick Gasson 8d0afa632d Subtraction and multiplication LPM devices 2008-06-16 19:49:24 +01:00
Nick Gasson 561953e494 Minial LPM to support continuous assignments 2008-06-16 19:41:01 +01:00
Nick Gasson 83a7796b74 Make sure signal names conform to VHDL rules 2008-06-16 17:37:17 +01:00
Nick Gasson ce72eb4eb4 Fix Valgrind warnings 2008-06-16 14:26:38 +01:00
Nick Gasson 7cde5f247e Add translation for not-equals operator 2008-06-16 12:47:41 +01:00
Nick Gasson 849e7cb4d5 Add equality operator 2008-06-16 12:20:28 +01:00
Nick Gasson 92c823680a Fix crash when if' statement had no else' 2008-06-16 12:13:01 +01:00
Stephen Williams 05f1541903 Make reg initializations account for generated scope.
During parse, reg initialization may be in generated scopes. Handle
that properly.
2008-06-14 21:50:48 -07:00
Stephen Williams 30d42e2806 Allow l-value part select to be out of bounds.
It is legal (though worthy of a warning, I think) for the part select
of an l-value to me out of bounds, so replace the error message with
a warning, and generate the appropriate code. In the process, clean
up some of the code for signal l-values to divide out the various kinds
of processing that can be done. This cleans things up a bit.
2008-06-14 21:22:55 -07:00
Cary R ebdf4e478a Rework more compiletf and calltf routines in the vpi directory.
This is a major rework on the sys_fileio routines. They now have
improved compiletf routines and the calltf routines are now
standardized. Along the way a few bug were fixed as well. Some
updates to other vpi files as well.

I changed the order of the $fputc() arguments to match C and the
rest of the system functions like it ($fungetc, etc.). I recently
fixed $fungetc() so I'm assuming the $fputc() needs the same fix.
It's an Icarus specific function.
2008-06-14 20:13:52 -07:00
Stephen Williams f6bc1afcbb Merge branch 'master' of ssh://[email protected]/home/u/icarus/steve/git/verilog 2008-06-14 20:00:51 -07:00
Stephen Williams 9013dcb527 Signed load-and-add for arrays.
The load-and-add for vectors %load/vp0/s can be combined with the
load-and-add for array words, and the %load/avp0/s added to round
out the combinations. This can make for fewer instructions when
words are padded in arithmetic expressions.
2008-06-14 19:59:57 -07:00
Stephen Williams dbe13aecea Signed load-and-add for arrays.
The load-and-add for vectors %load/vp0/s can be combined with the
load-and-add for array words, and the %load/avp0/s added to round
out the combinations. This can make for fewer instructions when
words are padded in arithmetic expressions.
2008-06-14 18:16:23 -07:00
Stephen Williams 6521ceaf92 Union scope and parent pointers for signals.
If a signal is part of an array, then it can get its scope from its
parent, so the scope and parent pointers can go into a union.
2008-06-14 16:17:25 -07:00
Stephen Williams f497dbf01e Created too mane vvp_net_t objects?
The functor_ref_lookup() function fills its argument in with the
vvp_net_t* pointer that matches the var name, so there is no need
to create the vvp_net_t object before then.
2008-06-14 15:31:48 -07:00
Nick Gasson 8a9486eb49 Eliminate useless Resize() call 2008-06-14 18:11:10 +01:00
Nick Gasson 2fb57805ea Use signed rather than std_logic_vector
Arithmetic operators now working correctly
2008-06-14 18:03:25 +01:00
Nick Gasson 919c1d695c Adding binary + 2008-06-14 17:09:31 +01:00
Stephen Williams 1530594b4b Implement vpiIndex for vpiMemoryWord objects.
The vpiIndex is really just a different view into the same object,
so implement the trickery needed to support a vpiIndex with the
absolute minimum memory cost.
2008-06-13 22:05:19 -07:00
Stephen Williams 6f0d8e8dda Load_add_immediate to work with signed expressions
The %load/vp0 instruction adds a signed value to the signal value being
loaded, but it doesn't allow for a signed source vector. Add the
%load/vp0/s instruction that pads the loaded vector, and add the code
generator details to properly use it.
2008-06-13 20:23:40 -07:00
Stephen Williams 62d7c081dc Sign extend signed vectors when getting vpiIntVal.
When getting values using vpi_get_value, the vpiIntVal is the integer
value and should be sign-extended if the source value is signed.
2008-06-13 19:47:48 -07:00
Cary R f78994b66c Allow &PV<> to reference a VPI object (signal) for the base.
This patch adds code to allow &PV<> to access a VPI object
(signal) for the base of an indexed part select. This
mirrors the code added to &A<>.
2008-06-13 18:42:08 -07:00
Cary R 50a8c17cf8 Comparison arguments are in a self determined context.
This patch makes comparison arguments be evaluated in a self
determined context. It also cleans up some other code items.
2008-06-13 18:05:46 -07:00
Stephen Williams 6f9643df79 Better array statistics.
Allocation counters for arrays and array words of various types.
2008-06-13 17:41:24 -07:00
Stephen Williams aeaf8e8433 Permalloc vvp_net_fun_t objects.
The vvp_net_fun_t objects, and derived objects, are small, and are
created in large quantities. Tightly pack them into permanently
allocated space in order to save on system allocation overhead, and
thus save overall on memory.
2008-06-13 17:08:11 -07:00
Stephen Williams 7afb280990 Allow that sum immediate values can be signed.
Actually, the immediate value handling is a little chaotic and should
be cleaned up. This patch opens the door for allowing signed immediate
values, and uses them in a few places where they are explicitly handled.
We must go through the opcodes that can take immediate values and make
explicit whether they are signed/unsigned/etc, and what their size
limits are.
2008-06-13 13:32:06 -07:00
Cary R 99a46fd5af Fix incorrect typecast.
This patch fixes an incorrect typecast in vvp/main.cc.
2008-06-13 11:38:18 -07:00
Larry Doolittle eed4ff7e2d Spelling fixes
Mostly comments, but includes quite a few
user-visible error, debug, and help messages.
2008-06-13 08:51:28 -07:00
Stephen Williams 659714f45d Merge branch 'master' of ssh://[email protected]/home/u/icarus/steve/git/verilog 2008-06-13 08:41:40 -07:00
Larry Doolittle 8f70c5ca35 Add missing include to vvp/vvp_net.h
Fixes FTBFS under gcc-4.3
2008-06-13 08:40:26 -07:00
Nick Gasson 0ea64ad8ab Correct misleading comment 2008-06-13 14:47:06 +01:00
Nick Gasson 9fbb449e06 Optimise away empty (VHDL) processes 2008-06-13 14:17:24 +01:00
Nick Gasson be3c4cf268 Generate signal initial values from `initial' processes 2008-06-13 14:10:28 +01:00
Nick Gasson 0a8fd50c4a Find assignments that could be initializers 2008-06-13 13:59:48 +01:00
Nick Gasson 70db096b6d Clean up the edge detector code a bit 2008-06-13 12:52:20 +01:00
Nick Gasson 005df31a0d Use renamed signal in expressions, if there is one 2008-06-13 12:39:18 +01:00
Nick Gasson d6193c1622 Add _Reg internal signal if output is registered 2008-06-13 12:34:27 +01:00
Stephen Williams a74f2827b2 Part select of signals is always unsigned.
Part select of an entire signal returns just the NetESignal itself,
but since part selects are always unsigned, even if the selected
signal is signed, we need to cast the NetESignal to unsigned first.
2008-06-12 21:56:46 -07:00
Stephen Williams 392b162024 Allow canonical part select of net vectors to be larger then the vector
The part select of a vector is converted by the compiler during
elaboration to a 0-based canonical address. But since it is legal
to address bits below the LSB, the canonical address can be negative.
So make the part select base for selecting from signals work with
signed arithmetic and make the code generator generate negative
indices when needed.
2008-06-12 21:41:11 -07:00
Stephen Williams 4af4c8cca9 Permallocate scheduler cells in chunks
Scheduler cells are small objects that come and go in great quantities.
Even though they are allocated and deallocated a lot, they tend to a
steady state quantity, so put together a heap that is unique for each
cell type.

This heap actually saves memory overall because cells are allocated in
chunks, thus eliminating allocator overhead, and they are pulled/pushed
from/to a heap very quickly so that what overhead remains is slight and
bounded.
2008-06-12 19:55:53 -07:00
Stephen Williams 3c4346acb2 ASSIGN transfer data to scheduler efficiently/permalloc vvp_net_t objects.
The vvp_net_t objects are never deleted, so overload the new operator
to do a more space efficient permanent allocation.

The %assign/v instruction copied the vvp_vector4_t object needlessly
on its way to the scheduler. Eliminate that duplication.(cherry picked from commit d0f303463d)
2008-06-12 13:00:31 -07:00
Nick Gasson b8c1f9ab67 A system for linking ivl_signal_t to entities 2008-06-12 20:26:23 +01:00
Stephen Williams 2e9970a98c Have vvp_vector8_t avoid allocating tiny scalar arrays.(cherry picked from commit 35fe8fae00) 2008-06-12 12:10:58 -07:00
Stephen Williams 4914b734dc Obvious optimizations of vvp_vector8_t handling.
The vvp_vector8_t constructor and destructor involve memory allocation
so it is best to pass these objects by reference as much as possible.

Also have the islands take more care not to perform resolution if the
inputs aren't really different.

NOTE: This is a port of commit 2f4e5bf5b6
from the "performance" branch, without the resolver scheduling changes.
This was causing test suite variances with pr1820472.v. It looks like
there might be a race in that program anyhow, but for now leave out the
resolver scheduling changes so that the rest of this commit can go in.
2008-06-12 12:08:02 -07:00
Nick Gasson 0df3eabe26 Convert if (foo) ..' to if foo = '1' then ..' 2008-06-12 11:36:21 +01:00
Nick Gasson 8fe2211e2b Generate after' modifier instead of wait' statements 2008-06-12 11:24:43 +01:00
Nick Gasson 645ee2003f Translation for unary not 2008-06-12 10:56:28 +01:00
Nick Gasson d6f1162547 Generate correct VHDL signal values 2008-06-12 10:50:46 +01:00
Nick Gasson 46991aa65c Generate process bodies in the right place 2008-06-12 10:47:52 +01:00
Nick Gasson 7eb41304e6 Generate rising/falling edge detectors 2008-06-12 10:36:38 +01:00
Stephen Williams 24da00bd5a Add value change callback for vpiPartSelect.
The __vpiPV objects express themselves as vpiPartSelect objects.
Add support for value change callbacks by attaching the callback
to the signal that we part select from.
2008-06-11 21:28:21 -07:00
Cary R 34efc7db51 Add parameter time/realtime types and other fixes.
This patch adds the time and realtime types to parameters
and local parameters. It also makes the width (range) of
an integer parameter match the variable "integer_width"
(normally 32 bits). It also converts a real value to
an integer when a range is implicitly or explicitly
given. This all matches what the standard specifies.

Fixed an error in converting -1 to a unsized verinum.
2008-06-11 19:48:15 -07:00
Cary R acf010326c Remove the signed/unsigned comparison warning 2008-06-11 19:44:21 -07:00
Stephen Williams d7814ed767 Better handle some vector size matters for %load/v
The %load/v instruction was doing some spurious resizes of the vector
that comes from the signal. Eliminate those resizes that can be
removed, and optimize some that remain.
2008-06-11 14:38:35 -07:00
Nick Gasson 19e60b698f Translate if statements 2008-06-11 14:20:05 +01:00
Nick Gasson a7cfdc3a87 Add VHDL if statement to AST types 2008-06-11 14:11:37 +01:00
Nick Gasson b010b8e3ca Use `assert false' as initial translation of $finish 2008-06-11 13:37:21 +01:00
Nick Gasson 26a2c69c2e Change architecture name to `FromVerilog' 2008-06-11 11:31:43 +01:00
Stephen Williams 608bad26cf Allow &A<> argument syntax to take a reference to a VPI object.
This allows the array index to be evaluated when the word is accessed,
and that in turn allows access in the ROSYNC scheduler phase to work
properly.
2008-06-10 20:36:31 -07:00
Stephen Williams 70768176f9 Change bit select instruction to a part select.
There is no point in having a bit select instruction and running it in
a loop (always) when we can simply turn it into a part select instruction.
2008-06-10 17:29:47 -07:00
Stephen Williams 694a6ed4a1 Remove some unused opcodes.
Codes from a dfiferent era.
2008-06-10 16:33:34 -07:00
Cary R dc15fa965b Remove MinGW unused variable warning
This patch moves the definition of rtn into the non-MinGW
branch since that is the only place it is used.
2008-06-10 15:42:56 -07:00
Cary R d78739d163 Make &PV<> put_value work correctly.
This patch finishes the put_value routine for &PV<>. It should
now work as expected.
2008-06-10 15:07:52 -07:00
Larry Doolittle d90ce68f5d Spelling fixes
No code changes.
2008-06-10 15:02:18 -07:00
Larry Doolittle d2c52ff35b Spelling fixes
No code changes.
2008-06-10 15:00:54 -07:00
Larry Doolittle 813b4cf74c Add explicit parentheses to elaborate_expr_param_part_
Removes gcc-4.3 warning: suggest parentheses around && within ||
2008-06-10 14:57:50 -07:00
Larry Doolittle a437b38270 Fix vpip_make_vthr_A prototype with duplicate parameters
Causes FTBFS with gcc-4.3
2008-06-10 14:56:55 -07:00
Stephen Williams f9d060146c Merge branch 'master' of ssh://[email protected]/~steve-icarus/git/verilog 2008-06-10 14:18:30 -07:00
Stephen Williams 7f0c6b9c21 Fix access to deleted memory.
When parameters are replaced, the expression that is replaced is deleted
so make sure the pointer in the map is properly updated. Also, make sure
the defparam expression itself is not deleted because it is used to
print messages, such as design dumps.
2008-06-10 13:25:40 -07:00
Nick Gasson 5a7cfd8c02 Clean up vhdl_comp_inst 2008-06-10 14:00:15 +01:00
Nick Gasson babe694366 Generate port mappings 2008-06-10 13:58:41 +01:00
Nick Gasson 7560b29fb9 Find signals to map together 2008-06-10 12:21:48 +01:00
Nick Gasson f6753a9013 Add ports to component declarations 2008-06-10 11:24:16 +01:00
Cary R 647e53bcbb Make &A<> use the same thread access syntax as &PV<>.
This patch makes &A<> use the same thread access syntax as
&PV<> this is two unsigned numbers separated by a space
instead of a single number.
2008-06-09 21:26:36 -07:00
Cary R 8439fc6c19 Remove two memory leaks.
This patch removes two memory leaks. One in the driver and one
in the runtime.
2008-06-09 21:23:27 -07:00
Cary R 6f61cf2e4e A memory word is a number
This will be cleaned up more once I finish all the compiletf
routines, but for now this allows the test to pass.
2008-06-09 20:00:03 -07:00
Nick Gasson 191187ed1b Cosmetic change to avoid useless `null' statement after delay 2008-06-09 16:40:32 +01:00
Nick Gasson 1fb01d4d98 Emit port declarations 2008-06-09 16:37:05 +01:00
Nick Gasson 3106fe0ed6 Generate port declarations for entities.
But doesn't emit them yet!
2008-06-09 16:27:04 +01:00
Nick Gasson e29954e03f Generate concurrent assignments from logic gates 2008-06-09 15:05:32 +01:00
Nick Gasson 3b5d56e087 Allow n-ary expressions 2008-06-09 14:53:50 +01:00
Nick Gasson aa91186119 Add AST elements for unary/binary expressions to model logic gates 2008-06-09 14:39:58 +01:00
Nick Gasson d08f5af9c6 Add concurrent assignments 2008-06-09 14:21:55 +01:00
Nick Gasson b96e471fa2 Stub code for handling logic gates 2008-06-09 14:08:27 +01:00
Nick Gasson 7120ab7b13 Expression type might be null in some cases 2008-06-09 12:54:21 +01:00
Nick Gasson 2f5dcda3b6 Delay statements now translated correctly 2008-06-09 12:49:38 +01:00
Nick Gasson 120b5dc80e Add constant integers 2008-06-09 12:46:55 +01:00
Nick Gasson d762253f74 Wait statements 2008-06-09 12:40:59 +01:00
Nick Gasson 1d28b935e8 Split vhdl_element.cc into multiple files 2008-06-08 13:27:48 +01:00
Nick Gasson 4b4a1c6cac Tidy up type casting 2008-06-08 12:55:18 +01:00
Nick Gasson 110a1b2ac7 Replace type classes with enumeration 2008-06-08 12:48:56 +01:00
Nick Gasson 79558910d1 Catch case where NULL return wasn't detected 2008-06-07 16:44:01 +01:00
Nick Gasson fbf85398da Support converting bit strings to std_logic 2008-06-07 16:19:10 +01:00
Nick Gasson 1e4b96aa0a Simplify code a bit as rval type is never needed 2008-06-07 14:57:20 +01:00
Nick Gasson c064ae6bc3 Generate VHDL for non-blocking assignments 2008-06-07 14:54:00 +01:00
Nick Gasson 39228f3495 VHDL AST element for non-blocking assignment 2008-06-07 14:31:33 +01:00
Nick Gasson 12e2237131 Add Type'Image cast to $display parameters 2008-06-07 14:21:50 +01:00
Nick Gasson 066a9b7a61 Add AST element for function call expressions 2008-06-07 13:29:27 +01:00
Nick Gasson cdb180e1d4 Associate a type with each VHDL expression node 2008-06-07 13:23:21 +01:00
Nick Gasson a8ecce7421 Make sure all declarations have a type 2008-06-07 12:15:46 +01:00
Nick Gasson 8c3461f0ff Generate sensitivity lists properly and add signal declarations 2008-06-07 11:48:38 +01:00
Nick Gasson 305f448d05 Generate code for signal references 2008-06-07 11:24:09 +01:00
Nick Gasson 5f90a3e48c Translate sub-statement of @{..} 2008-06-06 18:22:03 +01:00
Nick Gasson 96cf190720 Generate signals and sensitivity list for @(..) statement 2008-06-06 17:56:52 +01:00
Nick Gasson 373832ba22 Specify correct sensitivity list 2008-06-06 17:36:15 +01:00
Nick Gasson 4f472e451e Stubs for statement types in mux2.v test 2008-06-06 16:55:45 +01:00
Nick Gasson d36bbec5b5 Generate VHDL for no-op statements 2008-06-05 13:16:35 +01:00
Nick Gasson e258058cf1 Fully qualify std.textio.Output to avoid name collisions 2008-06-04 21:58:51 +01:00
Nick Gasson c3ac1aac8c Remove debugging messages from output 2008-06-04 21:07:50 +01:00
Nick Gasson 234f73e7bf Don't generate any output if there were errors 2008-06-04 21:03:36 +01:00
Nick Gasson f49dd97d24 Add support for blocks and make hello1.v test pass 2008-06-04 20:57:15 +01:00
Nick Gasson 7bd1565cfb $display now (mostly) working 2008-06-04 20:42:44 +01:00
Nick Gasson 6e448da90d Emit Write() calls for parameters of $display 2008-06-04 15:19:44 +01:00
Nick Gasson 9f035108e1 Stub code for translating expressions 2008-06-04 14:59:04 +01:00
Nick Gasson 4bf2e1669d Store packages required with entity rather than globally
Add parent link to architecture and process so code generators can push things higher up
$display now prints blank lines
2008-06-04 13:52:56 +01:00
Nick Gasson dd30c1b39d Support procedure call generation for $display 2008-06-04 13:27:42 +01:00
Nick Gasson 94006cb44c Working on code generation for $display task 2008-06-03 19:46:10 +01:00
Nick Gasson 2e6ec91ce0 Scalar types 2008-06-03 19:20:45 +01:00
Nick Gasson fe80da362c Collect required packages as compilation progresses 2008-06-03 19:14:47 +01:00
Nick Gasson 82aca1b02e Stub code for handling $display 2008-06-03 18:44:17 +01:00
Nick Gasson 4211e651d0 Stub file for processing statements 2008-06-03 18:26:36 +01:00
Nick Gasson f9e1289463 Tidy up vhdl_element.cc 2008-06-03 17:43:54 +01:00
Nick Gasson a09b4e3b92 Initial process have wait at the end
(do it properly this time rather than a hack :-)
2008-06-03 17:39:24 +01:00
Nick Gasson ab6ae621cb Remove useless comments in output 2008-06-02 20:24:25 +01:00
Nick Gasson 17ae0a6a09 Fix a bug where the same instantiation appeared multiple times 2008-06-02 18:05:39 +01:00
Nick Gasson 041925c123 Component instantiation to replicate Verilog hierarchy 2008-06-02 17:45:58 +01:00
Nick Gasson 9292a087e8 Generate VHDL processes from Verilog processes 2008-06-02 16:17:01 +01:00
Nick Gasson fef0fd82ff Comments 2008-06-02 00:12:47 +01:00
Nick Gasson 5cbd587833 Clean up generated objects 2008-05-31 16:08:57 +01:00
Nick Gasson 7c9d154461 Forgot source files for entity generation 2008-05-31 15:31:48 +01:00
Nick Gasson 8189c4ee43 Generate VHDL entities and architectures for all module scopes 2008-05-31 15:28:25 +01:00
Nick Gasson 05de2f56b4 Dummy code for processes 2008-05-30 01:04:47 +01:00
Nick Gasson e38494a10c Pretty-print VHDL output 2008-05-29 16:24:16 +01:00
Nick Gasson e178baefbd Merge branch 'master' of git://github.com/steveicarus/iverilog into vhdl 2008-05-28 17:23:12 +01:00
Nick Gasson bfa2bfc8ae Makefile and autoconf changes to build VHDL code generator 2008-05-28 17:17:39 +01:00
465 changed files with 57716 additions and 33309 deletions
-27
View File
@@ -1,27 +0,0 @@
lexor_keyword.cc
parse.h
parse.cc
parse.cc.output
parse.output
syn-rules.cc
syn-rules.cc.output
syn-rules.output
lexor.cc
iverilog-vpi
iverilog-vpi.pdf
iverilog-vpi.ps
ivl
ivl.exp
dep
configure
Makefile
check
check.cc
check.vvp
config.status
config.log
config.cache
autom4te.cache
config.h
_pli_types.h
dosify
+83
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@@ -0,0 +1,83 @@
# Lines that start with '#' are comments.
#
# This file is for the development branch of Icarus Verilog.
#
# The following files will be ignored by git.
# Object files and libraries
*.[oa]
*~
# From autoconf
configure
config.log
config.status
Makefile
/_pli_types.h
config.h
/tgt-vvp/vvp_config.h
/tgt-vhdl/vhdl_config.h
/vpi/vpi_config.h
stamp-*-h
/version.h
/version_tag.h
# Directories
autom4te.cache
dep
# Compiler back end and library files
/tgt-vvp/*.conf
*.tgt
*.vpi
/cadpli/cadpli.vpl
# lex, yacc and gperf output
/driver/cflexor.c
/driver/cfparse.c
/driver/cfparse.h
/driver/cfparse.output
/ivlpp/lexor.c
/lexor.cc
/lexor_keyword.cc
/parse.cc
/parse.h
/parse.output
/syn-rules.cc
/syn-rules.output
/vpi/sdf_lexor.c
/vpi/sdf_parse.c
/vpi/sdf_parse.h
/vpi/sdf_parse.output
/vpi/sys_readmem_lex.c
/vvp/lexor.cc
/vvp/parse.cc
/vvp/parse.h
/vvp/parse.output
# Program created files
/vvp/tables.cc
/iverilog-vpi.man
/driver-vpi/res.rc
/driver/iverilog.man
/vvp/vvp.man
# The executables.
*.exe
/driver/iverilog
/iverilog-vpi
/ivl
/ivlpp/ivlpp
/vvp/vvp
/ivl.exp
/vvp/vvp.exp
# Check output
/check.vvp
+15 -12
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2000-2005 Stephen Williams (steve@icarus.com)
* Copyright (c) 2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,19 +16,22 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: memory.c,v 1.1 2005/03/03 04:34:42 steve Exp $"
#endif
# include "config.h"
# include "priv.h"
# include <assert.h>
void show_memory(ivl_memory_t mem)
# include "AStatement.h"
AContrib::AContrib(PExpr*lv, PExpr*rv)
: lval_(lv), rval_(rv)
{
}
AContrib::~AContrib()
{
delete lval_;
delete rval_;
}
AProcess::~AProcess()
{
fprintf(out, " mem [%u] %s [%u] <root=%d>\n",
ivl_memory_width(mem),
ivl_memory_basename(mem),
ivl_memory_size(mem),
ivl_memory_root(mem));
}
+85
View File
@@ -0,0 +1,85 @@
#ifndef __AStatement_H
#define __AStatement_H
/*
* Copyright (c) 2008 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
# include <map>
# include "ivl_target.h"
# include "StringHeap.h"
# include "LineInfo.h"
# include "Statement.h"
# include "PExpr.h"
class PExpr;
class NetAnalog;
class NetScope;
class Design;
/*
* A contribution statement is like an assignment: there is an l-value
* expression and an r-value expression. The l-value is a branch probe
* expression.
*/
class AContrib : public Statement {
public:
AContrib(PExpr*lval, PExpr*rval);
~AContrib();
virtual void dump(ostream&out, unsigned ind) const;
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
private:
PExpr*lval_;
PExpr*rval_;
};
/*
* An analog process is not a statement, but contains an analog
* statement. The process is where we attach process characteristics
* such as initial vs. always, attributes....
*/
class AProcess : public LineInfo {
public:
AProcess(ivl_process_type_t t, Statement*st)
: type_(t), statement_(st) { }
~AProcess();
bool elaborate(Design*des, NetScope*scope) const;
ivl_process_type_t type() const { return type_; }
Statement*statement() { return statement_; }
map<perm_string,PExpr*> attributes;
// Dump the analog process
void dump(ostream&out, unsigned ind) const;
private:
ivl_process_type_t type_;
Statement*statement_;
private: // not implemented
AProcess(const AProcess&);
AProcess& operator= (const AProcess&);
};
#endif
+2 -39
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
* Copyright (c) 2000-2010 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,14 +16,11 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: Attrib.cc,v 1.6 2004/02/20 18:53:33 steve Exp $"
#endif
# include "config.h"
# include "Attrib.h"
# include <assert.h>
# include <cassert>
Attrib::Attrib()
{
@@ -102,37 +99,3 @@ const verinum& Attrib::attr_value(unsigned idx) const
assert(idx < nlist_);
return list_[idx].val;
}
/*
* $Log: Attrib.cc,v $
* Revision 1.6 2004/02/20 18:53:33 steve
* Addtrbute keys are perm_strings.
*
* Revision 1.5 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.4 2002/05/26 01:39:02 steve
* Carry Verilog 2001 attributes with processes,
* all the way through to the ivl_target API.
*
* Divide signal reference counts between rval
* and lval references.
*
* Revision 1.3 2002/05/23 03:08:50 steve
* Add language support for Verilog-2001 attribute
* syntax. Hook this support into existing $attribute
* handling, and add number and void value types.
*
* Add to the ivl_target API new functions for access
* of complex attributes attached to gates.
*
* Revision 1.2 2001/07/25 03:10:48 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.1 2000/12/04 17:37:03 steve
* Add Attrib class for holding NetObj attributes.
*
*/
+2 -32
View File
@@ -1,7 +1,7 @@
#ifndef __Attrib_H
#define __Attrib_H
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
* Copyright (c) 2000-2009 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: Attrib.h,v 1.5 2004/02/20 18:53:33 steve Exp $"
#endif
# include "StringHeap.h"
# include "verinum.h"
@@ -33,7 +30,7 @@ class Attrib {
public:
Attrib();
~Attrib();
virtual ~Attrib();
const verinum&attribute(perm_string key) const;
void attribute(perm_string key, const verinum&value);
@@ -60,31 +57,4 @@ class Attrib {
Attrib& operator= (const Attrib&);
};
/*
* $Log: Attrib.h,v $
* Revision 1.5 2004/02/20 18:53:33 steve
* Addtrbute keys are perm_strings.
*
* Revision 1.4 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.3 2002/05/26 01:39:02 steve
* Carry Verilog 2001 attributes with processes,
* all the way through to the ivl_target API.
*
* Divide signal reference counts between rval
* and lval references.
*
* Revision 1.2 2002/05/23 03:08:50 steve
* Add language support for Verilog-2001 attribute
* syntax. Hook this support into existing $attribute
* handling, and add number and void value types.
*
* Add to the ivl_target API new functions for access
* of complex attributes attached to gates.
*
* Revision 1.1 2000/12/04 17:37:03 steve
* Add Attrib class for holding NetObj attributes.
*
*/
#endif
+63 -69
View File
@@ -4,23 +4,24 @@ HOW TO REPORT BUGS
Before I can fix an error, I need to understand what the problem
is. Try to explain what is wrong and why you think it is wrong. Please
try to include sample code that demonstrates the problem. Include a
description of what ivl does that is wrong, and what you expect should
happen. And include the command line flags passed to the compiler to make
the error happen. (This is often overlooked, and sometimes important.)
description of what Icarus Verilog does that is wrong, and what you
expect should happen. And include the command line flags passed to the
compiler to make the error happen. (This is often overlooked, and
sometimes important.)
* The Compiler Doesn't Compile
If the Icarus Verilog don't compile, I need to know about the
If Icarus Verilog doesn't compile, I need to know about the
compilation tools you are using. Specifically, I need to know:
- Operating system and processor type,
- Compiler w/ version,
- Library version, and
- Versions of any libraries being linked, and
- anything else you think relevant.
Be aware that I do not have at my disposal a porting lab. I have the
alpha on my desk, and the Linux/Intel box with a logic analyzer and
'scope hanging off it.
workstation on my desk, a Mac laptop, and the Linux/Intel box with a
logic analyzer and 'scope hanging off it.
* The Compiler Crashes
@@ -28,53 +29,54 @@ No compiler should crash, no matter what kind of garbage is fed to
it. If the compiler crashes, you definitely found a bug and I need to
know about it.
Ivl internally checks its state while it works, and if it detects
something wrong that it cannot recover from, it will abort
Icarus Verilog internally checks its state while it works, and if it
detects something wrong that it cannot recover from, it will abort
intentionally. The "assertion failure" message that the program
prints in the process of dying is very important. It tells me where in
the source the bad thing happened. Include that message in the bug
report.
If there are not assertion messages, I need to know that as well.
If there are no assertion messages, I need to know that as well.
I also need a complete test program that demonstrates the crash.
* It Doesn't Like My Perfectly Valid Program(tm)
I need to know what you think is right that ivl gets wrong. Does it
reject your "Perfectly Valid Program(tm)" or does it compile it but
give incorrect results? The latter is the most insidious as it doesn't
scream out to be fixed unless someone is watching closely. However, if
I get a sample program from you, and I can compile it, and I run it
and nuclear junk doesn't fall from the sky, I'm moving on to the next
problem.
I need to know what you think is right that Icarus Verilog gets
wrong. Does it reject your "Perfectly Valid Program(tm)" or does it
compile it but give incorrect results? The latter is the most
insidious as it doesn't scream out to be fixed unless someone is
watching closely. However, if I get a sample program from you, and I
can compile it, and I run it and nuclear junk doesn't fall from the
sky, I'm moving on to the next problem.
So, if your program doesn't compile, tell me so, tell me where the
error occurs, and include a complete Perfectly Valid Test Program(tm).
You tell me that it fails to compile for you, and I find that it
compiles for me, then hooray I fixed it. It can happen, you
know. What's on my disk is more recent then the latest snapshot.
know. What's on my disk is more recent than the latest snapshot.
If your program does compile, but generates incorrect output, I need
to know what it says and what you think it should say. From this I can
take your sample program and work on ivl until it gets the proper
results. For this to work, of course, I first need to know what is
wrong with the output. Spell it out, because I've been known to miss
the obvious. Compiler writers often get buried in the details of the
wrong problem.
take your sample program and work on Icarus Verilog until it gets the
proper results. For this to work, of course, I first need to know what
is wrong with the output. Spell it out, because I've been known to
miss the obvious. Compiler writers often get buried in the details of
the wrong problem.
* It Generates Incorrect Target Code (XNF, EDIF/LPM, etc.)
* It Generates Incorrect Target Code
As ivl adds target code generators, there will be cases where errors
in the output netlist format occur. This is a tough nut because I
might not have all the tools to test the target format you are
reporting problems with. However, if you clearly explain what is right
and wrong about the generated netlist, I will probably be able to fix
the problem. It may take a few iterations.
As Icarus Verilog adds target code generators, there will be cases
where errors in the output netlist format occur. This is a tough nut
because I might not have all the tools to test the target format you
are reporting problems with. However, if you clearly explain what is
right and wrong about the generated output, I will probably be able
to fix the problem. It may take a few iterations.
In this case, if possible include not only the sample Verilog program,
but the generated netlist file(s) and a clear indication of what went
wrong. If it is not clear to me, I will ask for clarification.
wrong or what is expected. If it is not clear to me, I will ask for
clarification.
* The Output is Correct, But Less Than Ideal
@@ -91,13 +93,13 @@ demonstrates the problem. If the error occurs after elaboration,
please include a top level module in the program that is suitable for
the target format. If I have to write the module myself, I might not
write it in a way that tickles the bug. So please, send all the
Verilog source (after preprocessing) that I need to invoke the error.
Verilog source that I need to invoke the error.
Also, include the command line you use to invoke the compiler. For
example:
ivl foo.vl -o foo.cc -tvvm
ivl foo.vl -s starthere
iverilog -o foo.out -tvvp foo.v
iverilog foo.vl -s starthere
If the error occurs with the null target (``-tnull'') then a top level
module may not be needed as long as the ``-s <name>'' switch is
@@ -108,15 +110,19 @@ invoke the error without any Verilog other than what is included?" And
while we are at it, please place a copyright notice in your test
program and include a GPL license statement if you can. Your test
program may find its way into the test suite, and the notices will
make it all nice and legal.
make it all nice and legal. Please look at the existing tests in the
test suite <http://sourceforge.net/ivtest> for examples of good test
programs.
RESEARCHING EXISTING/PAST BUGS, AND FILING REPORTS
The URL <http://www.icarus.com/cgi-bin/ivl-bugs> is the main bug
tracking system. Once you believe you have found a bug, you may browse
the bugs database for existing bugs that may be related to yours. You
might find that your bug has already been fixed in a later release or
snapshot. If that's the case, then you are set.
The URL <http://sourceforge.net/tracker/?group_id=149850> is the main
bug tracking system. Once you believe you have found a bug, you may
browse the bugs database for existing bugs that may be related to
yours. You might find that your bug has already been fixed in a later
release or snapshot. If that's the case, then you are set. Also,
consider if you are reporting a bug or really asking for a new
feature, and use the appropriate tracker.
The bug database supports basic keyword searches, and you can
optionally limit your search to active bugs, or fixed bugs. You may
@@ -125,8 +131,7 @@ broken. You may for example find a related bug that explains your
symptom.
The root page of the bug report database describes how to submit your
completed bug report. You may submit it via the web form, or via
e-mail.
completed bug report.
HOW TO SEND PATCHES
@@ -134,21 +139,26 @@ Bug reports with patches are very welcome, especially if they are
formatted such that I can inspect them, decide that they are obviously
correct, and apply them without worry.
I prefer context diffs as emitted by diff from GNU diffutils. Human
beings can read such things, and they are resilient to changing
originals. A good set of flags to diff are ``diff -cNB''. With such
diffs, I can look at the changes you are offering and probably tell at
a glance that they are plausible. Then I can use patch(1) to apply
them. Or I can apply them by hand.
I prefer patches generated by the git source code tracking system. If
you are editing the source, you really should be using the latest
version from git. Please see the developer documentation for more
detailed instructions -- <http://iverilog.wikia.com/wiki/>.
However, if you send patches, *please* tell me what this patch is
supposed to accomplish, and if appropriate include a test program that
demonstrates the efficacy of the patch. (If I have no idea what the
patch is for, I will ask for clarification before applying it.)
When you make a patch, submit it to the "Patches" tracker at
<http://sourceforge.net/tracker/?group_id=149850>. Patches added to
the "Patches" tracker enter the developer workflow, are checked,
applied to the appropriate git branch, and are pushed. Then the
tracker item is closed.
If you send patches, *please* tell me what this patch is supposed to
accomplish, which branch you intended to be patched, and if
appropriate include a test program that demonstrates the efficacy of
the patch. (If I have no idea what the patch is for, I will ask for
clarification before applying it.)
COPYRIGHT ISSUES
Icarus Verilog is Copyright (c) 1998-2003 Stephen Williams except
Icarus Verilog is Copyright (c) 1998-2008 Stephen Williams except
where otherwise noted. Minor patches are covered as derivative works
(or editorial comment or whatever the appropriate legal term is) and
folded into the rest of ivl. However, if a submission can reasonably
@@ -158,19 +168,3 @@ then falls under the "otherwise noted" category.
I must insist that any copyright material submitted for inclusion
include the GPL license notice as shown in the rest of the source.
$Id: BUGS.txt,v 1.5 2007/03/22 16:08:14 steve Exp $
$Log: BUGS.txt,v $
Revision 1.5 2007/03/22 16:08:14 steve
Spelling fixes from Larry
Revision 1.4 2003/02/19 04:36:31 steve
Notes on hte bug database.
Revision 1.3 2003/01/30 16:23:07 steve
Spelling fixes.
Revision 1.2 1999/08/06 04:05:28 steve
Handle scope of parameters.
+1 -38
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
* Copyright (c) 2001-2010 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: HName.cc,v 1.8 2007/06/02 03:42:12 steve Exp $"
#endif
# include "config.h"
# include "HName.h"
@@ -26,9 +23,6 @@
# include <cstring>
# include <cstdlib>
# include <climits>
#ifdef HAVE_MALLOC_H
# include <malloc.h>
#endif
hname_t::hname_t()
@@ -119,34 +113,3 @@ ostream& operator<< (ostream&out, const hname_t&that)
return out;
}
/*
* $Log: HName.cc,v $
* Revision 1.8 2007/06/02 03:42:12 steve
* Properly evaluate scope path expressions.
*
* Revision 1.7 2007/05/16 19:12:33 steve
* Fix hname_t use of space for 1 perm_string.
*
* Revision 1.6 2007/04/26 03:06:21 steve
* Rework hname_t to use perm_strings.
*
* Revision 1.5 2002/11/02 03:27:52 steve
* Allow named events to be referenced by
* hierarchical names.
*
* Revision 1.4 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.3 2002/01/05 04:36:06 steve
* include malloc.h only when available.
*
* Revision 1.2 2001/12/18 04:52:45 steve
* Include config.h for namespace declaration.
*
* Revision 1.1 2001/12/03 04:47:14 steve
* Parser and pform use hierarchical names as hname_t
* objects instead of encoded strings.
*
*/
+15 -31
View File
@@ -1,7 +1,7 @@
#ifndef __HName_H
#define __HName_H
/*
* Copyright (c) 2001-2007 Stephen Williams ([email protected])
* Copyright (c) 2001-2008 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,11 +18,9 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: HName.h,v 1.7 2007/06/02 03:42:12 steve Exp $"
#endif
# include <iostream>
# include <list>
# include "StringHeap.h"
#ifdef __GNUC__
#if __GNUC__ > 2
@@ -57,7 +55,7 @@ class hname_t {
private:
perm_string name_;
// If the number is anything other then INT_MIN, then this is
// If the number is anything other than INT_MIN, then this is
// the numeric part of the name. Otherwise, it is not part of
// the name at all.
int number_;
@@ -70,30 +68,16 @@ extern bool operator == (const hname_t&, const hname_t&);
extern bool operator != (const hname_t&, const hname_t&);
extern ostream& operator<< (ostream&, const hname_t&);
/*
* $Log: HName.h,v $
* Revision 1.7 2007/06/02 03:42:12 steve
* Properly evaluate scope path expressions.
*
* Revision 1.6 2007/05/16 19:12:33 steve
* Fix hname_t use of space for 1 perm_string.
*
* Revision 1.5 2007/04/26 03:06:21 steve
* Rework hname_t to use perm_strings.
*
* Revision 1.4 2002/11/02 03:27:51 steve
* Allow named events to be referenced by
* hierarchical names.
*
* Revision 1.3 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.2 2002/06/14 03:25:51 steve
* Compiler portability.
*
* Revision 1.1 2001/12/03 04:47:14 steve
* Parser and pform use hierarchical names as hname_t
* objects instead of encoded strings.
*
*/
inline ostream& operator<< (ostream&out, const list<hname_t>&ll)
{
list<hname_t>::const_iterator cur = ll.begin();
out << *cur;
cur ++;
while (cur != ll.end()) {
out << "." << *cur;
cur ++;
}
return out;
}
#endif
+2 -2
View File
@@ -1,7 +1,7 @@
#ifndef __LineInfo_H
#define __LineInfo_H
/*
* Copyright (c) 1999 Stephen Williams ([email protected])
* Copyright (c) 1999-2009 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -36,7 +36,7 @@ using namespace std;
class LineInfo {
public:
LineInfo();
~LineInfo();
virtual ~LineInfo();
// Get a fully formatted file/lineno
string get_fileline() const;
+179 -135
View File
@@ -18,30 +18,58 @@
#
SHELL = /bin/sh
# This version string is only used in the version message printed
# by the compiler. It reflects the assigned version number for the
# product as a whole. Most components also print the CVS Name: token
# in order to get a more automatic version stamp as well.
VERSION = 0.9.devel
# The interesting make targets are:
#
# make version
# Force the version_tag.h file to be rebuilt. Otherwise, it will only
# be built if it is missing.
#
# make all
# make install
#
# The "suffix" is used as an installation suffix. It modifies certain
# key install paths/files such that a build and install of Icarus Verilog
# with the same $(prefix) but a different $(suffix) will not interfere.
# The normal configuration leaves suffix empty
suffix = @install_suffix@
prefix = @prefix@
exec_prefix = @exec_prefix@
srcdir = @srcdir@
datarootdir = @datarootdir@
SUBDIRS = @subdirs@
SUBDIRS = ivlpp vvp vpi libveriuser cadpli tgt-null tgt-stub tgt-vvp \
tgt-vhdl driver
# Only run distclean for these directories.
NOTUSED = tgt-fpga tgt-pal tgt-verilog
VPATH = $(srcdir)
ifeq (@MINGW32@,yes)
SUBDIRS += driver-vpi
else
NOTUSED += driver-vpi
endif
# To get the version headers to build correctly we only want to look
# for C++ files in the source directory. All other files will require
# an explicit $(srcdir). The one exception to this is if we need to
# rebuild the lexor_keyword.cc file. If we do, then we want to use the
# local version instead of the one is $(srcdir).
vpath lexor_keyword.cc .
vpath %.cc $(srcdir)
bindir = @bindir@
libdir = @libdir@
includedir = @includedir@
# This is actually the directory where we install our own header files.
# It is a little different from the generic includedir.
includedir = @includedir@/iverilog$(suffix)
mandir = @mandir@
dllib=@DLLIB@
CC = @CC@
HOSTCC = @CC@
CXX = @CXX@
DLLTOOL = @DLLTOOL@
INSTALL = @INSTALL@
INSTALL_SCRIPT = @INSTALL_SCRIPT@
INSTALL_PROGRAM = @INSTALL_PROGRAM@
@@ -52,72 +80,103 @@ MAN = @MAN@
PS2PDF = @PS2PDF@
GIT = @GIT@
CPPFLAGS = @ident_support@ @DEFS@ -I. -I$(srcdir) @CPPFLAGS@
CXXFLAGS = -Wall @CXXFLAGS@
CPPFLAGS = @DEFS@ -I. -I$(srcdir) @CPPFLAGS@
CXXFLAGS = @WARNING_FLAGS@ @CXXFLAGS@
PICFLAGS = @PICFLAG@
LDFLAGS = @rdynamic@ @LDFLAGS@
all: dep version.h ivl@EXEEXT@
for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) $@); done
for dir in ivlpp ; \
do (cd $$dir ; $(MAKE) $@); done
cd driver ; $(MAKE) VERSION=$(VERSION) $@
all: dep config.h _pli_types.h version_tag.h ivl@EXEEXT@ version.exe iverilog-vpi.man
$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
# In the windows world, the installer will need a dosify program to
# dosify text files.
ifeq (@MINGW32@,yes)
all: dep dosify.exe
dosify.exe: dosify.c
$(CC) -o dosify.exe dosify.c
dosify.exe: $(srcdir)/dosify.c
$(HOSTCC) -o dosify.exe $(srcdir)/dosify.c
endif
# This rule rules the compiler in the trivial hello.vl program to make
# sure the basics were compiled properly.
check: all
for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) check); done
$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
test -r check.conf || cp $(srcdir)/check.conf .
driver/iverilog -B. -BPivlpp -tcheck -ocheck.vvp $(srcdir)/examples/hello.vl
ifeq (@WIN32@,yes)
ifeq (@install_suffix@,)
vvp/vvp -M- -M./vpi ./check.vvp | grep 'Hello, World'
else
# On Windows if we have a suffix we must run the vvp part of
# the test with a suffix since it was built/linked that way.
ln vvp/vvp.exe vvp/vvp$(suffix).exe
vvp/vvp$(suffix) -M- -M./vpi ./check.vvp | grep 'Hello, World'
rm vvp/vvp$(suffix).exe
endif
else
vvp/vvp -M- -M./vpi ./check.vvp | grep 'Hello, World'
endif
clean:
for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) $@); done
for dir in vpi ivlpp tgt-verilog tgt-pal driver driver-vpi; \
do (cd $$dir ; $(MAKE) $@); done
rm -f *.o parse.cc parse.cc.output parse.h lexor.cc
rm -f ivl.exp iverilog-vpi.pdf iverilog-vpi.ps parse.output
rm -f syn-rules.output dosify.exe ivl@EXEEXT@ check.vvp
rm -f lexor_keyword.cc libivl.a libvpi.a iverilog-vpi syn-rules.cc*
$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
rm -f *.o parse.cc parse.h lexor.cc
rm -f ivl.exp iverilog-vpi.man iverilog-vpi.pdf iverilog-vpi.ps
rm -f parse.output syn-rules.output dosify.exe ivl@EXEEXT@ check.vvp
rm -f lexor_keyword.cc libivl.a libvpi.a iverilog-vpi syn-rules.cc
rm -rf dep
rm -f version.exe
distclean: clean
for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) $@); done
for dir in vpi ivlpp tgt-verilog tgt-pal driver driver-vpi; \
do (cd $$dir ; $(MAKE) $@); done
rm -f Makefile config.status config.log config.cache config.h
rm -f _pli_types.h
$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
$(foreach dir,$(NOTUSED),$(MAKE) -C $(dir) $@ && ) true
rm -f Makefile config.status config.log config.cache
rm -f stamp-config-h config.h
rm -f stamp-_pli_types-h _pli_types.h
ifneq (@srcdir@,.)
rm -f version_tag.h check.conf
rmdir $(SUBDIRS) $(NOTUSED)
endif
rm -rf autom4te.cache
TT = t-dll.o t-dll-api.o t-dll-expr.o t-dll-proc.o
TT = t-dll.o t-dll-api.o t-dll-expr.o t-dll-proc.o t-dll-analog.o
FF = cprop.o nodangle.o synth.o synth2.o syn-rules.o
O = main.o async.o design_dump.o discipline.o dup_expr.o elaborate.o elab_expr.o \
O = main.o async.o design_dump.o discipline.o dup_expr.o \
elaborate.o elab_expr.o elaborate_analog.o \
elab_lval.o elab_net.o elab_pexpr.o elab_scope.o \
elab_sig.o emit.o eval.o eval_attrib.o \
elab_sig.o elab_sig_analog.o emit.o eval.o eval_attrib.o \
eval_tree.o expr_synth.o functor.o lexor.o lexor_keyword.o link_const.o \
load_module.o netlist.o netmisc.o net_assign.o \
net_design.o net_event.o net_expr.o net_force.o net_func.o \
load_module.o netlist.o netmisc.o net_analog.o net_assign.o \
net_design.o net_event.o net_expr.o net_func.o \
net_link.o net_modulo.o net_nex_input.o net_nex_output.o \
net_proc.o net_scope.o net_tran.o net_udp.o pad_to_width.o \
parse.o parse_misc.o pform.o pform_disciplines.o pform_dump.o pform_types.o \
parse.o parse_misc.o pform.o pform_analog.o pform_disciplines.o \
pform_dump.o pform_types.o \
set_width.o symbol_search.o sync.o sys_funcs.o \
verinum.o verireal.o target.o targets.o \
verinum.o verireal.o target.o \
Attrib.o HName.o LineInfo.o Module.o PDelays.o PEvent.o \
PExpr.o PGate.o PGenerate.o PScope.o PSpec.o \
PTask.o PUdp.o PFunction.o PWire.o Statement.o StringHeap.o \
PTask.o PUdp.o PFunction.o PWire.o Statement.o AStatement.o StringHeap.o \
$(FF) $(TT)
Makefile: Makefile.in config.h.in config.status
./config.status
Makefile: $(srcdir)/Makefile.in config.status
./config.status --file=$@
stamp-config-h: $(srcdir)/config.h.in config.status
@rm -f $@
./config.status config.h
config.h: stamp-config-h
stamp-_pli_types-h: $(srcdir)/_pli_types.h.in config.status
@rm -f $@
./config.status _pli_types.h
_pli_types.h: stamp-_pli_types-h
$(srcdir)/configure: $(srcdir)/configure.in $(srcdir)/aclocal.m4
cd $(srcdir) && autoconf
config.status: $(srcdir)/configure
./config.status --recheck
./config.status
ifeq (@WIN32@,yes)
# Under Windows (mingw) I need to make the ivl.exe in two steps.
@@ -126,7 +185,7 @@ ifeq (@WIN32@,yes)
# that really exports the things that the import library imports.
ivl@EXEEXT@: $O $(srcdir)/ivl.def
$(CXX) -o ivl@EXEEXT@ $O $(dllib) @EXTRALIBS@
dlltool --dllname ivl@EXEEXT@ --def $(srcdir)/ivl.def \
$(DLLTOOL) --dllname ivl@EXEEXT@ --def $(srcdir)/ivl.def \
--output-lib libivl.a --output-exp ivl.exp
$(CXX) $(LDFLAGS) -o ivl@EXEEXT@ ivl.exp $O $(dllib) @EXTRALIBS@
else
@@ -134,184 +193,169 @@ ivl@EXEEXT@: $O
$(CXX) $(LDFLAGS) -o ivl@EXEEXT@ $O $(dllib)
endif
ifeq (@MINGW32@,yes)
SUBDIRS += driver-vpi
else
ifeq (@MINGW32@,no)
all: dep iverilog-vpi
iverilog-vpi: iverilog-vpi.sh
iverilog-vpi: $(srcdir)/iverilog-vpi.sh Makefile
sed -e 's;@SHARED@;@shared@;' -e 's;@PIC@;@PICFLAG@;' \
-e 's;@SUFFIX@;$(suffix);' \
-e 's;@IVCC@;$(CC);' \
-e 's;@IVCXX@;$(CXX);' \
-e 's;@IVCFLAGS@;$(CXXFLAGS);' \
-e 's;@INCLUDEDIR@;@includedir@;' \
-e 's;@INCLUDEDIR@;$(includedir);' \
-e 's;@LIBDIR@;@libdir@;' $< > $@
chmod +x $@
endif
version.exe: $(srcdir)/version.c $(srcdir)/version_base.h version_tag.h
$(HOSTCC) @WARNING_FLAGS@ -o version.exe -I. -I$(srcdir) $(srcdir)/version.c
dep:
mkdir dep
%.o: %.cc
$(CXX) $(CPPFLAGS) $(CXXFLAGS) -MD -c $< -o $*.o
%.o: %.cc config.h
$(CXX) $(CPPFLAGS) $(CXXFLAGS) @DEPENDENCY_FLAG@ -c $< -o $*.o
mv $*.d dep/$*.d
# Here are some explicit dependencies needed to get things going.
main.o: main.cc version_tag.h
lexor.o: lexor.cc parse.h
parse.o: parse.cc
parse.cc parse.h: $(srcdir)/parse.y
$(YACC) --verbose -t -p VL -d -o parse.cc $(srcdir)/parse.y
# Build this in two steps to avoid parallel build issues (see pr3462585)
parse.cc: $(srcdir)/parse.y
$(YACC) --verbose -t -p VL -d -o $@ $<
parse.h: parse.cc
mv parse.cc.h parse.h 2>/dev/null || mv parse.hh parse.h
syn-rules.cc: $(srcdir)/syn-rules.y
$(YACC) --verbose -p syn_ -o syn-rules.cc $(srcdir)/syn-rules.y
$(YACC) --verbose -t -p syn_ -o $@ $<
lexor.cc: $(srcdir)/lexor.lex
$(LEX) -PVL -s -olexor.cc $(srcdir)/lexor.lex
$(LEX) -PVL -s -t $< > $@
lexor_keyword.o: lexor_keyword.cc parse.h
lexor_keyword.cc: lexor_keyword.gperf
gperf -o -i 7 -C -k 1-4,$$ -L ANSI-C -H keyword_hash -N check_identifier -t $(srcdir)/lexor_keyword.gperf > lexor_keyword.cc || (rm -f lexor_keyword.cc ; false)
lexor_keyword.cc: $(srcdir)/lexor_keyword.gperf
gperf -o -i 7 -C -k 1-4,$$ -H keyword_hash -N check_identifier -t $(srcdir)/lexor_keyword.gperf > lexor_keyword.cc || (rm -f lexor_keyword.cc ; false)
iverilog-vpi.ps: $(srcdir)/iverilog-vpi.man
$(MAN) -t $(srcdir)/iverilog-vpi.man > iverilog-vpi.ps
iverilog-vpi.man: $(srcdir)/iverilog-vpi.man.in version.exe
./version.exe `head -1 $(srcdir)/iverilog-vpi.man.in`'\n' > $@
tail -n +2 $(srcdir)/iverilog-vpi.man.in >> $@
iverilog-vpi.ps: iverilog-vpi.man
$(MAN) -t ./iverilog-vpi.man > iverilog-vpi.ps
iverilog-vpi.pdf: iverilog-vpi.ps
$(PS2PDF) iverilog-vpi.ps iverilog-vpi.pdf
# For VERSION_TAG in driver/main.c, first try git-describe, then look for a
# version.h file in the source tree (included in snapshots and releases), and
# finally use nothing.
.PHONY: version.h
# version_tag.h file in the source tree (included in snapshots and releases),
# and finally use nothing.
# "true" and "false" in the next few lines are Unix shell command names
ifeq ($(GIT),none)
GIT_PRESENT = false
else
GIT_PRESENT = true
endif
version.h:
version_tag.h version:
@if $(GIT_PRESENT) && test -d $(srcdir)/.git; then \
echo "Using git-describe for VERSION_TAG"; \
tmp=`$(GIT) --git-dir $(srcdir)/.git describe \
| sed -e 's;\(.*\);#define VERSION_TAG "\1";'`; \
echo "$$tmp" | diff - $@ > /dev/null 2>&1 || echo "$$tmp" > $@ || exit 1; \
elif test -r $(srcdir)/$@; then \
echo "Using $(srcdir)/$@ for VERSION_TAG"; \
diff $(srcdir)/$@ $@ > /dev/null 2>&1 || cp $(srcdir)/$@ $@; \
tag=`$(GIT) --git-dir $(srcdir)/.git describe --always --dirty`; \
tmp=`printf "#ifndef VERSION_TAG\n#define VERSION_TAG \"$$tag\"\n#endif\n"`; \
echo "$$tmp" | diff - version_tag.h > /dev/null 2>&1 || echo "$$tmp" > version_tag.h || exit 1; \
elif test -r $(srcdir)/version_tag.h; then \
echo "Using $(srcdir)/version_tag.h for VERSION_TAG"; \
diff $(srcdir)/version_tag.h version_tag.h > /dev/null 2>&1 || cp $(srcdir)/version_tag.h version_tag.h; \
else \
echo "Using empty VERSION_TAG"; \
echo '#define VERSION_TAG ""' > $@; \
tmp=`printf "#ifndef VERSION_TAG\n#define VERSION_TAG \"\"\n#endif\n"`; \
echo "$$tmp" | diff - version_tag.h > /dev/null 2>&1 || echo "$$tmp" > version_tag.h || exit 1; \
fi
ifeq (@MINGW32@,yes)
ifeq ($(MAN),none)
INSTALL_DOC = $(mandir)/man1/iverilog-vpi.1
INSTALL_DOC = $(mandir)/man1/iverilog-vpi$(suffix).1
else
ifeq ($(PS2PDF),none)
INSTALL_DOC = $(mandir)/man1/iverilog-vpi.1
INSTALL_DOC = $(mandir)/man1/iverilog-vpi$(suffix).1
else
INSTALL_DOC = $(prefix)/iverilog-vpi.pdf $(mandir)/man1/iverilog-vpi.1
INSTALL_DOC = $(prefix)/iverilog-vpi$(suffix).pdf $(mandir)/man1/iverilog-vpi$(suffix).1
all: dep iverilog-vpi.pdf
endif
endif
INSTALL_DOCDIR = $(mandir)/man1
else
INSTALL_DOC = $(mandir)/man1/iverilog-vpi.1
INSTALL_DOC = $(mandir)/man1/iverilog-vpi$(suffix).1
INSTALL_DOCDIR = $(mandir)/man1
endif
ifeq (@MINGW32@,yes)
WIN32_INSTALL = $(prefix)/hello.vl $(prefix)/sqrt.vl $(prefix)/sqrt-virtex.v $(prefix)/QUICK_START.txt
WIN32_INSTALL =
else
WIN32_INSTALL = $(bindir)/iverilog-vpi
WIN32_INSTALL = $(bindir)/iverilog-vpi$(suffix)
endif
XNF_INSTALL = $(libdir)/ivl/xnf.conf $(libdir)/ivl/xnf-s.conf
install: all installdirs $(libdir)/ivl$(suffix)/ivl@EXEEXT@ $(libdir)/ivl$(suffix)/include/constants.vams $(libdir)/ivl$(suffix)/include/disciplines.vams $(includedir)/ivl_target.h $(includedir)/_pli_types.h $(includedir)/vpi_user.h $(includedir)/acc_user.h $(includedir)/veriuser.h $(WIN32_INSTALL) $(INSTALL_DOC)
$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
install: all installdirs $(libdir)/ivl/ivl@EXEEXT@ $(libdir)/ivl/include/constants.vams $(libdir)/ivl/include/disciplines.vams $(includedir)/ivl_target.h $(includedir)/_pli_types.h $(includedir)/vpi_user.h $(includedir)/acc_user.h $(includedir)/veriuser.h $(WIN32_INSTALL) $(INSTALL_DOC)
for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) $@); done
for dir in vpi ivlpp driver; \
do (cd $$dir ; $(MAKE) $@); done
$(bindir)/iverilog-vpi$(suffix): ./iverilog-vpi
$(INSTALL_SCRIPT) ./iverilog-vpi "$(DESTDIR)$(bindir)/iverilog-vpi$(suffix)"
$(bindir)/iverilog-vpi: ./iverilog-vpi
$(INSTALL_SCRIPT) ./iverilog-vpi $(DESTDIR)$(bindir)/iverilog-vpi
$(libdir)/ivl$(suffix)/ivl@EXEEXT@: ./ivl@EXEEXT@
$(INSTALL_PROGRAM) ./ivl@EXEEXT@ "$(DESTDIR)$(libdir)/ivl$(suffix)/ivl@EXEEXT@"
$(libdir)/ivl/ivl@EXEEXT@: ./ivl@EXEEXT@
$(INSTALL_PROGRAM) ./ivl@EXEEXT@ $(DESTDIR)$(libdir)/ivl/ivl@EXEEXT@
$(libdir)/ivl$(suffix)/include/constants.vams: $(srcdir)/constants.vams
$(INSTALL_DATA) $(srcdir)/constants.vams "$(DESTDIR)$(libdir)/ivl$(suffix)/include/constants.vams"
$(libdir)/ivl/include/constants.vams: $(srcdir)/constants.vams
$(INSTALL_DATA) $(srcdir)/constants.vams $@
$(libdir)/ivl/include/disciplines.vams: $(srcdir)/disciplines.vams
$(INSTALL_DATA) $(srcdir)/disciplines.vams $@
$(libdir)/ivl/xnf-s.conf: $(srcdir)/xnf-s.conf
$(INSTALL_DATA) $(srcdir)/xnf-s.conf $(DESTDIR)$(libdir)/ivl/xnf-s.conf
$(libdir)/ivl/xnf.conf: $(srcdir)/xnf.conf
$(INSTALL_DATA) $(srcdir)/xnf.conf $(DESTDIR)$(libdir)/ivl/xnf.conf
$(libdir)/ivl$(suffix)/include/disciplines.vams: $(srcdir)/disciplines.vams
$(INSTALL_DATA) $(srcdir)/disciplines.vams "$(DESTDIR)$(libdir)/ivl$(suffix)/include/disciplines.vams"
$(includedir)/ivl_target.h: $(srcdir)/ivl_target.h
$(INSTALL_DATA) $(srcdir)/ivl_target.h $(DESTDIR)$(includedir)/ivl_target.h
$(INSTALL_DATA) $(srcdir)/ivl_target.h "$(DESTDIR)$(includedir)/ivl_target.h"
$(includedir)/_pli_types.h: _pli_types.h
$(INSTALL_DATA) $< $(DESTDIR)$(includedir)/_pli_types.h
$(INSTALL_DATA) $< "$(DESTDIR)$(includedir)/_pli_types.h"
$(includedir)/vpi_user.h: $(srcdir)/vpi_user.h
$(INSTALL_DATA) $(srcdir)/vpi_user.h $(DESTDIR)$(includedir)/vpi_user.h
$(INSTALL_DATA) $(srcdir)/vpi_user.h "$(DESTDIR)$(includedir)/vpi_user.h"
$(includedir)/acc_user.h: $(srcdir)/acc_user.h
$(INSTALL_DATA) $(srcdir)/acc_user.h $(DESTDIR)$(includedir)/acc_user.h
$(INSTALL_DATA) $(srcdir)/acc_user.h "$(DESTDIR)$(includedir)/acc_user.h"
$(includedir)/veriuser.h: $(srcdir)/veriuser.h
$(INSTALL_DATA) $(srcdir)/veriuser.h $(DESTDIR)$(includedir)/veriuser.h
$(INSTALL_DATA) $(srcdir)/veriuser.h "$(DESTDIR)$(includedir)/veriuser.h"
$(mandir)/man1/iverilog-vpi.1: $(srcdir)/iverilog-vpi.man
$(INSTALL_DATA) $(srcdir)/iverilog-vpi.man $(DESTDIR)$(mandir)/man1/iverilog-vpi.1
$(mandir)/man1/iverilog-vpi$(suffix).1: iverilog-vpi.man
$(INSTALL_DATA) iverilog-vpi.man "$(DESTDIR)$(mandir)/man1/iverilog-vpi$(suffix).1"
$(prefix)/iverilog-vpi.pdf: iverilog-vpi.pdf
$(INSTALL_DATA) iverilog-vpi.pdf $(DESTDIR)$(prefix)/iverilog-vpi.pdf
$(prefix)/iverilog-vpi$(suffix).pdf: iverilog-vpi.pdf
$(INSTALL_DATA) iverilog-vpi.pdf "$(DESTDIR)$(prefix)/iverilog-vpi$(suffix).pdf"
# In windows installations, put a few examples and the quick_start
# into the destination directory.
ifeq (@MINGW32@,yes)
$(prefix)/hello.vl: $(srcdir)/examples/hello.vl
./dosify.exe $(srcdir)/examples/hello.vl tmp.vl
mv tmp.vl $(prefix)/hello.vl
$(prefix)/sqrt.vl: $(srcdir)/examples/sqrt.vl
./dosify.exe $(srcdir)/examples/sqrt.vl tmp.vl
mv tmp.vl $(prefix)/sqrt.vl
$(prefix)/sqrt-virtex.v: $(srcdir)/examples/sqrt-virtex.v
./dosify.exe $(srcdir)/examples/sqrt-virtex.v tmp.vl
mv tmp.vl $(prefix)/sqrt-virtex.v
$(prefix)/QUICK_START.txt: $(srcdir)/QUICK_START.txt
./dosify.exe $(srcdir)/QUICK_START.txt tmp.txt
mv tmp.txt $(prefix)/QUICK_START.txt
endif
installdirs: mkinstalldirs
$(srcdir)/mkinstalldirs $(DESTDIR)$(bindir) $(DESTDIR)$(includedir) $(DESTDIR)$(libdir)/ivl \
$(DESTDIR)$(libdir)/ivl/include $(DESTDIR)$(mandir) $(DESTDIR)$(mandir)/man1
installdirs: $(srcdir)/mkinstalldirs
$(srcdir)/mkinstalldirs "$(DESTDIR)$(bindir)" \
"$(DESTDIR)$(includedir)" \
"$(DESTDIR)$(libdir)/ivl$(suffix)" \
"$(DESTDIR)$(libdir)/ivl$(suffix)/include" \
"$(DESTDIR)$(mandir)" \
"$(DESTDIR)$(mandir)/man1"
uninstall:
for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) $@); done
for dir in vpi ivlpp driver; \
do (cd $$dir ; $(MAKE) $@); done
for f in xnf.conf xnf-s.conf ivl@EXEEXT@ include/constants.vams include/disciplines.vams; \
do rm -f $(DESTDIR)$(libdir)/ivl/$$f; done
-rmdir $(DESTDIR)$(libdir)/ivl/include
-rmdir $(DESTDIR)$(libdir)/ivl
for f in verilog iverilog-vpi gverilog@EXEEXT@; \
do rm -f $(DESTDIR)$(bindir)/$$f; done
$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
for f in ivl@EXEEXT@ include/constants.vams include/disciplines.vams; \
do rm -f "$(DESTDIR)$(libdir)/ivl$(suffix)/$$f"; done
-rmdir "$(DESTDIR)$(libdir)/ivl$(suffix)/include"
-rmdir "$(DESTDIR)$(libdir)/ivl$(suffix)"
for f in verilog$(suffix) iverilog-vpi$(suffix) gverilog$(suffix)@EXEEXT@; \
do rm -f "$(DESTDIR)$(bindir)/$$f"; done
for f in ivl_target.h vpi_user.h _pli_types.h acc_user.h veriuser.h; \
do rm -f $(DESTDIR)$(includedir)/$$f; done
rm -f $(DESTDIR)$(mandir)/man1/iverilog-vpi.1 $(DESTDIR)$(prefix)/iverilog-vpi.pdf
do rm -f "$(DESTDIR)$(includedir)/$$f"; done
-test X$(suffix) = X || rmdir "$(DESTDIR)$(includedir)"
rm -f "$(DESTDIR)$(mandir)/man1/iverilog-vpi$(suffix).1" "$(DESTDIR)$(prefix)/iverilog-vpi$(suffix).pdf"
-include $(patsubst %.o, dep/%.d, $O)
+12 -19
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1998-2008 Stephen Williams ([email protected])
* Copyright (c) 1998-2009 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -22,14 +22,17 @@
# include "Module.h"
# include "PGate.h"
# include "PWire.h"
# include <assert.h>
# include <cassert>
/* n is a permallocated string. */
Module::Module(perm_string n)
: PScope(n, 0)
: PScope(n)
{
library_flag = false;
is_cell = false;
uc_drive = UCD_NONE;
default_nettype = NetNet::NONE;
timescale_warn_done = false;
}
Module::~Module()
@@ -41,19 +44,9 @@ void Module::add_gate(PGate*gate)
gates_.push_back(gate);
}
void Module::add_task(perm_string name, PTask*task)
{
tasks_[name] = task;
}
void Module::add_function(perm_string name, PFunction *func)
{
funcs_[name] = func;
}
unsigned Module::port_count() const
{
return ports.count();
return ports.size();
}
/*
@@ -61,10 +54,10 @@ unsigned Module::port_count() const
* module. If the port is internally unconnected, return an empty
* array.
*/
const svector<PEIdent*>& Module::get_port(unsigned idx) const
const vector<PEIdent*>& Module::get_port(unsigned idx) const
{
assert(idx < ports.count());
static svector<PEIdent*> zero;
assert(idx < ports.size());
static const vector<PEIdent*> zero;
if (ports[idx])
return ports[idx]->expr;
@@ -75,7 +68,7 @@ const svector<PEIdent*>& Module::get_port(unsigned idx) const
unsigned Module::find_port(const char*name) const
{
assert(name != 0);
for (unsigned idx = 0 ; idx < ports.count() ; idx += 1) {
for (unsigned idx = 0 ; idx < ports.size() ; idx += 1) {
if (ports[idx] == 0) {
/* It is possible to have undeclared ports. These
are ports that are skipped in the declaration,
@@ -89,7 +82,7 @@ unsigned Module::find_port(const char*name) const
return idx;
}
return ports.count();
return ports.size();
}
+20 -45
View File
@@ -1,7 +1,7 @@
#ifndef __Module_H
#define __Module_H
/*
* Copyright (c) 1998-2008 Stephen Williams ([email protected])
* Copyright (c) 1998-2009 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -22,7 +22,8 @@
# include <list>
# include <map>
# include "svector.h"
# include <vector>
# include <utility>
# include "StringHeap.h"
# include "HName.h"
# include "named.h"
@@ -58,7 +59,7 @@ class Module : public PScope, public LineInfo {
public:
struct port_t {
perm_string name;
svector<PEIdent*> expr;
vector<PEIdent*> expr;
};
public:
@@ -73,42 +74,13 @@ class Module : public PScope, public LineInfo {
other effect. */
bool library_flag;
bool is_cell;
enum UCDriveType { UCD_NONE, UCD_PULL0, UCD_PULL1 };
UCDriveType uc_drive;
NetNet::Type default_nettype;
struct range_t {
// True if this is an exclude
bool exclude_flag;
// lower bound
// If low_open_flag is false and low_expr=0, then use -inf
bool low_open_flag;
PExpr*low_expr;
// upper bound
// If high_open_flag is false and high_expr=0, then use +inf
bool high_open_flag;
PExpr*high_expr;
// Next range description in list
struct range_t*next;
};
/* The module has parameters that are evaluated when the
module is elaborated. During parsing, I put the parameters
into this map. */
struct param_expr_t : public LineInfo {
param_expr_t() : type(IVL_VT_NO_TYPE), msb(0), lsb(0), signed_flag(false), expr(0), range(0) { }
// Type information
ivl_variable_type_t type;
PExpr*msb;
PExpr*lsb;
bool signed_flag;
// Value expression
PExpr*expr;
// If there are range constrants, list them here
range_t*range;
};
map<perm_string,param_expr_t>parameters;
map<perm_string,param_expr_t>localparams;
/* specparams are simpler then other params, in that they have
no type information. They are merely constant
expressions. */
@@ -118,7 +90,8 @@ class Module : public PScope, public LineInfo {
new parameters within the module, but may be used to set
values within this module (when instantiated) or in other
instantiated modules. */
map<pform_name_t,PExpr*>defparms;
typedef pair<pform_name_t,PExpr*> named_expr_t;
list<named_expr_t>defparms;
/* Parameters may be overridden at instantiation time;
the overrides do not contain explicit parameter names,
@@ -130,13 +103,19 @@ class Module : public PScope, public LineInfo {
/* This is an array of port descriptors, which is in turn a
named array of PEident pointers. */
svector<port_t*> ports;
vector<port_t*> ports;
map<perm_string,PExpr*> attributes;
/* These are the timescale for this module. The default is
set by the `timescale directive. */
int time_unit, time_precision;
bool time_from_timescale;
bool timescale_warn_done;
/* Task definitions within this module */
map<perm_string,PTask*> tasks;
map<perm_string,PFunction*> funcs;
/* The module has a list of genvars that may be used in
various generate schemes. */
@@ -152,11 +131,9 @@ class Module : public PScope, public LineInfo {
perm_string mod_name() const { return pscope_name(); }
void add_gate(PGate*gate);
void add_task(perm_string name, PTask*def);
void add_function(perm_string name, PFunction*def);
unsigned port_count() const;
const svector<PEIdent*>& get_port(unsigned idx) const;
const vector<PEIdent*>& get_port(unsigned idx) const;
unsigned find_port(const char*name) const;
PGate* get_gate(perm_string name);
@@ -167,14 +144,12 @@ class Module : public PScope, public LineInfo {
bool elaborate(Design*, NetScope*scope) const;
typedef map<perm_string,NetExpr*> replace_t;
bool elaborate_scope(Design*, NetScope*scope, const replace_t&rep) const;
bool elaborate_scope(Design*, NetScope*scope, const replace_t&rep);
bool elaborate_sig(Design*, NetScope*scope) const;
private:
list<PGate*> gates_;
map<perm_string,PTask*> tasks_;
map<perm_string,PFunction*> funcs_;
static void elaborate_parm_item_(perm_string name, const param_expr_t&cur,
Design*des, NetScope*scope);
+50 -16
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1999-2008 Stephen Williams ([email protected])
* Copyright (c) 1999-2009 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -26,6 +26,11 @@
# include "verinum.h"
# include "netmisc.h"
bool dly_used_no_timescale = false;
bool dly_used_timescale = false;
bool display_ts_dly_warning = true;
PDelays::PDelays()
{
delete_flag_ = true;
@@ -60,12 +65,28 @@ void PDelays::set_delays(const svector<PExpr*>*del, bool df)
delete_flag_ = df;
}
static NetExpr*calculate_val(Design*des, NetScope*scope, const PExpr*expr)
static NetExpr*calculate_val(Design*des, NetScope*scope, PExpr*expr)
{
ivl_variable_type_t tmp_type = IVL_VT_NO_TYPE;
bool tmp_flag = false;
expr->test_width(des, scope, 0, 0, tmp_type, tmp_flag);
NetExpr*dex = expr->elaborate_expr(des, scope, -1, false);
eval_expr(dex);
/* Print a warning if we find default and `timescale based
* delays in the design, since this is likely an error. */
if (scope->time_from_timescale()) dly_used_timescale = true;
else dly_used_no_timescale = true;
if (display_ts_dly_warning &&
dly_used_no_timescale && dly_used_timescale) {
cerr << "warning: Found both default and "
"`timescale based delays. Use" << endl;
cerr << " -Wtimescale to find the "
"module(s) with no `timescale." << endl;
display_ts_dly_warning = false;
}
/* If the delay expression is a real constant or vector
constant, then evaluate it, scale it to the local time
units, and return an adjusted value. */
@@ -74,7 +95,7 @@ static NetExpr*calculate_val(Design*des, NetScope*scope, const PExpr*expr)
verireal fn = tmp->value();
int shift = scope->time_unit() - des->get_precision();
long delay = fn.as_long(shift);
int64_t delay = fn.as_long64(shift);
if (delay < 0)
delay = 0;
@@ -88,8 +109,7 @@ static NetExpr*calculate_val(Design*des, NetScope*scope, const PExpr*expr)
if (NetEConst*tmp = dynamic_cast<NetEConst*>(dex)) {
verinum fn = tmp->value();
unsigned long delay =
des->scale_to_precision(fn.as_ulong(), scope);
uint64_t delay = des->scale_to_precision(fn.as_ulong64(), scope);
delete tmp;
NetEConst*tmp2 = new NetEConst(verinum(delay));
@@ -101,7 +121,7 @@ static NetExpr*calculate_val(Design*des, NetScope*scope, const PExpr*expr)
return dex;
}
static NetExpr* make_delay_nets(Design*des, NetExpr*expr)
static NetExpr* make_delay_nets(Design*des, NetScope*scope, NetExpr*expr)
{
if (dynamic_cast<NetESignal*> (expr))
return expr;
@@ -109,7 +129,7 @@ static NetExpr* make_delay_nets(Design*des, NetExpr*expr)
if (dynamic_cast<NetEConst*> (expr))
return expr;
NetNet*sig = expr->synthesize(des);
NetNet*sig = expr->synthesize(des, scope, expr);
if (sig == 0) {
cerr << expr->get_fileline() << ": error: Expression " << *expr
<< " is not suitable for delay expression." << endl;
@@ -120,6 +140,20 @@ static NetExpr* make_delay_nets(Design*des, NetExpr*expr)
return expr;
}
static NetExpr* calc_decay_time(NetExpr *rise, NetExpr *fall)
{
NetEConst *c_rise = dynamic_cast<NetEConst*>(rise);
NetEConst *c_fall = dynamic_cast<NetEConst*>(fall);
if (c_rise && c_fall) {
if (c_rise->value() < c_fall->value()) return rise;
else return fall;
}
cerr << fall->get_fileline() << ": sorry: can not calculate the "
<< "decay time from " << *rise << " and " << *fall << endl;
return 0;
}
void PDelays::eval_delays(Design*des, NetScope*scope,
NetExpr*&rise_time,
NetExpr*&fall_time,
@@ -132,23 +166,23 @@ void PDelays::eval_delays(Design*des, NetScope*scope,
if (delay_[0]) {
rise_time = calculate_val(des, scope, delay_[0]);
if (as_nets_flag)
rise_time = make_delay_nets(des, rise_time);
rise_time = make_delay_nets(des, scope, rise_time);
if (delay_[1]) {
fall_time = calculate_val(des, scope, delay_[1]);
if (as_nets_flag)
fall_time = make_delay_nets(des, fall_time);
fall_time = make_delay_nets(des, scope, fall_time);
if (delay_[2]) {
decay_time = calculate_val(des, scope, delay_[2]);
if (as_nets_flag)
decay_time = make_delay_nets(des, decay_time);
if (as_nets_flag)
decay_time = make_delay_nets(des, scope,
decay_time);
} else {
if (rise_time < fall_time)
decay_time = rise_time;
else
decay_time = fall_time;
// If this is zero then we need to do the min()
// at run time.
decay_time = calc_decay_time(rise_time, fall_time);
}
} else {
assert(delay_[2] == 0);
-33
View File
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PDelays.h,v 1.9 2006/01/03 05:22:14 steve Exp $"
#endif
# include "svector.h"
# include <string>
@@ -72,34 +69,4 @@ class PDelays {
ostream& operator << (ostream&o, const PDelays&);
/*
* $Log: PDelays.h,v $
* Revision 1.9 2006/01/03 05:22:14 steve
* Handle complex net node delays.
*
* Revision 1.8 2006/01/02 05:33:19 steve
* Node delays can be more general expressions in structural contexts.
*
* Revision 1.7 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.6 2002/06/14 03:25:51 steve
* Compiler portability.
*
* Revision 1.5 2001/12/29 20:19:31 steve
* Do not delete delay expressions of UDP instances.
*
* Revision 1.4 2001/11/22 06:20:59 steve
* Use NetScope instead of string for scope path.
*
* Revision 1.3 2001/01/16 02:44:17 steve
* Use the iosfwd header if available.
*
* Revision 1.2 2000/02/23 02:56:53 steve
* Macintosh compilers do not support ident.
*
* Revision 1.1 1999/09/04 19:11:46 steve
* Add support for delayed non-blocking assignments.
*
*/
#endif
-26
View File
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PEvent.cc,v 1.5 2004/02/19 06:57:10 steve Exp $"
#endif
# include "config.h"
@@ -38,26 +35,3 @@ perm_string PEvent::name() const
return name_;
}
/*
* $Log: PEvent.cc,v $
* Revision 1.5 2004/02/19 06:57:10 steve
* Memory and Event names use perm_string.
*
* Revision 1.4 2003/03/01 06:25:30 steve
* Add the lex_strings string handler, and put
* scope names and system task/function names
* into this table. Also, permallocate event
* names from the beginning.
*
* Revision 1.3 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.2 2001/07/25 03:10:48 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.1 2000/04/01 19:31:57 steve
* Named events as far as the pform.
*
*/
-37
View File
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PEvent.h,v 1.9 2004/02/19 06:57:10 steve Exp $"
#endif
# include "LineInfo.h"
# include "StringHeap.h"
@@ -54,38 +51,4 @@ class PEvent : public LineInfo {
PEvent& operator= (const PEvent&);
};
/*
* $Log: PEvent.h,v $
* Revision 1.9 2004/02/19 06:57:10 steve
* Memory and Event names use perm_string.
*
* Revision 1.8 2003/03/01 06:25:30 steve
* Add the lex_strings string handler, and put
* scope names and system task/function names
* into this table. Also, permallocate event
* names from the beginning.
*
* Revision 1.7 2003/01/30 16:23:07 steve
* Spelling fixes.
*
* Revision 1.6 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.5 2001/12/03 04:47:14 steve
* Parser and pform use hierarchical names as hname_t
* objects instead of encoded strings.
*
* Revision 1.4 2001/01/16 02:44:18 steve
* Use the iosfwd header if available.
*
* Revision 1.3 2000/04/09 17:44:30 steve
* Catch event declarations during scope elaborate.
*
* Revision 1.2 2000/04/04 03:20:15 steve
* Simulate named event trigger and waits.
*
* Revision 1.1 2000/04/01 19:31:57 steve
* Named events as far as the pform.
*
*/
#endif
+105 -66
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1998-2007 Stephen Williams <[email protected]>
* Copyright (c) 1998-2008,2011 Stephen Williams <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -21,28 +21,31 @@
# include <iostream>
# include "compiler.h"
# include "PExpr.h"
# include "Module.h"
# include "netmisc.h"
# include <typeinfo>
PExpr::PExpr()
{
expr_type_ = IVL_VT_NO_TYPE;
}
PExpr::~PExpr()
{
}
bool PExpr::has_aa_term(Design*, NetScope*) const
{
return false;
}
bool PExpr::is_the_same(const PExpr*that) const
{
return typeid(this) == typeid(that);
}
bool PExpr::is_constant(Module*) const
{
return false;
}
NetNet* PExpr::elaborate_lnet(Design*des, NetScope*) const
{
cerr << get_fileline() << ": error: expression not valid in assign l-value: "
@@ -58,6 +61,11 @@ NetNet* PExpr::elaborate_bi_net(Design*des, NetScope*) const
return 0;
}
bool PExpr::is_collapsible_net(Design*, NetScope*) const
{
return false;
}
PEBinary::PEBinary(char op, PExpr*l, PExpr*r)
: op_(op), left_(l), right_(r)
{
@@ -67,22 +75,53 @@ PEBinary::~PEBinary()
{
}
bool PEBinary::is_constant(Module*mod) const
bool PEBinary::has_aa_term(Design*des, NetScope*scope) const
{
return left_->is_constant(mod) && right_->is_constant(mod);
assert(left_ && right_);
return left_->has_aa_term(des, scope) || right_->has_aa_term(des, scope);
}
PEBComp::PEBComp(char op, PExpr*l, PExpr*r)
: PEBinary(op, l, r)
{
left_width_ = 0;
right_width_ = 0;
}
PEBComp::~PEBComp()
{
}
PEBShift::PEBShift(char op, PExpr*l, PExpr*r)
PEBLogic::PEBLogic(char op, PExpr*l, PExpr*r)
: PEBinary(op, l, r)
{
assert(op == 'a' || op == 'o');
}
PEBLogic::~PEBLogic()
{
}
PEBLeftWidth::PEBLeftWidth(char op, PExpr*l, PExpr*r)
: PEBinary(op, l, r)
{
}
PEBLeftWidth::~PEBLeftWidth()
{
}
PEBPower::PEBPower(char op, PExpr*l, PExpr*r)
: PEBLeftWidth(op, l, r)
{
}
PEBPower::~PEBPower()
{
}
PEBShift::PEBShift(char op, PExpr*l, PExpr*r)
: PEBLeftWidth(op, l, r)
{
}
@@ -90,7 +129,7 @@ PEBShift::~PEBShift()
{
}
PECallFunction::PECallFunction(const pform_name_t&n, const svector<PExpr *> &parms)
PECallFunction::PECallFunction(const pform_name_t&n, const vector<PExpr *> &parms)
: path_(n), parms_(parms)
{
}
@@ -103,7 +142,7 @@ static pform_name_t pn_from_ps(perm_string n)
return tmp;
}
PECallFunction::PECallFunction(perm_string n, const svector<PExpr*>&parms)
PECallFunction::PECallFunction(perm_string n, const vector<PExpr*>&parms)
: path_(pn_from_ps(n)), parms_(parms)
{
}
@@ -113,22 +152,33 @@ PECallFunction::PECallFunction(perm_string n)
{
}
// NOTE: Anachronism. Try to work all use of svector out.
PECallFunction::PECallFunction(const pform_name_t&n, const svector<PExpr *> &parms)
: path_(n), parms_(vector_from_svector(parms))
{
}
PECallFunction::PECallFunction(perm_string n, const svector<PExpr*>&parms)
: path_(pn_from_ps(n)), parms_(vector_from_svector(parms))
{
}
PECallFunction::~PECallFunction()
{
}
PEConcat::PEConcat(const svector<PExpr*>&p, PExpr*r)
: parms_(p), repeat_(r)
bool PECallFunction::has_aa_term(Design*des, NetScope*scope) const
{
bool flag = false;
for (unsigned idx = 0 ; idx < parms_.size() ; idx += 1) {
flag = parms_[idx]->has_aa_term(des, scope) || flag;
}
return flag;
}
bool PEConcat::is_constant(Module *mod) const
PEConcat::PEConcat(const svector<PExpr*>&p, PExpr*r)
: parms_(p), tested_widths_(p.count()), repeat_(r)
{
bool constant = repeat_? repeat_->is_constant(mod) : true;
for (unsigned i = 0; constant && i < parms_.count(); ++i) {
constant = constant && parms_[i]->is_constant(mod);
}
return constant;
}
PEConcat::~PEConcat()
@@ -136,6 +186,18 @@ PEConcat::~PEConcat()
delete repeat_;
}
bool PEConcat::has_aa_term(Design*des, NetScope*scope) const
{
bool flag = false;
for (unsigned idx = 0 ; idx < parms_.count() ; idx += 1) {
flag = parms_[idx]->has_aa_term(des, scope) || flag;
}
if (repeat_)
flag = repeat_->has_aa_term(des, scope) || flag;
return flag;
}
PEEvent::PEEvent(PEEvent::edge_t t, PExpr*e)
: type_(t), expr_(e)
{
@@ -150,6 +212,12 @@ PEEvent::edge_t PEEvent::type() const
return type_;
}
bool PEEvent::has_aa_term(Design*des, NetScope*scope) const
{
assert(expr_);
return expr_->has_aa_term(des, scope);
}
PExpr* PEEvent::expr() const
{
return expr_;
@@ -170,11 +238,6 @@ const verireal& PEFNumber::value() const
return *value_;
}
bool PEFNumber::is_constant(Module*) const
{
return true;
}
PEIdent::PEIdent(const pform_name_t&that)
: path_(that)
{
@@ -189,35 +252,20 @@ PEIdent::~PEIdent()
{
}
/*
* An identifier can be in a constant expression if (and only if) it is
* a parameter or genvar.
*
* NOTE: This test does not work if the name is hierarchical!
*/
bool PEIdent::is_constant(Module*mod) const
bool PEIdent::has_aa_term(Design*des, NetScope*scope) const
{
if (mod == 0) return false;
NetNet* net = 0;
const NetExpr*par = 0;
NetEvent* eve = 0;
/* */
perm_string tmp = path_.back().name;
const NetExpr*ex1, *ex2;
{ map<perm_string,Module::param_expr_t>::const_iterator cur;
cur = mod->parameters.find(tmp);
if (cur != mod->parameters.end()) return true;
}
scope = symbol_search(0, des, scope, path_, net, par, eve, ex1, ex2);
{ map<perm_string,Module::param_expr_t>::const_iterator cur;
cur = mod->localparams.find(tmp);
if (cur != mod->localparams.end()) return true;
}
{ map<perm_string,LineInfo*>::const_iterator cur;
cur = mod->genvars.find(tmp);
if (cur != mod->genvars.end()) return true;
}
return false;
if (scope)
return scope->is_auto();
else
return false;
}
PENumber::PENumber(verinum*vp)
@@ -245,11 +293,6 @@ bool PENumber::is_the_same(const PExpr*that) const
return *value_ == *obj->value_;
}
bool PENumber::is_constant(Module*) const
{
return true;
}
PEString::PEString(char*s)
: text_(s)
{
@@ -265,11 +308,6 @@ string PEString::value() const
return text_;
}
bool PEString::is_constant(Module*) const
{
return true;
}
PETernary::PETernary(PExpr*e, PExpr*t, PExpr*f)
: expr_(e), tru_(t), fal_(f)
{
@@ -279,11 +317,12 @@ PETernary::~PETernary()
{
}
bool PETernary::is_constant(Module*m) const
bool PETernary::has_aa_term(Design*des, NetScope*scope) const
{
return expr_->is_constant(m)
&& tru_->is_constant(m)
&& fal_->is_constant(m);
assert(expr_ && tru_ && fal_);
return expr_->has_aa_term(des, scope)
|| tru_->has_aa_term(des, scope)
|| fal_->has_aa_term(des, scope);
}
PEUnary::PEUnary(char op, PExpr*ex)
@@ -295,8 +334,8 @@ PEUnary::~PEUnary()
{
}
bool PEUnary::is_constant(Module*m) const
bool PEUnary::has_aa_term(Design*des, NetScope*scope) const
{
return expr_->is_constant(m);
assert(expr_);
return expr_->has_aa_term(des, scope);
}
+202 -242
View File
@@ -1,7 +1,7 @@
#ifndef __PExpr_H
#define __PExpr_H
/*
* Copyright (c) 1998-2008 Stephen Williams <[email protected]>
* Copyright (c) 1998-2011 Stephen Williams <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -21,6 +21,7 @@
# include <string>
# include <vector>
# include <valarray>
# include "netlist.h"
# include "verinum.h"
# include "LineInfo.h"
@@ -36,9 +37,6 @@ class NetScope;
* The PExpr class hierarchy supports the description of
* expressions. The parser can generate expression objects from the
* source, possibly reducing things that it knows how to reduce.
*
* The elaborate_net method is used by structural elaboration to build
* up a netlist interpretation of the expression.
*/
class PExpr : public LineInfo {
@@ -49,11 +47,15 @@ class PExpr : public LineInfo {
virtual void dump(ostream&) const;
// This method tests whether the expression contains any
// references to automatically allocated variables.
virtual bool has_aa_term(Design*des, NetScope*scope) const;
// This method tests the width that the expression wants to
// be. It is used by elaboration of assignments to figure out
// the width of the expression.
//
// The "min" is the width of the local context, so it the
// The "min" is the width of the local context, so is the
// minimum width that this function should return. Initially
// this is the same as the lval width.
//
@@ -66,13 +68,22 @@ class PExpr : public LineInfo {
// the subexpression should not make l-value related
// optimizations.
//
// The unsigned_flag is set to true if the expression is
// The expr_type is an output argument that gives the
// calculated type for the expression.
//
// The unsized_flag is set to true if the expression is
// unsized and therefore expandable. This happens if a
// sub-expression is an unsized literal. Some expressions make
// special use of that.
virtual unsigned test_width(Design*des, NetScope*scope,
unsigned min, unsigned lval,
bool&unsized_flag) const;
ivl_variable_type_t&expr_type,
bool&unsized_flag);
// After the test_width method is complete, these methods
// return valid results.
ivl_variable_type_t expr_type() const { return expr_type_; }
unsigned expr_width() const { return expr_width_; }
// During the elaborate_sig phase, we may need to scan
// expressions to find implicit net declarations.
@@ -98,17 +109,6 @@ class PExpr : public LineInfo {
// evaluation of parameters.
virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
// This method elaborate the expression as gates, for use in a
// continuous assign or other wholly structural context.
virtual NetNet* elaborate_net(Design*des, NetScope*scope,
unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0 =Link::STRONG,
Link::strength_t drive1 =Link::STRONG)
const;
// This method elaborates the expression as gates, but
// restricted for use as l-values of continuous assignments.
virtual NetNet* elaborate_lnet(Design*des, NetScope*scope) const;
@@ -133,16 +133,21 @@ class PExpr : public LineInfo {
// evaluated, return 0.
virtual verinum* eval_const(Design*des, NetScope*sc) const;
// This method returns true if the expression represents a
// structural net that can have multiple drivers. This is
// used to test whether an input port connection can be
// collapsed to a single wire.
virtual bool is_collapsible_net(Design*des, NetScope*scope) const;
// This method returns true if that expression is the same as
// this expression. This method is used for comparing
// expressions that must be structurally "identical".
virtual bool is_the_same(const PExpr*that) const;
// Return true if this expression is a valid constant
// expression. the Module pointer is needed to find parameter
// identifiers and any other module specific interpretations
// of expressions.
virtual bool is_constant(Module*) const;
protected:
// The derived class test_width methods should fill these in.
ivl_variable_type_t expr_type_;
unsigned expr_width_;
private: // not implemented
PExpr(const PExpr&);
@@ -160,29 +165,30 @@ class PEConcat : public PExpr {
virtual verinum* eval_const(Design*des, NetScope*sc) const;
virtual void dump(ostream&) const;
virtual bool has_aa_term(Design*des, NetScope*scope) const;
virtual unsigned test_width(Design*des, NetScope*scope,
unsigned min, unsigned lval,
ivl_variable_type_t&expr_type,
bool&unsized_flag);
virtual bool elaborate_sig(Design*des, NetScope*scope) const;
virtual NetNet* elaborate_lnet(Design*des, NetScope*scope) const;
virtual NetNet* elaborate_bi_net(Design*des, NetScope*scope) const;
virtual NetNet* elaborate_net(Design*des, NetScope*scope,
unsigned width,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
virtual NetExpr*elaborate_expr(Design*des, NetScope*,
int expr_width, bool sys_task_arg) const;
virtual NetEConcat*elaborate_pexpr(Design*des, NetScope*) const;
virtual NetAssign_* elaborate_lval(Design*des,
NetScope*scope,
bool is_force) const;
virtual bool is_constant(Module*) const;
virtual bool is_collapsible_net(Design*des, NetScope*scope) const;
private:
NetNet* elaborate_lnet_common_(Design*des, NetScope*scope,
bool bidirectional_flag) const;
private:
svector<PExpr*>parms_;
std::valarray<unsigned>tested_widths_;
PExpr*repeat_;
};
@@ -208,6 +214,8 @@ class PEEvent : public PExpr {
virtual void dump(ostream&) const;
virtual bool has_aa_term(Design*des, NetScope*scope) const;
private:
edge_t type_;
PExpr *expr_;
@@ -229,21 +237,14 @@ class PEFNumber : public PExpr {
any rounding that is needed to get the value. */
virtual verinum* eval_const(Design*des, NetScope*sc) const;
/* A PEFNumber is a constant, so this returns true. */
virtual bool is_constant(Module*) const;
virtual unsigned test_width(Design*des, NetScope*scope,
unsigned min, unsigned lval,
ivl_variable_type_t&expr_type,
bool&unsized_flag);
virtual NetExpr*elaborate_expr(Design*des, NetScope*,
int expr_width, bool sys_task_arg) const;
virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
virtual NetNet* elaborate_net(Design*des, NetScope*scope,
unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
virtual void dump(ostream&) const;
private:
@@ -262,9 +263,13 @@ class PEIdent : public PExpr {
void append_name(perm_string);
virtual void dump(ostream&) const;
virtual bool has_aa_term(Design*des, NetScope*scope) const;
virtual unsigned test_width(Design*des, NetScope*scope,
unsigned min, unsigned lval,
bool&unsized_flag) const;
ivl_variable_type_t&expr_type,
bool&unsized_flag);
virtual bool elaborate_sig(Design*des, NetScope*scope) const;
@@ -278,15 +283,6 @@ class PEIdent : public PExpr {
NetScope*scope,
bool is_force) const;
// Structural r-values are OK.
virtual NetNet* elaborate_net(Design*des, NetScope*scope,
unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
virtual NetExpr*elaborate_expr(Design*des, NetScope*,
int expr_width, bool sys_task_arg) const;
virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
@@ -295,37 +291,51 @@ class PEIdent : public PExpr {
// only applies to Ident expressions.
NetNet* elaborate_port(Design*des, NetScope*sc) const;
virtual bool is_constant(Module*) const;
verinum* eval_const(Design*des, NetScope*sc) const;
virtual bool is_collapsible_net(Design*des, NetScope*scope) const;
const pform_name_t& path() const { return path_; }
private:
pform_name_t path_;
private:
// Common functions to calculate parts of part/bit selects.
bool calculate_parts_(Design*, NetScope*, long&msb, long&lsb) const;
// Common functions to calculate parts of part/bit
// selects. These methods return true if the expressions
// elaborate/calculate, or false if there is some sort of
// source error.
// The calculate_parts_ method calculates the range
// expressions of a part select for the current object. The
// part select expressions are elaborated and evaluated, and
// the values written to the msb/lsb arguments. If there are
// invalid bits (xz) in either expression, then the defined
// flag is set to *false*.
bool calculate_parts_(Design*, NetScope*, long&msb, long&lsb, bool&defined) const;
NetExpr* calculate_up_do_base_(Design*, NetScope*) const;
bool calculate_param_range_(Design*, NetScope*,
const NetExpr*msb_ex, long&msb,
const NetExpr*lsb_ex, long&lsb) const;
const NetExpr*lsb_ex, long&lsb,
long length) const;
bool calculate_up_do_width_(Design*, NetScope*, unsigned long&wid) const;
private:
NetAssign_*elaborate_lval_net_word_(Design*, NetScope*, NetNet*) const;
bool elaborate_lval_net_bit_(Design*, NetScope*, NetAssign_*) const;
bool elaborate_lval_net_part_(Design*, NetScope*, NetAssign_*) const;
bool elaborate_lval_net_idx_(Design*, NetScope*, NetAssign_*,
index_component_t::ctype_t) const;
private:
NetExpr*elaborate_expr_param(Design*des,
NetScope*scope,
const NetExpr*par,
NetScope*found,
const NetExpr*par_msb,
const NetExpr*par_lsb) const;
NetExpr*elaborate_expr_param_(Design*des,
NetScope*scope,
const NetExpr*par,
NetScope*found,
const NetExpr*par_msb,
const NetExpr*par_lsb,
int expr_wid) const;
NetExpr*elaborate_expr_param_part_(Design*des,
NetScope*scope,
const NetExpr*par,
@@ -338,6 +348,12 @@ class PEIdent : public PExpr {
NetScope*found,
const NetExpr*par_msb,
const NetExpr*par_lsb) const;
NetExpr*elaborate_expr_param_idx_do_(Design*des,
NetScope*scope,
const NetExpr*par,
NetScope*found,
const NetExpr*par_msb,
const NetExpr*par_lsb) const;
NetExpr*elaborate_expr_net(Design*des,
NetScope*scope,
NetNet*net,
@@ -365,38 +381,6 @@ class PEIdent : public PExpr {
NetESignal*net,
NetScope*found) const;
public:
NetNet* elaborate_net_array_(Design*des, NetScope*scope,
NetNet*sig, unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
NetNet* elaborate_net_net_(Design*des, NetScope*scope,
NetNet*sig, unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
NetNet* elaborate_net_net_idx_up_(Design*des, NetScope*scope,
NetNet*sig, unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
NetNet* elaborate_net_bitmux_(Design*des, NetScope*scope,
NetNet*sig,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
private:
NetNet* elaborate_lnet_common_(Design*des, NetScope*scope,
bool bidirectional_flag) const;
@@ -405,8 +389,6 @@ class PEIdent : public PExpr {
bool eval_part_select_(Design*des, NetScope*scope, NetNet*sig,
long&midx, long&lidx) const;
NetNet*process_select_(Design*des, NetScope*scope, NetNet*sig) const;
};
class PENumber : public PExpr {
@@ -420,15 +402,9 @@ class PENumber : public PExpr {
virtual void dump(ostream&) const;
virtual unsigned test_width(Design*des, NetScope*scope,
unsigned min, unsigned lval,
bool&unsized_flag) const;
ivl_variable_type_t&expr_type,
bool&unsized_flag);
virtual NetNet* elaborate_net(Design*des, NetScope*scope,
unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
virtual NetEConst*elaborate_expr(Design*des, NetScope*,
int expr_width, bool) const;
virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
@@ -439,7 +415,6 @@ class PENumber : public PExpr {
virtual verinum* eval_const(Design*des, NetScope*sc) const;
virtual bool is_the_same(const PExpr*that) const;
virtual bool is_constant(Module*) const;
private:
verinum*const value_;
@@ -463,22 +438,14 @@ class PEString : public PExpr {
virtual unsigned test_width(Design*des, NetScope*scope,
unsigned min, unsigned lval,
bool&unsized_flag) const;
ivl_variable_type_t&expr_type,
bool&unsized_flag);
virtual NetNet* elaborate_net(Design*des, NetScope*scope,
unsigned width,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
virtual NetEConst*elaborate_expr(Design*des, NetScope*,
int expr_width, bool) const;
virtual NetEConst*elaborate_pexpr(Design*des, NetScope*sc) const;
verinum* eval_const(Design*, NetScope*) const;
virtual bool is_constant(Module*) const;
private:
char*text_;
};
@@ -491,47 +458,22 @@ class PEUnary : public PExpr {
virtual void dump(ostream&out) const;
virtual bool has_aa_term(Design*des, NetScope*scope) const;
virtual unsigned test_width(Design*des, NetScope*scope,
unsigned min, unsigned lval,
ivl_variable_type_t&expr_type,
bool&unsized_flag);
virtual bool elaborate_sig(Design*des, NetScope*scope) const;
virtual NetNet* elaborate_net(Design*des, NetScope*scope,
unsigned width,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
virtual NetExpr*elaborate_expr(Design*des, NetScope*,
int expr_width, bool sys_task_arg) const;
virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
virtual verinum* eval_const(Design*des, NetScope*sc) const;
virtual bool is_constant(Module*) const;
private:
NetNet* elab_net_uminus_const_logic_(Design*des, NetScope*scope,
NetEConst*expr,
unsigned width,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
NetNet* elab_net_uminus_const_real_(Design*des, NetScope*scope,
NetECReal*expr,
unsigned width,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
NetNet* elab_net_unary_real_(Design*des, NetScope*scope,
NetExpr*expr,
unsigned width,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
NetExpr* elaborate_expr_bits_(NetExpr*operand, int expr_wid) const;
private:
char op_;
@@ -544,23 +486,17 @@ class PEBinary : public PExpr {
explicit PEBinary(char op, PExpr*l, PExpr*r);
~PEBinary();
virtual bool is_constant(Module*) const;
virtual void dump(ostream&out) const;
virtual bool has_aa_term(Design*des, NetScope*scope) const;
virtual unsigned test_width(Design*des, NetScope*scope,
unsigned min, unsigned lval,
bool&unsized_flag) const;
ivl_variable_type_t&expr_type,
bool&unsized_flag);
virtual bool elaborate_sig(Design*des, NetScope*scope) const;
virtual NetNet* elaborate_net(Design*des, NetScope*scope,
unsigned width,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
virtual NetExpr*elaborate_expr(Design*des, NetScope*,
int expr_width, bool sys_task_arg) const;
virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
@@ -571,57 +507,21 @@ class PEBinary : public PExpr {
PExpr*left_;
PExpr*right_;
NetExpr*elaborate_expr_base_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const;
NetExpr*elaborate_eval_expr_base_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const;
NetExpr*elaborate_expr_base_(Design*, NetExpr*lp, NetExpr*rp,
int use_wid, bool is_pexpr =false) const;
NetExpr*elaborate_eval_expr_base_(Design*, NetExpr*lp, NetExpr*rp,
int use_wid) const;
static void suppress_operand_sign_if_needed_(NetExpr*lp, NetExpr*rp);
NetExpr*elaborate_expr_base_bits_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const;
NetExpr*elaborate_expr_base_div_(Design*, NetExpr*lp, NetExpr*rp,
int use_wid, bool is_pexpr) const;
NetExpr*elaborate_expr_base_lshift_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const;
NetExpr*elaborate_expr_base_rshift_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const;
NetExpr*elaborate_expr_base_mult_(Design*, NetExpr*lp, NetExpr*rp,
int use_wid, bool is_pexpr) const;
NetExpr*elaborate_expr_base_add_(Design*, NetExpr*lp, NetExpr*rp,
int use_wid, bool is_pexpr) const;
private:
NetNet* elaborate_net_add_(Design*des, NetScope*scope,
unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay) const;
NetNet* elaborate_net_bit_(Design*des, NetScope*scope,
unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay) const;
NetNet* elaborate_net_cmp_(Design*des, NetScope*scope,
unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay) const;
NetNet* elaborate_net_div_(Design*des, NetScope*scope,
unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay) const;
NetNet* elaborate_net_mod_(Design*des, NetScope*scope,
unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay) const;
NetNet* elaborate_net_log_(Design*des, NetScope*scope,
unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay) const;
NetNet* elaborate_net_mul_(Design*des, NetScope*scope,
unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay) const;
NetNet* elaborate_net_pow_(Design*des, NetScope*scope,
unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay) const;
NetNet* elaborate_net_shift_(Design*des, NetScope*scope,
unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay) const;
};
/*
@@ -636,20 +536,82 @@ class PEBComp : public PEBinary {
virtual unsigned test_width(Design*des, NetScope*scope,
unsigned min, unsigned lval,
bool&flag) const;
ivl_variable_type_t&expr_type,
bool&flag);
NetExpr* elaborate_expr(Design*des, NetScope*scope,
int expr_width, bool sys_task_arg) const;
NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
private:
int left_width_;
int right_width_;
};
class PEBShift : public PEBinary {
/*
* This derived class is for handling logical expressions: && and ||.
*/
class PEBLogic : public PEBinary {
public:
explicit PEBLogic(char op, PExpr*l, PExpr*r);
~PEBLogic();
virtual unsigned test_width(Design*des, NetScope*scope,
unsigned min, unsigned lval,
ivl_variable_type_t&expr_type,
bool&flag);
NetExpr* elaborate_expr(Design*des, NetScope*scope,
int expr_width, bool sys_task_arg) const;
NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
};
/*
* A couple of the binary operands have a special sub-expression rule
* where the expression width is carried entirely by the left
* expression, and the right operand is self-determined.
*/
class PEBLeftWidth : public PEBinary {
public:
explicit PEBLeftWidth(char op, PExpr*l, PExpr*r);
~PEBLeftWidth() =0;
virtual NetExpr*elaborate_expr_leaf(Design*des, NetExpr*lp, NetExpr*rp,
int expr_wid) const =0;
protected:
virtual unsigned test_width(Design*des, NetScope*scope,
unsigned min, unsigned lval,
ivl_variable_type_t&expr_type,
bool&flag);
virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
int expr_width, bool sys_task_arg) const;
virtual NetExpr*elaborate_pexpr(Design*des, NetScope*scope) const;
};
class PEBPower : public PEBLeftWidth {
public:
explicit PEBPower(char op, PExpr*l, PExpr*r);
~PEBPower();
NetExpr*elaborate_expr_leaf(Design*des, NetExpr*lp, NetExpr*rp,
int expr_wid) const;
};
class PEBShift : public PEBLeftWidth {
public:
explicit PEBShift(char op, PExpr*l, PExpr*r);
~PEBShift();
virtual unsigned test_width(Design*des, NetScope*scope,
unsigned min, unsigned lval, bool&flag) const;
NetExpr*elaborate_expr_leaf(Design*des, NetExpr*lp, NetExpr*rp,
int expr_wid) const;
};
/*
@@ -662,27 +624,26 @@ class PETernary : public PExpr {
explicit PETernary(PExpr*e, PExpr*t, PExpr*f);
~PETernary();
virtual bool is_constant(Module*) const;
virtual void dump(ostream&out) const;
virtual bool has_aa_term(Design*des, NetScope*scope) const;
virtual unsigned test_width(Design*des, NetScope*scope,
unsigned min, unsigned lval,
bool&unsized_flag) const;
ivl_variable_type_t&expr_type,
bool&unsized_flag);
virtual bool elaborate_sig(Design*des, NetScope*scope) const;
virtual NetNet* elaborate_net(Design*des, NetScope*scope,
unsigned width,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
virtual NetETernary*elaborate_expr(Design*des, NetScope*,
virtual NetExpr*elaborate_expr(Design*des, NetScope*,
int expr_width, bool sys_task_arg) const;
virtual NetETernary*elaborate_pexpr(Design*des, NetScope*sc) const;
virtual verinum* eval_const(Design*des, NetScope*sc) const;
private:
NetExpr* elab_and_eval_alternative_(Design*des, NetScope*scope,
PExpr*expr, int use_wid) const;
private:
PExpr*expr_;
PExpr*tru_;
@@ -696,45 +657,44 @@ class PETernary : public PExpr {
*/
class PECallFunction : public PExpr {
public:
explicit PECallFunction(const pform_name_t&n, const svector<PExpr *> &parms);
explicit PECallFunction(const pform_name_t&n, const vector<PExpr *> &parms);
// Call of system function (name is not hierarchical)
explicit PECallFunction(perm_string n, const svector<PExpr *> &parms);
explicit PECallFunction(perm_string n, const vector<PExpr *> &parms);
explicit PECallFunction(perm_string n);
// svector versions. Should be removed!
explicit PECallFunction(const pform_name_t&n, const svector<PExpr *> &parms);
explicit PECallFunction(perm_string n, const svector<PExpr *> &parms);
~PECallFunction();
virtual void dump(ostream &) const;
virtual NetNet* elaborate_net(Design*des, NetScope*scope,
unsigned width,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
virtual bool has_aa_term(Design*des, NetScope*scope) const;
virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
int expr_wid, bool sys_task_arg) const;
virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
virtual unsigned test_width(Design*des, NetScope*scope,
unsigned min, unsigned lval,
bool&unsized_flag) const;
ivl_variable_type_t&expr_type,
bool&unsized_flag);
private:
pform_name_t path_;
svector<PExpr *> parms_;
vector<PExpr *> parms_;
bool check_call_matches_definition_(Design*des, NetScope*dscope) const;
NetExpr* cast_to_width_(NetExpr*expr, int wid, bool signed_flag) const;
NetExpr* elaborate_sfunc_(Design*des, NetScope*scope, int expr_wid) const;
NetNet* elaborate_net_sfunc_(Design*des, NetScope*scope,
unsigned width,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
NetExpr* elaborate_access_func_(Design*des, NetScope*scope, ivl_nature_t) const;
unsigned test_width_sfunc_(Design*des, NetScope*scope,
unsigned min, unsigned lval,
bool&unsized_flag) const;
ivl_variable_type_t&expr_type,
bool&unsized_flag);
};
#endif
+2 -1
View File
@@ -21,9 +21,10 @@
#include "PTask.h"
PFunction::PFunction(perm_string name, PScope*parent)
PFunction::PFunction(perm_string name, PScope*parent, bool is_auto__)
: PScope(name, parent), ports_(0), statement_(0)
{
is_auto_ = is_auto__;
return_type_.type = PTF_NONE;
}
+2 -56
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1999-2007 Stephen Williams ([email protected])
* Copyright (c) 1999-2010 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -22,7 +22,7 @@
# include "PGate.h"
# include "PExpr.h"
# include "verinum.h"
# include <assert.h>
# include <cassert>
PGate::PGate(perm_string name,
svector<PExpr*>*pins,
@@ -99,59 +99,6 @@ void PGate::eval_delays(Design*des, NetScope*scope,
as_net_flag);
}
void PGate::eval_delays(Design*des, NetScope*scope,
unsigned long&rise_time,
unsigned long&fall_time,
unsigned long&decay_time) const
{
NetExpr*rise_expr, *fall_expr, *decay_expr;
delay_.eval_delays(des, scope, rise_expr, fall_expr, decay_expr);
if (rise_expr == 0) {
rise_time = 0;
fall_time = 0;
decay_time = 0;
}
if (NetEConst*tmp = dynamic_cast<NetEConst*> (rise_expr)) {
rise_time = tmp->value().as_ulong();
} else {
cerr << get_fileline() << ": error: Delay expressions must be "
<< "constant here." << endl;
cerr << get_fileline() << ": : Cannot calculate "
<< *rise_expr << endl;
des->errors += 1;
rise_time = 0;
}
if (NetEConst*tmp = dynamic_cast<NetEConst*> (fall_expr)) {
fall_time = tmp->value().as_ulong();
} else {
if (fall_expr != rise_expr) {
cerr << get_fileline() << ": error: Delay expressions must be "
<< "constant here." << endl;
cerr << get_fileline() << ": : Cannot calculate "
<< *rise_expr << endl;
}
des->errors += 1;
fall_time = 0;
}
if (NetEConst*tmp = dynamic_cast<NetEConst*> (decay_expr)) {
decay_time = tmp->value().as_ulong();
} else {
cerr << get_fileline() << ": error: Delay expressions must be "
<< "constant here." << endl;
cerr << get_fileline() << ": : Cannot calculate "
<< *rise_expr << endl;
des->errors += 1;
decay_time = 0;
}
}
PGAssign::PGAssign(svector<PExpr*>*pins)
: PGate(perm_string(), pins)
{
@@ -242,4 +189,3 @@ perm_string PGModule::get_type()
{
return type_;
}
+15 -16
View File
@@ -1,7 +1,7 @@
#ifndef __PGate_H
#define __PGate_H
/*
* Copyright (c) 1998-2004 Stephen Williams ([email protected])
* Copyright (c) 1998-2008 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PGate.h,v 1.32 2006/04/10 00:37:42 steve Exp $"
#endif
# include "svector.h"
# include "StringHeap.h"
@@ -65,15 +62,6 @@ class PGate : public LineInfo {
perm_string get_name() const { return name_; }
// This method evaluates the delays all the way to an
// integer. If the delay is non-constant, then set the times
// to 0, print an error message and mark an error to the
// design.
void eval_delays(Design*des, NetScope*scope,
unsigned long&rise_time,
unsigned long&fall_time,
unsigned long&decay_time) const;
// This evaluates the delays as far as possible, but returns
// an expression, and do not signal errors.
void eval_delays(Design*des, NetScope*scope,
@@ -83,7 +71,7 @@ class PGate : public LineInfo {
bool as_net_flag =false) const;
unsigned pin_count() const { return pins_? pins_->count() : 0; }
const PExpr*pin(unsigned idx) const { return (*pins_)[idx]; }
PExpr*pin(unsigned idx) const { return (*pins_)[idx]; }
strength_t strength0() const;
strength_t strength1() const;
@@ -170,8 +158,17 @@ class PGBuiltin : public PGate {
virtual bool elaborate_sig(Design*des, NetScope*scope) const;
private:
Type type_;
unsigned calculate_array_count_(Design*, NetScope*,
long&high, long&low) const;
void calculate_gate_and_lval_count_(unsigned&gate_count,
unsigned&lval_count) const;
NetNode* create_gate_for_output_(Design*, NetScope*,
perm_string gate_name,
unsigned instance_width) const;
Type type_;
PExpr*msb_;
PExpr*lsb_;
};
@@ -232,15 +229,17 @@ class PGModule : public PGate {
PExpr*msb_;
PExpr*lsb_;
friend class delayed_elaborate_scope_mod_instances;
void elaborate_mod_(Design*, Module*mod, NetScope*scope) const;
void elaborate_udp_(Design*, PUdp *udp, NetScope*scope) const;
void elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const;
void elaborate_scope_mod_instances_(Design*des, Module*mod, NetScope*sc) const;
bool elaborate_sig_mod_(Design*des, NetScope*scope, Module*mod) const;
bool elaborate_sig_udp_(Design*des, NetScope*scope, PUdp*udp) const;
NetNet*resize_net_to_port_(Design*des, NetScope*scope,
NetNet*sig, unsigned port_wid,
NetNet::PortType dir) const;
NetNet::PortType dir, bool as_signed) const;
};
#endif
+74 -15
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006 Stephen Williams ([email protected])
* Copyright (c) 2006,2009 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,38 +16,97 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PGenerate.cc,v 1.4 2007/06/02 03:42:12 steve Exp $"
#endif
# include "PGenerate.h"
# include "PWire.h"
# include "ivl_assert.h"
PGenerate::PGenerate(unsigned id)
: id_number(id)
{
direct_nested_ = false;
parent = 0;
lexical_scope = 0;
}
PGenerate::~PGenerate()
{
}
PWire* PGenerate::get_wire(perm_string name) const
{
map<perm_string,PWire*>::const_iterator obj = wires.find(name);
if (obj == wires.end())
return 0;
else
return (*obj).second;
}
void PGenerate::add_gate(PGate*gate)
{
gates.push_back(gate);
}
void PGenerate::add_behavior(PProcess*proc)
void PGenerate::probe_for_direct_nesting_(void)
{
behaviors.push_back(proc);
direct_nested_ = false;
ivl_assert(*this, scheme_type==GS_CASE_ITEM || scheme_type==GS_CONDIT || scheme_type==GS_ELSE);
// If this scheme has received an explicit name, then it
// cannot be direct nested.
if (scope_name[0] != '$') return;
if (tasks.size() > 0) return;
if (funcs.size() > 0) return;
if (gates.size() > 0) return;
if (parameters.size() > 0) return;
if (localparams.size() > 0) return;
if (events.size() > 0) return;
if (wires.size() > 0) return;
if (genvars.size() > 0) return;
if (behaviors.size() > 0) return;
if (analog_behaviors.size() > 0) return;
if (generate_schemes.size() == 0) return;
switch (generate_schemes.size()) {
case 1: {
PGenerate*child = generate_schemes.front();
if (child->scheme_type == GS_CONDIT)
direct_nested_ = true;
if (child->scheme_type == GS_CASE)
direct_nested_ = true;
break;
}
case 2: {
PGenerate*child1 = generate_schemes.front();
PGenerate*child2 = generate_schemes.back();
if (child1->scheme_type==GS_CONDIT && child2->scheme_type==GS_ELSE)
direct_nested_ = true;
if (child2->scheme_type==GS_CONDIT && child1->scheme_type==GS_ELSE)
direct_nested_ = true;
break;
}
}
}
ostream& operator << (ostream&out, PGenerate::scheme_t type)
{
switch (type) {
case PGenerate::GS_NONE:
out << "GS_NONE";
break;
case PGenerate::GS_LOOP:
out << "GS_LOOP";
break;
case PGenerate::GS_CONDIT:
out << "GS_CONDIT";
break;
case PGenerate::GS_ELSE:
out << "GS_ELSE";
break;
case PGenerate::GS_CASE:
out << "GS_CASE";
break;
case PGenerate::GS_CASE_ITEM:
out << "GS_CASE_ITEM";
break;
case PGenerate::GS_NBLOCK:
out << "GS_NBLOCK";
break;
}
return out;
}
+40 -12
View File
@@ -1,7 +1,7 @@
#ifndef __PGenerate_H
#define __PGenerate_H
/*
* Copyright (c) 2006 Stephen Williams ([email protected])
* Copyright (c) 2006-2009,2012 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,21 +18,22 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PGenerate.h,v 1.4 2007/06/02 03:42:12 steve Exp $"
#endif
# include "LineInfo.h"
# include "StringHeap.h"
# include "HName.h"
# include "PScope.h"
# include <list>
# include <map>
# include <valarray>
# include "pform_types.h"
class Design;
class NetScope;
class PExpr;
class PFunction;
class PProcess;
class PTask;
class PGate;
class PWire;
@@ -49,10 +50,10 @@ class PWire;
* The parent points to the GS_CASE that contains this item.
* the loop_test is compared with the parent->loop_test expression.
*/
class PGenerate : public LineInfo {
class PGenerate : public LineInfo, public LexicalScope {
public:
PGenerate(unsigned id_number);
explicit PGenerate(unsigned id_number);
~PGenerate();
// Generate schemes have an ID number, for when the scope is
@@ -60,8 +61,12 @@ class PGenerate : public LineInfo {
const unsigned id_number;
perm_string scope_name;
// This is used during parsing to stack lexical scopes within
// this generate scheme.
PScope*lexical_scope;
enum scheme_t {GS_NONE, GS_LOOP, GS_CONDIT, GS_ELSE,
GS_CASE, GS_CASE_ITEM};
GS_CASE, GS_CASE_ITEM, GS_NBLOCK};
scheme_t scheme_type;
// generate loops have an index variable and three
@@ -70,17 +75,27 @@ class PGenerate : public LineInfo {
PExpr*loop_init;
PExpr*loop_test;
PExpr*loop_step;
// Case items may have multiple guard expression values. It is
// enough for any on of the guards to match the case statement
// test value.
std::valarray<PExpr*> item_test;
map<perm_string,PWire*>wires;
PWire* get_wire(perm_string name) const;
// defparam assignments found in this scope.
typedef pair<pform_name_t,PExpr*> named_expr_t;
list<named_expr_t>defparms;
list<PGate*> gates;
void add_gate(PGate*);
list<PProcess*> behaviors;
void add_behavior(PProcess*behave);
// Tasks instantiated within this scheme.
map<perm_string,PTask*> tasks;
map<perm_string,PFunction*>funcs;
list<PGenerate*> generates;
// genvars declared within this scheme.
map<perm_string,LineInfo*> genvars;
// Generate schemes can contain further generate schemes.
list<PGenerate*> generate_schemes;
PGenerate*parent;
// This method is called by the elaboration of a module to
@@ -99,19 +114,32 @@ class PGenerate : public LineInfo {
bool generate_scope_loop_(Design*des, NetScope*container);
bool generate_scope_condit_(Design*des, NetScope*container, bool else_flag);
bool generate_scope_case_(Design*des, NetScope*container);
bool generate_scope_nblock_(Design*des, NetScope*container);
// Call probe during elaborate_scope to calculate the
// direct_nested_ flag. It is OK to store the direct_nested_
// information here because "direct nested" is a property of
// the lexical generate code.
void probe_for_direct_nesting_(void);
bool direct_nested_;
// Elaborate_scope within a generated scope.
void elaborate_subscope_(Design*des, NetScope*scope);
void elaborate_subscope_direct_(Design*des, NetScope*scope);
// These are the scopes created by generate_scope.
list<NetScope*>scope_list_;
// internal function called on each scope generated by this scheme.
bool elaborate_sig_(Design*des, NetScope*scope) const;
bool elaborate_sig_direct_(Design*des, NetScope*scope) const;
bool elaborate_(Design*des, NetScope*scope) const;
bool elaborate_direct_(Design*des, NetScope*scope) const;
private: // not implemented
PGenerate(const PGenerate&);
PGenerate& operator= (const PGenerate&);
};
extern std::ostream& operator << (std::ostream&, PGenerate::scheme_t);
#endif
+8 -3
View File
@@ -19,8 +19,13 @@
# include "PScope.h"
PScope::PScope(perm_string n, PScope*p)
: name_(n), parent_(p)
PScope::PScope(perm_string n, PScope*parent)
: name_(n), parent_(parent)
{
}
PScope::PScope(perm_string n)
: name_(n), parent_(0)
{
}
@@ -28,7 +33,7 @@ PScope::~PScope()
{
}
PWire* PScope::wires_find(perm_string name)
PWire* LexicalScope::wires_find(perm_string name)
{
map<perm_string,PWire*>::const_iterator cur = wires.find(name);
if (cur == wires.end())
+71 -14
View File
@@ -19,11 +19,15 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
# include "LineInfo.h"
# include "StringHeap.h"
# include "pform_types.h"
# include "ivl_target.h"
# include <map>
class PEvent;
class PExpr;
class AProcess;
class PProcess;
class PWire;
@@ -35,10 +39,74 @@ class NetScope;
* represents lexical scope. For example, a module, a function/task, a
* named block is derived from a PScope.
*
* NOTE: This is note the same concept as the "scope" of an elaborated
* NOTE: This is not the same concept as the "scope" of an elaborated
* hierarchy. That is represented by NetScope objects after elaboration.
*/
class PScope {
class LexicalScope {
public:
explicit LexicalScope() { }
// A virtual destructor is so that dynamic_cast can work.
virtual ~LexicalScope() { }
struct range_t {
// True if this is an exclude
bool exclude_flag;
// lower bound
// If low_open_flag is false and low_expr=0, then use -inf
bool low_open_flag;
PExpr*low_expr;
// upper bound
// If high_open_flag is false and high_expr=0, then use +inf
bool high_open_flag;
PExpr*high_expr;
// Next range description in list
struct range_t*next;
};
/* The scope has parameters that are evaluated when the scope
is elaborated. During parsing, I put the parameters into
this map. */
struct param_expr_t : public LineInfo {
param_expr_t() : type(IVL_VT_NO_TYPE), msb(0), lsb(0), signed_flag(false), expr(0), range(0) { }
// Type information
ivl_variable_type_t type;
PExpr*msb;
PExpr*lsb;
bool signed_flag;
// Value expression
PExpr*expr;
// If there are range constraints, list them here
range_t*range;
};
map<perm_string,param_expr_t>parameters;
map<perm_string,param_expr_t>localparams;
// Named events in the scope.
map<perm_string,PEvent*>events;
// Nets and variables (wires) in the scope
map<perm_string,PWire*>wires;
PWire* wires_find(perm_string name);
// Behaviors (processes) in this scope
list<PProcess*> behaviors;
list<AProcess*> analog_behaviors;
protected:
void dump_parameters_(ostream&out, unsigned indent) const;
void dump_localparams_(ostream&out, unsigned indent) const;
void dump_events_(ostream&out, unsigned indent) const;
void dump_wires_(ostream&out, unsigned indent) const;
private:
};
class PScope : public LexicalScope {
public:
// When created, a scope has a name and a parent. The name is
@@ -50,24 +118,13 @@ class PScope {
// modules. Scopes for tasks and functions point to their
// containing module.
PScope(perm_string name, PScope*parent);
PScope(perm_string name);
virtual ~PScope();
perm_string pscope_name() const { return name_; }
PScope* pscope_parent() { return parent_; }
// Nets an variables (wires) in the scope
map<perm_string,PWire*>wires;
PWire* wires_find(perm_string name);
// Named events in the scope.
map<perm_string,PEvent*>events;
// Behaviors (processes) in this scope
list<PProcess*> behaviors;
protected:
void dump_wires_(ostream&out, unsigned indent) const;
bool elaborate_sig_wires_(Design*des, NetScope*scope) const;
bool elaborate_behaviors_(Design*des, NetScope*scope) const;
-3
View File
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PSpec.cc,v 1.2 2007/02/12 01:52:21 steve Exp $"
#endif
# include "PSpec.h"
+11 -4
View File
@@ -1,7 +1,7 @@
#ifndef __PSpec_H
#define __PSpec_H
/*
* Copyright (c) 2006 Stephen Williams <[email protected]>
* Copyright (c) 2006-2011 Stephen Williams <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PSpec.h,v 1.3 2007/04/13 02:34:35 steve Exp $"
#endif
# include "LineInfo.h"
# include "StringHeap.h"
@@ -49,6 +46,12 @@ class PExpr;
*
* If data_source_expression != nil, then the path is edge sensitive
* and the edge might not be 0.
*
* The full flag is used to verify that only vectors of the same size
* are used in a parallel connection. Icarus always creates a full
* connection between the source and destination. The polarity is for
* informational (display) purposes only. The polarity is either '+',
* '-' or 0.
*/
class PSpecPath : public LineInfo {
@@ -66,6 +69,10 @@ class PSpecPath : public LineInfo {
class PExpr* condition;
// Edge specification (-1==negedge, 0 = no edge, 1==posedge)
int edge;
// Is this a full connection.
bool full_flag;
// What is the polarity of the connection.
char polarity;
// Ordered set of source nodes of a path
std::vector<perm_string> src;
// Ordered set of destination nodes of a path
+2 -29
View File
@@ -21,9 +21,10 @@
# include "PTask.h"
PTask::PTask(perm_string name, PScope*parent)
PTask::PTask(perm_string name, PScope*parent, bool is_auto__)
: PScope(name, parent), ports_(0), statement_(0)
{
is_auto_ = is_auto__;
}
PTask::~PTask()
@@ -41,31 +42,3 @@ void PTask::set_statement(Statement*s)
assert(statement_ == 0);
statement_ = s;
}
/*
* $Log: PTask.cc,v $
* Revision 1.7 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.6 2001/07/25 03:10:48 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.5 2001/04/19 03:04:47 steve
* Spurious assert of empty statemnt.
*
* Revision 1.4 2001/01/13 22:20:08 steve
* Parse parameters within nested scopes.
*
* Revision 1.3 2000/02/23 02:56:53 steve
* Macintosh compilers do not support ident.
*
* Revision 1.2 1999/07/24 02:11:19 steve
* Elaborate task input ports.
*
* Revision 1.1 1999/07/03 02:12:51 steve
* Elaborate user defined tasks.
*
*/
+8 -2
View File
@@ -51,7 +51,7 @@ struct PTaskFuncArg {
class PTask : public PScope, public LineInfo {
public:
explicit PTask(perm_string name, PScope*parent);
explicit PTask(perm_string name, PScope*parent, bool is_auto);
~PTask();
void set_ports(svector<PWire *>*p);
@@ -69,11 +69,14 @@ class PTask : public PScope, public LineInfo {
// Elaborate the statement to finish off the task definition.
void elaborate(Design*des, NetScope*scope) const;
bool is_auto() const { return is_auto_; };
void dump(ostream&, unsigned) const;
private:
svector<PWire*>*ports_;
Statement*statement_;
bool is_auto_;
private: // Not implemented
PTask(const PTask&);
@@ -90,7 +93,7 @@ class PTask : public PScope, public LineInfo {
class PFunction : public PScope, public LineInfo {
public:
explicit PFunction(perm_string name, PScope*parent);
explicit PFunction(perm_string name, PScope*parent, bool is_auto);
~PFunction();
void set_ports(svector<PWire *>*p);
@@ -105,12 +108,15 @@ class PFunction : public PScope, public LineInfo {
/* Elaborate the behavioral statement. */
void elaborate(Design *des, NetScope*) const;
bool is_auto() const { return is_auto_; };
void dump(ostream&, unsigned) const;
private:
PTaskFuncArg return_type_;
svector<PWire *> *ports_;
Statement *statement_;
bool is_auto_;
};
#endif
-16
View File
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PUdp.cc,v 1.3 2004/03/08 00:47:44 steve Exp $"
#endif
# include "PUdp.h"
@@ -38,16 +35,3 @@ unsigned PUdp::find_port(const char*name)
return ports.count();
}
/*
* $Log: PUdp.cc,v $
* Revision 1.3 2004/03/08 00:47:44 steve
* primitive ports can bind bi name.
*
* Revision 1.2 2004/02/18 17:11:54 steve
* Use perm_strings for named langiage items.
*
* Revision 1.1 2003/07/15 05:07:13 steve
* Move PUdp constructor into compiled file.
*
*/
-52
View File
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PUdp.h,v 1.12 2004/03/08 00:47:44 steve Exp $"
#endif
# include <map>
# include "StringHeap.h"
@@ -78,53 +75,4 @@ class PUdp {
PUdp& operator= (const PUdp&);
};
/*
* $Log: PUdp.h,v $
* Revision 1.12 2004/03/08 00:47:44 steve
* primitive ports can bind bi name.
*
* Revision 1.11 2004/02/18 17:11:54 steve
* Use perm_strings for named langiage items.
*
* Revision 1.10 2003/07/15 05:07:13 steve
* Move PUdp constructor into compiled file.
*
* Revision 1.9 2003/07/15 03:49:22 steve
* Spelling fixes.
*
* Revision 1.8 2003/01/30 16:23:07 steve
* Spelling fixes.
*
* Revision 1.7 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.6 2002/05/23 03:08:51 steve
* Add language support for Verilog-2001 attribute
* syntax. Hook this support into existing $attribute
* handling, and add number and void value types.
*
* Add to the ivl_target API new functions for access
* of complex attributes attached to gates.
*
* Revision 1.5 2001/04/22 23:09:45 steve
* More UDP consolidation from Stephan Boettcher.
*
* Revision 1.4 2000/02/23 02:56:53 steve
* Macintosh compilers do not support ident.
*
* Revision 1.3 1999/06/15 03:44:53 steve
* Get rid of the STL vector template.
*
* Revision 1.2 1998/12/01 00:42:13 steve
* Elaborate UDP devices,
* Support UDP type attributes, and
* pass those attributes to nodes that
* are instantiated by elaboration,
* Put modules into a map instead of
* a simple list.
*
* Revision 1.1 1998/11/25 02:35:53 steve
* Parse UDP primitives all the way to pform.
*
*/
#endif
+24 -8
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1999-2007 Stephen Williams ([email protected])
* Copyright (c) 1999-2011 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -20,7 +20,7 @@
# include "config.h"
# include "PWire.h"
# include "PExpr.h"
# include <assert.h>
# include <cassert>
PWire::PWire(perm_string n,
NetNet::Type t,
@@ -29,8 +29,8 @@ PWire::PWire(perm_string n,
: name_(n), type_(t), port_type_(pt), data_type_(dt),
signed_(false), isint_(false),
port_msb_(0), port_lsb_(0), port_set_(false),
net_msb_(0), net_lsb_(0), net_set_(false), error_cnt_(0),
lidx_(0), ridx_(0), discipline_(0)
net_msb_(0), net_lsb_(0), net_set_(false), is_scalar_(false),
error_cnt_(0), lidx_(0), ridx_(0), discipline_(0)
{
if (t == NetNet::INTEGER) {
type_ = NetNet::REG;
@@ -58,7 +58,15 @@ bool PWire::set_wire_type(NetNet::Type t)
type_ = t;
return true;
case NetNet::IMPLICIT_REG:
if (t == NetNet::REG) { type_ = t; return true; }
if (t == NetNet::REG) {
type_ = t;
return true;
}
if (t == NetNet::INTEGER) {
type_ = NetNet::REG;
isint_ = true;
return true;
}
return false;
case NetNet::REG:
if (t == NetNet::INTEGER) {
@@ -135,7 +143,12 @@ bool PWire::get_isint() const
return isint_;
}
void PWire::set_range(PExpr*m, PExpr*l, PWSRType type)
bool PWire::get_scalar() const
{
return is_scalar_;
}
void PWire::set_range(PExpr*m, PExpr*l, PWSRType type, bool is_scalar)
{
switch (type) {
case SR_PORT:
@@ -147,6 +160,7 @@ void PWire::set_range(PExpr*m, PExpr*l, PWSRType type)
port_msb_ = m;
port_lsb_ = l;
port_set_ = true;
is_scalar_ = is_scalar;
}
return;
@@ -159,6 +173,7 @@ void PWire::set_range(PExpr*m, PExpr*l, PWSRType type)
net_msb_ = m;
net_lsb_ = l;
net_set_ = true;
is_scalar_ = is_scalar;
}
return;
@@ -181,6 +196,7 @@ void PWire::set_range(PExpr*m, PExpr*l, PWSRType type)
net_msb_ = m;
net_lsb_ = l;
net_set_ = true;
is_scalar_ = is_scalar;
}
return;
}
@@ -198,13 +214,13 @@ void PWire::set_memory_idx(PExpr*ldx, PExpr*rdx)
}
}
void PWire::set_discipline(discipline_t*d)
void PWire::set_discipline(ivl_discipline_t d)
{
assert(discipline_ == 0);
discipline_ = d;
}
discipline_t* PWire::get_discipline(void) const
ivl_discipline_t PWire::get_discipline(void) const
{
return discipline_;
}
+7 -9
View File
@@ -1,7 +1,7 @@
#ifndef __PWire_H
#define __PWire_H
/*
* Copyright (c) 1998-2007 Stephen Williams ([email protected])
* Copyright (c) 1998-2009 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PWire.h,v 1.21 2007/05/24 04:07:11 steve Exp $"
#endif
# include "netlist.h"
# include "LineInfo.h"
@@ -36,7 +33,6 @@ class ostream;
class PExpr;
class Design;
class discipline_t;
/*
* The different type of PWire::set_range() calls.
@@ -74,16 +70,17 @@ class PWire : public LineInfo {
void set_signed(bool flag);
bool get_signed() const;
bool get_isint() const;
bool get_scalar() const;
bool set_data_type(ivl_variable_type_t dt);
ivl_variable_type_t get_data_type() const;
void set_range(PExpr*msb, PExpr*lsb, PWSRType type);
void set_range(PExpr*msb, PExpr*lsb, PWSRType type, bool is_scalar);
void set_memory_idx(PExpr*ldx, PExpr*rdx);
void set_discipline(discipline_t*);
discipline_t* get_discipline(void) const;
void set_discipline(ivl_discipline_t);
ivl_discipline_t get_discipline(void) const;
map<perm_string,PExpr*> attributes;
@@ -108,6 +105,7 @@ class PWire : public LineInfo {
PExpr*net_msb_;
PExpr*net_lsb_;
bool net_set_;
bool is_scalar_;
unsigned error_cnt_;
// If this wire is actually a memory, these indices will give
@@ -115,7 +113,7 @@ class PWire : public LineInfo {
PExpr*lidx_;
PExpr*ridx_;
discipline_t*discipline_;
ivl_discipline_t discipline_;
private: // not implemented
PWire(const PWire&);
+14 -31
View File
@@ -12,10 +12,7 @@ home page at <http://www.icarus.com/eda/verilog>.
Icarus Verilog is not aimed at being a simulator in the traditional
sense, but a compiler that generates code employed by back-end
tools. These back-end tools currently include a simulator engine
called VVP, an XNF (Xilinx Netlist Format) generator and an EDIF FPGA
netlist generator. In the future, backends are expected for EDIF/LPM,
structural Verilog, VHDL, etc.
tools.
For instructions on how to run Icarus Verilog,
see the ``iverilog'' man page.
@@ -88,10 +85,6 @@ Normally, this command automatically figures out everything it needs
to know. It generally works pretty well. There are a few flags to the
configure script that modify its behavior:
--without-ipal
This turns off support for Icarus PAL, whether ipal
libraries are installed or not.
--prefix=<root>
The default is /usr/local, which causes the tool suite to
be compiled for install in /usr/local/bin,
@@ -102,27 +95,16 @@ configure script that modify its behavior:
common to use --prefix=/opt. You can configure for a non-root
install with --prefix=$HOME.
--enable-vvp32 (experimental)
If compiling on AMD64 systems, this enables the
compilation of 32bit compatible vvp (vvp32) and the vpi
modules that match.
2.2.1 Special AMD64 Instructions
(The Icarus Verilog RPM for x86_64 is build using these instructions.)
If you are building for Linux/AMD64 (a.k.a x86_64) then to get the
most out of your install, first make sure you have both 64bit and
32bit development libraries installed. Then configure with this
somewhat more complicated command:
./configure libdir64='$(prefix)/lib64' vpidir1=vpi64 vpidir2=. --enable-vvp32
This reflects the convention on AMD64 systems that 64bit libraries go
into lib64 directories. The "--enable-vvp32" also turns on 32bit
compatibility files. A 32bit version of vvp (vvp32) will be created,
as well as 32bit versions of the development libraries and bundled VPI
libraries.
--enable-suffix
--enable-suffix=<your-suffix>
--disable-suffix
Enable/disable changing the names of install files to use
a suffix string so that this version or install can co-
exist with other versions. This renames the installed
commands (iverilog, iverilog-vpi, vvp) and the installed
library files and include directory so that installations
with the same prefix but different suffix are guaranteed
to not interfere with each other.
2.3 (Optional) Testing
@@ -174,8 +156,9 @@ step. There may be dangling references, and it is not yet clear which
module is the root.
One can see a human readable version of the final pform by using the
``-P <path>'' flag to the compiler. This will cause iverilog to dump
the pform into the file named <path>.
``-P <path>'' flag to the ``ivl'' subcommand. This will cause ivl
to dump the pform into the file named <path>. (Note that this is not
normally done, unless debugging the ``ivl'' subcommand.)
3.3 Elaboration
+37 -56
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1998-1999 Stephen Williams ([email protected])
* Copyright (c) 1998-2008 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: Statement.cc,v 1.30 2007/05/24 04:07:11 steve Exp $"
#endif
# include "config.h"
@@ -29,20 +26,20 @@ Statement::~Statement()
{
}
PAssign_::PAssign_(PExpr*lval, PExpr*ex)
: event_(0), lval_(lval), rval_(ex)
PAssign_::PAssign_(PExpr*lval__, PExpr*ex, bool is_constant)
: event_(0), count_(0), lval_(lval__), rval_(ex), is_constant_(is_constant)
{
delay_ = 0;
}
PAssign_::PAssign_(PExpr*lval, PExpr*de, PExpr*ex)
: event_(0), lval_(lval), rval_(ex)
PAssign_::PAssign_(PExpr*lval__, PExpr*de, PExpr*ex)
: event_(0), count_(0), lval_(lval__), rval_(ex), is_constant_(false)
{
delay_ = de;
}
PAssign_::PAssign_(PExpr*lval, PEventStatement*ev, PExpr*ex)
: event_(ev), lval_(lval), rval_(ex)
PAssign_::PAssign_(PExpr*lval__, PExpr*cnt, PEventStatement*ev, PExpr*ex)
: event_(ev), count_(cnt), lval_(lval__), rval_(ex), is_constant_(false)
{
delay_ = 0;
}
@@ -53,18 +50,23 @@ PAssign_::~PAssign_()
delete rval_;
}
PAssign::PAssign(PExpr*lval, PExpr*ex)
: PAssign_(lval, ex)
PAssign::PAssign(PExpr*lval__, PExpr*ex)
: PAssign_(lval__, ex, false)
{
}
PAssign::PAssign(PExpr*lval, PExpr*d, PExpr*ex)
: PAssign_(lval, d, ex)
PAssign::PAssign(PExpr*lval__, PExpr*d, PExpr*ex)
: PAssign_(lval__, d, ex)
{
}
PAssign::PAssign(PExpr*lval, PEventStatement*d, PExpr*ex)
: PAssign_(lval, d, ex)
PAssign::PAssign(PExpr*lval__, PExpr*cnt, PEventStatement*d, PExpr*ex)
: PAssign_(lval__, cnt, d, ex)
{
}
PAssign::PAssign(PExpr*lval__, PExpr*ex, bool is_constant)
: PAssign_(lval__, ex, is_constant)
{
}
@@ -72,13 +74,18 @@ PAssign::~PAssign()
{
}
PAssignNB::PAssignNB(PExpr*lval, PExpr*ex)
: PAssign_(lval, ex)
PAssignNB::PAssignNB(PExpr*lval__, PExpr*ex)
: PAssign_(lval__, ex, false)
{
}
PAssignNB::PAssignNB(PExpr*lval, PExpr*d, PExpr*ex)
: PAssign_(lval, d, ex)
PAssignNB::PAssignNB(PExpr*lval__, PExpr*d, PExpr*ex)
: PAssign_(lval__, d, ex)
{
}
PAssignNB::PAssignNB(PExpr*lval__, PExpr*cnt, PEventStatement*d, PExpr*ex)
: PAssign_(lval__, cnt, d, ex)
{
}
@@ -92,7 +99,7 @@ PBlock::PBlock(perm_string n, PScope*parent, BL_TYPE t)
}
PBlock::PBlock(BL_TYPE t)
: PScope(perm_string(),0), bl_type_(t)
: PScope(perm_string()), bl_type_(t)
{
}
@@ -221,6 +228,15 @@ void PEventStatement::set_statement(Statement*st)
statement_ = st;
}
bool PEventStatement::has_aa_term(Design*des, NetScope*scope)
{
bool flag = false;
for (unsigned idx = 0 ; idx < expr_.count() ; idx += 1) {
flag = expr_[idx]->has_aa_term(des, scope) || flag;
}
return flag;
}
PForce::PForce(PExpr*l, PExpr*r)
: lval_(l), expr_(r)
{
@@ -298,38 +314,3 @@ PWhile::~PWhile()
delete cond_;
delete statement_;
}
/*
* $Log: Statement.cc,v $
* Revision 1.30 2007/05/24 04:07:11 steve
* Rework the heirarchical identifier parse syntax and pform
* to handle more general combinations of heirarch and bit selects.
*
* Revision 1.29 2004/02/18 17:11:54 steve
* Use perm_strings for named langiage items.
*
* Revision 1.28 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.27 2002/04/21 22:31:02 steve
* Redo handling of assignment internal delays.
* Leave it possible for them to be calculated
* at run time.
*
* Revision 1.26 2002/04/21 04:59:07 steve
* Add support for conbinational events by finding
* the inputs to expressions and some statements.
* Get case and assignment statements working.
*
* Revision 1.25 2001/12/03 04:47:14 steve
* Parser and pform use hierarchical names as hname_t
* objects instead of encoded strings.
*
* Revision 1.24 2001/11/22 06:20:59 steve
* Use NetScope instead of string for scope path.
*
* Revision 1.23 2001/07/25 03:10:48 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*/
+23 -9
View File
@@ -20,6 +20,7 @@
*/
# include <string>
# include "ivl_target.h"
# include "svector.h"
# include "StringHeap.h"
# include "PDelays.h"
@@ -46,16 +47,14 @@ class NetScope;
class PProcess : public LineInfo {
public:
enum Type { PR_INITIAL, PR_ALWAYS };
PProcess(Type t, Statement*st)
PProcess(ivl_process_type_t t, Statement*st)
: type_(t), statement_(st) { }
virtual ~PProcess();
bool elaborate(Design*des, NetScope*scope) const;
Type type() const { return type_; }
ivl_process_type_t type() const { return type_; }
Statement*statement() { return statement_; }
map<perm_string,PExpr*> attributes;
@@ -63,7 +62,7 @@ class PProcess : public LineInfo {
virtual void dump(ostream&out, unsigned ind) const;
private:
Type type_;
ivl_process_type_t type_;
Statement*statement_;
};
@@ -82,6 +81,8 @@ class Statement : public LineInfo {
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
virtual void elaborate_scope(Design*des, NetScope*scope) const;
virtual void elaborate_sig(Design*des, NetScope*scope) const;
map<perm_string,PExpr*> attributes;
};
/*
@@ -91,23 +92,27 @@ class Statement : public LineInfo {
*/
class PAssign_ : public Statement {
public:
explicit PAssign_(PExpr*lval, PExpr*ex);
explicit PAssign_(PExpr*lval, PExpr*ex, bool is_constant);
explicit PAssign_(PExpr*lval, PExpr*de, PExpr*ex);
explicit PAssign_(PExpr*lval, PEventStatement*de, PExpr*ex);
explicit PAssign_(PExpr*lval, PExpr*cnt, PEventStatement*de, PExpr*ex);
virtual ~PAssign_() =0;
const PExpr* lval() const { return lval_; }
const PExpr* rval() const { return rval_; }
PExpr* rval() const { return rval_; }
protected:
NetAssign_* elaborate_lval(Design*, NetScope*scope) const;
NetExpr* elaborate_rval_(Design*, NetScope*, unsigned lv_width,
ivl_variable_type_t type) const;
PExpr* delay_;
PEventStatement*event_;
PExpr* count_;
private:
PExpr* lval_;
PExpr* rval_;
bool is_constant_;
};
class PAssign : public PAssign_ {
@@ -115,7 +120,8 @@ class PAssign : public PAssign_ {
public:
explicit PAssign(PExpr*lval, PExpr*ex);
explicit PAssign(PExpr*lval, PExpr*de, PExpr*ex);
explicit PAssign(PExpr*lval, PEventStatement*de, PExpr*ex);
explicit PAssign(PExpr*lval, PExpr*cnt, PEventStatement*de, PExpr*ex);
explicit PAssign(PExpr*lval, PExpr*ex, bool is_constant);
~PAssign();
virtual void dump(ostream&out, unsigned ind) const;
@@ -129,6 +135,7 @@ class PAssignNB : public PAssign_ {
public:
explicit PAssignNB(PExpr*lval, PExpr*ex);
explicit PAssignNB(PExpr*lval, PExpr*de, PExpr*ex);
explicit PAssignNB(PExpr*lval, PExpr*cnt, PEventStatement*de, PExpr*ex);
~PAssignNB();
virtual void dump(ostream&out, unsigned ind) const;
@@ -333,10 +340,15 @@ class PEventStatement : public Statement {
void set_statement(Statement*st);
virtual void dump(ostream&out, unsigned ind) const;
// Call this with a NULL statement only. It is used to print
// the event expression for inter-assignment event controls.
virtual void dump_inline(ostream&out) const;
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
virtual void elaborate_scope(Design*des, NetScope*scope) const;
virtual void elaborate_sig(Design*des, NetScope*scope) const;
bool has_aa_term(Design*des, NetScope*scope);
// This method is used to elaborate, but attach a previously
// elaborated statement to the event.
NetProc* elaborate_st(Design*des, NetScope*scope, NetProc*st) const;
@@ -348,6 +360,8 @@ class PEventStatement : public Statement {
Statement*statement_;
};
ostream& operator << (ostream&o, const PEventStatement&obj);
class PForce : public Statement {
public:
+30 -35
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2002-2004 Stephen Williams (steve@icarus.com)
* Copyright (c) 2002-2010 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,17 +16,16 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: StringHeap.cc,v 1.6 2004/02/18 17:11:54 steve Exp $"
#endif
# include "StringHeap.h"
#ifdef HAVE_MALLOC_H
# include <malloc.h>
# include <cstdlib>
# include <cstring>
# include <cassert>
#ifdef CHECK_WITH_VALGRIND
static char **string_pool = NULL;
static unsigned string_pool_count = 0;
#endif
# include <stdlib.h>
# include <string.h>
# include <assert.h>
StringHeap::StringHeap()
{
@@ -49,6 +48,12 @@ const char* StringHeap::add(const char*text)
unsigned rem = HEAPCELL - cell_ptr_;
if (rem < (len+1)) {
cell_base_ = (char*)malloc(HEAPCELL);
#ifdef CHECK_WITH_VALGRIND
string_pool_count += 1;
string_pool = (char **) realloc(string_pool,
string_pool_count*sizeof(char **));
string_pool[string_pool_count-1] = cell_base_;
#endif
cell_ptr_ = 0;
cell_count_ += 1;
assert(cell_base_ != 0);
@@ -83,6 +88,22 @@ StringHeapLex::~StringHeapLex()
{
}
void StringHeapLex::cleanup()
{
#ifdef CHECK_WITH_VALGRIND
for (unsigned idx = 0 ; idx < string_pool_count ; idx += 1) {
free(string_pool[idx]);
}
free(string_pool);
string_pool = NULL;
string_pool_count = 0;
for (unsigned idx = 0 ; idx < HASH_SIZE ; idx += 1) {
hash_table_[idx] = 0;
}
#endif
}
unsigned StringHeapLex::add_hit_count() const
{
return hit_count_;
@@ -178,29 +199,3 @@ bool operator < (perm_string a, perm_string b)
return false;
}
/*
* $Log: StringHeap.cc,v $
* Revision 1.6 2004/02/18 17:11:54 steve
* Use perm_strings for named langiage items.
*
* Revision 1.5 2003/03/01 06:25:30 steve
* Add the lex_strings string handler, and put
* scope names and system task/function names
* into this table. Also, permallocate event
* names from the beginning.
*
* Revision 1.4 2003/01/27 05:09:17 steve
* Spelling fixes.
*
* Revision 1.3 2003/01/16 21:44:46 steve
* Keep some debugging status.
*
* Revision 1.2 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.1 2002/08/04 19:13:16 steve
* dll uses StringHeap for named items.
*
*/
+3 -29
View File
@@ -1,7 +1,7 @@
#ifndef __StringHeap_H
#define __StringHeap_H
/*
* Copyright (c) 2002-2004 Stephen Williams (steve@icarus.com)
* Copyright (c) 2002-2009 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: StringHeap.h,v 1.6 2005/06/14 19:13:43 steve Exp $"
#endif
# include "config.h"
# include <string>
@@ -41,7 +38,7 @@ class perm_string {
operator const char* () const { return str(); }
// This is an escape for making perm_string objects out of
// literals. For example, per_string::literal("Label"); Please
// literals. For example, perm_string::literal("Label"); Please
// do *not* cheat and pass arbitrary const char* items here.
static perm_string literal(const char*t) { return perm_string(t); }
@@ -107,6 +104,7 @@ class StringHeapLex : private StringHeap {
unsigned add_count() const;
unsigned add_hit_count() const;
void cleanup();
private:
enum { HASH_SIZE = 4096 };
@@ -120,28 +118,4 @@ class StringHeapLex : private StringHeap {
StringHeapLex& operator= (const StringHeapLex&);
};
/*
* $Log: StringHeap.h,v $
* Revision 1.6 2005/06/14 19:13:43 steve
* gcc3/4 compile errors.
*
* Revision 1.5 2004/02/18 17:11:54 steve
* Use perm_strings for named langiage items.
*
* Revision 1.4 2003/03/01 06:25:30 steve
* Add the lex_strings string handler, and put
* scope names and system task/function names
* into this table. Also, permallocate event
* names from the beginning.
*
* Revision 1.3 2003/01/16 21:44:46 steve
* Keep some debugging status.
*
* Revision 1.2 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.1 2002/08/04 19:13:16 steve
* dll uses StringHeap for named items.
*
*/
#endif
-41
View File
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: _pli_types.h.in,v 1.8 2007/06/05 21:32:30 steve Exp $"
#endif
# undef HAVE_INTTYPES_H
@@ -88,42 +85,4 @@ typedef char PLI_BYTE8;
typedef unsigned char PLI_UBYTE8;
#endif
/*
* $Log: _pli_types.h.in,v $
* Revision 1.8 2007/06/05 21:32:30 steve
* More standard PLI_BYTE8.
*
* Revision 1.7 2003/11/12 02:38:44 steve
* Clean up manual definitions of PLI_UINT64_FMT.
*
* Revision 1.6 2003/11/08 20:06:21 steve
* Spelling fixes in comments.
*
* Revision 1.5 2003/10/29 03:28:27 steve
* Add the PLU_UINT64_FMT string for formatting output.
*
* Revision 1.4 2003/10/29 03:23:12 steve
* Portably handle time format of VCD prints.
*
* Revision 1.3 2003/10/02 21:30:06 steve
* Use configured TIME_FMT in vcd dump printf.
*
* Revision 1.2 2003/10/02 19:33:44 steve
* Put libraries in libdir64.
*
* Revision 1.1 2003/09/30 01:33:13 steve
* Add PLI_UINT64 to _pli_types.h.
*
* Revision 1.2 2003/05/26 04:39:16 steve
* Typo type name.
*
* Revision 1.1 2003/02/17 06:39:47 steve
* Add at least minimal implementations for several
* acc_ functions. Add support for standard ACC
* string handling.
*
* Add the _pli_types.h header file to carry the
* IEEE1364-2001 standard PLI type declarations.
*
*/
#endif
-81
View File
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: acc_user.h,v 1.20 2003/12/17 15:45:07 steve Exp $"
#endif
/*
* This header file contains the definitions and declarations needed
@@ -273,82 +270,4 @@ extern char* acc_version(void);
EXTERN_C_END
/*
* $Log: acc_user.h,v $
* Revision 1.20 2003/12/17 15:45:07 steve
* Add acc_set_scope function.
*
* Revision 1.19 2003/10/10 02:57:45 steve
* Some PLI1 stubs.
*
* Revision 1.18 2003/06/13 19:23:41 steve
* Add a bunch more PLI1 routines.
*
* Revision 1.17 2003/06/04 01:56:20 steve
* 1) Adds configure logic to clean up compiler warnings
* 2) adds acc_compare_handle, acc_fetch_range, acc_next_scope and
* tf_isetrealdelay, acc_handle_scope
* 3) makes acc_next reentrant
* 4) adds basic vpiWire type support
* 5) fills in some acc_object_of_type() and acc_fetch_{full}type()
* 6) add vpiLeftRange/RigthRange to signals
*
* Revision 1.16 2003/05/30 04:18:31 steve
* Add acc_next function.
*
* Revision 1.15 2003/05/29 02:35:41 steve
* acc_fetch_type supports module.
*
* Revision 1.14 2003/05/29 02:21:45 steve
* Implement acc_fetch_defname and its infrastructure in vvp.
*
* Revision 1.13 2003/05/24 03:02:04 steve
* Add implementation of acc_handle_by_name.
*
* Revision 1.12 2003/05/18 00:16:35 steve
* Add PLI_TRACE tracing of PLI1 modules.
*
* Add tf_isetdelay and friends, and add
* callback return values for acc_vcl support.
*
* Revision 1.11 2003/04/24 18:57:05 steve
* Add acc_fetch_fulltype function.
*
* Revision 1.10 2003/04/20 02:48:39 steve
* Support value change callbacks.
*
* Revision 1.9 2003/04/12 18:57:13 steve
* More acc_ function stubs.
*
* Revision 1.8 2003/03/13 04:35:09 steve
* Add a bunch of new acc_ and tf_ functions.
*
* Revision 1.7 2003/02/17 06:39:47 steve
* Add at least minimal implementations for several
* acc_ functions. Add support for standard ACC
* string handling.
*
* Add the _pli_types.h header file to carry the
* IEEE1364-2001 standard PLI type declarations.
*
* Revision 1.6 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.5 2002/06/11 15:19:12 steve
* Add acc_fetch_argc/argv/version (mruff)
*
* Revision 1.4 2002/06/07 02:58:58 steve
* Add a bunch of acc/tf functions. (mruff)
*
* Revision 1.3 2002/06/02 19:03:29 steve
* Add acc_handle_tfarg and acc_next_topmode
*
* Revision 1.2 2002/05/30 02:06:05 steve
* Implement acc_product_version.
*
* Revision 1.1 2002/05/23 03:46:42 steve
* Add the acc_user.h header file.
*
*/
#endif
Vendored
+84 -35
View File
@@ -1,29 +1,23 @@
# AX_CPP_IDENT
# ------------
# Check if the C compiler supports #ident
# Define and substitute ident_support if so.
#
# It would be simpler and more consistent with the rest of the autoconf
# structure to AC_DEFINE(HAVE_CPP_IDENT) instead of
# ident_support='-DHAVE_CVS_IDENT=1' and AC_SUBST(ident_support), but that
# change would require all C files in the icarus top level directory to
# put #include <config.h> before the #ifdef HAVE_CVS_IDENT (and change
# HAVE_CVS_IDENT to HAVE_CPP_IDENT). That would also remove all special
# ident_support handling from the Makefile. Manyana.
#
AC_DEFUN([AX_CPP_IDENT],
[AC_CACHE_CHECK([for ident support in C compiler], ax_cv_cpp_ident,
[AC_TRY_COMPILE([
#ident "$Id: aclocal.m4,v 1.7 2007/05/16 23:59:12 steve Exp $"
],[while (0) {}],
[AS_VAR_SET(ax_cv_cpp_ident, yes)],
[AS_VAR_SET(ax_cv_cpp_ident, no)])])
if test $ax_cv_cpp_ident = yes; then
ident_support='-DHAVE_CVS_IDENT=1'
fi
AC_SUBST(ident_support)
])# AC_CPP_IDENT
# AX_ENABLE_SUFFIX
# ----------------
# Create the configure option --enable-suffix[=suffix] to generate suffix
# strings for the installed commands. This allows for shared installs of
# different builds. Remember to change the default suffix string to some
# value appropriate for the current version.
AC_DEFUN([AX_ENABLE_SUFFIX],
[AC_ARG_ENABLE([suffix],[AC_HELP_STRING([--enable-suffix],
[Use/set the installation command suffix])],
[true],[enable_suffix=no])
if test X$enable_suffix = Xyes; then
install_suffix='-0.9'
elif test X$enable_suffix = Xno; then
install_suffix=''
else
install_suffix="$enable_suffix"
fi
AC_SUBST(install_suffix)
])# AX_ENABLE_SUFFIX
# _AX_C_UNDERSCORES_MATCH_IFELSE(PATTERN, ACTION-IF-MATCH, ACTION-IF-NOMATCH)
# ------------------------------
@@ -32,7 +26,7 @@ AC_SUBST(ident_support)
# - the object file produced by AC_COMPILE_IFELSE is called "conftest.$ac_objext"
# - the nm(1) utility is available, and its name is "nm".
AC_DEFUN([_AX_C_UNDERSCORES_MATCH_IF],
[AC_COMPILE_IFELSE([void underscore(void){}],
[AC_COMPILE_IFELSE([AC_LANG_SOURCE([void underscore(void){}])],
[AS_IF([nm conftest.$ac_objext|grep $1 >/dev/null 2>/dev/null],[$2],[$3])],
[AC_MSG_ERROR([underscore test crashed])]
)])
@@ -70,19 +64,24 @@ fi
# AX_WIN32
# --------
# Combined check for several flavors of Microsoft Windows so
# their "issues" can be dealt with
# their "issues" can be dealt with
AC_DEFUN([AX_WIN32],
[AC_CYGWIN
AC_MINGW32
WIN32=no
AC_MSG_CHECKING([for Microsoft Windows])
if test "$CYGWIN" = "yes" -o "$MINGW32" = "yes"
then
WIN32=yes
fi
[AC_MSG_CHECKING([for Microsoft Windows])
AC_REQUIRE([AC_CANONICAL_HOST]) []dnl
case $host_os in
*cygwin*) MINGW32=no; WIN32=yes;;
*mingw*) MINGW32=yes; WIN32=yes;;
*) MINGW32=no; WIN32=no;;
esac
AC_SUBST(MINGW32)
AC_SUBST(WIN32)
AC_MSG_RESULT($WIN32)
if test $WIN32 = yes; then
AC_MSG_CHECKING([for MinGW])
AC_MSG_RESULT($MINGW32)
fi
])# AX_WIN32
# AX_LD_EXTRALIBS
@@ -113,6 +112,10 @@ case "${host}" in
shared="-shared -Wl,--enable-auto-image-base"
;;
*-*-mingw*)
shared="-shared -Wl,--enable-auto-image-base"
;;
*-*-hpux*)
shared="-b"
;;
@@ -124,6 +127,13 @@ case "${host}" in
*-*-darwin*)
shared="-bundle -undefined suppress -flat_namespace"
;;
*-*-solaris*)
if test ${using_sunpro_c} = 1
then
shared="-G"
fi
;;
esac
AC_SUBST(shared)
AC_MSG_RESULT($shared)
@@ -142,10 +152,20 @@ case "${host}" in
PICFLAG=
;;
*-*-mingw*)
PICFLAG=
;;
*-*-hpux*)
PICFLAG=+z
;;
*-*-solaris*)
if test ${using_sunpro_c} = 1
then
PICFLAG=-G
fi
;;
esac
AC_SUBST(PICFLAG)
AC_MSG_RESULT($PICFLAG)
@@ -177,6 +197,10 @@ case "${host}" in
rdynamic=""
;;
*-*-mingw*)
rdynamic=""
;;
*-*-hpux*)
rdynamic="-E"
;;
@@ -205,3 +229,28 @@ case "${host}" in
;;
esac
])# AX_CPP_PRECOMP
# AX_C99_STRTOD
# -------------
AC_DEFUN([AX_C99_STRTOD],
[# On MinGW we need to jump through hoops to get a C99 compliant strtod().
case "${host}" in
*-*-mingw*)
LDFLAGS+=" -Wl,--undefined=___strtod,--wrap,strtod,--defsym,___wrap_strtod=___strtod"
;;
esac
])# AX_C99_STRTOD
# When config.status generates a header, we must update the stamp-h file.
# This file resides in the same directory as the config header
# that is generated. The stamp file name are based on the header name.
# Autoconf calls _AC_AM_CONFIG_HEADER_HOOK (when defined) in the
# loop where config.status creates the headers, so we can generate
# our stamp files there.
AC_DEFUN([_AC_AM_CONFIG_HEADER_HOOK],
[
_config_header=$1
_stamp_name=stamp-`expr //$_config_header : '.*/\([[^./]]*\)\.[[^./]]*$'`-h
echo "timestamp for $_config_header" > `AS_DIRNAME(["$_config_header"])`/[]$_stamp_name
]) #_AC_AM_CONFIG_HEADER_HOOK
+3 -32
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2002 Stephen Williams (steve@icarus.com)
* Copyright (c) 2002-2010 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,15 +16,12 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: async.cc,v 1.7 2004/01/18 23:26:54 steve Exp $"
#endif
# include "config.h"
# include "functor.h"
# include "netlist.h"
# include <assert.h>
# include <cassert>
bool NetAssign::is_asynchronous()
{
@@ -87,34 +84,8 @@ bool NetProc::is_asynchronous()
bool NetProcTop::is_asynchronous()
{
if (type_ == NetProcTop::KINITIAL)
if (type_ == IVL_PR_INITIAL)
return false;
return statement_->is_asynchronous();
}
/*
* $Log: async.cc,v $
* Revision 1.7 2004/01/18 23:26:54 steve
* The is_combinational function really need not recurse.
*
* Revision 1.6 2003/12/20 00:33:39 steve
* More thorough check that NetEvWait is asynchronous.
*
* Revision 1.5 2003/09/04 20:28:05 steve
* Support time0 resolution of combinational threads.
*
* Revision 1.4 2002/08/18 22:07:16 steve
* Detect temporaries in sequential block synthesis.
*
* Revision 1.3 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.2 2002/07/04 00:24:16 steve
* initial statements are not asynchronous.
*
* Revision 1.1 2002/06/30 02:21:31 steve
* Add structure for asynchronous logic synthesis.
*
*/
+1 -7
View File
@@ -9,11 +9,5 @@
echo "Autoconf in root..."
autoconf -f
for dir in vpip vpi vvp tgt-vvp tgt-fpga tgt-stub libveriuser cadpli
do
echo "Autoconf in $dir..."
( cd ./$dir ; autoconf -f --include=.. )
done
echo "Precompiling lexor_keyword.gperf"
gperf -o -i 7 -C -k 1-4,\$ -L ANSI-C -H keyword_hash -N check_identifier -t ./lexor_keyword.gperf > lexor_keyword.cc
gperf -o -i 7 -C -k 1-4,\$ -H keyword_hash -N check_identifier -t ./lexor_keyword.gperf > lexor_keyword.cc
-7
View File
@@ -1,7 +0,0 @@
Makefile
cadpli.vpl
dep
configure
config.log
config.status
autom4te.cache
+16 -15
View File
@@ -18,7 +18,7 @@
#
SHELL = /bin/sh
VERSION = 0.9.devel
suffix = @install_suffix@
prefix = @prefix@
exec_prefix = @exec_prefix@
@@ -30,19 +30,17 @@ bindir = @bindir@
libdir = @libdir@
includedir = $(prefix)/include
vpidir = @libdir@/ivl
vpidir = @libdir@/ivl$(suffix)
CC = @CC@
INSTALL = @INSTALL@
INSTALL_PROGRAM = @INSTALL_PROGRAM@
INSTALL_DATA = @INSTALL_DATA@
CPPFLAGS = @ident_support@ -I$(srcdir) -I$(srcdir)/.. -I.. @CPPFLAGS@ @DEFS@ @PICFLAG@
CFLAGS = -Wall @CFLAGS@
CPPFLAGS = -I$(srcdir) -I$(srcdir)/.. -I.. @CPPFLAGS@ @DEFS@ @PICFLAG@
CFLAGS = @WARNING_FLAGS@ @CFLAGS@
LDFLAGS = @LDFLAGS@
SHARED = @shared@
all:
all: dep cadpli.vpl $(ALL32)
@@ -54,35 +52,38 @@ dep:
mkdir dep
%.o: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) -MD -c $<
$(CC) $(CPPFLAGS) $(CFLAGS) @DEPENDENCY_FLAG@ -c $<
mv $*.d dep
O = cadpli.o
Makefile: $(srcdir)/Makefile.in ../config.status
cd ..; ./config.status --file=cadpli/$@
SYSTEM_VPI_LDFLAGS = -L../vvp -lvpi
ifeq (@MINGW32@,yes)
SYSTEM_VPI_LDFLAGS += @EXTRALIBS@
endif
cadpli.vpl: $O ../vvp/libvpi.a ../libveriuser/libveriuser.o
$(CC) @shared@ -o $@ $O ../libveriuser/libveriuser.o $(SYSTEM_VPI_LDFLAGS)
$(CC) @shared@ $(LDFLAGS) -o $@ $O ../libveriuser/libveriuser.o $(SYSTEM_VPI_LDFLAGS)
clean:
rm -rf *.o dep cadpli.vpl bin32
rm -rf *.o dep cadpli.vpl
distclean: clean
rm -f Makefile config.status config.log config.cache
rm -f Makefile config.log
install: all installdirs $(vpidir)/cadpli.vpl $(INSTALL32)
install: all installdirs $(vpidir)/cadpli.vpl
$(vpidir)/cadpli.vpl: ./cadpli.vpl
$(INSTALL_PROGRAM) ./cadpli.vpl $(vpidir)/cadpli.vpl
$(INSTALL_PROGRAM) ./cadpli.vpl "$(DESTDIR)$(vpidir)/cadpli.vpl"
installdirs: ../mkinstalldirs
$(srcdir)/../mkinstalldirs $(vpidir)
installdirs: $(srcdir)/../mkinstalldirs
$(srcdir)/../mkinstalldirs "$(DESTDIR)$(vpidir)"
uninstall: $(UNINSTALL32)
rm -f $(vpidir)/cadpli.vpl
rm -f "$(DESTDIR)$(vpidir)/cadpli.vpl"
uninstall32:
+2 -38
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2003 Stephen Williams (steve@icarus.com)
* Copyright (c) 2003-2010 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,18 +16,13 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: cadpli.c,v 1.7 2004/09/10 00:15:45 steve Exp $"
#endif
# include <vpi_user.h>
# include <veriuser.h>
# include <stdlib.h>
#ifdef HAVE_MALLOC_H
# include <malloc.h>
#endif
# include <string.h>
# include <assert.h>
# include "config.h"
# include "ivl_dlfcn.h"
typedef void* (*funcvp)(void);
@@ -87,34 +82,3 @@ void (*vlog_startup_routines[])() = {
thunker_register,
0
};
/*
* $Log: cadpli.c,v $
* Revision 1.7 2004/09/10 00:15:45 steve
* Remove bad casts.
*
* Revision 1.6 2004/09/05 21:19:51 steve
* Better type safety.
*
* Revision 1.5 2003/08/26 16:26:02 steve
* ifdef idents correctly.
*
* Revision 1.4 2003/04/30 01:28:06 steve
* Remove veriusertfs stuf.
*
* Revision 1.3 2003/02/22 04:04:38 steve
* Only include malloc.h if it is present.
*
* Revision 1.2 2003/02/17 00:01:25 steve
* Use a variant of ivl_dlfcn to do dynamic loading
* from within the cadpli module.
*
* Change the +cadpli flag to -cadpli, to keep the
* plusargs namespace clear.
*
* Revision 1.1 2003/02/16 02:23:54 steve
* Add the cadpli interface module.
*
*/
-13
View File
@@ -2,7 +2,6 @@
CADENCE PLI1 MODULES
Copyright 2003 Stephen Williams
$Id: cadpli.txt,v 1.2 2003/02/17 00:01:25 steve Exp $
With the cadpli module, Icarus Verilog is able to load PLI1
applications that were compiled and linked to be dynamic loaded by
@@ -34,15 +33,3 @@ the +loadpli1= argument to Verilog-XL.
The integration from this point is seamless. The PLI application
hardly knows that it is being invoked by Icarus Verilog instead of
Verilog-XL, so operates as it would otherwise.
$Log: cadpli.txt,v $
Revision 1.2 2003/02/17 00:01:25 steve
Use a variant of ivl_dlfcn to do dynamic loading
from within the cadpli module.
Change the +cadpli flag to -cadpli, to keep the
plusargs namespace clear.
Revision 1.1 2003/02/16 02:44:47 steve
Add the cadpli HOWTO.
-61
View File
@@ -1,61 +0,0 @@
AC_INIT(Makefile.in)
AC_PROG_CC
AC_PROG_CXX
AC_CHECK_TOOL(STRIP, strip, true)
AC_EXEEXT
AC_SUBST(EXEEXT)
# Combined check for Microsoft-related bogosities; sets WIN32 if found
AX_WIN32
AC_PROG_INSTALL
AC_CHECK_HEADERS(malloc.h)
AC_CHECK_SIZEOF(unsigned long long)
AC_CHECK_SIZEOF(unsigned long)
AC_CHECK_SIZEOF(unsigned)
# --
# Look for a dl library to use. First look for the standard dlopen
# functions, and failing that look for the HP specific shl_load function.
AC_CHECK_HEADERS(dlfcn.h dl.h, break)
DLLIB=''
AC_CHECK_LIB(dl,dlopen,[DLLIB=-ldl])
if test -z "$DLLIB" ; then
AC_CHECK_LIB(dld,shl_load,[DLLIB=-ldld])
fi
AC_SUBST(DLLIB)
AX_CPP_PRECOMP
# Compiler option for position independent code, needed when making shared objects.
AX_C_PICFLAG
# Linker option used when compiling the target
AX_LD_RDYNAMIC
# linker options when building a shared library
AX_LD_SHAREDLIB_OPTS
AX_LD_EXTRALIBS
#######################
## test for underscores. The vpi module loader in vvm needs to know this
## in order to know the name of the start symbol for the .vpi module.
#######################
AX_C_UNDERSCORES_LEADING
AX_C_UNDERSCORES_TRAILING
#######################
## end of test for underscores
#######################
AX_CPP_IDENT
AC_OUTPUT(Makefile)
+11 -30
View File
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: ivl_dlfcn.h,v 1.3 2004/10/04 01:10:56 steve Exp $"
#endif
#if defined(__MINGW32__)
# include <windows.h>
@@ -35,16 +32,16 @@ typedef shl_t ivl_dll_t;
#endif
#if defined(__MINGW32__)
static inline ivl_dll_t ivl_dlopen(const char *name)
static __inline__ ivl_dll_t ivl_dlopen(const char *name)
{ return (void *)LoadLibrary(name); }
static inline void *ivl_dlsym(ivl_dll_t dll, const char *nm)
static __inline__ void *ivl_dlsym(ivl_dll_t dll, const char *nm)
{ return (void *)GetProcAddress((HINSTANCE)dll,nm);}
static inline void ivl_dlclose(ivl_dll_t dll)
static __inline__ void ivl_dlclose(ivl_dll_t dll)
{ (void)FreeLibrary((HINSTANCE)dll);}
static inline const char *dlerror(void)
static __inline__ const char *dlerror(void)
{
static char msg[256];
unsigned long err = GetLastError();
@@ -61,10 +58,10 @@ static inline const char *dlerror(void)
}
#elif defined(HAVE_DLFCN_H)
static inline ivl_dll_t ivl_dlopen(const char*name)
static __inline__ ivl_dll_t ivl_dlopen(const char*name)
{ return dlopen(name,RTLD_LAZY); }
static inline void* ivl_dlsym(ivl_dll_t dll, const char*nm)
static __inline__ void* ivl_dlsym(ivl_dll_t dll, const char*nm)
{
void*sym = dlsym(dll, nm);
/* Not found? try without the leading _ */
@@ -73,41 +70,25 @@ static inline void* ivl_dlsym(ivl_dll_t dll, const char*nm)
return sym;
}
static inline void ivl_dlclose(ivl_dll_t dll)
static __inline__ void ivl_dlclose(ivl_dll_t dll)
{ dlclose(dll); }
#elif defined(HAVE_DL_H)
static inline ivl_dll_t ivl_dlopen(const char*name)
static __inline__ ivl_dll_t ivl_dlopen(const char*name)
{ return shl_load(name, BIND_IMMEDIATE, 0); }
static inline void* ivl_dlsym(ivl_dll_t dll, const char*nm)
static __inline__ void* ivl_dlsym(ivl_dll_t dll, const char*nm)
{
void*sym;
int rc = shl_findsym(&dll, nm, TYPE_PROCEDURE, &sym);
return (rc == 0) ? sym : 0;
}
static inline void ivl_dlclose(ivl_dll_t dll)
static __inline__ void ivl_dlclose(ivl_dll_t dll)
{ shl_unload(dll); }
static inline const char*dlerror(void)
static __inline__ const char*dlerror(void)
{ return strerror( errno ); }
#endif
/*
* $Log: ivl_dlfcn.h,v $
* Revision 1.3 2004/10/04 01:10:56 steve
* Clean up spurious trailing white space.
*
* Revision 1.2 2003/12/12 05:43:08 steve
* Some systems dlsym requires leading _ or not on whim.
*
* Revision 1.1 2003/02/17 00:01:25 steve
* Use a variant of ivl_dlfcn to do dynamic loading
* from within the cadpli module.
*
* Change the +cadpli flag to -cadpli, to keep the
* plusargs namespace clear.
*
*/
#endif
+33 -4
View File
@@ -1,7 +1,7 @@
#ifndef __compiler_H
#define __compiler_H
/*
* Copyright (c) 1999-2008 Stephen Williams (steve@icarus.com)
* Copyright (c) 1999-2009 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -36,6 +36,12 @@
*/
extern unsigned integer_width;
/*
* This is the maximum number of recursive module loops allowed within
* a generate block.
*/
extern unsigned recursive_mod_limit;
/* The TIME_WIDTH is the width of time variables. */
#ifndef TIME_WIDTH
# define TIME_WIDTH 64
@@ -76,18 +82,33 @@ extern bool warn_timescale;
/* Warn about legal but questionable module port bindings. */
extern bool warn_portbinding;
/* Warn about constant out of bound selects. */
extern bool warn_ob_select;
/* Warn about structures that may have infinite loops. */
extern bool warn_inf_loop;
/* Warn about always @* statements where a part or word select causes
sensitivity to an entire vector or array. */
extern bool warn_sens_entire_vec;
extern bool warn_sens_entire_arr;
/* This is true if verbose output is requested. */
extern bool verbose_flag;
extern bool debug_scopes;
extern bool debug_eval_tree;
extern bool debug_elaborate;
extern bool debug_elab_pexpr;
extern bool debug_synth2;
extern bool debug_optimizer;
/* Possibly temporary flag to control virtualization of pin arrays */
extern bool disable_virtual_pins;
/* Limit to size of devirtualized arrays */
extern unsigned long array_size_limit;
/* Path to a directory useful for finding subcomponents. */
extern const char*basedir;
@@ -100,9 +121,10 @@ extern int build_library_index(const char*path, bool key_case_sensitive);
specific language features. */
enum generation_t {
GN_VER1995 = 1,
GN_VER2001 = 2,
GN_VER2005 = 3,
GN_DEFAULT = 3
GN_VER2001_NOCONFIG = 2,
GN_VER2001 = 3,
GN_VER2005 = 4,
GN_DEFAULT = 4
};
extern generation_t generation_flag;
@@ -124,6 +146,11 @@ extern bool gn_verilog_ams_flag;
is scalar and the net/register definition is vectored. */
extern bool gn_io_range_error_flag;
/* If this flag is true, then force re-evaluation of user functions
in a continuous assignment when any part of the expression is
re-evaluated. */
extern bool gn_strict_ca_eval_flag;
/* The bits of these GN_KEYWORDS_* constants define non-intersecting
sets of keywords. The compiler enables groups of keywords by setting
lexor_keyword_mask with the OR of the bits for the keywords to be
@@ -133,6 +160,7 @@ enum { GN_KEYWORDS_1364_1995 = 0x0001,
GN_KEYWORDS_1364_2001_CONFIG = 0x0004,
GN_KEYWORDS_1364_2005 = 0x0008,
GN_KEYWORDS_VAMS_2_3 = 0x0010,
GN_KEYWORDS_1800_2005 = 0x0020,
GN_KEYWORDS_ICARUS = 0x8000
};
extern int lexor_keyword_mask;
@@ -182,5 +210,6 @@ struct sfunc_return_type {
extern const struct sfunc_return_type* lookup_sys_func(const char*name);
extern int load_sys_func_table(const char*path);
extern void cleanup_sys_func_table();
#endif
+581 -384
View File
File diff suppressed because it is too large Load Diff
+12 -44
View File
@@ -1,7 +1,7 @@
#ifndef __config_H /* -*- c++ -*- */
#define __config_H
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
* Copyright (c) 2001-2012 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: config.h.in,v 1.12 2007/02/02 04:33:00 steve Exp $"
#endif
#if defined(__cplusplus)
# if !defined(__GNUC__)
@@ -39,7 +36,6 @@
# undef HAVE_GETOPT_H
# undef HAVE_INTTYPES_H
# undef HAVE_LIBIBERTY_H
# undef HAVE_MALLOC_H
# undef HAVE_DLFCN_H
# undef HAVE_DL_H
# undef HAVE_FCHMOD
@@ -53,44 +49,16 @@
# include <inttypes.h>
#endif
/* These two are needed by the lxt and lxt2 files (copied from GTKWave). */
# undef HAVE_ALLOCA_H
# undef HAVE_FSEEKO
/* And this is needed by the fst files (copied from GTKWave). */
# undef HAVE_LIBPTHREAD
/*
* $Log: config.h.in,v $
* Revision 1.12 2007/02/02 04:33:00 steve
* Use inttypes.h instead of stdint.h for portability.
*
* Revision 1.11 2004/10/04 01:10:52 steve
* Clean up spurious trailing white space.
*
* Revision 1.10 2003/08/26 16:26:01 steve
* ifdef idents correctly.
*
* Revision 1.9 2003/07/03 16:29:55 steve
* spemm WORDS_BIGENDIAN correctly.
*
* Revision 1.8 2003/03/07 02:44:33 steve
* Implement $realtobits.
*
* Revision 1.7 2003/02/20 00:49:24 steve
* detect -lz and -lbz2 libraries.
*
* Revision 1.6 2003/01/10 19:01:04 steve
* Only use libiberty.h if available.
*
* Revision 1.5 2002/08/11 23:39:33 steve
* Remove VVM option.
*
* Revision 1.4 2002/02/16 03:18:53 steve
* Make vvm optional, normally off.
*
* Revision 1.3 2001/10/18 16:16:23 steve
* Include HAVE_SYS_WAIT in config.h (PR#306)
*
* Revision 1.2 2001/09/15 18:27:04 steve
* Make configure detect malloc.h
*
* Revision 1.1 2001/07/25 03:10:48 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Define this if you want to compile vvp with memory freeing and
* special valgrind hooks for the memory pools.
*/
#endif // __config_H
# undef CHECK_WITH_VALGRIND
#endif /* __config_H */
Vendored
+322 -93
View File
@@ -1,9 +1,10 @@
#! /bin/sh
# Configuration validation subroutine script.
# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
# 2000, 2001, 2002 Free Software Foundation, Inc.
# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
# Free Software Foundation, Inc.
timestamp='2002-07-03'
timestamp='2009-04-17'
# This file is (in principle) common to ALL GNU software.
# The presence of a machine in this file suggests that SOME GNU software
@@ -21,14 +22,15 @@ timestamp='2002-07-03'
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330,
# Boston, MA 02111-1307, USA.
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
# 02110-1301, USA.
#
# As a special exception to the GNU General Public License, if you
# distribute this file as part of a program that contains a
# configuration script generated by Autoconf, you may include it under
# the same distribution terms that you use for the rest of that program.
# Please send patches to <[email protected]>. Submit a context
# diff and a properly formatted ChangeLog entry.
#
@@ -70,8 +72,8 @@ Report bugs and patches to <[email protected]>."
version="\
GNU config.sub ($timestamp)
Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
Free Software Foundation, Inc.
Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."
@@ -83,11 +85,11 @@ Try \`$me --help' for more information."
while test $# -gt 0 ; do
case $1 in
--time-stamp | --time* | -t )
echo "$timestamp" ; exit 0 ;;
echo "$timestamp" ; exit ;;
--version | -v )
echo "$version" ; exit 0 ;;
echo "$version" ; exit ;;
--help | --h* | -h )
echo "$usage"; exit 0 ;;
echo "$usage"; exit ;;
-- ) # Stop option processing
shift; break ;;
- ) # Use stdin as input.
@@ -99,7 +101,7 @@ while test $# -gt 0 ; do
*local*)
# First pass through any local machine types.
echo $1
exit 0;;
exit ;;
* )
break ;;
@@ -118,7 +120,10 @@ esac
# Here we must recognize all the valid KERNEL-OS combinations.
maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'`
case $maybe_os in
nto-qnx* | linux-gnu* | freebsd*-gnu* | storm-chaos* | os2-emx* | windows32-* | rtmk-nova*)
nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | \
uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | \
kopensolaris*-gnu* | \
storm-chaos* | os2-emx* | rtmk-nova*)
os=-$maybe_os
basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'`
;;
@@ -144,7 +149,7 @@ case $os in
-convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\
-c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \
-harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \
-apple | -axis)
-apple | -axis | -knuth | -cray)
os=
basic_machine=$1
;;
@@ -169,6 +174,10 @@ case $os in
-hiux*)
os=-hiuxwe2
;;
-sco6)
os=-sco5v6
basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
;;
-sco5)
os=-sco3.2v5
basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
@@ -185,6 +194,10 @@ case $os in
# Don't forget version if it is 3.2v4 or newer.
basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
;;
-sco5v6*)
# Don't forget version if it is 3.2v4 or newer.
basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
;;
-sco*)
os=-sco3.2v2
basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
@@ -228,40 +241,57 @@ case $basic_machine in
| a29k \
| alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \
| alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \
| arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr \
| am33_2.0 \
| arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \
| bfin \
| c4x | clipper \
| d10v | d30v | dlx | dsp16xx \
| fr30 | frv \
| fido | fr30 | frv \
| h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \
| i370 | i860 | i960 | ia64 \
| ip2k \
| m32r | m68000 | m68k | m88k | mcore \
| ip2k | iq2000 \
| lm32 \
| m32c | m32r | m32rle | m68000 | m68k | m88k \
| maxq | mb | microblaze | mcore | mep | metag \
| mips | mipsbe | mipseb | mipsel | mipsle \
| mips16 \
| mips64 | mips64el \
| mips64octeon | mips64octeonel \
| mips64orion | mips64orionel \
| mips64r5900 | mips64r5900el \
| mips64vr | mips64vrel \
| mips64vr4100 | mips64vr4100el \
| mips64vr4300 | mips64vr4300el \
| mips64vr5000 | mips64vr5000el \
| mips64vr5900 | mips64vr5900el \
| mipsisa32 | mipsisa32el \
| mipsisa32r2 | mipsisa32r2el \
| mipsisa64 | mipsisa64el \
| mipsisa64r2 | mipsisa64r2el \
| mipsisa64sb1 | mipsisa64sb1el \
| mipsisa64sr71k | mipsisa64sr71kel \
| mipstx39 | mipstx39el \
| mn10200 | mn10300 \
| moxie \
| mt \
| msp430 \
| nios | nios2 \
| ns16k | ns32k \
| openrisc | or32 \
| or32 \
| pdp10 | pdp11 | pj | pjl \
| powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \
| pyramid \
| sh | sh[1234] | sh3e | sh[34]eb | shbe | shle | sh[1234]le | sh3ele \
| score \
| sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
| sh64 | sh64le \
| sparc | sparc64 | sparc86x | sparclet | sparclite | sparcv9 | sparcv9b \
| strongarm \
| tahoe | thumb | tic80 | tron \
| sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \
| sparcv8 | sparcv9 | sparcv9b | sparcv9v \
| spu | strongarm \
| tahoe | thumb | tic4x | tic80 | tron \
| v850 | v850e \
| we32k \
| x86 | xscale | xstormy16 | xtensa \
| z8k)
| x86 | xc16x | xscale | xscalee[bl] | xstormy16 | xtensa \
| z8k | z80)
basic_machine=$basic_machine-unknown
;;
m6811 | m68hc11 | m6812 | m68hc12)
@@ -271,6 +301,9 @@ case $basic_machine in
;;
m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | v70 | w65 | z8k)
;;
ms1)
basic_machine=mt-unknown
;;
# We use `pc' rather than `unknown'
# because (1) that's what they normally are, and
@@ -290,48 +323,67 @@ case $basic_machine in
| alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \
| alphapca5[67]-* | alpha64pca5[67]-* | arc-* \
| arm-* | armbe-* | armle-* | armeb-* | armv*-* \
| avr-* \
| bs2000-* \
| c[123]* | c30-* | [cjt]90-* | c54x-* \
| clipper-* | cydra-* \
| avr-* | avr32-* \
| bfin-* | bs2000-* \
| c[123]* | c30-* | [cjt]90-* | c4x-* | c54x-* | c55x-* | c6x-* \
| clipper-* | craynv-* | cydra-* \
| d10v-* | d30v-* | dlx-* \
| elxsi-* \
| f30[01]-* | f700-* | fr30-* | frv-* | fx80-* \
| f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \
| h8300-* | h8500-* \
| hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \
| i*86-* | i860-* | i960-* | ia64-* \
| ip2k-* \
| m32r-* \
| ip2k-* | iq2000-* \
| lm32-* \
| m32c-* | m32r-* | m32rle-* \
| m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \
| m88110-* | m88k-* | mcore-* \
| m88110-* | m88k-* | maxq-* | mcore-* | metag-* \
| mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \
| mips16-* \
| mips64-* | mips64el-* \
| mips64octeon-* | mips64octeonel-* \
| mips64orion-* | mips64orionel-* \
| mips64r5900-* | mips64r5900el-* \
| mips64vr-* | mips64vrel-* \
| mips64vr4100-* | mips64vr4100el-* \
| mips64vr4300-* | mips64vr4300el-* \
| mips64vr5000-* | mips64vr5000el-* \
| mips64vr5900-* | mips64vr5900el-* \
| mipsisa32-* | mipsisa32el-* \
| mipsisa32r2-* | mipsisa32r2el-* \
| mipsisa64-* | mipsisa64el-* \
| mipsisa64r2-* | mipsisa64r2el-* \
| mipsisa64sb1-* | mipsisa64sb1el-* \
| mipstx39 | mipstx39el \
| mipsisa64sr71k-* | mipsisa64sr71kel-* \
| mipstx39-* | mipstx39el-* \
| mmix-* \
| mt-* \
| msp430-* \
| nios-* | nios2-* \
| none-* | np1-* | ns16k-* | ns32k-* \
| orion-* \
| pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \
| powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \
| pyramid-* \
| romp-* | rs6000-* \
| sh-* | sh[1234]-* | sh3e-* | sh[34]eb-* | shbe-* \
| sh-* | sh[1234]-* | sh[24]a-* | sh[24]aeb-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \
| shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \
| sparc-* | sparc64-* | sparc86x-* | sparclet-* | sparclite-* \
| sparcv9-* | sparcv9b-* | strongarm-* | sv1-* | sx?-* \
| tahoe-* | thumb-* | tic30-* | tic54x-* | tic80-* | tron-* \
| sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \
| sparclite-* \
| sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | strongarm-* | sv1-* | sx?-* \
| tahoe-* | thumb-* \
| tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* | tile-* \
| tron-* \
| v850-* | v850e-* | vax-* \
| we32k-* \
| x86-* | x86_64-* | xps100-* | xscale-* | xstormy16-* \
| xtensa-* \
| x86-* | x86_64-* | xc16x-* | xps100-* | xscale-* | xscalee[bl]-* \
| xstormy16-* | xtensa*-* \
| ymp-* \
| z8k-*)
| z8k-* | z80-*)
;;
# Recognize the basic CPU types without company name, with glob match.
xtensa*)
basic_machine=$basic_machine-unknown
;;
# Recognize the various machine names and aliases which stand
# for a CPU type and a company and sometimes even an OS.
@@ -349,6 +401,9 @@ case $basic_machine in
basic_machine=a29k-amd
os=-udi
;;
abacus)
basic_machine=abacus-unknown
;;
adobe68k)
basic_machine=m68010-adobe
os=-scout
@@ -363,6 +418,12 @@ case $basic_machine in
basic_machine=a29k-none
os=-bsd
;;
amd64)
basic_machine=x86_64-pc
;;
amd64-*)
basic_machine=x86_64-`echo $basic_machine | sed 's/^[^-]*-//'`
;;
amdahl)
basic_machine=580-amdahl
os=-sysv
@@ -386,6 +447,10 @@ case $basic_machine in
basic_machine=m68k-apollo
os=-bsd
;;
aros)
basic_machine=i386-pc
os=-aros
;;
aux)
basic_machine=m68k-apple
os=-aux
@@ -394,10 +459,22 @@ case $basic_machine in
basic_machine=ns32k-sequent
os=-dynix
;;
blackfin)
basic_machine=bfin-unknown
os=-linux
;;
blackfin-*)
basic_machine=bfin-`echo $basic_machine | sed 's/^[^-]*-//'`
os=-linux
;;
c90)
basic_machine=c90-cray
os=-unicos
;;
cegcc)
basic_machine=arm-unknown
os=-cegcc
;;
convex-c1)
basic_machine=c1-convex
os=-bsd
@@ -422,12 +499,27 @@ case $basic_machine in
basic_machine=j90-cray
os=-unicos
;;
craynv)
basic_machine=craynv-cray
os=-unicosmp
;;
cr16)
basic_machine=cr16-unknown
os=-elf
;;
crds | unos)
basic_machine=m68k-crds
;;
crisv32 | crisv32-* | etraxfs*)
basic_machine=crisv32-axis
;;
cris | cris-* | etrax*)
basic_machine=cris-axis
;;
crx)
basic_machine=crx-unknown
os=-elf
;;
da30 | da30-*)
basic_machine=m68k-da30
;;
@@ -450,6 +542,14 @@ case $basic_machine in
basic_machine=m88k-motorola
os=-sysv3
;;
dicos)
basic_machine=i686-pc
os=-dicos
;;
djgpp)
basic_machine=i586-pc
os=-msdosdjgpp
;;
dpx20 | dpx20-*)
basic_machine=rs6000-bull
os=-bosx
@@ -600,6 +700,14 @@ case $basic_machine in
basic_machine=m68k-isi
os=-sysv
;;
m68knommu)
basic_machine=m68k-unknown
os=-linux
;;
m68knommu-*)
basic_machine=m68k-`echo $basic_machine | sed 's/^[^-]*-//'`
os=-linux
;;
m88k-omron*)
basic_machine=m88k-omron
;;
@@ -615,6 +723,10 @@ case $basic_machine in
basic_machine=i386-pc
os=-mingw32
;;
mingw32ce)
basic_machine=arm-unknown
os=-mingw32ce
;;
miniframe)
basic_machine=m68000-convergent
;;
@@ -628,10 +740,6 @@ case $basic_machine in
mips3*)
basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`-unknown
;;
mmix*)
basic_machine=mmix-knuth
os=-mmixware
;;
monitor)
basic_machine=m68k-rom68k
os=-coff
@@ -644,6 +752,9 @@ case $basic_machine in
basic_machine=i386-pc
os=-msdos
;;
ms1-*)
basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'`
;;
mvs)
basic_machine=i370-ibm
os=-mvs
@@ -719,9 +830,12 @@ case $basic_machine in
basic_machine=hppa1.1-oki
os=-proelf
;;
or32 | or32-*)
openrisc | openrisc-*)
basic_machine=or32-unknown
os=-coff
;;
os400)
basic_machine=powerpc-ibm
os=-os400
;;
OSE68000 | ose68000)
basic_machine=m68000-ericsson
@@ -739,55 +853,75 @@ case $basic_machine in
basic_machine=i860-intel
os=-osf
;;
parisc)
basic_machine=hppa-unknown
os=-linux
;;
parisc-*)
basic_machine=hppa-`echo $basic_machine | sed 's/^[^-]*-//'`
os=-linux
;;
pbd)
basic_machine=sparc-tti
;;
pbb)
basic_machine=m68k-tti
;;
pc532 | pc532-*)
pc532 | pc532-*)
basic_machine=ns32k-pc532
;;
pc98)
basic_machine=i386-pc
;;
pc98-*)
basic_machine=i386-`echo $basic_machine | sed 's/^[^-]*-//'`
;;
pentium | p5 | k5 | k6 | nexgen | viac3)
basic_machine=i586-pc
;;
pentiumpro | p6 | 6x86 | athlon)
pentiumpro | p6 | 6x86 | athlon | athlon_*)
basic_machine=i686-pc
;;
pentiumii | pentium2)
pentiumii | pentium2 | pentiumiii | pentium3)
basic_machine=i686-pc
;;
pentium4)
basic_machine=i786-pc
;;
pentium-* | p5-* | k5-* | k6-* | nexgen-* | viac3-*)
basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'`
;;
pentiumpro-* | p6-* | 6x86-* | athlon-*)
basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'`
;;
pentiumii-* | pentium2-*)
pentiumii-* | pentium2-* | pentiumiii-* | pentium3-*)
basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'`
;;
pentium4-*)
basic_machine=i786-`echo $basic_machine | sed 's/^[^-]*-//'`
;;
pn)
basic_machine=pn-gould
;;
power) basic_machine=power-ibm
;;
ppc) basic_machine=powerpc-unknown
;;
;;
ppc-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'`
;;
ppcle | powerpclittle | ppc-le | powerpc-little)
basic_machine=powerpcle-unknown
;;
;;
ppcle-* | powerpclittle-*)
basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'`
;;
ppc64) basic_machine=powerpc64-unknown
;;
;;
ppc64-*) basic_machine=powerpc64-`echo $basic_machine | sed 's/^[^-]*-//'`
;;
ppc64le | powerpc64little | ppc64-le | powerpc64-little)
basic_machine=powerpc64le-unknown
;;
;;
ppc64le-* | powerpc64little-*)
basic_machine=powerpc64le-`echo $basic_machine | sed 's/^[^-]*-//'`
;;
@@ -798,6 +932,10 @@ case $basic_machine in
basic_machine=i586-unknown
os=-pw32
;;
rdos)
basic_machine=i386-pc
os=-rdos
;;
rom68k)
basic_machine=m68k-rom68k
os=-coff
@@ -818,6 +956,20 @@ case $basic_machine in
basic_machine=a29k-amd
os=-udi
;;
sb1)
basic_machine=mipsisa64sb1-unknown
;;
sb1el)
basic_machine=mipsisa64sb1el-unknown
;;
sde)
basic_machine=mipsisa32-sde
os=-elf
;;
sei)
basic_machine=mips-sei
os=-seiux
;;
sequent)
basic_machine=i386-sequent
;;
@@ -825,6 +977,12 @@ case $basic_machine in
basic_machine=sh-hitachi
os=-hms
;;
sh5el)
basic_machine=sh5le-unknown
;;
sh64)
basic_machine=sh64-unknown
;;
sparclite-wrs | simso-wrs)
basic_machine=sparclite-wrs
os=-vxworks
@@ -883,7 +1041,7 @@ case $basic_machine in
sun386 | sun386i | roadrunner)
basic_machine=i386-sun
;;
sv1)
sv1)
basic_machine=sv1-cray
os=-unicos
;;
@@ -891,10 +1049,6 @@ case $basic_machine in
basic_machine=i386-sequent
os=-dynix
;;
t3d)
basic_machine=alpha-cray
os=-unicos
;;
t3e)
basic_machine=alphaev5-cray
os=-unicos
@@ -907,6 +1061,18 @@ case $basic_machine in
basic_machine=tic54x-unknown
os=-coff
;;
tic55x | c55x*)
basic_machine=tic55x-unknown
os=-coff
;;
tic6x | c6x*)
basic_machine=tic6x-unknown
os=-coff
;;
tile*)
basic_machine=tile-unknown
os=-linux-gnu
;;
tx39)
basic_machine=mipstx39-unknown
;;
@@ -920,6 +1086,10 @@ case $basic_machine in
tower | tower-32)
basic_machine=m68k-ncr
;;
tpf)
basic_machine=s390x-ibm
os=-tpf
;;
udi29k)
basic_machine=a29k-amd
os=-udi
@@ -941,8 +1111,8 @@ case $basic_machine in
os=-vms
;;
vpp*|vx|vx-*)
basic_machine=f301-fujitsu
;;
basic_machine=f301-fujitsu
;;
vxworks960)
basic_machine=i960-wrs
os=-vxworks
@@ -963,11 +1133,11 @@ case $basic_machine in
basic_machine=hppa1.1-winbond
os=-proelf
;;
windows32)
basic_machine=i386-pc
os=-windows32-msvcrt
xbox)
basic_machine=i686-pc
os=-mingw32
;;
xps | xps100)
xps | xps100)
basic_machine=xps100-honeywell
;;
ymp)
@@ -978,6 +1148,10 @@ case $basic_machine in
basic_machine=z8k-unknown
os=-sim
;;
z80-*-coff)
basic_machine=z80-unknown
os=-sim
;;
none)
basic_machine=none-none
os=-none
@@ -997,6 +1171,9 @@ case $basic_machine in
romp)
basic_machine=romp-ibm
;;
mmix)
basic_machine=mmix-knuth
;;
rs6000)
basic_machine=rs6000-ibm
;;
@@ -1013,16 +1190,13 @@ case $basic_machine in
we32k)
basic_machine=we32k-att
;;
sh3 | sh4 | sh3eb | sh4eb | sh[1234]le | sh3ele)
sh[1234] | sh[24]a | sh[24]aeb | sh[34]eb | sh[1234]le | sh[23]ele)
basic_machine=sh-unknown
;;
sh64)
basic_machine=sh64-unknown
;;
sparc | sparcv9 | sparcv9b)
sparc | sparcv8 | sparcv9 | sparcv9b | sparcv9v)
basic_machine=sparc-sun
;;
cydra)
cydra)
basic_machine=cydra-cydrome
;;
orion)
@@ -1037,10 +1211,6 @@ case $basic_machine in
pmac | pmac-mpw)
basic_machine=powerpc-apple
;;
c4x*)
basic_machine=c4x-none
os=-coff
;;
*-unknown)
# Make sure to match an already-canonicalized machine name.
;;
@@ -1092,22 +1262,28 @@ case $os in
-gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \
| -*vms* | -sco* | -esix* | -isc* | -aix* | -sunos | -sunos[34]*\
| -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \
| -kopensolaris* \
| -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \
| -aos* \
| -aos* | -aros* \
| -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \
| -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \
| -hiux* | -386bsd* | -netbsd* | -openbsd* | -freebsd* | -riscix* \
| -lynxos* | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \
| -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \
| -openbsd* | -solidbsd* \
| -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \
| -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \
| -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \
| -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \
| -chorusos* | -chorusrdb* \
| -chorusos* | -chorusrdb* | -cegcc* \
| -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \
| -mingw32* | -linux* | -uxpv* | -beos* | -mpeix* | -udk* \
| -interix* | -uwin* | -rhapsody* | -darwin* | -opened* \
| -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* \
| -uxpv* | -beos* | -mpeix* | -udk* \
| -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \
| -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \
| -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \
| -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \
| -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* | -powermax*)
| -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \
| -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \
| -skyos* | -haiku* | -rdos* | -toppers* | -drops*)
# Remember, each alternative MUST END IN *, to match a version number.
;;
-qnx*)
@@ -1119,16 +1295,24 @@ case $os in
;;
esac
;;
-nto-qnx*)
;;
-nto*)
os=-nto-qnx
os=`echo $os | sed -e 's|nto|nto-qnx|'`
;;
-sim | -es1800* | -hms* | -xray | -os68k* | -none* | -v88r* \
| -windows* | -osx | -abug | -netware* | -os9* | -beos* \
| -windows* | -osx | -abug | -netware* | -os9* | -beos* | -haiku* \
| -macos* | -mpw* | -magic* | -mmixware* | -mon960* | -lnews*)
;;
-mac*)
os=`echo $os | sed -e 's|mac|macos|'`
;;
-linux-dietlibc)
os=-linux-dietlibc
;;
-linux*)
os=`echo $os | sed -e 's|linux|linux-gnu|'`
;;
-sunos5*)
os=`echo $os | sed -e 's|sunos5|solaris2|'`
;;
@@ -1138,6 +1322,9 @@ case $os in
-opened*)
os=-openedition
;;
-os400*)
os=-os400
;;
-wince*)
os=-wince
;;
@@ -1159,6 +1346,9 @@ case $os in
-atheos*)
os=-atheos
;;
-syllable*)
os=-syllable
;;
-386bsd)
os=-bsd
;;
@@ -1169,7 +1359,7 @@ case $os in
os=-rtmk-nova
;;
-ns2 )
os=-nextstep2
os=-nextstep2
;;
-nsk*)
os=-nsk
@@ -1181,6 +1371,9 @@ case $os in
-sinix*)
os=-sysv4
;;
-tpf*)
os=-tpf
;;
-triton*)
os=-sysv3
;;
@@ -1208,8 +1401,20 @@ case $os in
-xenix)
os=-xenix
;;
-*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*)
os=-mint
-*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*)
os=-mint
;;
-aros*)
os=-aros
;;
-kaos*)
os=-kaos
;;
-zvmoe)
os=-zvmoe
;;
-dicos*)
os=-dicos
;;
-none)
;;
@@ -1233,6 +1438,12 @@ else
# system, and we'll never get to this point.
case $basic_machine in
score-*)
os=-elf
;;
spu-*)
os=-elf
;;
*-acorn)
os=-riscix1.2
;;
@@ -1242,11 +1453,14 @@ case $basic_machine in
arm*-semi)
os=-aout
;;
c4x-* | tic4x-*)
os=-coff
;;
# This must come before the *-dec entry.
pdp10-*)
os=-tops20
;;
pdp11-*)
pdp11-*)
os=-none
;;
*-dec | vax-*)
@@ -1267,6 +1481,9 @@ case $basic_machine in
m68*-cisco)
os=-aout
;;
mep-*)
os=-elf
;;
mips*-cisco)
os=-elf
;;
@@ -1285,9 +1502,15 @@ case $basic_machine in
*-be)
os=-beos
;;
*-haiku)
os=-haiku
;;
*-ibm)
os=-aix
;;
*-knuth)
os=-mmixware
;;
*-wec)
os=-proelf
;;
@@ -1339,19 +1562,19 @@ case $basic_machine in
*-next)
os=-nextstep3
;;
*-gould)
*-gould)
os=-sysv
;;
*-highlevel)
*-highlevel)
os=-bsd
;;
*-encore)
os=-bsd
;;
*-sgi)
*-sgi)
os=-irix
;;
*-siemens)
*-siemens)
os=-sysv4
;;
*-masscomp)
@@ -1420,9 +1643,15 @@ case $basic_machine in
-mvs* | -opened*)
vendor=ibm
;;
-os400*)
vendor=ibm
;;
-ptx*)
vendor=sequent
;;
-tpf*)
vendor=ibm
;;
-vxsim* | -vxworks* | -windiss*)
vendor=wrs
;;
@@ -1447,7 +1676,7 @@ case $basic_machine in
esac
echo $basic_machine$os
exit 0
exit
# Local variables:
# eval: (add-hook 'write-file-hooks 'time-stamp)
+172 -6
View File
@@ -2,12 +2,29 @@ dnl Process this file with autoconf to produce a configure script.
AC_INIT(netlist.h)
AC_CONFIG_HEADER(config.h)
AC_CONFIG_HEADER(_pli_types.h)
AC_CONFIG_HEADER(vvp/config.h)
AC_CONFIG_HEADER(vpi/vpi_config.h)
AC_CONFIG_HEADER(libveriuser/config.h)
AC_CONFIG_HEADER(tgt-vvp/vvp_config.h)
AC_CONFIG_HEADER(tgt-vhdl/vhdl_config.h)
AC_CANONICAL_HOST
dnl Checks for programs.
AC_PROG_CC
# AC_PROG_CC_C99 is only available in autoconf version 2.60 and later.
# If you must use an older version then comment out the following two
# lines, but be warned that there could be issues with finding the
# nan(), etc. functions. It is really best to upgrade to a supported
# version of autoconf.
AC_PREREQ([2.60])
AC_PROG_CC_C99
AC_PROG_CXX
AC_PROG_RANLIB
AC_CHECK_TOOL(LD, ld, true)
AC_CHECK_TOOL(AR, ar, true)
AC_CHECK_TOOL(DLLTOOL, dlltool, true)
AC_CHECK_TOOL(STRIP, strip, true)
AC_CHECK_TOOL(WINDRES, windres, true)
AC_CHECK_PROGS(XGPERF,gperf,none)
AC_CHECK_PROGS(MAN,man,none)
AC_CHECK_PROGS(PS2PDF,ps2pdf,none)
@@ -45,10 +62,56 @@ AC_SUBST(EXEEXT)
# Combined check for Microsoft-related bogosities; sets WIN32 if found
AX_WIN32
AC_LANG_CPLUSPLUS
# Check to see if we are using the Sun compiler. If so then configure
# some of the flags to match the Sun compiler syntax. This is also used
# in the aclocal.m4 file to configure the flags used to build and link
# dynamic libraries
AC_CHECK_DECL(__SUNPRO_C, using_sunpro_c=1, using_sunpro_c=0)
if test ${using_sunpro_c} = 1
then
AC_SUBST(DEPENDENCY_FLAG, [-xMMD])
AC_SUBST(WARNING_FLAGS, [""])
else
AC_SUBST(DEPENDENCY_FLAG, [-MD])
AC_SUBST(WARNING_FLAGS, ["-Wall -Wshadow"])
fi
AC_CHECK_HEADERS(getopt.h malloc.h inttypes.h libiberty.h iosfwd sys/wait.h)
AC_LANG(C++)
# Check that we are using either the GNU compilers or the Sun compilers
# but not a mixture of the two (not currently supported).
AC_CHECK_DECL(__SUNPRO_CC, using_sunpro_cc=1, using_sunpro_cc=0)
if test ${using_sunpro_c} = 1
then
if test ${using_sunpro_cc} = 0
then
echo "*** Error: No support for mixing GNU and Sun compilers. ***"
echo " Using Sun C compiler and GNU C++ compiler.."
exit 1
fi
else
if test ${using_sunpro_cc} = 1
then
echo "*** Error: No support for mixing GNU and Sun compilers. ***"
echo " Using GNU C compiler and Sun C++ compiler.."
exit 1
fi
fi
AC_CHECK_HEADERS(getopt.h inttypes.h libiberty.h iosfwd sys/wait.h)
AC_CHECK_SIZEOF(unsigned long long)
AC_CHECK_SIZEOF(unsigned long)
AC_CHECK_SIZEOF(unsigned)
# vvp uses these...
AC_CHECK_LIB(termcap, tputs)
AC_CHECK_LIB(readline, readline)
AC_CHECK_LIB(history, add_history)
AC_CHECK_HEADERS(readline/readline.h readline/history.h sys/resource.h)
case "${host}" in *linux*) AC_DEFINE([LINUX], [1], [Host operating system is Linux.]) ;; esac
# vpi uses these
AC_CHECK_LIB(z, gzwrite)
AC_CHECK_LIB(z, gzwrite, HAVE_LIBZ=yes, HAVE_LIBZ=no)
AC_SUBST(HAVE_LIBZ)
@@ -61,6 +124,23 @@ AC_CHECK_LIB(bz2, BZ2_bzdopen, HAVE_LIBBZ2=yes, HAVE_LIBBZ2=no)
fi
AC_SUBST(HAVE_LIBBZ2)
# The lxt/lxt2 files from GTKWave use these...
AC_FUNC_ALLOCA
AC_FUNC_FSEEKO
# valgrind checks
AC_ARG_WITH([valgrind], [AC_HELP_STRING([--with-valgrind],
[Add valgrind hooks])],
[], [check_valgrind=yes])
AS_IF([test "x$check_valgrind" = xyes],
[AC_MSG_NOTICE([Not using valgrind hooks])],
[AC_CHECK_HEADER([valgrind/memcheck.h],
[AC_DEFINE([CHECK_WITH_VALGRIND], [1],
[Define to one to use the valgrind hooks])],
[AC_MSG_ERROR([Could not find <valgrind/memcheck.h>])])])
AC_MSG_CHECKING(for sys/times)
AC_TRY_LINK(
#include <unistd.h>
@@ -87,11 +167,13 @@ AC_SUBST(DLLIB)
AC_PROG_INSTALL
AC_LANG_C
AC_LANG(C)
AC_C_BIGENDIAN
# $host
AX_ENABLE_SUFFIX
AX_LD_EXTRALIBS
# Compiler option for position independent code, needed when making shared objects.
@@ -101,6 +183,68 @@ AX_C_PICFLAG
# may modify CPPFLAGS and CFLAGS
AX_CPP_PRECOMP
# may modify LDFLAGS
AX_C99_STRTOD
# Processor specific compile flags
case "${host}" in
alpha*-*-linux*)
CPPFLAGS="-mieee $CPPFLAGS"
CFLAGS="-mieee $CFLAGS"
;;
esac
# Do some more operating system specific setup. We put the file64_support
# define in a substitution instead of simply a define because there
# are source files (namely lxt support files) that don't include any
# config.h header file.
file64_support=''
case "${host}" in
*-*-linux*)
AC_DEFINE([_LARGEFILE_SOURCE], [1], [Indicates LFS (i.e. the ability to create files larger than 2 GiB on 32-bit operating systems).])
file64_support='-D_LARGEFILE_SOURCE=1 -D_FILE_OFFSET_BITS=64'
;;
esac
AC_SUBST(file64_support)
# Check that these functions exist. They are mostly C99
# functions that older compilers may not yet support.
AC_CHECK_FUNCS(fopen64)
# The following math functions may be defined in the math library so look
# in the default libraries first and then look in -lm for them. On some
# systems we may need to use the compiler in C99 mode to get a definition.
# We requested C99 mode earlier with AC_PROG_CC_C99.
AC_SEARCH_LIBS([lround], [m], [AC_DEFINE([HAVE_LROUND], [1])])
AC_SEARCH_LIBS([llround], [m], [AC_DEFINE([HAVE_LLROUND], [1])])
AC_SEARCH_LIBS([nan], [m], [AC_DEFINE([HAVE_NAN], [1])])
AC_SEARCH_LIBS([fmin], [m], [AC_DEFINE([HAVE_FMIN], [1])])
AC_SEARCH_LIBS([fmax], [m], [AC_DEFINE([HAVE_FMAX], [1])])
# Check to see if an unsigned long and uint64_t are the same from
# a compiler perspective. We can not just check that they are the
# same size since unsigned long and unsigned long long are not the
# same from an overloading perspective even though they could be
# the same size on some 64 bit machines. The result from this test
# is only used if inttypes.h is available, so if the test fails for
# that reason we don't care.
AC_LANG(C++)
AC_MSG_CHECKING(if uint64_t and unsigned long are identical)
AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[#include "inttypes.h"
static bool check(unsigned long val)
{
return val != 0;
}
static bool check(uint64_t val)
{
return val != 0;
}]], [[unsigned long ulval = 1;
bool result = check(ulval);
uint64_t uival = 1;
result &= check(uival);
return !result;]])],
[AC_MSG_RESULT(no)],
[AC_DEFINE([UINT64_T_AND_ULONG_SAME], [1]) AC_MSG_RESULT(yes)])
# Linker option used when compiling the target
AX_LD_RDYNAMIC
@@ -119,9 +263,31 @@ AX_C_UNDERSCORES_TRAILING
## end of test for underscores
#######################
AX_CPP_IDENT
#######################
# Sanity check the configured results
#######################
AC_MSG_CHECKING(for sanity of prefix)
if test `echo "$prefix" | wc -w` != 1
then
AC_MSG_ERROR(cannot configure white space in prefix: $prefix)
fi
AC_MSG_RESULT(ok)
AC_MSG_CHECKING(for sanity of exec_prefix)
if test `echo "$exec_prefix" | wc -w` != 1
then
AC_MSG_ERROR(cannot configure white space in exec_prefix: $exec_prefix)
fi
AC_MSG_RESULT(ok)
AC_MSG_CHECKING(for sanity of libdir)
if test `echo "$libdir" | wc -w` != 1
then
AC_MSG_ERROR(cannot configure white space in libdir: $libdir)
fi
AC_MSG_RESULT(ok)
# XXX disable tgt-fpga for the moment
AC_CONFIG_SUBDIRS(vvp vpi tgt-stub tgt-null tgt-vvp libveriuser cadpli)
AC_OUTPUT(Makefile ivlpp/Makefile driver/Makefile driver-vpi/Makefile tgt-null/Makefile tgt-verilog/Makefile tgt-pal/Makefile)
AC_OUTPUT(Makefile ivlpp/Makefile vvp/Makefile vpi/Makefile driver/Makefile driver-vpi/Makefile cadpli/Makefile libveriuser/Makefile tgt-null/Makefile tgt-stub/Makefile tgt-vvp/Makefile tgt-vhdl/Makefile tgt-fpga/Makefile tgt-verilog/Makefile tgt-pal/Makefile)
+1 -1
View File
@@ -3,7 +3,7 @@
`ifdef CONSTANTS_VAMS
`else
`define CONSTANTS_VAMS 1
// M_ is a mathematical constant
`define M_E 2.7182818284590452354
`define M_LOG2E 1.4426950408889634074
+28 -34
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1998-2005 Stephen Williams (steve@icarus.com)
* Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -739,7 +739,8 @@ v }
}
}
static void replace_with_bufif(Design*des, NetMux*obj, NetLogic::TYPE type)
#if 0
static void replace_with_mos(Design*des, NetMux*obj, NetLogic::TYPE type)
{
NetScope*scope = obj->scope();
NetLogic*tmp = new NetLogic(obj->scope(),
@@ -749,7 +750,7 @@ static void replace_with_bufif(Design*des, NetMux*obj, NetLogic::TYPE type)
des->add_node(tmp);
connect(obj->pin_Result(), tmp->pin(0));
connect(obj->pin_Data(type==NetLogic::BUFIF0? 0 : 1), tmp->pin(1));
connect(obj->pin_Data(type==NetLogic::PMOS? 0 : 1), tmp->pin(1));
if (obj->width() == 1) {
/* Special case that the expression is 1 bit
@@ -780,10 +781,11 @@ static void replace_with_bufif(Design*des, NetMux*obj, NetLogic::TYPE type)
delete obj;
}
#endif
/*
* This detects the case where the mux selects between a value and
* Vz. In this case, replace the device with a bufif with the sel
* Vz. In this case, replace the device with a mos with the sel
* input used to enable the output.
*/
void cprop_functor::lpm_mux(Design*des, NetMux*obj)
@@ -793,45 +795,38 @@ void cprop_functor::lpm_mux(Design*des, NetMux*obj)
if (obj->sel_width() != 1)
return;
#if 0
/*
* This is slower than the actual MUXZ so we are skipping this for now.
* If we had a half mux functor this could be faster and more compact
* so I'm leaving the code for future reference.
*/
/* If the first input is all constant Vz, then replace the
NetMux with an array of BUFIF1 devices, with the enable
NetMux with an array of NMOS devices, with the enable
connected to the select input. */
bool flag = true;
if (! obj->pin_Data(0).nexus()->drivers_constant()) {
flag = false;
}
if (flag && obj->pin_Data(0).nexus()->driven_value() != verinum::Vz) {
flag = false;
}
if (flag) {
replace_with_bufif(des, obj, NetLogic::BUFIF1);
if (obj->pin_Data(0).nexus()->drivers_constant() &&
obj->pin_Data(0).nexus()->driven_value() == verinum::Vz) {
replace_with_mos(des, obj, NetLogic::NMOS);
count += 1;
return;
}
/* If instead the second input is all constant Vz, replace the
NetMux with an array of BUFIF0 devices. */
flag = true;
if (! obj->pin_Data(1).nexus()->drivers_constant()) {
flag = false;
}
if (flag && obj->pin_Data(1).nexus()->driven_value() != verinum::Vz) {
flag = false;
}
if (flag) {
replace_with_bufif(des, obj, NetLogic::BUFIF0);
NetMux with an array of PMOS devices. */
if (obj->pin_Data(1).nexus()->drivers_constant() &&
obj->pin_Data(1).nexus()->driven_value() == verinum::Vz) {
replace_with_mos(des, obj, NetLogic::PMOS);
count += 1;
return;
}
#endif
/* If the select input is constant, then replace with a BUFZ */
flag = obj->pin_Sel().nexus()->drivers_constant();
bool flag = obj->pin_Sel().nexus()->drivers_constant();
/* Note that this cannot be constant if there are assignments
to this nexus. (Assignments include "force" to nets.) */
flag &= !obj->pin_Sel().nexus()->assign_lval();
verinum::V sel_val = flag? obj->pin_Sel().nexus()->driven_value() : verinum::Vx;
if ((sel_val != verinum::Vz) && (sel_val != verinum::Vx)) {
NetBUFZ*tmp = new NetBUFZ(obj->scope(), obj->name(), obj->width());
@@ -897,7 +892,7 @@ void cprop_dc_functor::lpm_const(Design*des, NetConst*obj)
for (Link*clnk = nex->first_nlink()
; clnk ; clnk = clnk->next_nlink()) {
NetObj*cur;
NetPins*cur;
unsigned pin;
clnk->cur_link(cur, pin);
@@ -923,7 +918,7 @@ void cprop_dc_functor::lpm_const(Design*des, NetConst*obj)
for (Link*clnk = nex->first_nlink()
; clnk ; clnk = clnk->next_nlink()) {
NetObj*cur;
NetPins*cur;
unsigned pin;
clnk->cur_link(cur, pin);
@@ -974,4 +969,3 @@ void cprop(Design*des)
cprop_dc_functor dc;
des->functor(&dc);
}
+181 -47
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com)
* Copyright (c) 1998-2010 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -27,6 +27,7 @@
# include <iomanip>
# include "netlist.h"
# include "compiler.h"
# include "discipline.h"
# include "ivl_assert.h"
static ostream& operator<< (ostream&o, NetBlock::Type t)
@@ -118,7 +119,8 @@ ostream& operator << (ostream&o, ivl_switch_type_t val)
static inline void dump_scope_path(ostream&o, const NetScope*scope)
{
if (const NetScope*parent = scope->parent()) {
const NetScope*parent = scope->parent();
if (parent) {
dump_scope_path(o, parent);
o << ".";
}
@@ -135,6 +137,17 @@ ostream& operator <<(ostream&o, struct __ScopePathManip marg)
return o;
}
void NetBranch::dump(ostream&o, unsigned ind) const
{
static const char*pin_names[2] = {
"terminal0",
"terminal1" };
o << setw(ind) << "" << "branch island=" << get_island();
o << " // " << get_fileline() << endl;
dump_node_pins(o, ind+4, pin_names);
}
void NetDelaySrc::dump(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "specify delay";
@@ -187,19 +200,30 @@ void NetNet::dump_net(ostream&o, unsigned ind) const
o << " inout";
break;
}
if (ivl_discipline_t dis = get_discipline())
o << " discipline=" << dis->name();
o << " (eref=" << peek_eref() << ", lref=" << peek_lref() << ")";
if (scope())
o << " scope=" << scope_path(scope());
o << " #(" << rise_time() << "," << fall_time() << ","
<< decay_time() << ") vector_width=" << vector_width()
<< " pin_count=" << pin_count()
<< " init=";
<< " pin_count=" << pin_count();
if (pins_are_virtual()) {
o << " pins_are_virtual" << endl;
return;
}
o << " init=";
for (unsigned idx = pin_count() ; idx > 0 ; idx -= 1)
o << pin(idx-1).get_init();
o << " (";
for (unsigned idx = pin_count() ; idx > 0 ; idx -= 1)
o << pin(idx-1).nexus()->get_init();
if (const Nexus*tmp = pin(idx-1).nexus())
o << tmp->get_init();
else
o << ".";
o << ")" << endl;
for (unsigned idx = 0 ; idx < pin_count() ; idx += 1) {
@@ -236,11 +260,14 @@ void NetNode::dump_node(ostream&o, unsigned ind) const
/* This is the generic dumping of all the signals connected to each
pin of the object. The "this" object is not printed, only the
signals connected to this. */
void NetObj::dump_node_pins(ostream&o, unsigned ind) const
void NetPins::dump_node_pins(ostream&o, unsigned ind, const char**pin_names) const
{
for (unsigned idx = 0 ; idx < pin_count() ; idx += 1) {
o << setw(ind) << "" << idx << " " << pin(idx).get_name()
<< "<" << pin(idx).get_inst() << ">";
o << setw(ind) << "" << idx;
if (pin_names && pin_names[idx])
o << " " << pin_names[idx];
else
o << " pin" << idx;
switch (pin(idx).get_dir()) {
case Link::PASSIVE:
@@ -289,7 +316,14 @@ void NetAddSub::dump_node(ostream&o, unsigned ind) const
o << setw(ind) << "" << "Adder (NetAddSub): " << name()
<< " width=" << width() << " pin_count=" << pin_count()
<< endl;
dump_node_pins(o, ind+4);
static const char* pin_names[] = {
"Cout ",
"DataA ",
"DataB ",
"Result"
};
dump_node_pins(o, ind+4, pin_names);
dump_obj_attr(o, ind+4);
}
@@ -302,6 +336,22 @@ void NetArrayDq::dump_node(ostream&o, unsigned ind) const
dump_obj_attr(o, ind+4);
}
void NetCastInt::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "Cast to int. (NetCastInt): " <<
name() << " width=" << width() << endl;
dump_node_pins(o, ind+4);
dump_obj_attr(o, ind+4);
}
void NetCastReal::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "Cast to real (NetCastReal): " <<
name() << endl;
dump_node_pins(o, ind+4);
dump_obj_attr(o, ind+4);
}
void NetCLShift::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "Combinatorial shift (NetCLShift): " <<
@@ -312,7 +362,9 @@ void NetCLShift::dump_node(ostream&o, unsigned ind) const
void NetCompare::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "LPM_COMPARE (NetCompare): " << name() << endl;
o << setw(ind) << "" << "LPM_COMPARE (NetCompare "
<< (get_signed()? "signed" : "unsigned") << "): "
<< name() << endl;
dump_node_pins(o, ind+4);
dump_obj_attr(o, ind+4);
}
@@ -546,8 +598,14 @@ void NetReplicate::dump_node(ostream&o, unsigned ind) const
void NetSignExtend::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "NetSignExtend: "
<< name() << " output width=" << width_ << endl;
o << setw(ind) << "" << "NetSignExtend: " << name();
if (rise_time())
o << " #(" << *rise_time()
<< "," << *fall_time()
<< "," << *decay_time() << ")";
else
o << " #(.,.,.)";
o << " output width=" << width_ << endl;
dump_node_pins(o, ind+4);
dump_obj_attr(o, ind+4);
}
@@ -639,7 +697,7 @@ void NetTaskDef::dump(ostream&o, unsigned ind) const
void NetTran::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << type_ << " " << name()
<< " island " << island;
<< " island " << get_island();
if (type_ == IVL_SW_TRAN_VP) {
o << " width=" << vector_width()
<< " part=" << part_width()
@@ -663,11 +721,11 @@ void NetUDP::dump_node(ostream&o, unsigned ind) const
void NetProcTop::dump(ostream&o, unsigned ind) const
{
switch (type_) {
case NetProcTop::KINITIAL:
case IVL_PR_INITIAL:
o << "initial /* " << get_fileline() << " in "
<< scope_path(scope_) << " */" << endl;
break;
case NetProcTop::KALWAYS:
case IVL_PR_ALWAYS:
o << "always /* " << get_fileline() << " in "
<< scope_path(scope_) << " */" << endl;
break;
@@ -681,6 +739,28 @@ void NetProcTop::dump(ostream&o, unsigned ind) const
statement_->dump(o, ind+2);
}
void NetAnalogTop::dump(ostream&o, unsigned ind) const
{
switch (type_) {
case IVL_PR_INITIAL:
o << "analog initial /* " << get_fileline() << " in "
<< scope_path(scope_) << " */" << endl;
break;
case IVL_PR_ALWAYS:
o << "analog /* " << get_fileline() << " in "
<< scope_path(scope_) << " */" << endl;
break;
}
statement_->dump(o, ind+2);
}
void NetAlloc::dump(ostream&o, unsigned ind) const
{
o << setw(ind) << "// allocate storage : " << scope_path(scope_) << endl;
}
void NetAssign_::dump_lval(ostream&o) const
{
if (sig_) {
@@ -732,6 +812,11 @@ void NetAssignNB::dump(ostream&o, unsigned ind) const
if (const NetExpr*de = get_delay())
o << "#(" << *de << ") ";
if (count_)
o << "repeat(" << *count_ << ") ";
if (event_) {
o << *event_;
}
o << *rval() << ";" << endl;
@@ -819,6 +904,15 @@ void NetCondit::dump(ostream&o, unsigned ind) const
}
}
void NetContribution::dump(ostream&o, unsigned ind) const
{
o << setw(ind) << "";
lval_->dump(o);
o << " <+ ";
rval_->dump(o);
o << ";" << endl;
}
void NetDeassign::dump(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "deassign ";
@@ -847,7 +941,7 @@ void NetEvProbe::dump_node(ostream&o, unsigned ind) const
o << "negedge ";
break;
}
o << setw(ind) << "" << "-> " << event_->name() << "; " << endl;
o << setw(ind) << "" << "-> " << scope_path(event_->scope()) << "." << event_->name() << "; " << endl;
dump_node_pins(o, ind+4);
dump_obj_attr(o, ind+4);
}
@@ -863,10 +957,10 @@ void NetEvWait::dump(ostream&o, unsigned ind) const
o << setw(ind) <<"" << "@(";
if (nevents() > 0)
o << event(0)->name();
o << scope_path(event(0)->scope()) << "." << event(0)->name();
for (unsigned idx = 1 ; idx < nevents() ; idx += 1)
o << " or " << event(idx)->name();
o << " or " << scope_path(event(idx)->scope()) << "." << event(idx)->name();
o << ") // " << get_fileline() << endl;
@@ -876,6 +970,25 @@ void NetEvWait::dump(ostream&o, unsigned ind) const
o << setw(ind+2) << "" << "/* noop */ ;" << endl;
}
ostream& operator << (ostream&out, const NetEvWait&obj)
{
obj.dump_inline(out);
return out;
}
void NetEvWait::dump_inline(ostream&o) const
{
o << "@(";
if (nevents() > 0)
o << scope_path(event(0)->scope()) << "." << event(0)->name();
for (unsigned idx = 1 ; idx < nevents() ; idx += 1)
o << " or " << scope_path(event(idx)->scope())<<"."<<event(idx)->name();
o << ") ";
}
void NetForce::dump(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "force ";
@@ -889,6 +1002,11 @@ void NetForever::dump(ostream&o, unsigned ind) const
statement_->dump(o, ind+2);
}
void NetFree::dump(ostream&o, unsigned ind) const
{
o << setw(ind) << "// free storage : " << scope_path(scope_) << endl;
}
void NetFuncDef::dump(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "function definition for " << scope_path(scope_) << endl;
@@ -960,28 +1078,11 @@ void NetRepeat::dump(ostream&o, unsigned ind) const
void NetScope::dump(ostream&o) const
{
/* This is a constructed hierarchical name. */
o << scope_path(this);
o << scope_path(this) << " ";
switch (type_) {
case BEGIN_END:
o << " sequential block";
break;
case FORK_JOIN:
o << " parallel block";
break;
case FUNC:
o << " function";
break;
case MODULE:
o << " module <" << (module_name_? module_name_.str() : "") << ">";
break;
case TASK:
o << " task";
break;
case GENBLOCK:
o << " generate block";
break;
}
print_type(o);
if (is_auto()) o << " (automatic)";
if (is_cell()) o << " (cell)";
o << endl;
for (unsigned idx = 0 ; idx < attr_cnt() ; idx += 1)
@@ -998,6 +1099,8 @@ void NetScope::dump(ostream&o) const
; pp != parameters.end() ; pp ++) {
o << " parameter ";
o << pp->second.type << " ";
if ((*pp).second.signed_flag)
o << "signed ";
@@ -1005,7 +1108,11 @@ void NetScope::dump(ostream&o) const
o << "[" << *(*pp).second.msb
<< ":" << *(*pp).second.lsb << "] ";
o << (*pp).first << " = " << *(*pp).second.expr;
o << (*pp).first << " = ";
if (pp->second.expr)
o << *(*pp).second.expr;
else
o << "<nil>";
for (range_t*ran = (*pp).second.range ; ran ; ran = ran->next) {
if (ran->exclude_flag)
@@ -1047,7 +1154,7 @@ void NetScope::dump(ostream&o) const
/* Dump the saved defparam assignments here. */
{
map<pform_name_t,NetExpr*>::const_iterator pp;
list<pair<pform_name_t,NetExpr*> >::const_iterator pp;
for (pp = defparams.begin()
; pp != defparams.end() ; pp ++ ) {
o << " defparam " << (*pp).first << " = " <<
@@ -1055,6 +1162,15 @@ void NetScope::dump(ostream&o) const
}
}
{
list<pair<list<hname_t>,NetExpr*> >::const_iterator pp;
for (pp = defparams_later.begin()
; pp != defparams_later.end() ; pp ++ ) {
o << " defparam(later) " << pp->first << " = " <<
*(pp->second) << ";" << endl;
}
}
/* Dump the events in this scope. */
for (NetEvent*cur = events_ ; cur ; cur = cur->snext_) {
o << " event " << cur->name() << "; nprobe="
@@ -1063,12 +1179,9 @@ void NetScope::dump(ostream&o) const
}
// Dump the signals,
if (signals_) {
NetNet*cur = signals_->sig_next_;
do {
cur->dump_net(o, 4);
cur = cur->sig_next_;
} while (cur != signals_->sig_next_);
for (signals_map_iter_t cur = signals_map_.begin()
; cur != signals_map_.end() ; cur ++) {
cur->second->dump_net(o, 4);
}
// Dump specparams
@@ -1157,6 +1270,18 @@ void NetExpr::dump(ostream&o) const
o << "(?" << typeid(*this).name() << "?)";
}
void NetEAccess::dump(ostream&o) const
{
o << nature_->name() << "." << nature_->access() << "(";
assert(branch_);
if (branch_->pin(0).is_linked())
o << branch_->pin(0).nexus()->name();
o << ", ";
if (branch_->pin(1).is_linked())
o << branch_->pin(1).nexus()->name();
o << ")";
}
void NetEBinary::dump(ostream&o) const
{
if (op_ == 'm' || op_ == 'M') {
@@ -1391,10 +1516,19 @@ void Design::dump(ostream&o) const
} while (cur != nodes_->node_next_);
}
o << "ELABORATED BRANCHES:" << endl;
if (branches_) {
for (NetBranch*cur = branches_ ; cur ; cur = cur->next_)
cur->dump(o, 0);
}
o << "ELABORATED PROCESSES:" << endl;
// Dump the processes.
for (const NetProcTop*idx = procs_ ; idx ; idx = idx->next_)
idx->dump(o, 0);
for (const NetAnalogTop*idx = aprocs_ ; idx ; idx = idx->next_)
idx->dump(o, 0);
}
+149
View File
@@ -0,0 +1,149 @@
Developer Quick Start for Icarus Verilog
The documentation for getting, building and installing Icarus Verilog
is kept and maintained at the iverilog documentation wiki at
<http://iverilog.wikia.com>. See the Installation Guide for getting
the current source from the git repository (and how to use the git
repository) and see the Developer Guide for instructions on
participating in the Icarus Verilog development process. That
information will not be repeated here.
What this documentation *will* cover is the gross structure of the
Icarus Verilog compiler source. This will help orient you to the
source code itself, so that you can find the global parts where you
can look for even better detail.
* Compiler Components
- The compiler driver (driver/)
This is the binary that is installed as "iverilog". This program takes
the command line arguments and assembles invocations of all the other
subcommands to perform the steps of compilation.
- The preprocessor (ivlpp/)
This implements the Verilog pre-processor. In Icarus Verilog, the
compiler directives `define, `include, `ifdef and etc. are implemented
in an external program. The ivlpp/ directory contains the source for
this program.
- The core compiler (this directory)
The "ivl" program is the core that does all the Verilog compiler
processing that is not handled elsewhere. This is the main core of the
Icarus Verilog compiler, not the runtime. See below for more details
on the core itself.
- The loadable code generators (tgt-*/)
This core compiler, after it is finished with parsing and semantic
analysis, uses loadable code generators to emit code for supported
targets. The tgt-*/ directories contains the source for the target
code generators that are bundled with Icarus Verilog. The tgt-vvp/
directory in particular contains the code generator for the vvp
runtime.
* Runtime Components
- The vvp runtime (vvp/)
This program implements the runtime environment for Icarus
Verilog. It implements the "vvp" command described in the user
documentation. See the vvp/ subdirectory for further developer
documentation.
- The system tasks implementations (vpi/)
The standard Verilog system tasks are implemented using VPI (PLI-2)
and the source is in this subdirectory.
- The PLI-1 compatibility library (libveriuser/)
The Icarus Verilog support for the deprecated PLI-1 is in this
subdirectory. The vvp runtime does not directly support the
PLI-1. Instead, the libveriuser library emulates it using the builtin
PLI-2 support.
- The Cadence PLI module compatibility module (cadpli/)
It is possible in some specialized situations to load and execute
PLI-1 code written for Verilog-XL. This directory contains the source
for the module that provides the Cadence PLI interface.
* The Core Compiler
The "ivl" binary is the core compiler that does the heavy lifting of
compiling the Verilog source (including libraries) and generating the
output. This is the most complex component of the Icarus Verilog
compilation system.
The process in the abstract starts with the Verilog lexical analysis
and parsing to generate an internal "pform". The pform is then
translated by elaboration into the "netlist" form. The netlist is
processed by some functors (which include some optimizations and
optional synthesis) then is translated into the ivl_target internal
form. And finally, the ivl_target form is passed via the ivl_target.h
API to the code generators.
- Lexical Analysis
Lexical analysis and parsing use the tools "flex", "gperf", and
"bison". The "flex" input file "lexor.lex" recognizes the tokens in
the input stream. This is called "lexical analysis". The lexical
analyzer also does some processing of compiler directives that are not
otherwise taken care of by the external preprocessor. The lexical
analyzer uses a table of keywords that is generated using the "gperf"
program and the input file "lexor_keywords.gperf". This table allows
the lexical analyzer to efficiently check input words with the rather
large set of potential keywords.
- Parsing
The parser input file "parse.y" is passed to the "bison" program to
generate the parser. The parser uses the functions in parse*.h,
parse*.cc, pform.h, and pform*.cc to generate the pform from the
stream of input tokens. The pform is what compiler writers call a
"decorated parse tree".
The pform itself is described by the classes in the header files
"PScope.h", "Module.h", "PGenerate.h", "Statement.h", and
"PExpr.h". The implementations of the classes in those header files
are in the similarly named C++ files.
- Elaboration
Elaboration transforms the pform to the netlist form. Elaboration is
conceptually divided into several major steps: Scope elaboration,
parameter overrides and defparam propagation, signal elaboration, and
statement and expression elaboration.
The elaboration of scopes and parameter overrides and defparam
propagation are conceptually separate, but are in practice
intermingled. The elaboration of scopes scans the pform to find and
instantiate all the scopes of the design. New scopes are created by
instantiation of modules (starting with the root instances) by user
defined tasks and functions, named blocks, and generate schemes. The
elaborate_scope methods implement scope elaboration, and the
elab_scope.cc source file has the implementations of those
methods.
The elaborate.cc source file contains the initial calls to the
elaborate_scope for the root scopes to get the process started. In
particular, see the "elaborate" function near the bottom of the
elaborate.cc source file. The calls to Design::make_root_scope create
the initial root scopes, and the creation and enqueue of the
elaborate_root_scope_t work items primes the scope elaboration work
list.
Intermingled in the work list are defparms work items that call the
Design::run_defparams and Design::evaluate_parameters methods that
override and evaluate parameters. The override and evaluation of
parameters must be intermingled with the elaboration of scopes because
the exact values of parameters may impact the scopes created (imagine
generate schemes and instance arrays) and the created scopes in turn
create new parameters that need override and evaluation.
+7 -7
View File
@@ -19,21 +19,21 @@
# include "discipline.h"
nature_t::nature_t(perm_string name, perm_string access)
: name_(name), access_(access)
ivl_nature_s::ivl_nature_s(perm_string name__, perm_string access__)
: name_(name__), access_(access__)
{
}
nature_t::~nature_t()
ivl_nature_s::~ivl_nature_s()
{
}
discipline_t::discipline_t(perm_string name, ddomain_t domain,
nature_t*pot, nature_t*flow)
: name_(name), domain_(domain), potential_(pot), flow_(flow)
ivl_discipline_s::ivl_discipline_s(perm_string name__, ivl_dis_domain_t domain__,
ivl_nature_t pot, ivl_nature_t flow__)
: name_(name__), domain_(domain__), potential_(pot), flow_(flow__)
{
}
discipline_t::~discipline_t()
ivl_discipline_s::~ivl_discipline_s()
{
}
+22 -20
View File
@@ -1,7 +1,7 @@
#ifndef __discipline_H
#define __discipline_H
/*
* Copyright (c) 2008 Stephen Williams (steve@icarus.com)
* Copyright (c) 2008-2010 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -28,15 +28,15 @@
# include "StringHeap.h"
# include <iostream>
# include <map>
# include "ivl_target.h"
# include "LineInfo.h"
typedef enum { DD_NONE, DD_DISCRETE, DD_CONTINUOUS } ddomain_t;
extern std::ostream& operator << (std::ostream&, ddomain_t);
extern std::ostream& operator << (std::ostream&, ivl_dis_domain_t);
class nature_t : public LineInfo {
class ivl_nature_s : public LineInfo {
public:
explicit nature_t(perm_string name, perm_string access);
~nature_t();
explicit ivl_nature_s(perm_string name, perm_string access);
~ivl_nature_s();
perm_string name() const { return name_; }
// Identifier for the access function for this nature
@@ -47,29 +47,31 @@ class nature_t : public LineInfo {
perm_string access_;
};
class discipline_t : public LineInfo {
class ivl_discipline_s : public LineInfo {
public:
explicit discipline_t (perm_string name, ddomain_t dom,
nature_t*pot, nature_t*flow);
~discipline_t();
explicit ivl_discipline_s (perm_string name, ivl_dis_domain_t dom,
ivl_nature_t pot, ivl_nature_t flow);
~ivl_discipline_s();
perm_string name() const { return name_; }
ddomain_t domain() const { return domain_; }
const nature_t*potential() const { return potential_; }
const nature_t*flow() const { return flow_; }
ivl_dis_domain_t domain() const { return domain_; }
ivl_nature_t potential() const { return potential_; }
ivl_nature_t flow() const { return flow_; }
private:
perm_string name_;
ddomain_t domain_;
nature_t*potential_;
nature_t*flow_;
ivl_dis_domain_t domain_;
ivl_nature_t potential_;
ivl_nature_t flow_;
private: // not implemented
discipline_t(const discipline_t&);
discipline_t& operator = (const discipline_t&);
ivl_discipline_s(const ivl_discipline_s&);
ivl_discipline_s& operator = (const ivl_discipline_s&);
};
extern map<perm_string,nature_t*> natures;
extern map<perm_string,discipline_t*> disciplines;
extern map<perm_string,ivl_nature_t> natures;
extern map<perm_string,ivl_discipline_t> disciplines;
// Map access function name to the nature that it accesses.
extern map<perm_string,ivl_nature_t> access_function_nature;
#endif
+4 -24
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
* Copyright (c) 2001-2009 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: dosify.c,v 1.5 2003/07/15 16:17:47 steve Exp $"
#endif
/*
* This is a simple program to make a dosified copy of the
@@ -51,6 +48,7 @@ int main(int argc, char*argv[])
ofile = fopen(argv[2], "wb");
if (ofile == 0) {
fprintf(stderr, "Unable to open %s for output.\n", argv[2]);
fclose(ifile);
return 2;
}
@@ -64,25 +62,7 @@ int main(int argc, char*argv[])
pr = ch;
}
fclose(ifile);
fclose(ofile);
return 0;
}
/*
* $Log: dosify.c,v $
* Revision 1.5 2003/07/15 16:17:47 steve
* Fix spelling of ifdef.
*
* Revision 1.4 2003/07/15 03:49:22 steve
* Spelling fixes.
*
* Revision 1.3 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.2 2002/08/11 23:47:04 steve
* Add missing Log and Ident strings.
*
* Revision 1.1 2001/08/03 17:06:47 steve
* Add install of examples for Windows.
*
*/
-2
View File
@@ -1,2 +0,0 @@
Makefile
iverilog-vpi.exe
+27 -17
View File
@@ -18,7 +18,7 @@
#
SHELL = /bin/sh
VERSION = 0.9.devel
suffix = @install_suffix@
prefix = @prefix@
exec_prefix = @exec_prefix@
@@ -27,6 +27,8 @@ datarootdir = @datarootdir@
VPATH = $(srcdir)
suffix = @install_suffix@
bindir = $(exec_prefix)/bin
libdir = $(exec_prefix)/lib
includedir = $(prefix)/include
@@ -35,12 +37,13 @@ mandir = @mandir@
dllib=@DLLIB@
CC = @CC@
WINDRES = @WINDRES@
INSTALL = @INSTALL@
INSTALL_PROGRAM = @INSTALL_PROGRAM@
INSTALL_DATA = @INSTALL_DATA@
CPPFLAGS = @ident_support@ -I. -I$(srcdir)/.. -DVERSION='"$(VERSION)"' @CPPFLAGS@ @DEFS@
CFLAGS = -Wall @CFLAGS@
CPPFLAGS = -I. -I$(srcdir)/.. @CPPFLAGS@ @DEFS@
CFLAGS = @WARNING_FLAGS@ @CFLAGS@
LDFLAGS = @LDFLAGS@
all: iverilog-vpi@EXEEXT@
@@ -48,38 +51,45 @@ all: iverilog-vpi@EXEEXT@
check: all
clean:
rm -f *.o config.h
rm -f iverilog-vpi@EXEEXT@
rm -f *.o config.h iverilog-vpi@EXEEXT@ res.rc
distclean: clean
rm -f Makefile
rm -f Makefile config.log
Makefile: $(srcdir)/Makefile.in ../config.status
cd ..; ./config.status --file=driver-vpi/$@
O = main.o res.o
iverilog-vpi@EXEEXT@: $O
$(CC) $(LDFLAGS) $O -o iverilog-vpi@EXEEXT@ @EXTRALIBS@
main.o: main.c config.h
main.o: $(srcdir)/main.c config.h
$(CC) $(CPPFLAGS) $(CFLAGS) -c $(srcdir)/main.c
config.h: config.h.in
config.h: $(srcdir)/config.h.in Makefile
sed -e 's;@IVLCC@;@CC@;' -e 's;@IVLCXX@;@CXX@;' \
-e 's;@IVLCFLAGS@;@CXXFLAGS@;' \
-e 's;@SUFFIX@;$(suffix);g' \
-e 's;@IVLCFLAGS@;$(CFLAGS);' \
-e 's;@SHARED@;@shared@;' $< > $@
# Windows specific...
res.rc: $(srcdir)/res.rc.in ../version.exe
sed -e 's;@PRODUCTVERSION@;'`../version.exe '%M,%m,%n,0'`';' \
$(srcdir)/res.rc.in > $@
res.o: res.rc
windres -i res.rc -o res.o
$(WINDRES) -i res.rc -o res.o
#
install: all installdirs $(bindir)/iverilog-vpi@EXEEXT@
install: all installdirs $(bindir)/iverilog-vpi$(suffix)@EXEEXT@
$(bindir)/iverilog-vpi@EXEEXT@: ./iverilog-vpi@EXEEXT@
$(INSTALL_PROGRAM) ./iverilog-vpi@EXEEXT@ $(bindir)/iverilog-vpi@EXEEXT@
$(bindir)/iverilog-vpi$(suffix)@EXEEXT@: ./iverilog-vpi@EXEEXT@
$(INSTALL_PROGRAM) ./iverilog-vpi@EXEEXT@ "$(bindir)/iverilog-vpi$(suffix)@EXEEXT@"
installdirs: ../mkinstalldirs
$(srcdir)/../mkinstalldirs $(bindir)
installdirs: $(srcdir)/../mkinstalldirs
$(srcdir)/../mkinstalldirs "$(bindir)"
uninstall:
rm -f $(bindir)/iverilog-vpi@EXEEXT@
rm -f $(bindir)/iverilog-vpi$(suffix)@EXEEXT@
+2 -1
View File
@@ -5,4 +5,5 @@
#define IVERILOG_VPI_CXX "@IVLCXX@"
#define IVERILOG_VPI_CFLAGS " @IVLCFLAGS@"
#define IVERILOG_VPI_LDFLAGS "@SHARED@"
#define IVERILOG_VPI_LDLIBS "-lveriuser -lvpi"
#define IVERILOG_VPI_LDLIBS "-lveriuser@SUFFIX@ -lvpi@SUFFIX@"
#define IVERILOG_SUFFIX "@SUFFIX@"
+26 -19
View File
@@ -87,9 +87,9 @@ static void myExit(int exitVal)
static void usage()
{
fprintf(stderr,"usage: iverilog-vpi [src and obj files]...\n");
fprintf(stderr," or iverilog-vpi -mingw=dir\n");
fprintf(stderr," or iverilog-vpi -ivl=dir\n");
fprintf(stderr,"usage: iverilog-vpi" IVERILOG_SUFFIX " [src and obj files]...\n");
fprintf(stderr," or iverilog-vpi" IVERILOG_SUFFIX " -mingw=dir\n");
fprintf(stderr," or iverilog-vpi" IVERILOG_SUFFIX " -ivl=dir\n");
myExit(1);
}
@@ -236,7 +236,9 @@ static int GetRegistryKey(char *key, char **value)
}
regKeyBuffer[regKeySize] = 0; /* makes sure there is a trailing NULL */
lrv = RegQueryValueEx(hkKey,key,NULL,&regKeyType,regKeyBuffer,&regKeySize);
/* This needs an unsigned char *, but for MinGW the char is signed. */
lrv = RegQueryValueEx(hkKey, key, NULL, &regKeyType,
(unsigned char *) regKeyBuffer, &regKeySize);
if ((lrv != ERROR_SUCCESS) || (regKeyType != REG_SZ) || (!regKeySize)) {
lrv = RegCloseKey(hkKey);
free(regKeyBuffer);
@@ -269,7 +271,9 @@ static void SetRegistryKey(char *key, char *value)
&res) != ERROR_SUCCESS)
return;
RegSetValueEx(hkKey,key,0,REG_SZ,value,strlen(value)+1);
/* This needs an unsigned char *, but for MinGW the char is signed. */
RegSetValueEx(hkKey, key, 0, REG_SZ, (unsigned char *) value,
strlen(value)+1);
RegCloseKey(hkKey);
printf("info: storing %s in Windows' registry entry\n",value);
@@ -384,7 +388,7 @@ static int parse(int argc, char *argv[])
/* Check for the --install-dir option */
else if (stricmp("--install-dir", argv[idx]) == 0) {
setup_ivl_environment();
printf("%s\\\\lib\\\\ivl\\\\.\n", gstr.pIVL);
printf("%s\\\\lib\\\\ivl" IVERILOG_SUFFIX "\\\\.\n", gstr.pIVL);
myExit(0);
}
/* This is different than iverilog-vpi.sh, we don't
@@ -413,11 +417,18 @@ static void checkMingwDir(char *root)
int irv;
struct _stat stat_buf;
char *path;
char *path, *comp, *cp;
initDynString(&path);
assign(&path,gstr.pMINGW);
appendBackSlash(&path);
append(&path,"bin\\" IVERILOG_VPI_CC ".exe");
append(&path,"bin\\");
/* Get just the compiler name (the first word) */
comp = strdup(IVERILOG_VPI_CC);
cp = strchr(comp, ' ');
if (cp != NULL) *cp = '\0';
append(&path, comp);
append(&path,".exe");
free(comp);
irv = _stat(path,&stat_buf);
deInitDynString(path);
@@ -444,14 +455,14 @@ static void checkIvlDir(char *root)
initDynString(&path);
assign(&path,gstr.pIVL);
appendBackSlash(&path);
append(&path,"bin\\vvp.exe");
append(&path,"bin\\vvp" IVERILOG_SUFFIX ".exe");
irv = _stat(path,&stat_buf);
deInitDynString(path);
if (irv) {
fprintf(stderr,"error: %s does not appear to be the valid root directory of\n",root);
fprintf(stderr," Icarus Verilog. Use the -ivl option of iverilog-vpi.exe to\n");
fprintf(stderr," Icarus Verilog. Use the -ivl option of iverilog-vpi" IVERILOG_SUFFIX " to\n");
fprintf(stderr," point to the Icarus Verilog root directory. For a Windows\n");
fprintf(stderr," command shell the option would be something like -ivl=c:\\iverilog\n");
fprintf(stderr," For a Cygwin shell the option would be something like\n");
@@ -503,7 +514,7 @@ static void setup_ivl_environment()
SetRegistryKey(IVL_REGKEY_IVL,gstr.pIVL);
} else if (!GetRegistryKey(IVL_REGKEY_IVL,&gstr.pIVL)) {
fprintf(stderr,"error: can not locate the Icarus Verilog root directory, use the -ivl option\n");
fprintf(stderr," of iverilog-vpi.exe to point to the Icarus Verilog root directory.\n");
fprintf(stderr," of iverilog-vpi" IVERILOG_SUFFIX " to point to the Icarus Verilog root directory.\n");
fprintf(stderr," For a Windows command shell the option would be something like\n");
fprintf(stderr," -ivl=c:\\iverilog For a Cygwin shell the option would be something\n");
fprintf(stderr," like -ivl=c:\\\\iverilog\n");
@@ -511,20 +522,16 @@ static void setup_ivl_environment()
}
/* Build up the CFLAGS option string */
assign(&gstr.pCFLAGS,IVERILOG_VPI_CFLAGS);
append(&gstr.pCFLAGS," -I");
assign(&gstr.pCFLAGS,IVERILOG_VPI_CFLAGS " -I\"");
append(&gstr.pCFLAGS,gstr.pIVL);
appendBackSlash(&gstr.pCFLAGS);
append(&gstr.pCFLAGS, "\\");
append(&gstr.pCFLAGS,"include");
append(&gstr.pCFLAGS,"\\include\\\\iverilog\"" IVERILOG_SUFFIX);
/* Build up the LDFLAGS option string */
assign(&gstr.pLDLIBS,"-L");
assign(&gstr.pLDLIBS,"-L\"");
append(&gstr.pLDLIBS,gstr.pIVL);
appendBackSlash(&gstr.pLDLIBS);
append(&gstr.pLDLIBS, "\\");
append(&gstr.pLDLIBS,"lib ");
append(&gstr.pLDLIBS,IVERILOG_VPI_LDLIBS);
append(&gstr.pLDLIBS,"\\lib\" " IVERILOG_VPI_LDLIBS);
}
/* compile source modules */
+2 -2
View File
@@ -10,7 +10,7 @@ LANGUAGE 9, 4
1 VERSIONINFO
FILEVERSION 2002,11,13,0
PRODUCTVERSION 0,7,0,0
PRODUCTVERSION @PRODUCTVERSION@
FILEFLAGSMASK 0x3fL
FILEFLAGS 0x2L
FILEOS 0x40004L
@@ -28,7 +28,7 @@ BEGIN
VALUE "LegalCopyright", "Copyright 2002 Gus Baldauf\0"
VALUE "OriginalFilename", "iverilog-vpi.exe\0"
VALUE "ProductName", "Icarus Verilog\0"
VALUE "ProductVersion", "0, 7, 0, 0\0"
VALUE "ProductVersion", "@PRODUCTVERSION@\0"
END
END
BLOCK "VarFileInfo"
-15
View File
@@ -1,15 +0,0 @@
a.out
Makefile
parse.c
parse.h
parse.output
lexor.c
cfparse.c
cfparse.h
cfparse.output
cflexor.c
foo.*
iverilog
iverilog.ps
iverilog.pdf
tmp.pdf
+53 -33
View File
@@ -18,7 +18,7 @@
#
SHELL = /bin/sh
VERSION = 0.9.devel
suffix = @install_suffix@
prefix = @prefix@
exec_prefix = @exec_prefix@
@@ -38,22 +38,29 @@ CC = @CC@
INSTALL = @INSTALL@
INSTALL_PROGRAM = @INSTALL_PROGRAM@
INSTALL_DATA = @INSTALL_DATA@
LEX = @LEX@
YACC = @YACC@
MAN = @MAN@
PS2PDF = @PS2PDF@
CPPFLAGS = @ident_support@ -I. -I.. -I$(srcdir)/.. -I$(srcdir) -DVERSION='"$(VERSION)"' @CPPFLAGS@ @DEFS@
CFLAGS = -Wall @CFLAGS@
CPPFLAGS = -I. -I.. -I$(srcdir)/.. -I$(srcdir) @CPPFLAGS@ @DEFS@
CFLAGS = @WARNING_FLAGS@ @CFLAGS@
LDFLAGS = @LDFLAGS@
all: iverilog@EXEEXT@
all: dep iverilog@EXEEXT@ iverilog.man
check: all
clean:
rm -f *.o lexor.c parse.c parse.h parse.output
rm -f cflexor.c cfparse.c cfparse.h cfparse.output
rm -f iverilog@EXEEXT@ iverilog.pdf iverilog.ps
rm -f *.o cflexor.c cfparse.c cfparse.h cfparse.output
rm -f iverilog@EXEEXT@ iverilog.man iverilog.pdf iverilog.ps
rm -rf dep
distclean: clean
rm -f Makefile
rm -f Makefile config.log
Makefile: $(srcdir)/Makefile.in ../config.status
cd ..; ./config.status --file=driver/$@
O = main.o substit.o cflexor.o cfparse.o
@@ -61,56 +68,69 @@ iverilog@EXEEXT@: $O
$(CC) $(LDFLAGS) $O -o iverilog@EXEEXT@ @EXTRALIBS@
cflexor.c: cflexor.lex
flex -s -Pcf -ocflexor.c $(srcdir)/cflexor.lex
$(LEX) -Pcf -s -t $< > $@
cfparse.h cfparse.c: cfparse.y
bison --verbose -t -d -o cfparse.c --name-prefix=cf $(srcdir)/cfparse.y
# Build this in two steps to avoid parallel build issues (see pr3462585)
cfparse.c: cfparse.y
$(YACC) --verbose -t -p cf -d -o $@ $<
cfparse.h: cfparse.c
dep:
mkdir dep
main.o: main.c globals.h ../version.h
$(CC) $(CPPFLAGS) $(CFLAGS) -c -DIVL_ROOT='"@libdir@/ivl"' -DIVL_INC='"@includedir@"' -DIVL_LIB='"@libdir@"' -DDLLIB='"@DLLIB@"' $(srcdir)/main.c
%.o: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) @DEPENDENCY_FLAG@ -c $< -o $*.o
mv $*.d dep
build_string.o: build_string.c globals.h
cflexor.o: cflexor.c cfparse.h cfparse_misc.h globals.h
cfparse.o: cfparse.c globals.h cfparse_misc.h
main.o: main.c globals.h $(srcdir)/../version_base.h ../version_tag.h Makefile
$(CC) $(CPPFLAGS) $(CFLAGS) @DEPENDENCY_FLAG@ -c -DIVL_ROOT='"@libdir@/ivl$(suffix)"' -DIVL_SUFFIX='"$(suffix)"' -DIVL_INC='"@includedir@"' -DIVL_LIB='"@libdir@"' -DDLLIB='"@DLLIB@"' $(srcdir)/main.c
mv $*.d dep
iverilog.ps: $(srcdir)/iverilog.man
$(MAN) -t $(srcdir)/iverilog.man > iverilog.ps
cflexor.o: cflexor.c cfparse.h
iverilog.man: $(srcdir)/iverilog.man.in ../version.exe
../version.exe `head -1 $(srcdir)/iverilog.man.in`'\n' > $@
tail -n +2 $(srcdir)/iverilog.man.in >> $@
iverilog.ps: iverilog.man
$(MAN) -t ./iverilog.man > iverilog.ps
iverilog.pdf: iverilog.ps
$(PS2PDF) iverilog.ps iverilog.pdf
ifeq (@MINGW32@,yes)
ifeq ($(MAN),none)
INSTALL_DOC = $(mandir)/man1/iverilog.1
INSTALL_DOC = $(mandir)/man1/iverilog$(suffix).1
else
ifeq ($(PS2PDF),none)
INSTALL_DOC = $(mandir)/man1/iverilog.1
INSTALL_DOC = $(mandir)/man1/iverilog$(suffix).1
else
INSTALL_DOC = $(prefix)/iverilog.pdf $(mandir)/man1/iverilog.1
INSTALL_DOC = $(prefix)/iverilog$(suffix).pdf $(mandir)/man1/iverilog$(suffix).1
all: iverilog.pdf
endif
endif
INSTALL_DOCDIR = $(mandir)/man1
else
INSTALL_DOC = $(mandir)/man1/iverilog.1
INSTALL_DOC = $(mandir)/man1/iverilog$(suffix).1
INSTALL_DOCDIR = $(mandir)/man1
endif
install: all installdirs $(bindir)/iverilog@EXEEXT@ $(INSTALL_DOC)
install: all installdirs $(bindir)/iverilog$(suffix)@EXEEXT@ $(INSTALL_DOC)
$(bindir)/iverilog@EXEEXT@: ./iverilog@EXEEXT@
$(INSTALL_PROGRAM) ./iverilog@EXEEXT@ $(bindir)/iverilog@EXEEXT@
$(bindir)/iverilog$(suffix)@EXEEXT@: ./iverilog@EXEEXT@
$(INSTALL_PROGRAM) ./iverilog@EXEEXT@ "$(DESTDIR)$(bindir)/iverilog$(suffix)@EXEEXT@"
$(mandir)/man1/iverilog.1: $(srcdir)/iverilog.man
$(INSTALL_DATA) $(srcdir)/iverilog.man $(mandir)/man1/iverilog.1
$(mandir)/man1/iverilog$(suffix).1: iverilog.man
$(INSTALL_DATA) iverilog.man "$(DESTDIR)$(mandir)/man1/iverilog$(suffix).1"
$(prefix)/iverilog.pdf: iverilog.pdf
$(INSTALL_DATA) iverilog.pdf $(prefix)/iverilog.pdf
$(prefix)/iverilog$(suffix).pdf: iverilog.pdf
$(INSTALL_DATA) iverilog.pdf "$(DESTDIR)$(prefix)/iverilog$(suffix).pdf"
installdirs: ../mkinstalldirs
$(srcdir)/../mkinstalldirs $(bindir) $(INSTALL_DOCDIR)
installdirs: $(srcdir)/../mkinstalldirs
$(srcdir)/../mkinstalldirs "$(DESTDIR)$(bindir)" "$(DESTDIR)$(INSTALL_DOCDIR)"
uninstall:
rm -f $(bindir)/iverilog@EXEEXT@
rm -f $(mandir)/man1/iverilog.1 $(prefix)/iverilog.pdf
rm -f "$(DESTDIR)$(bindir)/iverilog$(suffix)@EXEEXT@"
rm -f "$(DESTDIR)$(mandir)/man1/iverilog$(suffix).1" "$(DESTDIR)$(prefix)/iverilog$(suffix).pdf"
-include $(patsubst %.o, dep/%.d, $O)
+19 -6
View File
@@ -4,7 +4,7 @@
%{
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
* Copyright (c) 2001-2010 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -21,9 +21,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: cflexor.lex,v 1.11 2007/03/22 16:08:18 steve Exp $"
#endif
# include "cfparse.h"
# include "cfparse_misc.h"
@@ -79,13 +76,15 @@ int cmdfile_stack_ptr = 0;
"+incdir+" { BEGIN(PLUS_ARGS); return TOK_INCDIR; }
"+integer-width+" { BEGIN(PLUS_ARGS); return TOK_INTEGER_WIDTH; }
"+libdir+" { BEGIN(PLUS_ARGS); return TOK_LIBDIR; }
"+libdir-nocase+" { BEGIN(PLUS_ARGS); return TOK_LIBDIR_NOCASE; }
"+libext+" { BEGIN(PLUS_ARGS); return TOK_LIBEXT; }
"+integer-width+" { BEGIN(PLUS_ARGS); return TOK_INTEGER_WIDTH; }
"+timescale+" { BEGIN(PLUS_ARGS); return TOK_TIMESCALE; }
/* If it is not any known plus-flag, return the generic form. */
"+"[^\n \t\b\f\r+]* {
@@ -149,7 +148,7 @@ int cmdfile_stack_ptr = 0;
cflval.text = trim_trailing_white(yytext, 0);
BEGIN(0);
return TOK_STRING; }
/* Fallback match. */
. { return yytext[0]; }
@@ -236,3 +235,17 @@ void cfreset(FILE*fd, const char*path)
current_file = strdup(path);
cflloc.first_line = 1;
}
/*
* Modern version of flex (>=2.5.9) can clean up the scanner data.
*/
void destroy_lexor()
{
# ifdef FLEX_SCANNER
# if YY_FLEX_MAJOR_VERSION >= 2 && YY_FLEX_MINOR_VERSION >= 5
# if defined(YY_FLEX_SUBMINOR_VERSION) && YY_FLEX_SUBMINOR_VERSION >= 9
yylex_destroy();
# endif
# endif
# endif
}
+13 -9
View File
@@ -1,6 +1,6 @@
%{
/*
* Copyright (c) 20001 Stephen Williams ([email protected])
* Copyright (c) 2001-2010 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -17,15 +17,12 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: cfparse.y,v 1.12 2007/04/19 02:52:53 steve Exp $"
#endif
# include "globals.h"
# include "cfparse_misc.h"
# include <ctype.h>
# include <stdlib.h>
# include <stdio.h>
# include <string.h>
@@ -41,13 +38,13 @@ static void translate_file_name(char*text)
break;
case 1:
while (*text) {
*text = toupper(*text);
*text = toupper((int)*text);
text += 1;
}
break;
case 2:
while (*text) {
*text = tolower(*text);
*text = tolower((int)*text);
text += 1;
}
break;
@@ -61,8 +58,8 @@ static void translate_file_name(char*text)
};
%token TOK_Da TOK_Dc TOK_Dv TOK_Dy
%token TOK_DEFINE TOK_INCDIR TOK_LIBDIR TOK_LIBDIR_NOCASE TOK_LIBEXT
%token TOK_INTEGER_WIDTH
%token TOK_DEFINE TOK_INCDIR TOK_INTEGER_WIDTH TOK_LIBDIR TOK_LIBDIR_NOCASE
%token TOK_LIBEXT TOK_TIMESCALE
%token <text> TOK_PLUSARG TOK_PLUSWORD TOK_STRING
%%
@@ -139,6 +136,13 @@ item
free(tmp);
}
| TOK_TIMESCALE TOK_PLUSARG
{ char*tmp = substitutions($2);
process_timescale(tmp);
free($2);
free(tmp);
}
| TOK_DEFINE TOK_PLUSARG
{ process_define($2);
free($2);
+3 -3
View File
@@ -1,8 +1,7 @@
#ifndef __cfparse_misc_H
#define __cfparse_misc_H
/*
* Copyright (c) 2001 Picture Elements, Inc.
* Stephen Williams (steve@picturel.com)
* Copyright (c) 2001-2009 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -17,7 +16,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
/*
@@ -38,6 +37,7 @@ int cflex(void);
int cferror(const char *);
int cfparse(void);
void switch_to_command_file(const char *);
void destroy_lexor();
char *current_file;
#endif
+3 -69
View File
@@ -1,7 +1,7 @@
#ifndef __globals_H
#define __globals_H
/*
* Copyright (c) 2000 Stephen Williams (steve@icarus.com)
* Copyright (c) 2000-2010 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,37 +18,9 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: globals.h,v 1.21 2007/04/19 02:52:53 steve Exp $"
#endif
# include <stddef.h>
/* This is the base (i.e. -B<value>) of the Icarus Verilog files. */
extern const char*base;
/* This is the path to the iconfig file sent to ivl. */
extern char* iconfig_path;
extern char* iconfig_common_path;
/* This is the optional -M<dependfile> value, if one was supplied. */
extern const char*depfile;
/* This is the optional -N<path> value, if one was supplied. */
extern const char*npath;
/* This is the name of the output file that the user selected. */
extern const char*opath;
/* This pointer is set if there were -s<value> parameters. */
extern char*start;
/* This flag is true if the -S flag was used on the command line. */
extern int synth_flag;
/* This is the name of the selected target. */
extern const char*targ;
/* This is the integer-width argument that will be passed to ivl. */
extern unsigned integer_width;
@@ -69,45 +41,7 @@ extern void process_include_dir(const char*name);
/* Add a new -D define. */
extern void process_define(const char*name);
/* -v */
extern int verbose_flag;
/* Set the default timescale for the simulator. */
extern void process_timescale(const char*ts_string);
extern char warning_flags[];
/* -y and -Y flags from the command line. */
extern char* library_flags;
extern char* library_flags2;
/*
* $Log: globals.h,v $
* Revision 1.21 2007/04/19 02:52:53 steve
* Add support for -v flag in command file.
*
* Revision 1.20 2007/03/07 04:24:59 steve
* Make integer width controllable.
*
* Revision 1.19 2003/11/18 06:31:46 steve
* Remove the iverilog.conf file.
*
* Revision 1.18 2003/11/13 04:09:49 steve
* Pass flags through the temporary config file.
*
* Revision 1.17 2003/11/01 04:21:57 steve
* Add support for a target static config file.
*
* Revision 1.16 2002/08/12 01:35:01 steve
* conditional ident string using autoconfig.
*
* Revision 1.15 2002/06/23 20:10:51 steve
* Variable substitution in command files.
*
* Revision 1.14 2002/05/28 20:40:37 steve
* ivl indexes the search path for libraries, and
* supports case insensitive module-to-file lookup.
*
* Revision 1.13 2002/05/28 00:50:40 steve
* Add the ivl -C flag for bulk configuration
* from the driver, and use that to run library
* modules through the preprocessor.
*/
#endif
+106 -57
View File
@@ -1,31 +1,30 @@
.TH iverilog 1 "April 22nd, 2008" Version "0.9.devel"
.TH iverilog 1 "January 22nd, 2010" "" "Version %M.%m.%n %E"
.SH NAME
iverilog - Icarus Verilog compiler
.SH SYNOPSIS
.B iverilog
[-ESVv] [-Bpath] [-ccmdfile|-fcmdfile] [-Dmacro[=defn]] [-pflag=value]
[-dname] [-g1995|-g2001|-g2005|-g<feature>]
[-Iincludedir] [-mmodule] [-Mfile] [-Nfile] [-ooutputfilename]
[-stopmodule] [-ttype] [-Tmin/typ/max] [-Wclass] [-ypath] sourcefile
[\-ESVv] [\-Bpath] [\-ccmdfile|\-fcmdfile] [\-Dmacro[=defn]] [\-pflag=value]
[\-dname] [\-g1995|\-g2001|\-g2005|\-g<feature>]
[\-Iincludedir] [\-mmodule] [\-Mfile] [\-Nfile] [\-ooutputfilename]
[\-stopmodule] [\-ttype] [\-Tmin/typ/max] [\-Wclass] [\-ypath] sourcefile
.SH DESCRIPTION
.PP
\fIiverilog\fP is a compiler that translates Verilog source code into
executable programs for simulation, or other netlist formats for
further processing. The currently supported targets are \fIvvp\fP for
simulation, and \fIxnf\fP and \fIfpga\fP for synthesis. Other target
simulation, and \fIfpga\fP for synthesis. Other target
types are added as code generators are implemented.
.SH OPTIONS
.l
\fIiverilog\fP accepts the following options:
.TP 8
.B -B\fIbase\fP
The \fIiverilog\fP program uses external programs and configuration
files to preprocess and compile the Verilog source. Normally, the path
used to locate these tools is built into the \fIiverilog\fP
program. However, the \fB-B\fP switch allows the user to select a
program. However, the \fB\-B\fP switch allows the user to select a
different set of programs. The path given is used to locate
\fIivlpp\fP, \fIivl\fP, code generators and the VPI modules.
.TP 8
@@ -44,7 +43,7 @@ Verilog source.
Defines macro \fImacro\fP as \fIdefn\fP.
.TP 8
.B -d\fIname\fP
Activate a class of compiler debugging messages. The \fB-d\fP switch may
Activate a class of compiler debugging messages. The \fB\-d\fP switch may
be used as often as necessary to activate all the desired messages.
Supported names are scopes, eval_tree, elaborate, and synth2;
any other names are ignored.
@@ -55,20 +54,21 @@ is the Verilog input, but with file inclusions and macro references
expanded and removed. This is useful, for example, to preprocess
Verilog source for use by other compilers.
.TP 8
.B -g1995\fI|\fP-g2001\fI|\fP-g2005
.B -g1995\fI|\fP-g2001\fI|\fP-g2001-noconfig\fI|\fP-g2005
Select the Verilog language \fIgeneration\fP to support in the
compiler. This selects between \fIIEEE1364-1995\fP,
\fIIEEE1364-2001\fP(2), or \fIIEEE1364-2005\fP. Normally,
compiler. This selects between \fIIEEE1364\-1995\fP,
\fIIEEE1364\-2001\fP, or \fIIEEE1364\-2005\fP. Normally,
Icarus Verilog defaults to the latest known generation of the
language. This flag is most useful to restrict the language to a set
supported by tools of specific generations, for compatibility with
other tools.
.TP 8
.B -gverilog-ams\fI|-fP-gno-verilog-ams
Enable or disable (default) support for Verilog-AMS.
.B -gverilog-ams\fI|\fP-gno-verilog-ams
Enable or disable (default) support for Verilog\-AMS.
Very little Verilog\-AMS specific functionality is currently supported.
.TP 8
.B -gspecify\fI|\fP-gno-specify
Enable (default) or disable specify block support. When enabled,
Enable or disable (default) specify block support. When enabled,
specify block code is elaborated. When disabled, specify blocks are
parsed but ignored. Specify blocks are commonly not needed for RTL
simulation, and in fact can hurt performance of the
@@ -81,6 +81,13 @@ include directory after all other explicit include directories. This
standard include directory is a convenient place to install standard
header files that a Verilog program may include.
.TP 8
.B -grelative-include\fI|\fP-gno-relative-include
Enable or disable (default) adding the local files directory to
the beginning of the include file search path. This allows files
to be included relative to the current file not the more common
files are only found in the working directory or in the specified
include file search path.
.TP 8
.B -gxtypes\fI|\fP-gno-xtypes
Enable (default) or disable support for extended types. Enabling
extended types allows for new types that are supported by Icarus
@@ -93,13 +100,23 @@ The standards requires that a vectored port have matching ranges for its
port declaration as well as any net/register declaration. It was common
practice in the past to only specify the range for the net/register
declaration and some tools still allow this. By default any mismatch is
reported as a error. Using \fI-gno-io-range-error\fP will produce a
reported as a error. Using \fB\-gno\-io\-range\-error\fP will produce a
warning instead of a fatal error for the case of a vectored net/register
and a scalar port declaration.
.TP 8
.B -gstrict-ca-eval\fI|\fP-gno-strict-ca-eval
The standard requires that if any input to a continuous assignment
expression changes value, the entire expression is re-evaluated. By
default, parts of the expression that do not depend on the changed
input value(s) are not re-evaluated. If an expression contains a call
to a function that doesn't depend solely on its input values or that
has side effects, the resulting behavior will differ from that
required by the standard. Using \fI\-gstrict\-ca\-eval\fP will force
standard compliant behavior (with some loss in performance).
.TP 8
.B -I\fIincludedir\fP
Append directory \fIincludedir\fP to list of directories searched
for Verilog include files. The \fB-I\fP switch may be used many times
for Verilog include files. The \fB\-I\fP switch may be used many times
to specify several directories to search, the directories are searched
in the order they appear on the command line.
.TP 8
@@ -128,7 +145,7 @@ Place output in the file \fIfilename\fP. If no output file name is
specified, \fIiverilog\fP uses the default name \fBa.out\fP.
.TP 8
.B -p\fIflag=value\fP
Assign a value to a target specific flag. The \fB-p\fP switch may be
Assign a value to a target specific flag. The \fB\-p\fP switch may be
used as often as necessary to specify all the desired flags. The flags
that are used depend on the target that is selected, and are described
in target specific documentation. Flags that are not used are ignored.
@@ -136,15 +153,15 @@ in target specific documentation. Flags that are not used are ignored.
.B -S
Synthesize. Normally, if the target can accept behavioral
descriptions the compiler will leave processes in behavioral
form. The \fB-S\fP switch causes the compiler to perform synthesis
form. The \fB\-S\fP switch causes the compiler to perform synthesis
even if it is not necessary for the target. If the target type is a
netlist format, the \fB-S\fP switch is unnecessary and has no effect.
netlist format, the \fB\-S\fP switch is unnecessary and has no effect.
.TP 8
.B -s \fItopmodule\fP
Specify the top level module to elaborate. Icarus Verilog will by default
choose modules that are not instantiated in any other modules, but
sometimes that is not sufficient, or instantiates too many modules. If
the user specifies one or more root modules with \fB-s\fP flags, then
the user specifies one or more root modules with \fB\-s\fP flags, then
they will be used as root modules instead.
.TP 8
.B -T\fImin|typ|max\fP
@@ -174,13 +191,18 @@ Print the version of the compiler, and exit.
.B -W\fIclass\fP
Turn on different classes of warnings. See the \fBWARNING TYPES\fP
section below for descriptions of the different warning groups. If
multiple \fB-W\fP switches are used, the warning set is the union of
multiple \fB\-W\fP switches are used, the warning set is the union of
all the requested classes.
.TP 8
.B -y\fIlibdir\fP
Append the directory to the library module search path. When the
compiler finds an undefined module, it looks in these directories for
files with the right name.
.TP 8
.B -Y\fIsuffix\fP
Add suffix to the list of accepted file name suffixes used when
searching a library for cells. The list defaults to the single
entry \fI.v\fP.
.SH MODULE LIBRARIES
@@ -199,7 +221,7 @@ library or in the main design.
.SH TARGETS
The Icarus Verilog compiler supports a variety of targets, for
different purposes, and the \fB-t\fP switch is used to select the
different purposes, and the \fB\-t\fP switch is used to select the
desired target.
.TP 8
@@ -212,27 +234,29 @@ This is the default. The vvp target generates code for the vvp
runtime. The output is a complete program that simulates the design
but must be run by the \fBvvp\fP command.
.TP 8
.B xnf
This is the Xilinx Netlist Format used by many tools for placing
devices in FPGAs or other programmable devices. This target is
obsolete, use the \fBfpga\fP target instead.
.TP 8
.B fpga
This is a synthesis target that supports a variety of fpga devices,
mostly by EDIF format output. The Icarus Verilog fpga code generator
can generate complete designs or EDIF macros that can in turn be
imported into larger designs by other tools. The \fBfpga\fP target
implies the synthesis \fB-S\fP flag.
implies the synthesis \fB\-S\fP flag.
.TP 8
.B vhdl
This target produces a VHDL translation of the Verilog netlist. The
output is a single file containing VHDL entities corresponding to
the modules in the Verilog source code. Note that only a subset of
the Verilog language is supported. See the wiki for more information.
.SH "WARNING TYPES"
These are the types of warnings that can be selected by the \fB-W\fP
These are the types of warnings that can be selected by the \fB\-W\fP
switch. All the warning types (other than \fBall\fP) can also be
prefixed with \fBno-\fP to turn off that warning. This is most useful
after a \fB-Wall\fP argument to suppress isolated warning types.
prefixed with \fBno\-\fP to turn off that warning. This is most useful
after a \fB\-Wall\fP argument to suppress isolated warning types.
.TP 8
.B all
This enables all supported warning categories.
This enables the implicit, portbind, select\-range, timescale, and
sensitivity\-entire\-array warning categories.
.TP 8
.B implicit
@@ -246,6 +270,12 @@ This enables warnings for ports of module instantiations that are not
connected but probably should be. Dangling input ports, for example,
will generate a warning.
.TP 8
.B select-range
This enables warnings for constant out of bound selects. This includes
partial or fully out of bound selects as well as a select containing
a 'bx or 'bz in the index.
.TP 8
.B timescale
This enables warnings for inconsistent use of the timescale
@@ -258,7 +288,7 @@ and dependent on compilation order.
.B infloop
This enables warnings for \fRalways\fP statements that may have runtime
infinite loops (has paths with no or zero delay). This class of warnings
is not included in \fB-Wall\fP and hence does not have a \fBno-\fP variant.
is not included in \fB\-Wall\fP and hence does not have a \fBno\-\fP variant.
A fatal error message will always be printed when the compiler can
determine that there will definitely be an infinite loop (all paths have
no or zero delay).
@@ -269,6 +299,22 @@ verified. It is expected that many of the warnings will be false
positives, since the code treats the value of all variables and signals
as indeterminate.
.TP 8
.B sensitivity-entire-vector
This enables warnings for when a part select within an "always @*"
statement results in the entire vector being added to the implicit
sensitivity list. Although this behaviour is prescribed by the IEEE
standard, it is not what might be expected and can have performance
implications if the vector is large.
.TP 8
.B sensitivity-entire-array
This enables warnings for when a word select within an "always @*"
statement results in the entire array being added to the implicit
sensitivity list. Although this behaviour is prescribed by the IEEE
standard, it is not what might be expected and can have performance
implications if the array is large.
.SH "SYSTEM FUNCTION TABLE FILES"
If the source file name as a \fB.sft\fP suffix, then it is taken to be
a system function table file. A System function table file is used to
@@ -310,14 +356,14 @@ character. Variables are substituted in file names.
.TP 8
.B -c\ \fIcmdfile\fP -f\ \fIcmdfile\fP
A \fB-c\fP or \fB-f\fP token prefixes a command file, exactly like it
A \fB\-c\fP or \fB\-f\fP token prefixes a command file, exactly like it
does on the command line. The cmdfile may be on the same line or the
next non-comment line.
.TP 8
.B -y\ \fIlibdir\fP
A \fB-y\fP token prefixes a library directory in the command file,
exactly like it does on the command line. The parameter to the \fB-y\fP
A \fB\-y\fP token prefixes a library directory in the command file,
exactly like it does on the command line. The parameter to the \fB\-y\fP
flag may be on the same line or the next non-comment line.
Variables in the \fIlibdir\fP are substituted.
@@ -325,7 +371,7 @@ Variables in the \fIlibdir\fP are substituted.
.TP 8
.B +incdir+\fIincludedir\fP
The \fB+incdir+\fP token in command files gives directories to search
for include files in much the same way that \fB-I\fP flags work on the
for include files in much the same way that \fB\-I\fP flags work on the
command line. The difference is that multiple \fI+includedir\fP
directories are valid parameters to a single \fB+incdir+\fP token,
although you may also have multiple \fB+incdir+\fP lines.
@@ -336,12 +382,12 @@ Variables in the \fIincludedir\fP are substituted.
.B +libext+\fIext\fP
The \fB+libext\fP token in command files fives file extensions to try
when looking for a library file. This is useful in conjunction with
\fB-y\fP flags to list suffixes to try in each directory before moving
\fB\-y\fP flags to list suffixes to try in each directory before moving
on to the next library directory.
.TP 8
.B +libdir+\fIdir\fP
This is another way to specify library directories. See the -y flag.
This is another way to specify library directories. See the \-y flag.
.TP 8
.B +libdir-nocase+\fIdir\fP
@@ -353,19 +399,26 @@ letters are correct. For example, "foo" matches "Foo.v" but not
.TP 8
.B +define+\fINAME\fP=\fIvalue\fP
The \fB+define+\fP token is the same as the \fB-D\fP option on the
The \fB+define+\fP token is the same as the \fB\-D\fP option on the
command line. The value part of the token is optional.
.TP 8
.B +toupper-filename\fP
.B +timescale+\fIvalue\fP
The \fB+timescale+\fP token is used to set the default timescale for
the simulation. This is the time units and precision before any
`timescale directive or after a `resetall directive. The default is
1s/1s.
.TP 8
.B +toupper-filename
This token causes file names after this in the command file to be
translated to uppercase. This helps with situations where a directory
has passed through a DOS machine, and in the process the file names
become munged.
.TP 8
.B +tolower-filename\fP
This is similar to the \fB+toupper-filename\fP hack described above.
.B +tolower-filename
This is similar to the \fB+toupper\-filename\fP hack described above.
.TP 8
.B +integer-width+\fIvalue\fP
@@ -376,7 +429,8 @@ integer value.
.SH "VARIABLES IN COMMAND FILES"
In certain cases, iverilog supports variables in command files. These
are strings of the form "$(\fIvarname\fP)", where \fIvarname\fP is the
are strings of the form "$(\fIvarname\fP)" or "${\fIvarname\fP}", where
\fIvarname\fP is the
name of the environment variable to read. The entire string is
replaced with the contents of that variable. Variables are only
substituted in contexts that explicitly support them, including file
@@ -389,12 +443,12 @@ from preprocessor defines elsewhere in the file or the command line.
The following macros are predefined by the compiler:
.TP 8
.B __ICARUS__ = 1\fP
This is defined always when compiling with Icarus Verilog.
.B __ICARUS__ = 1
This is always defined when compiling with Icarus Verilog.
.TP 8
.B __VAMS_ENABLE__ = 1\fp
This is defined if Verilog-AMS is enabled.
.B __VAMS_ENABLE__ = 1
This is defined if Verilog\-AMS is enabled.
.SH EXAMPLES
These examples assume that you have a Verilog source file called hello.v in
@@ -406,16 +460,11 @@ To compile hello.v to an executable file called a.out:
To compile hello.v to an executable file called hello:
iverilog -o hello hello.v
iverilog \-o hello hello.v
To compile and run explicitly using the vvp runtime:
iverilog -ohello.vvp -tvvp hello.v
To compile hello.v to a file in XNF-format called hello.xnf
iverilog -txnf -ohello.xnf hello.v
iverilog \-ohello.vvp \-tvvp hello.v
.SH "AUTHOR"
.nf
@@ -430,7 +479,7 @@ Tips on using, debugging, and developing the compiler can be found at
.SH COPYRIGHT
.nf
Copyright \(co 2002-2008 Stephen Williams
Copyright \(co 2002\-2010 Stephen Williams
This document can be freely redistributed according to the terms of the
GNU General Public License version 2.0
+330 -134
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2000-2008 Stephen Williams (steve@icarus.com)
* Copyright (c) 2000-2015 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,7 +18,8 @@
*/
# include "config.h"
# include "version.h"
# include "version_base.h"
# include "version_tag.h"
const char NOTICE[] =
" This program is free software; you can redistribute it and/or modify\n"
@@ -31,13 +32,14 @@ const char NOTICE[] =
" MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n"
" GNU General Public License for more details.\n"
"\n"
" You should have received a copy of the GNU General Public License\n"
" along with this program; if not, write to the Free Software\n"
" Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA\n"
" You should have received a copy of the GNU General Public License along\n"
" with this program; if not, write to the Free Software Foundation, Inc.,\n"
" 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.\n"
;
const char HELP[] =
"Usage: iverilog [-ESvV] [-B base] [-c cmdfile|-f cmdfile] [-g1|-g2|-g2x]\n"
"Usage: iverilog [-ESvV] [-B base] [-c cmdfile|-f cmdfile]\n"
" [-g1995|-g2001|-g2005] [-g<feature>]\n"
" [-D macro[=defn]] [-I includedir] [-M depfile] [-m module]\n"
" [-N file] [-o filename] [-p flag=value]\n"
" [-s topmodule] [-t target] [-T min|typ|max]\n"
@@ -51,6 +53,7 @@ const char HELP[] =
#include <unistd.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include <assert.h>
#include <sys/types.h>
@@ -106,16 +109,22 @@ const char*npath = 0;
const char*targ = "vvp";
const char*depfile = 0;
const char*generation = "2x";
const char*gen_specify = "specify";
const char*generation = "2005";
const char*gen_specify = "no-specify";
const char*gen_xtypes = "xtypes";
const char*gen_icarus = "icarus-misc";
const char*gen_io_range_error = "io-range-error";
const char*gen_strict_ca_eval = "no-strict-ca-eval";
const char*gen_verilog_ams = "no-verilog-ams";
const char*gen_system_verilog = "no-system-verilog";
/* Boolean: true means use a default include dir, false means don't */
int gen_std_include = 1;
/* Boolean: true means add the local file directory to the start
of the include list. */
int gen_relative_include = 0;
char warning_flags[16] = "";
unsigned integer_width = 32;
@@ -138,8 +147,7 @@ FILE*iconfig_file = 0;
char*compiled_defines_path = 0;
static char iconfig_common_path_buf[4096] = "";
char*iconfig_common_path = iconfig_common_path_buf;
static char iconfig_common_path[4096] = "";
int synth_flag = 0;
int verbose_flag = 0;
@@ -222,6 +230,23 @@ static FILE*fopen_safe(const char*path)
}
#endif
#ifdef __MINGW32__
/*
* The MinGW version of getenv() returns the path with a forward
* slash. This should be converted to a back slash to keep every
* thing in the code using a back slash. This function wraps the
* code for this in one place. The conversion can not be done
* directly on the getenv() result since it is const char*.
*/
static void convert_to_MS_path(char *path)
{
char *t;
for (t = path; *t; t++) {
if (*t == '/') *t = '\\';
}
}
#endif
static const char*my_tempfile(const char*str, FILE**fout)
{
FILE*file;
@@ -250,7 +275,11 @@ static const char*my_tempfile(const char*str, FILE**fout)
file = NULL;
while ((retry > 0) && (file == NULL)) {
unsigned code = rand();
sprintf(pathbuf, "%s%c%s%04x", tmpdir, sep, str, code);
snprintf(pathbuf, sizeof pathbuf, "%s%c%s%04x",
tmpdir, sep, str, code);
#ifdef __MINGW32__
convert_to_MS_path(pathbuf);
#endif
file = fopen_safe(pathbuf);
retry -= 1;
}
@@ -259,19 +288,120 @@ static const char*my_tempfile(const char*str, FILE**fout)
return pathbuf;
}
static int t_version_only(void)
{
int rc;
remove(source_path);
free(source_path);
fflush(0);
snprintf(tmp, sizeof tmp, "%s%civlpp -V", pbase, sep);
rc = system(tmp);
if (rc != 0) {
fprintf(stderr, "Unable to get version from \"%s\"\n", tmp);
}
fflush(0);
snprintf(tmp, sizeof tmp, "%s%civl -V -C\"%s\" -C\"%s\"", base, sep,
iconfig_path, iconfig_common_path);
rc = system(tmp);
if (rc != 0) {
fprintf(stderr, "Unable to get version from \"%s\"\n", tmp);
}
if ( ! getenv("IVERILOG_ICONFIG")) {
remove(iconfig_path);
free(iconfig_path);
remove(defines_path);
free(defines_path);
remove(compiled_defines_path);
free(compiled_defines_path);
}
return 0;
}
static void build_preprocess_command(int e_flag)
{
snprintf(tmp, sizeof tmp, "%s%civlpp %s%s -F\"%s\" -f\"%s\" -p\"%s\" ",
pbase, sep, verbose_flag?" -v":"",
e_flag?"":" -L", defines_path, source_path,
compiled_defines_path);
}
static int t_preprocess_only(void)
{
int rc;
char*cmd;
unsigned ncmd;
build_preprocess_command(1);
ncmd = strlen(tmp);
cmd = malloc(ncmd+1);
strcpy(cmd, tmp);
if (strcmp(opath,"-") != 0) {
snprintf(tmp, sizeof tmp, " > \"%s\"", opath);
cmd = realloc(cmd, ncmd+strlen(tmp)+1);
strcpy(cmd+ncmd, tmp);
ncmd += strlen(tmp);
}
if (verbose_flag)
printf("preprocess: %s\n", cmd);
rc = system(cmd);
remove(source_path);
free(source_path);
if ( ! getenv("IVERILOG_ICONFIG")) {
remove(iconfig_path);
free(iconfig_path);
remove(defines_path);
free(defines_path);
remove(compiled_defines_path);
free(compiled_defines_path);
}
if (rc != 0) {
if (WIFEXITED(rc)) {
fprintf(stderr, "errors preprocessing Verilog program.\n");
free(cmd);
return WEXITSTATUS(rc);
}
fprintf(stderr, "Command signaled: %s\n", cmd);
free(cmd);
return -1;
}
free(cmd);
return 0;
}
/*
* This is the default target type. It looks up the bits that are
* needed to run the command from the configuration file (which is
* already parsed for us) so we can handle must of the generic cases.
*/
static int t_default(char*cmd, unsigned ncmd)
static int t_compile()
{
unsigned rc;
#ifdef __MINGW32__
unsigned ncmd_start = ncmd;
/* Start by building the preprocess command line. */
build_preprocess_command(0);
size_t ncmd = strlen(tmp);
char*cmd = malloc(ncmd + 1);
strcpy(cmd, tmp);
#ifndef __MINGW32__
int rtn;
#endif
snprintf(tmp, sizeof tmp, " | %s/ivl", base);
/* Build the ivl command and pipe it to the preprocessor. */
snprintf(tmp, sizeof tmp, " | %s%civl", base, sep);
rc = strlen(tmp);
cmd = realloc(cmd, ncmd+rc+1);
strcpy(cmd+ncmd, tmp);
@@ -286,35 +416,25 @@ static int t_default(char*cmd, unsigned ncmd)
}
if (npath != 0) {
snprintf(tmp, sizeof tmp, " -N%s", npath);
snprintf(tmp, sizeof tmp, " -N\"%s\"", npath);
rc = strlen(tmp);
cmd = realloc(cmd, ncmd+rc+1);
strcpy(cmd+ncmd, tmp);
ncmd += rc;
}
snprintf(tmp, sizeof tmp, " -C%s", iconfig_path);
snprintf(tmp, sizeof tmp, " -C\"%s\"", iconfig_path);
rc = strlen(tmp);
cmd = realloc(cmd, ncmd+rc+1);
strcpy(cmd+ncmd, tmp);
ncmd += rc;
snprintf(tmp, sizeof tmp, " -C%s -- -", iconfig_common_path);
snprintf(tmp, sizeof tmp, " -C\"%s\" -- -", iconfig_common_path);
rc = strlen(tmp);
cmd = realloc(cmd, ncmd+rc+1);
strcpy(cmd+ncmd, tmp);
ncmd += rc;
#ifdef __MINGW32__
{
char *t;
for (t = cmd+ncmd_start; *t; t++)
{
if (*t == '/') *t = '\\';
}
}
#endif
if (verbose_flag)
printf("translate: %s\n", cmd);
@@ -323,28 +443,33 @@ static int t_default(char*cmd, unsigned ncmd)
rc = system(cmd);
if ( ! getenv("IVERILOG_ICONFIG")) {
remove(source_path);
free(source_path);
remove(iconfig_path);
free(iconfig_path);
remove(defines_path);
free(defines_path);
remove(compiled_defines_path);
free(compiled_defines_path);
}
#ifdef __MINGW32__ /* MinGW just returns the exit status, so return it! */
free(cmd);
return rc;
#else
rtn = 0;
if (rc != 0) {
if (rc == 127) {
fprintf(stderr, "Failed to execute: %s\n", cmd);
return 1;
rtn = 1;
} else if (WIFEXITED(rc)) {
rtn = WEXITSTATUS(rc);
} else {
fprintf(stderr, "Command signaled: %s\n", cmd);
rtn = -1;
}
if (WIFEXITED(rc))
return WEXITSTATUS(rc);
fprintf(stderr, "Command signaled: %s\n", cmd);
return -1;
}
return 0;
free(cmd);
return rtn;
#endif
}
@@ -354,13 +479,18 @@ static void process_warning_switch(const char*name)
if (strcmp(name,"all") == 0) {
process_warning_switch("implicit");
process_warning_switch("portbind");
process_warning_switch("select-range");
process_warning_switch("timescale");
process_warning_switch("sensitivity-entire-array");
} else if (strcmp(name,"implicit") == 0) {
if (! strchr(warning_flags, 'i'))
strcat(warning_flags, "i");
} else if (strcmp(name,"portbind") == 0) {
if (! strchr(warning_flags, 'p'))
strcat(warning_flags, "p");
} else if (strcmp(name,"select-range") == 0) {
if (! strchr(warning_flags, 's'))
strcat(warning_flags, "s");
} else if (strcmp(name,"timescale") == 0) {
if (! strchr(warning_flags, 't'))
strcat(warning_flags, "t");
@@ -369,6 +499,12 @@ static void process_warning_switch(const char*name)
} else if (strcmp(name,"infloop") == 0) {
if (! strchr(warning_flags, 'l'))
strcat(warning_flags, "l");
} else if (strcmp(name,"sensitivity-entire-vector") == 0) {
if (! strchr(warning_flags, 'v'))
strcat(warning_flags, "v");
} else if (strcmp(name,"sensitivity-entire-array") == 0) {
if (! strchr(warning_flags, 'a'))
strcat(warning_flags, "a");
} else if (strcmp(name,"no-implicit") == 0) {
char*cp = strchr(warning_flags, 'i');
if (cp) while (*cp) {
@@ -381,12 +517,33 @@ static void process_warning_switch(const char*name)
cp[0] = cp[1];
cp += 1;
}
} else if (strcmp(name,"no-select-range") == 0) {
char*cp = strchr(warning_flags, 's');
if (cp) while (*cp) {
cp[0] = cp[1];
cp += 1;
}
} else if (strcmp(name,"no-timescale") == 0) {
char*cp = strchr(warning_flags, 't');
if (cp) while (*cp) {
cp[0] = cp[1];
cp += 1;
}
} else if (strcmp(name,"no-sensitivity-entire-vector") == 0) {
char*cp = strchr(warning_flags, 'v');
if (cp) while (*cp) {
cp[0] = cp[1];
cp += 1;
}
} else if (strcmp(name,"no-sensitivity-entire-array") == 0) {
char*cp = strchr(warning_flags, 'a');
if (cp) while (*cp) {
cp[0] = cp[1];
cp += 1;
}
} else {
fprintf(stderr, "Ignoring unknown warning class "
"%s\n", name);
}
}
@@ -415,6 +572,11 @@ void process_define(const char*name)
fprintf(defines_file,"D:%s\n", name);
}
void process_timescale(const char*ts_string)
{
fprintf(iconfig_file, "timescale:%s\n", ts_string);
}
/*
* This function is called while processing a file name in a command
* file, or a file name on the command line. Look to see if there is a
@@ -442,6 +604,9 @@ int process_generation(const char*name)
else if (strcmp(name,"2001") == 0)
generation = "2001";
else if (strcmp(name,"2001-noconfig") == 0)
generation = "2001-noconfig";
else if (strcmp(name,"2005") == 0)
generation = "2005";
@@ -484,18 +649,33 @@ int process_generation(const char*name)
else if (strcmp(name,"no-std-include") == 0)
gen_std_include = 0;
else if (strcmp(name,"relative-include") == 0)
gen_relative_include = 1;
else if (strcmp(name,"no-relative-include") == 0)
gen_relative_include = 0;
else if (strcmp(name,"io-range-error") == 0)
gen_io_range_error = "io-range-error";
else if (strcmp(name,"no-io-range-error") == 0)
gen_io_range_error = "no-io-range-error";
else if (strcmp(name,"strict-ca-eval") == 0)
gen_strict_ca_eval = "strict-ca-eval";
else if (strcmp(name,"no-strict-ca-eval") == 0)
gen_strict_ca_eval = "no-strict-ca-eval";
else if (strcmp(name,"verilog-ams") == 0)
gen_verilog_ams = "verilog-ams";
else if (strcmp(name,"no-verilog-ams") == 0)
gen_verilog_ams = "no-verilog-ams";
else if (strcmp(name,"system-verilog") == 0)
gen_system_verilog = "system-verilog";
else {
fprintf(stderr, "Unknown/Unsupported Language generation "
"%s\n\n", name);
@@ -505,11 +685,14 @@ int process_generation(const char*name)
" 2005 -- IEEE1364-2005\n"
"Other generation flags:\n"
" specify | no-specify\n"
" verilog-ams | no-verinlog-ams\n"
" verilog-ams | no-verilog-ams\n"
" std-include | no-std-include\n"
" relative-include | no-relative-include\n"
" xtypes | no-xtypes\n"
" icarus-misc | no-icarus-misc\n"
" io-range-error | no-io-range-error\n");
" io-range-error | no-io-range-error\n"
" strict-ca-eval | no-strict-ca-eval\n"
" system-verilog\n");
return 1;
}
@@ -522,7 +705,7 @@ int process_generation(const char*name)
void add_sft_file(const char *module)
{
char *file;
file = (char *) malloc(strlen(base)+1+strlen(module)+4+1);
sprintf(file, "%s%c%s.sft", base, sep, module);
if (access(file, R_OK) == 0)
@@ -532,41 +715,47 @@ void add_sft_file(const char *module)
int main(int argc, char **argv)
{
char*cmd;
unsigned ncmd;
int e_flag = 0;
int version_flag = 0;
int opt, idx, rc;
int opt, idx;
#ifdef __MINGW32__
{ char * s;
char basepath[1024];
GetModuleFileName(NULL,basepath,1024);
/* Calculate the ivl_root from the path to the command. This
is necessary because of the installation process on
Windows. Mostly, it is those darn drive letters, but oh
well. We know the command path is formed like this:
/* Calculate the ivl_root from the path to the command. This
is necessary because of the installation process in
Windows. Mostly, it is those darn drive letters, but oh
well. We know the command path is formed like this:
D:\iverilog\bin\iverilog.exe
D:\iverilog\bin\iverilog.exe
The module path in a Windows installation is the path:
The IVL_ROOT in a Windows installation is the path:
D:\iverilog\lib\ivl$(suffix)
D:\iverilog\lib\ivl
so we chop the file name and the last directory by
turning the last two \ characters to null. Then we append
the lib\ivl to finish. */
strncpy(ivl_root, basepath, MAXSIZE);
s = strrchr(ivl_root, sep);
if (s) *s = 0;
s = strrchr(ivl_root, sep);
if (s) *s = 0;
strcat(ivl_root, "\\lib\\ivl");
base = ivl_root;
so we chop the file name and the last directory by
turning the last two \ characters to null. Then we append
the lib\ivl$(suffix) to finish. */
char *s;
char tmppath[MAXSIZE];
GetModuleFileName(NULL, tmppath, sizeof tmppath);
/* Convert to a short name to remove any embedded spaces. */
GetShortPathName(tmppath, ivl_root, sizeof ivl_root);
s = strrchr(ivl_root, sep);
if (s) *s = 0;
else {
fprintf(stderr, "%s: Missing first %c in exe path!\n",
argv[0], sep);
exit(1);
}
s = strrchr(ivl_root, sep);
if (s) *s = 0;
else {
fprintf(stderr, "%s: Missing second %c in exe path!\n",
argv[0], sep);
exit(1);
}
strcat(ivl_root, "\\lib\\ivl" IVL_SUFFIX);
base = ivl_root;
#else
/* In a UNIX environment, the IVL_ROOT from the Makefile is
@@ -653,7 +842,7 @@ int main(int argc, char **argv)
case 'c':
case 'f':
add_cmd_file(optarg);
break;
break;
case 'D':
process_define(optarg);
break;
@@ -668,13 +857,12 @@ int main(int argc, char **argv)
break;
case 'g':
rc = process_generation(optarg);
if (rc != 0)
if (process_generation(optarg) != 0)
return -1;
break;
case 'h':
fprintf(stderr, "%s\n", HELP);
return 1;
case 'h':
fprintf(stderr, "%s\n", HELP);
return 1;
case 'I':
process_include_dir(optarg);
@@ -736,6 +924,20 @@ int main(int argc, char **argv)
break;
case '?':
default:
fclose(source_file);
remove(source_path);
free(source_path);
fclose(defines_file);
remove(defines_path);
free(defines_path);
fclose(iconfig_file);
remove(iconfig_path);
free(iconfig_path);
remove(compiled_defines_path);
free(compiled_defines_path);
while( (command_filename = get_cmd_file()) ) {
free(command_filename);
}
return 1;
}
}
@@ -745,16 +947,22 @@ int main(int argc, char **argv)
if (version_flag || verbose_flag) {
printf("Icarus Verilog version " VERSION " (" VERSION_TAG ")\n\n");
printf("Copyright 1998-2008 Stephen Williams\n");
printf("Copyright 1998-2010 Stephen Williams\n\n");
puts(NOTICE);
}
if (version_flag)
return 0;
if (synth_flag) {
fprintf(stderr, "Warning: Synthesis is not currently being "
"maintained and may not\n");
fprintf(stderr, " function correctly. V0.8 was the "
"last release branch to\n");
fprintf(stderr, " have active synthesis development "
"and support!\n");
}
/* Make a common conf file path to reflect the target. */
sprintf(iconfig_common_path, "%s%c%s%s.conf",
base,sep, targ, synth_flag? "-s" : "");
snprintf(iconfig_common_path, sizeof iconfig_common_path, "%s%c%s%s.conf",
base, sep, targ, synth_flag? "-s" : "");
/* Write values to the iconfig file. */
fprintf(iconfig_file, "basedir:%s\n", base);
@@ -764,9 +972,18 @@ int main(int argc, char **argv)
how to handle them. */
fprintf(iconfig_file, "sys_func:%s%csystem.sft\n", base, sep);
/* If verilog-ams is enabled, then include the va_math module
as well. */
if (strcmp(gen_verilog_ams,"verilog-ams") == 0) {
/* If verilog-2005 is enabled or icarus-misc or verilog-ams,
* then include the v2005_math library. */
if (strcmp(generation, "2005") == 0 ||
strcmp(gen_icarus, "icarus-misc") == 0 ||
strcmp(gen_verilog_ams, "verilog-ams") == 0) {
fprintf(iconfig_file, "sys_func:%s%cv2005_math.sft\n", base, sep);
fprintf(iconfig_file, "module:v2005_math\n");
}
/* If verilog-ams or icarus_misc is enabled, then include the
* va_math module as well. */
if (strcmp(gen_verilog_ams,"verilog-ams") == 0 ||
strcmp(gen_icarus, "icarus-misc") == 0) {
fprintf(iconfig_file, "sys_func:%s%cva_math.sft\n", base, sep);
fprintf(iconfig_file, "module:va_math\n");
}
@@ -776,8 +993,10 @@ int main(int argc, char **argv)
fprintf(iconfig_file, "generation:%s\n", gen_specify);
fprintf(iconfig_file, "generation:%s\n", gen_xtypes);
fprintf(iconfig_file, "generation:%s\n", gen_io_range_error);
fprintf(iconfig_file, "generation:%s\n", gen_strict_ca_eval);
fprintf(iconfig_file, "generation:%s\n", gen_verilog_ams);
fprintf(iconfig_file, "generation:%s\n", gen_icarus);
fprintf(iconfig_file, "generation:%s\n", gen_system_verilog);
fprintf(iconfig_file, "warnings:%s\n", warning_flags);
fprintf(iconfig_file, "out:%s\n", opath);
if (depfile) fprintf(iconfig_file, "depfile:%s\n", depfile);
@@ -799,7 +1018,9 @@ int main(int argc, char **argv)
return 1;
}
free(command_filename);
fclose(fp);
}
destroy_lexor();
if (depfile) {
fprintf(defines_file, "M:%s\n", depfile);
@@ -814,7 +1035,13 @@ int main(int argc, char **argv)
specifically disabled, then write that directory as the
very last include directory to use... always. */
if (gen_std_include) {
fprintf(defines_file, "I:%s%cinclude", base, sep);
fprintf(defines_file, "I:%s%cinclude\n", base, sep);
}
if (gen_relative_include) {
fprintf(defines_file, "relative include:true\n");
} else {
fprintf(defines_file, "relative include:false\n");
}
fclose(source_file);
@@ -823,58 +1050,18 @@ int main(int argc, char **argv)
fclose(defines_file);
defines_file = 0;
if (source_count == 0) {
fprintf(stderr, "%s: no source files.\n\n%s\n", argv[0], HELP);
return 1;
/* If we are planning on opening a dependencies file, then
open and truncate it here. The other phases of compilation
will append to the file, so this is necessary to make sure
it starts out empty. */
if (depfile) {
FILE*fd = fopen(depfile, "w");
fclose(fd);
}
/* Start building the preprocess command line. */
sprintf(tmp, "%s%civlpp %s%s -F%s -f%s -p%s ", pbase,sep,
verbose_flag?" -v":"",
e_flag?"":" -L", defines_path, source_path,
compiled_defines_path);
ncmd = strlen(tmp);
cmd = malloc(ncmd + 1);
strcpy(cmd, tmp);
/* If the -E flag was given on the command line, then all we
do is run the preprocessor and put the output where the
user wants it. */
if (e_flag) {
int rc;
if (strcmp(opath,"-") != 0) {
sprintf(tmp, " > %s", opath);
cmd = realloc(cmd, ncmd+strlen(tmp)+1);
strcpy(cmd+ncmd, tmp);
ncmd += strlen(tmp);
}
if (verbose_flag)
printf("preprocess: %s\n", cmd);
rc = system(cmd);
remove(source_path);
fclose(iconfig_file);
if ( ! getenv("IVERILOG_ICONFIG")) {
remove(iconfig_path);
remove(defines_path);
remove(compiled_defines_path);
}
if (rc != 0) {
if (WIFEXITED(rc)) {
fprintf(stderr, "errors preprocessing Verilog program.\n");
return WEXITSTATUS(rc);
}
fprintf(stderr, "Command signaled: %s\n", cmd);
return -1;
}
return 0;
if (source_count == 0 && !version_flag) {
fprintf(stderr, "%s: no source files.\n\n%s\n", argv[0], HELP);
return 1;
}
fprintf(iconfig_file, "iwidth:%u\n", integer_width);
@@ -882,13 +1069,22 @@ int main(int argc, char **argv)
/* Write the preprocessor command needed to preprocess a
single file. This may be used to preprocess library
files. */
fprintf(iconfig_file, "ivlpp:%s%civlpp -L -F%s -P%s\n",
fprintf(iconfig_file, "ivlpp:%s%civlpp -L -F\"%s\" -P\"%s\"\n",
pbase, sep, defines_path, compiled_defines_path);
/* Done writing to the iconfig file. Close it now. */
fclose(iconfig_file);
return t_default(cmd, ncmd);
/* If we're only here for the version output, then we're done. */
if (version_flag)
return t_version_only();
return 0;
/* If the -E flag was given on the command line, then all we
do is run the preprocessor and put the output where the
user wants it. */
if (e_flag)
return t_preprocess_only();
/* Otherwise, this is a full compile. */
return t_compile();
}
+12 -33
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2002 Stephen Williams (steve@icarus.com)
* Copyright (c) 2002-2010 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,15 +16,10 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: substit.c,v 1.5 2003/12/19 01:27:10 steve Exp $"
#endif
# include <string.h>
# include <stdlib.h>
#ifdef HAVE_MALLOC_H
# include <malloc.h>
#endif
# include <stdio.h>
char* substitutions(const char*str)
@@ -35,13 +30,13 @@ char* substitutions(const char*str)
while (*str) {
if ((str[0] == '$') && (str[1] == '(')) {
/* If I find a $(x) string in the source, replace
if ((str[0] == '$') && ((str[1] == '(') || str[1] == '{')) {
/* If I find a $(x) or ${x} string in the source, replace
it in the destination with the contents of the
environment variable x. */
char*name;
char*value;
const char*ep = strchr(str, ')');
const char*ep = strchr(str, (str[1]=='(') ? ')' : '}');
str += 2;
name = malloc(ep-str+1);
@@ -51,9 +46,14 @@ char* substitutions(const char*str)
str = ep + 1;
value = getenv(name);
free(name);
if (value == 0)
if (value == 0) {
fprintf(stderr, "Warning: environment variable "
"\"%s\" not found during command file "
"processing.\n", name);
free(name);
continue;
}
free(name);
if (strlen(value) >= (nbuf - (cp-buf))) {
size_t old_size = cp - buf;
@@ -92,24 +92,3 @@ char* substitutions(const char*str)
return buf;
}
/*
* $Log: substit.c,v $
* Revision 1.5 2003/12/19 01:27:10 steve
* Fix various unsigned compare warnings.
*
* Revision 1.4 2002/08/12 01:35:01 steve
* conditional ident string using autoconfig.
*
* Revision 1.3 2002/08/11 23:47:04 steve
* Add missing Log and Ident strings.
*
* Revision 1.2 2002/06/25 01:33:01 steve
* include malloc.h only when available.
*
* Revision 1.1 2002/06/23 20:10:51 steve
* Variable substitution in command files.
*
*/
+21 -3
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1999-2008 Stephen Williams (steve@icarus.com)
* Copyright (c) 1999-2010 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -21,6 +21,16 @@
# include "netlist.h"
# include <cassert>
# include <cstdlib>
# include "ivl_assert.h"
NetEAccess* NetEAccess::dup_expr() const
{
NetEAccess*tmp = new NetEAccess(branch_, nature_);
ivl_assert(*this, tmp);
tmp->set_line(*this);
return tmp;
}
NetEBComp* NetEBComp::dup_expr() const
{
@@ -84,8 +94,8 @@ NetESFunc* NetESFunc::dup_expr() const
tmp->cast_signed(has_sign());
for (unsigned idx = 0 ; idx < nparms() ; idx += 1) {
assert(tmp->parm(idx));
tmp->parm(idx, tmp->parm(idx)->dup_expr());
assert(parm(idx));
tmp->parm(idx, parm(idx)->dup_expr());
}
tmp->set_line(*this);
@@ -128,6 +138,14 @@ NetEUFunc* NetEUFunc::dup_expr() const
return tmp;
}
NetEUBits* NetEUBits::dup_expr() const
{
NetEUBits*tmp = new NetEUBits(op_, expr_->dup_expr());
assert(tmp);
tmp->set_line(*this);
return tmp;
}
NetEUnary* NetEUnary::dup_expr() const
{
NetEUnary*tmp = new NetEUnary(op_, expr_->dup_expr());
+1 -49
View File
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: elab_anet.cc,v 1.13 2007/03/22 16:08:14 steve Exp $"
#endif
# include "config.h"
@@ -115,7 +112,7 @@ NetNet* PEIdent::elaborate_anet(Design*des, NetScope*scope) const
const NetExpr*par = 0;
NetEvent* eve = 0;
symbol_search(des, scope, path_, sig, mem, par, eve);
symbol_search(this, des, scope, path_, sig, mem, par, eve);
if (mem != 0) {
@@ -167,48 +164,3 @@ NetNet* PEIdent::elaborate_anet(Design*des, NetScope*scope) const
return sig;
}
/*
* $Log: elab_anet.cc,v $
* Revision 1.13 2007/03/22 16:08:14 steve
* Spelling fixes from Larry
*
* Revision 1.12 2006/05/01 20:47:58 steve
* More explicit datatype setup.
*
* Revision 1.11 2005/07/11 16:56:50 steve
* Remove NetVariable and ivl_variable_t structures.
*
* Revision 1.10 2004/10/04 01:10:52 steve
* Clean up spurious trailing white space.
*
* Revision 1.9 2003/09/19 03:50:12 steve
* Remove find_memory method from Design class.
*
* Revision 1.8 2003/06/21 01:21:43 steve
* Harmless fixup of warnings.
*
* Revision 1.7 2003/03/06 00:28:41 steve
* All NetObj objects have lex_string base names.
*
* Revision 1.6 2003/01/27 05:09:17 steve
* Spelling fixes.
*
* Revision 1.5 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.4 2001/12/03 04:47:14 steve
* Parser and pform use hierarchical names as hname_t
* objects instead of encoded strings.
*
* Revision 1.3 2001/07/25 03:10:48 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.2 2001/01/06 02:29:36 steve
* Support arrays of integers.
*
* Revision 1.1 2000/12/06 06:31:09 steve
* Check lvalue of procedural continuous assign (PR#29)
*
*/
+2326 -537
View File
File diff suppressed because it is too large Load Diff
+227 -140
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2000-2008 Stephen Williams (steve@icarus.com)
* Copyright (c) 2000-2013 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -118,17 +118,20 @@ NetAssign_* PEConcat::elaborate_lval(Design*des,
NetAssign_*tmp = parms_[idx]->elaborate_lval(des, scope, is_force);
if (tmp->expr_type() == IVL_VT_REAL) {
cerr << parms_[idx]->get_fileline() << ": error: "
<< "concatenation operand can not be real: "
<< *parms_[idx] << endl;
des->errors += 1;
continue;
}
/* If the l-value doesn't elaborate, the error was
already detected and printed. We just skip it and let
the compiler catch more errors. */
if (tmp == 0)
continue;
assert(tmp);
if (tmp == 0) continue;
/* Link the new l-value to the previous one. */
NetAssign_*last = tmp;
while (last->more)
last = last->more;
@@ -152,7 +155,7 @@ NetAssign_* PEIdent::elaborate_lval(Design*des,
const NetExpr*par = 0;
NetEvent* eve = 0;
symbol_search(des, scope, path_, reg, par, eve);
symbol_search(this, des, scope, path_, reg, par, eve);
if (reg == 0) {
cerr << get_fileline() << ": error: Could not find variable ``"
<< path_ << "'' in ``" << scope_path(scope) <<
@@ -179,9 +182,33 @@ NetAssign_* PEIdent::elaborate_lval(Design*des,
return 0;
}
/* Get the signal referenced by the identifier, and make sure
it is a register. Wires are not allows in this context,
unless this is the l-value of a force. */
if ((reg->type() != NetNet::REG) && !is_force) {
cerr << get_fileline() << ": error: " << path_ <<
" is not a valid l-value in " << scope_path(scope) <<
"." << endl;
cerr << reg->get_fileline() << ": : " << path_ <<
" is declared here as " << reg->type() << "." << endl;
des->errors += 1;
return 0;
}
if (reg->array_dimensions() > 0)
return elaborate_lval_net_word_(des, scope, reg);
// This must be after the array word elaboration above!
if (reg->get_scalar() &&
use_sel != index_component_t::SEL_NONE) {
cerr << get_fileline() << ": error: can not select part of ";
if (reg->data_type() == IVL_VT_REAL) cerr << "real: ";
else cerr << "scalar: ";
cerr << reg->name() << endl;
des->errors += 1;
return 0;
}
if (use_sel == index_component_t::SEL_PART) {
NetAssign_*lv = new NetAssign_(reg);
elaborate_lval_net_part_(des, scope, lv);
@@ -195,114 +222,18 @@ NetAssign_* PEIdent::elaborate_lval(Design*des,
return lv;
}
/* Get the signal referenced by the identifier, and make sure
it is a register. Wires are not allows in this context,
unless this is the l-value of a force. */
if ((reg->type() != NetNet::REG) && !is_force) {
cerr << get_fileline() << ": error: " << path_ <<
" is not a valid l-value in " << scope_path(scope) <<
"." << endl;
cerr << reg->get_fileline() << ": : " << path_ <<
" is declared here as " << reg->type() << "." << endl;
des->errors += 1;
return 0;
}
long msb, lsb;
NetExpr*mux;
if (use_sel == index_component_t::SEL_BIT) {
const index_component_t&index_tail = name_tail.index.back();
ivl_assert(*this, index_tail.msb != 0);
ivl_assert(*this, index_tail.lsb == 0);
/* If there is only a single select expression, it is a
bit select. Evaluate the constant value and treat it
as a part select with a bit width of 1. If the
expression it not constant, then return the
expression as a mux. */
NetExpr*index_expr = elab_and_eval(des, scope, index_tail.msb, -1);
if (NetEConst*index_con = dynamic_cast<NetEConst*> (index_expr)) {
msb = index_con->value().as_long();
lsb = index_con->value().as_long();
mux = 0;
} else {
msb = 0;
lsb = 0;
mux = index_expr;
}
} else {
/* No select expressions, so presume a part select the
width of the register. */
msb = reg->msb();
lsb = reg->lsb();
mux = 0;
NetAssign_*lv = new NetAssign_(reg);
elaborate_lval_net_bit_(des, scope, lv);
return lv;
}
ivl_assert(*this, use_sel == index_component_t::SEL_NONE);
NetAssign_*lv;
if (mux) {
/* If there is a non-constant bit select, make a
NetAssign_ to the target reg and attach a
bmux to select the target bit. */
lv = new NetAssign_(reg);
/* Correct the mux for the range of the vector. */
if (reg->msb() < reg->lsb())
mux = make_sub_expr(reg->lsb(), mux);
else if (reg->lsb() != 0)
mux = make_add_expr(mux, - reg->lsb());
lv->set_part(mux, 1);
} else if (msb == reg->msb() && lsb == reg->lsb()) {
/* No bit select, and part select covers the entire
vector. Simplest case. */
lv = new NetAssign_(reg);
} else {
/* If the bit/part select is constant, then make the
NetAssign_ only as wide as it needs to be and connect
only to the selected bits of the reg. */
unsigned loff = reg->sb_to_idx(lsb);
unsigned moff = reg->sb_to_idx(msb);
unsigned wid = moff - loff + 1;
if (moff < loff) {
cerr << get_fileline() << ": error: part select "
<< reg->name() << "[" << msb<<":"<<lsb<<"]"
<< " is reversed." << endl;
des->errors += 1;
return 0;
}
/* If the part select extends beyond the extreme of the
variable, then report an error. Note that loff is
converted to normalized form so is relative the
variable pins. */
if ((wid + loff) > reg->vector_width()) {
cerr << get_fileline() << ": error: bit/part select "
<< reg->name() << "[" << msb<<":"<<lsb<<"]"
<< " is out of range." << endl;
des->errors += 1;
return 0;
}
lv = new NetAssign_(reg);
lv->set_part(new NetEConst(verinum(loff)), wid);
}
/* No select expressions. */
NetAssign_*lv = new NetAssign_(reg);
return lv;
}
@@ -326,13 +257,20 @@ NetAssign_* PEIdent::elaborate_lval_net_word_(Design*des,
ivl_assert(*this, index_head.msb != 0);
ivl_assert(*this, index_head.lsb == 0);
// These are not used, but they need to have a default value.
ivl_variable_type_t expr_type_tmp = IVL_VT_NO_TYPE;
bool unsized_flag_tmp = false;
index_head.msb->test_width(des, scope, integer_width, integer_width,
expr_type_tmp, unsized_flag_tmp);
NetExpr*word = elab_and_eval(des, scope, index_head.msb, -1);
// If there is a non-zero base to the memory, then build an
// expression to calculate the canonical address.
if (long base = reg->array_first()) {
word = make_add_expr(word, 0-base);
word = normalize_variable_array_base(word, base,
reg->array_count());
eval_expr(word);
}
@@ -349,7 +287,7 @@ NetAssign_* PEIdent::elaborate_lval_net_word_(Design*des,
if (NetEConst*word_const = dynamic_cast<NetEConst*>(word)) {
verinum word_val = word_const->value();
long index = word_val.as_long();
assert (reg->array_count() <= LONG_MAX);
if (index < 0 || index >= (long) reg->array_count()) {
cerr << get_fileline() << ": warning: Constant array index "
<< (index + reg->array_first())
@@ -364,6 +302,20 @@ NetAssign_* PEIdent::elaborate_lval_net_word_(Design*des,
if (name_tail.index.size() > 1)
use_sel = name_tail.index.back().sel;
if (reg->get_scalar() &&
use_sel != index_component_t::SEL_NONE) {
cerr << get_fileline() << ": error: can not select part of ";
if (reg->data_type() == IVL_VT_REAL) cerr << "real";
else cerr << "scalar";
cerr << " array word: " << reg->name()
<< "[" << *word << "]" << endl;
des->errors += 1;
return 0;
}
if (use_sel == index_component_t::SEL_BIT)
elaborate_lval_net_bit_(des, scope, lv);
if (use_sel == index_component_t::SEL_PART)
elaborate_lval_net_part_(des, scope, lv);
@@ -374,31 +326,111 @@ NetAssign_* PEIdent::elaborate_lval_net_word_(Design*des,
return lv;
}
bool PEIdent::elaborate_lval_net_part_(Design*des,
NetScope*scope,
NetAssign_*lv) const
bool PEIdent::elaborate_lval_net_bit_(Design*des,
NetScope*scope,
NetAssign_*lv) const
{
long msb, lsb;
bool flag = calculate_parts_(des, scope, msb, lsb);
if (!flag)
return false;
const name_component_t&name_tail = path_.back();
const index_component_t&index_tail = name_tail.index.back();
ivl_assert(*this, index_tail.msb != 0);
ivl_assert(*this, index_tail.lsb == 0);
NetNet*reg = lv->sig();
assert(reg);
// These are not used, but they need to have a default value.
ivl_variable_type_t expr_type_tmp = IVL_VT_NO_TYPE;
bool unsized_flag_tmp = false;
index_tail.msb->test_width(des, scope, integer_width, integer_width,
expr_type_tmp, unsized_flag_tmp);
// Bit selects have a single select expression. Evaluate the
// constant value and treat it as a part select with a bit
// width of 1.
NetExpr*mux = elab_and_eval(des, scope, index_tail.msb, -1);
long lsb = 0;
if (NetEConst*index_con = dynamic_cast<NetEConst*> (mux)) {
// The index has a constant defined value.
if (index_con->value().is_defined()) {
lsb = index_con->value().as_long();
mux = 0;
// The index is undefined.
} else {
cerr << get_fileline() << ": warning: L-value bit select of "
<< reg->name();
if (reg->array_dimensions() > 0) cerr << "[]";
cerr << " has an undefined index." << endl;
lv->set_part(new NetEConst(verinum(verinum::Vx)), 1);
return true;
}
}
if (mux) {
// Non-constant bit mux. Correct the mux for the range
// of the vector, then set the l-value part select expression.
mux = normalize_variable_base(mux, reg->msb(), reg->lsb(), 1, true);
lv->set_part(mux, 1);
} else if (lsb == reg->msb() && lsb == reg->lsb()) {
// Constant bit mux that happens to select the only bit
// of the l-value. Don't bother with any select at all.
} else {
// Constant bit select that does something useful.
long loff = reg->sb_to_idx(lsb);
if (loff < 0 || loff >= (long)reg->vector_width()) {
cerr << get_fileline() << ": error: bit select "
<< reg->name() << "[" <<lsb<<"]"
<< " is out of range." << endl;
des->errors += 1;
return 0;
}
lv->set_part(new NetEConst(verinum(loff)), 1);
}
return true;
}
bool PEIdent::elaborate_lval_net_part_(Design*des,
NetScope*scope,
NetAssign_*lv) const
{
// The range expressions of a part select must be
// constant. The calculate_parts_ function calculates the
// values into msb and lsb.
long msb, lsb;
bool parts_defined_flag;
bool flag = calculate_parts_(des, scope, msb, lsb, parts_defined_flag);
if (!flag) return false;
NetNet*reg = lv->sig();
assert(reg);
if (! parts_defined_flag) {
cerr << get_fileline() << ": warning: L-value part select of "
<< reg->name();
if (reg->array_dimensions() > 0) cerr << "[]";
cerr << " has an undefined index." << endl;
lv->set_part(new NetEConst(verinum(verinum::Vx)), 1);
return true;
}
if (msb == reg->msb() && lsb == reg->lsb()) {
/* No bit select, and part select covers the entire
vector. Simplest case. */
/* Part select covers the entire vector. Simplest case. */
} else {
/* If the bit/part select is constant, then make the
NetAssign_ only as wide as it needs to be and connect
only to the selected bits of the reg. */
unsigned loff = reg->sb_to_idx(lsb);
unsigned moff = reg->sb_to_idx(msb);
unsigned wid = moff - loff + 1;
/* Get the canonical offsets into the vector. */
long loff = reg->sb_to_idx(lsb);
long moff = reg->sb_to_idx(msb);
long wid = moff - loff + 1;
if (moff < loff) {
cerr << get_fileline() << ": error: part select "
@@ -408,17 +440,15 @@ bool PEIdent::elaborate_lval_net_part_(Design*des,
return false;
}
/* If the part select extends beyond the extreme of the
/* If the part select extends beyond the extremes of the
variable, then report an error. Note that loff is
converted to normalized form so is relative the
variable pins. */
if ((wid + loff) > reg->vector_width()) {
cerr << get_fileline() << ": error: bit/part select "
if (loff < 0 || moff >= (signed)reg->vector_width()) {
cerr << get_fileline() << ": warning: Part select "
<< reg->name() << "[" << msb<<":"<<lsb<<"]"
<< " is out of range." << endl;
des->errors += 1;
return false;
}
lv->set_part(new NetEConst(verinum(loff)), wid);
@@ -455,16 +485,73 @@ bool PEIdent::elaborate_lval_net_idx_(Design*des,
unsigned long wid;
calculate_up_do_width_(des, scope, wid);
// These are not used, but they need to have a default value.
ivl_variable_type_t expr_type_tmp = IVL_VT_NO_TYPE;
bool unsized_flag_tmp = false;
index_tail.msb->test_width(des, scope, integer_width, integer_width,
expr_type_tmp, unsized_flag_tmp);
NetExpr*base = elab_and_eval(des, scope, index_tail.msb, -1);
/* Correct the mux for the range of the vector. */
if (reg->msb() < reg->lsb())
base = make_sub_expr(reg->lsb(), base);
else if (reg->lsb() != 0)
base = make_add_expr(base, - reg->lsb());
if (use_sel == index_component_t::SEL_IDX_DO && wid > 1 ) {
base = make_add_expr(base, 1-(long)wid);
// Handle the special case that the base is constant. For this
// case we can reduce the expression.
if (NetEConst*base_c = dynamic_cast<NetEConst*> (base)) {
// For the undefined case just let the constant pass and
// we will handle it in the code generator.
if (base_c->value().is_defined()) {
long lsv = base_c->value().as_long();
long offset = 0;
if (((reg->msb() < reg->lsb()) &&
use_sel == index_component_t::SEL_IDX_UP) ||
((reg->msb() > reg->lsb()) &&
use_sel == index_component_t::SEL_IDX_DO)) {
offset = -wid + 1;
}
delete base;
long rel_base = reg->sb_to_idx(lsv) + offset;
/* If we cover the entire lvalue just skip the select. */
if (rel_base == 0 && wid == reg->vector_width()) return true;
base = new NetEConst(verinum(rel_base));
if (warn_ob_select) {
if (rel_base < 0) {
cerr << get_fileline() << ": warning: " << reg->name();
if (reg->array_dimensions() > 0) cerr << "[]";
cerr << "[" << lsv;
if (use_sel == index_component_t::SEL_IDX_UP) {
cerr << "+:";
} else {
cerr << "-:";
}
cerr << wid << "] is selecting before vector." << endl;
}
if (rel_base + wid > reg->vector_width()) {
cerr << get_fileline() << ": warning: " << reg->name();
if (reg->array_dimensions() > 0) cerr << "[]";
cerr << "[" << lsv;
if (use_sel == index_component_t::SEL_IDX_UP) {
cerr << "+:";
} else {
cerr << "-:";
}
cerr << wid << "] is selecting after vector." << endl;
}
}
} else {
cerr << get_fileline() << ": warning: L-value indexed part "
<< "select of " << reg->name();
if (reg->array_dimensions() > 0) cerr << "[]";
cerr << " has an undefined base." << endl;
}
} else {
/* Correct the mux for the range of the vector. */
if (use_sel == index_component_t::SEL_IDX_UP) {
base = normalize_variable_base(base, reg->msb(), reg->lsb(),
wid, true);
} else {
// This is assumed to be a SEL_IDX_DO.
base = normalize_variable_base(base, reg->msb(), reg->lsb(),
wid, false);
}
}
if (debug_elaborate)
+212 -3108
View File
File diff suppressed because it is too large Load Diff
+254 -9
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2000-2008 Stephen Williams (steve@icarus.com)
* Copyright (c) 2000-2010 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -53,7 +53,65 @@ NetExpr*PEBinary::elaborate_pexpr (Design*des, NetScope*scope) const
return 0;
}
NetExpr*tmp = elaborate_expr_base_(des, lp, rp, -2);
NetExpr*tmp = elaborate_expr_base_(des, lp, rp, -2, true);
return tmp;
}
NetExpr*PEBComp::elaborate_pexpr(Design*des, NetScope*scope) const
{
NetExpr*lp = left_->elaborate_pexpr(des, scope);
NetExpr*rp = right_->elaborate_pexpr(des, scope);
if ((lp == 0) || (rp == 0)) {
delete lp;
delete rp;
return 0;
}
NetEBComp*tmp = new NetEBComp(op_, lp, rp);
tmp->set_line(*this);
bool flag = tmp->set_width(1);
if (flag == false) {
cerr << get_fileline() << ": internal error: "
"expression bit width of comparison != 1." << endl;
des->errors += 1;
}
return tmp;
}
NetExpr*PEBLeftWidth::elaborate_pexpr (Design*des, NetScope*scope) const
{
NetExpr*lp = left_->elaborate_pexpr(des, scope);
NetExpr*rp = right_->elaborate_pexpr(des, scope);
if ((lp == 0) || (rp == 0)) {
delete lp;
delete rp;
return 0;
}
NetExpr*tmp = elaborate_expr_leaf(des, lp, rp, -2);
return tmp;
}
NetExpr*PEBLogic::elaborate_pexpr(Design*des, NetScope*scope) const
{
NetExpr*lp = left_->elaborate_pexpr(des, scope);
NetExpr*rp = right_->elaborate_pexpr(des, scope);
if ((lp == 0) || (rp == 0)) {
delete lp;
delete rp;
return 0;
}
NetEBLogic*tmp = new NetEBLogic(op_, lp, rp);
tmp->set_line(*this);
bool flag = tmp->set_width(1);
if (flag == false) {
cerr << get_fileline() << ": internal error: "
"expression bit width of comparison != 1." << endl;
des->errors += 1;
}
return tmp;
}
@@ -92,11 +150,19 @@ NetEConcat* PEConcat::elaborate_pexpr(Design*des, NetScope*scope) const
/* Elaborate all the operands and attach them to the concat
node. Use the elaborate_pexpr method instead of the
elaborate_expr method. */
bool fail = false;
for (unsigned idx = 0 ; idx < parms_.count() ; idx += 1) {
assert(parms_[idx]);
NetExpr*ex = parms_[idx]->elaborate_pexpr(des, scope);
if (ex == 0) continue;
if (ex->expr_type() == IVL_VT_REAL) {
cerr << ex->get_fileline() << ": error: concatenation "
<< "operand can not be real: " << *ex << endl;
des->errors += 1;
fail = true;
continue;
}
ex->set_line(*parms_[idx]);
if (dynamic_cast<NetEParam*>(ex)) {
@@ -109,13 +175,18 @@ NetEConcat* PEConcat::elaborate_pexpr(Design*des, NetScope*scope) const
<< "concatenation has indefinite width: "
<< *ex << endl;
des->errors += 1;
delete tmp;
return 0;
fail = true;
continue;
}
tmp->set(idx, ex);
}
if (fail) {
delete tmp;
return 0;
}
return tmp;
}
@@ -132,13 +203,21 @@ NetExpr*PEFNumber::elaborate_pexpr(Design*des, NetScope*scope) const
*/
NetExpr*PEIdent::elaborate_pexpr(Design*des, NetScope*scope) const
{
pform_name_t path = path_;
pform_name_t oldpath = path_;
name_component_t name_tail = path_.back();
path.pop_back();
oldpath.pop_back();
if (path_.size() > 1) {
cerr << get_fileline() << ": error: parameter r-value expression "
"does not support hierarchical references `" << path_
<< "`." << endl;
des->errors += 1;
return 0;
}
NetScope*pscope = scope;
if (path_.size() > 0) {
list<hname_t> tmp = eval_scope_path(des, scope, path);
list<hname_t> tmp = eval_scope_path(des, scope, oldpath);
pscope = des->find_scope(scope, tmp);
}
@@ -158,8 +237,9 @@ NetExpr*PEIdent::elaborate_pexpr(Design*des, NetScope*scope) const
ivl_assert(*this, pscope);
}
if (ex == 0) {
cerr << get_fileline() << ": error: identifier ``" << name_tail.name <<
"'' is not a parameter in "<< scope_path(scope)<< "." << endl;
cerr << get_fileline() << ": error: identifier `"
<< name_tail.name << "` is not a parameter in "
<< scope_path(scope)<< "." << endl;
des->errors += 1;
return 0;
}
@@ -267,3 +347,168 @@ NetExpr*PEUnary::elaborate_pexpr (Design*des, NetScope*scope) const
return tmp;
}
NetExpr* PECallFunction::elaborate_pexpr(Design*des, NetScope*scope) const
{
/* Only $clog2 and the builtin mathematical functions can
* be a constant system function. */
perm_string nm = peek_tail_name(path_);
if (nm[0] == '$' && (generation_flag >= GN_VER2005 ||
gn_icarus_misc_flag || gn_verilog_ams_flag)) {
if (nm == "$clog2" ||
nm == "$ln" ||
nm == "$log10" ||
nm == "$exp" ||
nm == "$sqrt" ||
nm == "$floor" ||
nm == "$ceil" ||
nm == "$sin" ||
nm == "$cos" ||
nm == "$tan" ||
nm == "$asin" ||
nm == "$acos" ||
nm == "$atan" ||
nm == "$sinh" ||
nm == "$cosh" ||
nm == "$tanh" ||
nm == "$asinh" ||
nm == "$acosh" ||
nm == "$atanh") {
if (parms_.size() != 1 || parms_[0] == 0) {
cerr << get_fileline() << ": error: " << nm
<< " takes a single argument." << endl;
des->errors += 1;
return 0;
}
NetExpr*arg = parms_[0]->elaborate_pexpr(des, scope);
if (arg == 0) return 0;
NetESFunc*rtn;
if (nm == "$clog2") {
rtn = new NetESFunc(nm, IVL_VT_BOOL, integer_width, 1);
} else {
rtn = new NetESFunc(nm, IVL_VT_REAL, 1, 1);
}
rtn->set_line(*this);
rtn->cast_signed(true);
rtn->parm(0, arg);
return rtn;
}
if (nm == "$pow" ||
nm == "$atan2" ||
nm == "$hypot") {
if (parms_.size() != 2 || parms_[0] == 0 || parms_[1] == 0) {
cerr << get_fileline() << ": error: " << nm
<< " takes two arguments." << endl;
des->errors += 1;
return 0;
}
NetExpr*arg0 = parms_[0]->elaborate_pexpr(des, scope);
NetExpr*arg1 = parms_[1]->elaborate_pexpr(des, scope);
if (arg0 == 0 || arg1 == 0) return 0;
NetESFunc*rtn = new NetESFunc(nm, IVL_VT_REAL, 1, 2);
rtn->set_line(*this);
rtn->cast_signed(true);
rtn->parm(0, arg0);
rtn->parm(1, arg1);
return rtn;
}
/* This is only available with verilog-ams or icarus-misc. */
if ((gn_icarus_misc_flag || gn_verilog_ams_flag) &&
(nm == "$abs")) {
if (parms_.size() != 1 || parms_[0] == 0) {
cerr << get_fileline() << ": error: " << nm
<< " takes a single argument." << endl;
des->errors += 1;
return 0;
}
NetExpr*arg = parms_[0]->elaborate_pexpr(des, scope);
if (arg == 0) return 0;
NetESFunc*rtn;
/* This can return either a real or an arbitrary
* width vector, so set things to fail if this
* does not get replaced with a constant during
* elaboration. */
rtn = new NetESFunc(nm, IVL_VT_NO_TYPE, 0, 1);
rtn->set_line(*this);
rtn->cast_signed(true);
rtn->parm(0, arg);
return rtn;
}
if ((gn_icarus_misc_flag || gn_verilog_ams_flag) &&
(nm == "$min" || nm == "$max")) {
if (parms_.size() != 2 || parms_[0] == 0 || parms_[1] == 0) {
cerr << get_fileline() << ": error: " << nm
<< " takes two arguments." << endl;
des->errors += 1;
return 0;
}
NetExpr*arg0 = parms_[0]->elaborate_pexpr(des, scope);
NetExpr*arg1 = parms_[1]->elaborate_pexpr(des, scope);
if (arg0 == 0 || arg1 == 0) return 0;
/* See $abs above for why this has no type or width. */
NetESFunc*rtn = new NetESFunc(nm, IVL_VT_NO_TYPE, 0, 2);
rtn->set_line(*this);
rtn->cast_signed(true);
rtn->parm(0, arg0);
rtn->parm(1, arg1);
return rtn;
}
cerr << get_fileline() << ": error: " << nm << "() is not a "
"constant system function." << endl;
des->errors += 1;
return 0;
}
/* Constant user function code goes here. */
cerr << get_fileline() << ": sorry: constant user functions are not "
"currently supported: " << nm << "()." << endl;
des->errors += 1;
return 0;
}
void NetExpr::resolve_pexpr_type(void)
{
}
void NetEBinary::resolve_pexpr_type(void)
{
if (debug_elab_pexpr) {
cerr << get_fileline() << ": debug: "
<< "Resolve_pexpr_type for binary " << human_readable_op(op_)
<< "." << endl;
}
left_->resolve_pexpr_type();
right_->resolve_pexpr_type();
switch (op_) {
case '+':
case '-':
case '*':
case '/':
suppress_binary_operand_sign_if_needed(left_, right_);
cast_signed_base_(left_->has_sign() && right_->has_sign());
break;
default:
break;
}
}
void NetEParam::resolve_pexpr_type(void)
{
if (debug_elab_pexpr) {
cerr << get_fileline() << ": debug: "
<< "Resolve_pexpr_type for parameter " << reference_->first
<< "." << endl;
}
if (reference_->second.signed_flag) {
cast_signed_base_(true);
} else if (reference_->second.expr) {
cast_signed_base_( reference_->second.expr->has_sign() );
}
}
+909 -218
View File
File diff suppressed because it is too large Load Diff
+272 -78
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2000-2008 Stephen Williams (steve@icarus.com)
* Copyright (c) 2000-2014 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -35,6 +35,14 @@
# include "util.h"
# include "ivl_assert.h"
/*
* Set the following to true when you need to process an expression
* that is being done in a constant context. This allows the
* elaboration to explicitly say we do not currently support constant
* user functions when the function is not found.
*/
bool need_constant_expr = false;
static bool get_const_argument(NetExpr*exp, verinum&res)
{
switch (exp->expr_type()) {
@@ -84,10 +92,10 @@ bool PScope::elaborate_sig_wires_(Design*des, NetScope*scope) const
&& (sig->port_type() == NetNet::PINPUT)
&& (sig->type() == NetNet::REG)) {
cerr << cur->get_fileline() << ": error: "
<< cur->basename() << " in "
cerr << cur->get_fileline() << ": error: Port "
<< cur->basename() << " of module "
<< scope->module_name()
<< " declared as input and as a reg type." << endl;
<< " is declared as input and as a reg type." << endl;
des->errors += 1;
}
@@ -96,10 +104,22 @@ bool PScope::elaborate_sig_wires_(Design*des, NetScope*scope) const
&& (sig->port_type() == NetNet::PINOUT)
&& (sig->type() == NetNet::REG)) {
cerr << cur->get_fileline() << ": error: "
<< cur->basename() << " in "
cerr << cur->get_fileline() << ": error: Port "
<< cur->basename() << " of module "
<< scope->module_name()
<< " declared as inout and as a reg type." << endl;
<< " is declared as inout and as a reg type." << endl;
des->errors += 1;
}
if (sig && (sig->scope() == scope)
&& (scope->type() == NetScope::MODULE)
&& (sig->port_type() == NetNet::PINOUT)
&& (sig->data_type() == IVL_VT_REAL)) {
cerr << cur->get_fileline() << ": error: Port "
<< cur->basename() << " of module "
<< scope->module_name()
<< " is declared as a real inout port." << endl;
des->errors += 1;
}
@@ -108,13 +128,49 @@ bool PScope::elaborate_sig_wires_(Design*des, NetScope*scope) const
return flag;
}
static void elaborate_sig_funcs(Design*des, NetScope*scope,
const map<perm_string,PFunction*>&funcs)
{
typedef map<perm_string,PFunction*>::const_iterator mfunc_it_t;
for (mfunc_it_t cur = funcs.begin()
; cur != funcs.end() ; cur ++) {
hname_t use_name ( (*cur).first );
NetScope*fscope = scope->child(use_name);
if (fscope == 0) {
cerr << (*cur).second->get_fileline() << ": internal error: "
<< "Child scope for function " << (*cur).first
<< " missing in " << scope_path(scope) << "." << endl;
des->errors += 1;
continue;
}
(*cur).second->elaborate_sig(des, fscope);
}
}
static void elaborate_sig_tasks(Design*des, NetScope*scope,
const map<perm_string,PTask*>&tasks)
{
typedef map<perm_string,PTask*>::const_iterator mtask_it_t;
for (mtask_it_t cur = tasks.begin()
; cur != tasks.end() ; cur ++) {
NetScope*tscope = scope->child( hname_t((*cur).first) );
assert(tscope);
(*cur).second->elaborate_sig(des, tscope);
}
}
bool Module::elaborate_sig(Design*des, NetScope*scope) const
{
bool flag = true;
// Scan all the ports of the module, and make sure that each
// is connected to wires that have port declarations.
for (unsigned idx = 0 ; idx < ports.count() ; idx += 1) {
for (unsigned idx = 0 ; idx < ports.size() ; idx += 1) {
Module::port_t*pp = ports[idx];
if (pp == 0)
continue;
@@ -123,7 +179,7 @@ bool Module::elaborate_sig(Design*des, NetScope*scope) const
// expression are all identifiers that should reference
// wires within the scope.
map<perm_string,PWire*>::const_iterator wt;
for (unsigned cc = 0 ; cc < pp->expr.count() ; cc += 1) {
for (unsigned cc = 0 ; cc < pp->expr.size() ; cc += 1) {
pform_name_t port_path (pp->expr[cc]->path());
// A concatenated wire of a port really should not
// have any hierarchy.
@@ -182,38 +238,12 @@ bool Module::elaborate_sig(Design*des, NetScope*scope) const
flag &= (*gt)->elaborate_sig(des, scope);
}
typedef map<perm_string,PFunction*>::const_iterator mfunc_it_t;
for (mfunc_it_t cur = funcs_.begin()
; cur != funcs_.end() ; cur ++) {
hname_t use_name ( (*cur).first );
NetScope*fscope = scope->child(use_name);
if (scope == 0) {
cerr << (*cur).second->get_fileline() << ": internal error: "
<< "Child scope for function " << (*cur).first
<< " missing in " << scope_path(scope) << "." << endl;
des->errors += 1;
continue;
}
(*cur).second->elaborate_sig(des, fscope);
}
// After all the wires are elaborated, we are free to
// elaborate the ports of the tasks defined within this
// module. Run through them now.
typedef map<perm_string,PTask*>::const_iterator mtask_it_t;
for (mtask_it_t cur = tasks_.begin()
; cur != tasks_.end() ; cur ++) {
NetScope*tscope = scope->child( hname_t((*cur).first) );
assert(tscope);
(*cur).second->elaborate_sig(des, tscope);
}
elaborate_sig_funcs(des, scope, funcs);
elaborate_sig_tasks(des, scope, tasks);
// initial and always blocks may contain begin-end and
// fork-join blocks that can introduce scopes. Therefore, I
@@ -256,7 +286,7 @@ bool PEIdent::elaborate_sig(Design*des, NetScope*scope) const
if (error_implicit)
return true;
symbol_search(des, scope, path_, sig, par, eve);
symbol_search(this, des, scope, path_, sig, par, eve);
if (eve != 0)
return false;
@@ -351,11 +381,11 @@ bool PGModule::elaborate_sig_mod_(Design*des, NetScope*scope,
continue;
flag = tmp->elaborate_sig(des, scope) && flag;
}
NetScope::scope_vec_t instance = scope->instance_arrays[get_name()];
for (unsigned idx = 0 ; idx < instance.count() ; idx += 1) {
for (unsigned idx = 0 ; idx < instance.size() ; idx += 1) {
// I know a priori that the elaborate_scope created the scope
// already, so just look it up as a child of the current scope.
NetScope*my_scope = instance[idx];
@@ -402,6 +432,9 @@ bool PGModule::elaborate_sig_udp_(Design*des, NetScope*scope, PUdp*udp) const
bool PGenerate::elaborate_sig(Design*des, NetScope*container) const
{
if (direct_nested_)
return elaborate_sig_direct_(des, container);
bool flag = true;
// Handle the special case that this is a CASE scheme. In this
@@ -415,10 +448,10 @@ bool PGenerate::elaborate_sig(Design*des, NetScope*container) const
<< scope_path(container) << "." << endl;
typedef list<PGenerate*>::const_iterator generate_it_t;
for (generate_it_t cur = generates.begin()
; cur != generates.end() ; cur ++) {
for (generate_it_t cur = generate_schemes.begin()
; cur != generate_schemes.end() ; cur ++) {
PGenerate*item = *cur;
if (! item->scope_list_.empty()) {
if (item->direct_nested_ || !item->scope_list_.empty()) {
flag &= item->elaborate_sig(des, container);
}
}
@@ -444,6 +477,32 @@ bool PGenerate::elaborate_sig(Design*des, NetScope*container) const
return flag;
}
bool PGenerate::elaborate_sig_direct_(Design*des, NetScope*container) const
{
if (debug_elaborate)
cerr << get_fileline() << ": debug: "
<< "Direct nesting " << scope_name
<< " (scheme_type=" << scheme_type << ")"
<< " elaborate_sig in scope "
<< scope_path(container) << "." << endl;
// Elaborate_sig for a direct nested generated scheme knows
// that there are only sub_schemes to be elaborated. There
// should be exactly 1 active generate scheme, search for it
// using this loop.
bool flag = true;
typedef list<PGenerate*>::const_iterator generate_it_t;
for (generate_it_t cur = generate_schemes.begin()
; cur != generate_schemes.end() ; cur ++) {
PGenerate*item = *cur;
if (item->direct_nested_ || !item->scope_list_.empty()) {
// Found the item, and it is direct nested.
flag &= item->elaborate_sig(des, container);
}
}
return flag;
}
bool PGenerate::elaborate_sig_(Design*des, NetScope*scope) const
{
// Scan the declared PWires to elaborate the obvious signals
@@ -461,9 +520,12 @@ bool PGenerate::elaborate_sig_(Design*des, NetScope*scope) const
cur->elaborate_sig(des, scope);
}
elaborate_sig_funcs(des, scope, funcs);
elaborate_sig_tasks(des, scope, tasks);
typedef list<PGenerate*>::const_iterator generate_it_t;
for (generate_it_t cur = generates.begin()
; cur != generates.end() ; cur ++ ) {
for (generate_it_t cur = generate_schemes.begin()
; cur != generate_schemes.end() ; cur ++ ) {
(*cur) -> elaborate_sig(des, scope);
}
@@ -473,6 +535,13 @@ bool PGenerate::elaborate_sig_(Design*des, NetScope*scope) const
(*cur) ->elaborate_sig(des, scope);
}
typedef list<PProcess*>::const_iterator proc_it_t;
for (proc_it_t cur = behaviors.begin()
; cur != behaviors.end() ; cur ++ ) {
(*cur) -> statement() -> elaborate_sig(des, scope);
}
return true;
}
@@ -510,12 +579,19 @@ void PFunction::elaborate_sig(Design*des, NetScope*scope) const
case PTF_REG:
case PTF_REG_S:
if (return_type_.range) {
NetExpr*me = elab_and_eval(des, scope,
NetScope*parent = scope->parent();
probe_expr_width(des, parent, (*return_type_.range)[0]);
probe_expr_width(des, parent, (*return_type_.range)[1]);
need_constant_expr = true;
NetExpr*me = elab_and_eval(des, parent,
(*return_type_.range)[0], -1);
assert(me);
NetExpr*le = elab_and_eval(des, scope,
NetExpr*le = elab_and_eval(des, parent,
(*return_type_.range)[1], -1);
assert(le);
need_constant_expr = false;
long mnum = 0, lnum = 0;
if (NetEConst*tmp = dynamic_cast<NetEConst*>(me)) {
@@ -537,9 +613,11 @@ void PFunction::elaborate_sig(Design*des, NetScope*scope) const
}
ret_sig = new NetNet(scope, fname, NetNet::REG, mnum, lnum);
ret_sig->set_scalar(false);
} else {
ret_sig = new NetNet(scope, fname, NetNet::REG);
ret_sig->set_scalar(true);
}
ret_sig->set_line(*this);
ret_sig->set_signed(return_type_.type == PTF_REG_S);
@@ -552,6 +630,7 @@ void PFunction::elaborate_sig(Design*des, NetScope*scope) const
ret_sig->set_line(*this);
ret_sig->set_signed(true);
ret_sig->set_isint(true);
ret_sig->set_scalar(false);
ret_sig->port_type(NetNet::POUTPUT);
ret_sig->data_type(IVL_VT_LOGIC);
break;
@@ -561,6 +640,7 @@ void PFunction::elaborate_sig(Design*des, NetScope*scope) const
ret_sig->set_line(*this);
ret_sig->set_signed(false);
ret_sig->set_isint(false);
ret_sig->set_scalar(false);
ret_sig->port_type(NetNet::POUTPUT);
ret_sig->data_type(IVL_VT_LOGIC);
break;
@@ -571,14 +651,23 @@ void PFunction::elaborate_sig(Design*des, NetScope*scope) const
ret_sig->set_line(*this);
ret_sig->set_signed(true);
ret_sig->set_isint(false);
ret_sig->set_scalar(true);
ret_sig->port_type(NetNet::POUTPUT);
ret_sig->data_type(IVL_VT_REAL);
break;
default:
cerr << get_fileline() << ": internal error: I don't know how "
<< "to deal with return type of function "
<< scope->basename() << "." << endl;
if (ports_) {
cerr << get_fileline() << ": internal error: I don't know "
<< "how to deal with return type of function "
<< scope->basename() << "." << endl;
} else {
/* If we do not have any ports or a return type this
* is probably a bad function definition. */
cerr << get_fileline() << ": error: Bad definition for "
<< "function " << scope->basename() << "?" << endl;
return;
}
}
svector<NetNet*>ports (ports_? ports_->count() : 0);
@@ -773,79 +862,146 @@ void PWhile::elaborate_sig(Design*des, NetScope*scope) const
/*
* Elaborate a source wire. The "wire" is the declaration of wires,
* registers, ports and memories. The parser has already merged the
* multiple properties of a wire (i.e., "input wire") so come the
* elaboration this creates an object in the design that represent the
* multiple properties of a wire (i.e., "input wire"), so come the
* elaboration this creates an object in the design that represents the
* defined item.
*/
NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
{
NetNet::Type wtype = type_;
if (wtype == NetNet::IMPLICIT)
bool is_implicit_scalar = false;
if (wtype == NetNet::IMPLICIT) {
wtype = NetNet::WIRE;
if (wtype == NetNet::IMPLICIT_REG)
is_implicit_scalar = true;
}
if (wtype == NetNet::IMPLICIT_REG) {
wtype = NetNet::REG;
is_implicit_scalar = true;
}
unsigned wid = 1;
long lsb = 0, msb = 0;
des->errors += error_cnt_;
// A signal can not have the same name as a scope object.
const NetScope *child = scope->child(hname_t(name_));
if (child) {
cerr << get_fileline() << ": error: signal and ";
child->print_type(cerr);
cerr << " in '" << scope->fullname()
<< "' have the same name '" << name_ << "'." << endl;
des->errors += 1;
}
// A signal can not have the same name as a genvar.
const LineInfo *genvar = scope->find_genvar(name_);
if (genvar) {
cerr << get_fileline() << ": error: signal and genvar in '"
<< scope->fullname() << "' have the same name '" << name_
<< "'." << endl;
des->errors += 1;
}
// A signal can not have the same name as a parameter.
const NetExpr *ex_msb, *ex_lsb;
const NetExpr *parm = scope->get_parameter(name_, ex_msb, ex_lsb);
if (parm) {
cerr << get_fileline() << ": error: signal and parameter in '"
<< scope->fullname() << "' have the same name '" << name_
<< "'." << endl;
des->errors += 1;
}
// A signal can not have the same name as a named event.
const NetEvent *event = scope->find_event(name_);
if (event) {
cerr << get_fileline() << ": error: signal and named event in '"
<< scope->fullname() << "' have the same name '" << name_
<< "'." << endl;
des->errors += 1;
}
if (port_set_ || net_set_) {
long pmsb = 0, plsb = 0, nmsb = 0, nlsb = 0;
bool bad_lsb = false, bad_msb = false;
/* If they exist get the port definition MSB and LSB */
if (port_set_ && port_msb_ != 0) {
probe_expr_width(des, scope, port_msb_);
/* We do not currently support constant user function. */
need_constant_expr = true;
NetExpr*texpr = elab_and_eval(des, scope, port_msb_, -1);
need_constant_expr = false;
if (! eval_as_long(pmsb, texpr)) {
cerr << port_msb_->get_fileline() << ": error: "
"Unable to evaluate MSB constant expression ``"
<< *port_msb_ << "''." << endl;
"Range expressions must be constant." << endl;
cerr << port_msb_->get_fileline() << " : "
"This MSB expression violates the rule: "
<< *port_msb_ << endl;
des->errors += 1;
return 0;
bad_msb = true;
}
delete texpr;
probe_expr_width(des, scope, port_lsb_);
/* We do not currently support constant user function. */
need_constant_expr = true;
texpr = elab_and_eval(des, scope, port_lsb_, -1);
need_constant_expr = false;
if (! eval_as_long(plsb, texpr)) {
cerr << port_lsb_->get_fileline() << ": error: "
"Unable to evaluate LSB constant expression ``"
<< *port_lsb_ << "''." << endl;
"Range expressions must be constant." << endl;
cerr << port_lsb_->get_fileline() << " : "
"This LSB expression violates the rule: "
<< *port_lsb_ << endl;
des->errors += 1;
return 0;
bad_lsb = true;
}
delete texpr;
nmsb = pmsb;
nlsb = plsb;
/* An implicit port can have a range so note that here. */
is_implicit_scalar = false;
}
if (!port_set_) assert(port_msb_ == 0 && port_lsb_ == 0);
if (port_msb_ == 0) assert(port_lsb_ == 0);
if (port_lsb_ == 0) assert(port_msb_ == 0);
/* If they exist get the net/etc. definition MSB and LSB */
if (net_set_ && net_msb_ != 0) {
if (net_set_ && net_msb_ != 0 && !bad_msb && !bad_lsb) {
probe_expr_width(des, scope, net_msb_);
/* We do not currently support constant user function. */
need_constant_expr = true;
NetExpr*texpr = elab_and_eval(des, scope, net_msb_, -1);
need_constant_expr = false;
if (! eval_as_long(nmsb, texpr)) {
cerr << net_msb_->get_fileline() << ": error: "
"Unable to evaluate MSB constant expression ``"
<< *net_msb_ << "''." << endl;
"Range expressions must be constant." << endl;
cerr << net_msb_->get_fileline() << " : "
"This MSB expression violates the rule: "
<< *net_msb_ << endl;
des->errors += 1;
return 0;
bad_msb = true;
}
delete texpr;
probe_expr_width(des, scope, net_lsb_);
/* We do not currently support constant user function. */
need_constant_expr = true;
texpr = elab_and_eval(des, scope, net_lsb_, -1);
need_constant_expr = false;
if (! eval_as_long(nlsb, texpr)) {
cerr << net_lsb_->get_fileline() << ": error: "
"Unable to evaluate LSB constant expression ``"
<< *net_lsb_ << "''." << endl;
"Range expressions must be constant." << endl;
cerr << net_lsb_->get_fileline() << " : "
"This LSB expression violates the rule: "
<< *net_lsb_ << endl;
des->errors += 1;
return 0;
bad_lsb = true;
}
delete texpr;
@@ -898,6 +1054,10 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
}
}
/* Attempt to recover from errors. */
if (bad_lsb) nlsb = 0;
if (bad_msb) nmsb = nlsb;
lsb = nlsb;
msb = nmsb;
if (nmsb > nlsb)
@@ -923,8 +1083,13 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
if (lidx_ || ridx_) {
assert(lidx_ && ridx_);
probe_expr_width(des, scope, lidx_);
probe_expr_width(des, scope, ridx_);
need_constant_expr = true;
NetExpr*lexp = elab_and_eval(des, scope, lidx_, -1);
NetExpr*rexp = elab_and_eval(des, scope, ridx_, -1);
need_constant_expr = false;
if ((lexp == 0) || (rexp == 0)) {
cerr << get_fileline() << ": internal error: There is "
@@ -942,16 +1107,29 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
delete lexp;
if (!const_flag) {
cerr << get_fileline() << ": internal error: The indices "
cerr << get_fileline() << ": error: The indices "
<< "are not constant for array ``"
<< name_ << "''." << endl;
des->errors += 1;
return 0;
}
/* Attempt to recover from error, */
array_s0 = 0;
array_e0 = 0;
} else {
array_s0 = lval.as_long();
array_e0 = rval.as_long();
}
array_dimensions = 1;
array_s0 = lval.as_long();
array_e0 = rval.as_long();
}
if (data_type_ == IVL_VT_REAL && (msb != 0 || lsb != 0)) {
cerr << get_fileline() << ": error: real ";
if (wtype == NetNet::REG) cerr << "variable";
else cerr << "net";
cerr << " '" << name_
<< "' cannot be declared as a vector, found a range ["
<< msb << ":" << lsb << "]." << endl;
des->errors += 1;
return 0;
}
/* If the net type is supply0 or supply1, replace it
@@ -983,15 +1161,23 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
if (debug_elaborate) {
cerr << get_fileline() << ": debug: "
<< "Generate a SUPPLY pulldown for the "
<< "supply0 net." << endl;
<< "Generate a SUPPLY pull for the ";
if (wtype == NetNet::SUPPLY0) cerr << "supply0";
else cerr << "supply1";
cerr << " net." << endl;
}
}
if (debug_elaborate) {
cerr << get_fileline() << ": debug: Create signal "
<< wtype << " ["<<msb<<":"<<lsb<<"] " << name_
<< " in scope " << scope_path(scope) << endl;
cerr << get_fileline() << ": debug: Create signal " << wtype;
if (!get_scalar()) {
cerr << " ["<<msb<<":"<<lsb<<"]";
}
cerr << " " << name_;
if (array_dimensions > 0) {
cerr << " [" << array_s0 << ":" << array_e0 << "]" << endl;
}
cerr << " in scope " << scope_path(scope) << endl;
}
@@ -999,6 +1185,8 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
? new NetNet(scope, name_, wtype, msb, lsb, array_s0, array_e0)
: new NetNet(scope, name_, wtype, msb, lsb);
if (wtype == NetNet::WIRE) sig->devirtualize_pins();
ivl_variable_type_t use_data_type = data_type_;
if (use_data_type == IVL_VT_NO_TYPE) {
use_data_type = IVL_VT_LOGIC;
@@ -1015,6 +1203,12 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
sig->port_type(port_type_);
sig->set_signed(get_signed());
sig->set_isint(get_isint());
if (is_implicit_scalar) sig->set_scalar(true);
else sig->set_scalar(get_scalar());
if (ivl_discipline_t dis = get_discipline()) {
sig->set_discipline(dis);
}
if (pull)
connect(sig->pin(0), pull->pin(0));
+26
View File
@@ -0,0 +1,26 @@
/*
* Copyright (c) 2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
# include "config.h"
# include "AStatement.h"
# include <cstdlib>
# include <iostream>
+1708 -855
View File
File diff suppressed because it is too large Load Diff
+74
View File
@@ -0,0 +1,74 @@
/*
* Copyright (c) 2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
# include "config.h"
# include "AStatement.h"
# include "netlist.h"
# include "netmisc.h"
# include "util.h"
# include <typeinfo>
NetProc* AContrib::elaborate(Design*des, NetScope*scope) const
{
probe_expr_width(des, scope, lval_);
probe_expr_width(des, scope, rval_);
NetExpr*lval = elab_and_eval(des, scope, lval_, -1);
NetExpr*rval = elab_and_eval(des, scope, rval_, -1);
NetEAccess*lacc = dynamic_cast<NetEAccess*> (lval);
if (lacc == 0) {
cerr << get_fileline() << ": error: The l-value of a contribution"
<< " statement must be a branch probe access function." << endl;
des->errors += 1;
return 0;
}
NetContribution*st = new NetContribution(lacc, rval);
st->set_line(*this);
return st;
}
bool AProcess::elaborate(Design*des, NetScope*scope) const
{
NetProc*estatement = statement_->elaborate(des, scope);
if (estatement == 0)
return false;
NetAnalogTop*top = new NetAnalogTop(scope, type_, estatement);
// Evaluate the attributes for this process, if there
// are any. These attributes are to be attached to the
// NetProcTop object.
struct attrib_list_t*attrib_list = 0;
unsigned attrib_list_n = 0;
attrib_list = evaluate_attributes(attributes, attrib_list_n, des, scope);
for (unsigned adx = 0 ; adx < attrib_list_n ; adx += 1)
top->attribute(attrib_list[adx].key,
attrib_list[adx].val);
delete[]attrib_list;
top->set_line(*this);
des->add_process(top);
return true;
}
+60 -32
View File
@@ -72,6 +72,16 @@ bool NetCaseCmp::emit_node(struct target_t*tgt) const
return true;
}
bool NetCastInt::emit_node(struct target_t*tgt) const
{
return tgt->lpm_cast_int(this);
}
bool NetCastReal::emit_node(struct target_t*tgt) const
{
return tgt->lpm_cast_real(this);
}
bool NetCLShift::emit_node(struct target_t*tgt) const
{
tgt->lpm_clshift(this);
@@ -180,16 +190,26 @@ bool NetProcTop::emit(struct target_t*tgt) const
return tgt->process(this);
}
bool NetAnalogTop::emit(struct target_t*tgt) const
{
return tgt->process(this);
}
bool NetProc::emit_proc(struct target_t*tgt) const
{
cerr << "EMIT: Proc type? " << typeid(*this).name() << endl;
return false;
}
bool NetAlloc::emit_proc(struct target_t*tgt) const
{
tgt->proc_alloc(this);
return true;
}
bool NetAssign::emit_proc(struct target_t*tgt) const
{
tgt->proc_assign(this);
return true;
return tgt->proc_assign(this);
}
bool NetAssignNB::emit_proc(struct target_t*tgt) const
@@ -219,6 +239,11 @@ bool NetCondit::emit_proc(struct target_t*tgt) const
return tgt->proc_condit(this);
}
bool NetContribution::emit_proc(struct target_t*tgt) const
{
return tgt->proc_contribution(this);
}
bool NetDeassign::emit_proc(struct target_t*tgt) const
{
return tgt->proc_deassign(this);
@@ -240,6 +265,12 @@ bool NetForever::emit_proc(struct target_t*tgt) const
return true;
}
bool NetFree::emit_proc(struct target_t*tgt) const
{
tgt->proc_free(this);
return true;
}
bool NetPDelay::emit_proc(struct target_t*tgt) const
{
return tgt->proc_delay(this);
@@ -352,23 +383,20 @@ void NetScope::emit_scope(struct target_t*tgt) const
for (NetScope*cur = sub_ ; cur ; cur = cur->sib_)
cur->emit_scope(tgt);
if (signals_) {
NetNet*cur = signals_->sig_next_;
do {
tgt->signal(cur);
cur = cur->sig_next_;
} while (cur != signals_->sig_next_);
for (signals_map_iter_t cur = signals_map_.begin()
; cur != signals_map_.end() ; cur ++) {
tgt->signal(cur->second);
}
/* Run the signals again, but this time to connect the
delay paths. This is done as a second pass because
the paths reference other signals that may be later
in the list. We can do it here becase delay paths are
always connected within the scope. */
cur = signals_->sig_next_;
do {
tgt->signal_paths(cur);
cur = cur->sig_next_;
} while (cur != signals_->sig_next_);
// Run the signals again, but this time to connect the
// delay paths. This is done as a second pass because
// the paths reference other signals that may be later
// in the list. We can do it here because delay paths are
// always connected within the scope.
for (signals_map_iter_t cur = signals_map_.begin()
; cur != signals_map_.end() ; cur ++) {
tgt->signal_paths(cur->second);
}
}
@@ -427,6 +455,11 @@ int Design::emit(struct target_t*tgt) const
}
bool branches_rc = true;
for (NetBranch*cur = branches_ ; cur ; cur = cur->next_) {
branches_rc = tgt->branch(cur) && branches_rc;
}
// emit task and function definitions
bool tasks_rc = true;
for (list<NetScope*>::const_iterator scope = root_scopes_.begin();
@@ -438,6 +471,8 @@ int Design::emit(struct target_t*tgt) const
bool proc_rc = true;
for (const NetProcTop*idx = procs_ ; idx ; idx = idx->next_)
proc_rc &= idx->emit(tgt);
for (const NetAnalogTop*idx = aprocs_ ; idx ; idx = idx->next_)
proc_rc &= idx->emit(tgt);
rc = tgt->end_design(this);
@@ -447,10 +482,17 @@ int Design::emit(struct target_t*tgt) const
return -2;
if (proc_rc == false)
return -3;
if (branches_rc == false)
return -4;
return rc;
}
void NetEAccess::expr_scan(struct expr_scan_t*tgt) const
{
tgt->expr_access_func(this);
}
void NetEBinary::expr_scan(struct expr_scan_t*tgt) const
{
tgt->expr_binary(this);
@@ -526,17 +568,3 @@ void NetEUnary::expr_scan(struct expr_scan_t*tgt) const
{
tgt->expr_unary(this);
}
int emit(const Design*des, const char*type)
{
for (unsigned idx = 0 ; target_table[idx] ; idx += 1) {
const struct target*tgt = target_table[idx];
if (strcmp(tgt->name, type) == 0)
return des->emit(tgt->meth);
}
cerr << "error: Code generator type " << type
<< " not found." << endl;
return -1;
}
+10 -2
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1998-1999 Stephen Williams (steve@icarus.com)
* Copyright (c) 1998-2014 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -44,6 +44,14 @@ verinum* PEBinary::eval_const(Design*des, NetScope*scope) const
verinum*res;
switch (op_) {
case 'p': {
if (l->is_defined() && r->is_defined()) {
res = new verinum(pow(*l, *r));
} else {
res = new verinum(verinum::Vx, l->len());
}
break;
}
case '+': {
if (l->is_defined() && r->is_defined()) {
res = new verinum(*l + *r);
@@ -185,7 +193,7 @@ verinum* PEIdent::eval_const(Design*des, NetScope*scope) const
return new verinum(scope->genvar_tmp_val);
}
symbol_search(des, scope, path_, net, expr, eve);
symbol_search(this, des, scope, path_, net, expr, eve);
if (expr == 0)
return 0;
+12 -47
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2002-2004 Stephen Williams (steve@icarus.com)
* Copyright (c) 2002-2010 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,16 +16,13 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: eval_attrib.cc,v 1.9 2007/06/04 19:14:06 steve Exp $"
#endif
# include "config.h"
# include "util.h"
# include "PExpr.h"
# include "netlist.h"
# include <iostream>
# include <assert.h>
# include <cassert>
/*
* The evaluate_attributes function evaluates the attribute
@@ -53,14 +50,19 @@ attrib_list_t* evaluate_attributes(const map<perm_string,PExpr*>&att,
/* If the attribute value is given in the source, then
evaluate it as a constant. If the value is not
given, then assume the value is 1. */
verinum*tmp;
if (exp)
verinum*tmp = 0;
if (exp) {
tmp = exp->eval_const(des, scope);
else
if (tmp == 0) {
cerr << exp->get_fileline() << ": error: ``"
<< *exp << "'' is not a constant expression."
<< endl;
des->errors += 1;
}
}
if (tmp == 0)
tmp = new verinum(1);
if (tmp == 0)
cerr << "internal error: no result for " << *exp << endl;
assert(tmp);
table[idx].val = *tmp;
@@ -70,40 +72,3 @@ attrib_list_t* evaluate_attributes(const map<perm_string,PExpr*>&att,
assert(idx == natt);
return table;
}
/*
* $Log: eval_attrib.cc,v $
* Revision 1.9 2007/06/04 19:14:06 steve
* Build errors in picky GCC compilers.
*
* Revision 1.8 2005/11/27 17:01:57 steve
* Fix for stubborn compiler.
*
* Revision 1.7 2004/02/20 18:53:35 steve
* Addtrbute keys are perm_strings.
*
* Revision 1.6 2003/01/27 05:09:17 steve
* Spelling fixes.
*
* Revision 1.5 2002/08/12 01:34:59 steve
* conditional ident string using autoconfig.
*
* Revision 1.4 2002/08/10 21:59:39 steve
* The default attribute value is 1.
*
* Revision 1.3 2002/06/06 18:57:18 steve
* Use standard name for iostream.
*
* Revision 1.2 2002/06/03 03:55:14 steve
* compile warnings.
*
* Revision 1.1 2002/05/23 03:08:51 steve
* Add language support for Verilog-2001 attribute
* syntax. Hook this support into existing $attribute
* handling, and add number and void value types.
*
* Add to the ivl_target API new functions for access
* of complex attributes attached to gates.
*
*/
+666 -199
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-3
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@@ -1,3 +0,0 @@
,*
hello_vpi.vpi
show_vcd.vcd
-1035
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+4 -4
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@@ -55,12 +55,12 @@
module register (out, val, clk, oe);
output [7:0] out;
input [7:0] val;
input clk, oe;
input [7:0] val;
input clk, oe;
reg [7:0] Q;
reg [7:0] Q;
wire [7:0] out;
wire [7:0] out;
bufif0 drv[7:0](out, Q, oe);
+3 -3
View File
@@ -154,7 +154,7 @@
*
* The POST_MAP compiler directive causes the GSR manipulations
* included in the test bench to be compiled in, to simulate the chip
* startup. Other then that, the test bench runs the post-map design
* startup. Other than that, the test bench runs the post-map design
* the same way the pre-synthesis design works.
*
* Run this design with the command:
@@ -252,7 +252,7 @@ endmodule // sqrt32
module main;
reg [31:0] x;
reg clk, reset;
reg clk, reset;
wire [15:0] y;
wire rdy;
@@ -354,7 +354,7 @@ module chip_root(clk, rdy, reset, x, y);
input [31:0] x;
output [15:0] y;
wire clk_int;
wire clk_int;
(* cellref="BUFG:O,I" *)
buf gbuf (clk_int, clk);
+505 -188
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+5 -13
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@@ -111,20 +111,12 @@ void NetScope::run_functor(Design*des, functor_t*fun)
// apply to signals. Each iteration, allow for the possibility
// that the current signal deletes itself.
if (signals_) {
unsigned count = 0;
NetNet*cur = signals_->sig_next_;
do {
count += 1;
cur = cur->sig_next_;
} while (cur != signals_->sig_next_);
cur = signals_->sig_next_;
for (unsigned idx = 0 ; idx < count ; idx += 1) {
NetNet*tmp = cur->sig_next_;
fun->signal(des, cur);
cur = tmp;
}
signals_map_iter_t cur = signals_map_.begin();
while (cur != signals_map_.end()) {
signals_map_iter_t tmp = cur;
cur ++;
fun->signal(des, tmp->second);
}
}
-62
View File
@@ -499,65 +499,3 @@ already seems to exist amongst VCD viewers in the wild, this behavior
seems to be acceptable according to the standard, is a better mirror
of 4-value behavior in the dead zone, and appears more user friendly
when viewed by reasonable viewers.
$Id: ieee1364-notes.txt,v 1.19 2007/04/18 02:36:13 steve Exp $
$Log: ieee1364-notes.txt,v $
Revision 1.19 2007/04/18 02:36:13 steve
Put to iverilog wiki for further notes.
Revision 1.18 2007/03/22 16:08:16 steve
Spelling fixes from Larry
Revision 1.17 2003/07/15 03:49:22 steve
Spelling fixes.
Revision 1.16 2003/04/14 03:40:21 steve
Make some effort to preserve bits while
operating on constant values.
Revision 1.15 2003/02/16 23:39:08 steve
NaN in dead zones of VCD dumps.
Revision 1.14 2003/02/06 17:51:36 steve
Edge of vectors notes.
Revision 1.13 2002/08/20 04:11:53 steve
Support parameters with defined ranges.
Revision 1.12 2002/06/11 03:34:33 steve
Spelling patch (Larry Doolittle)
Revision 1.11 2002/04/27 02:38:04 steve
Support selecting bits from parameters.
Revision 1.10 2002/03/31 01:54:13 steve
Notes about scheduling
Revision 1.9 2002/01/26 02:08:07 steve
Handle x in l-value of set/x
Revision 1.8 2001/08/01 05:17:31 steve
Accept empty port lists to module instantiation.
Revision 1.7 2001/02/17 05:27:31 steve
I allow function ports to have types.
Revision 1.6 2001/02/12 16:48:04 steve
Rant about bit widths.
Revision 1.5 2001/01/02 17:28:08 steve
Resolve repeat ambiguity in favor of loop.
Revision 1.4 2001/01/01 19:12:35 steve
repeat loops ambiguity.
Revision 1.3 2000/12/15 00:21:46 steve
rounding of time and x in primitives.
Revision 1.2 2000/11/19 22:03:04 steve
Integer parameter comments.
Revision 1.1 2000/07/23 18:06:31 steve
Document ieee1364 issues.
+11 -12
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@@ -1,15 +1,15 @@
.TH iverilog-vpi 1 "$Date: 2004/10/04 01:10:53 $" Version "$Date: 2004/10/04 01:10:53 $"
.TH iverilog-vpi 1 "April 17th, 2009" "" "Version %M.%m.%n %E"
.SH NAME
iverilog-vpi - Compile front end for VPI modules
.SH SYNOPSIS
.B iverilog-vpi
[--name=\fIname\fP]
[\-\-name=\fIname\fP]
\fIsourcefile\fP...
.SH DESCRIPTION
.PP
\fIiverilog-vpi\fP is a tool to simplify the compilation of VPI
\fIiverilog\-vpi\fP is a tool to simplify the compilation of VPI
modules for use with Icarus Verilog. It takes on the command line a
list of C or C++ source files, and generates as output a linked VPI
module. See the \fBvvp\fP(1) man page for a description of how the
@@ -20,8 +20,7 @@ first source file is named \fIfoo.c\fP, the output becomes
\fIfoo.vpi\fP.
.SH OPTIONS
.l
\fIiverilog-vpi\fP accepts the following options:
\fIiverilog\-vpi\fP accepts the following options:
.TP 8
.B -l\fIlibrary\fP
Include the named library in the link of the VPI module. This allows
@@ -49,12 +48,12 @@ modules, then exit. It is a convenience for makefiles or automated
plug-in installers.
.TP 8
.B --cflags, --ldflags and -ldlibs
.B --cflags, --ldflags and --ldlibs
These flags provide compile time information.
.SH "PC-ONLY OPTIONS"
The PC port of \fIiverilog-vpi\fP includes two special flags needed to
The PC port of \fIiverilog\-vpi\fP includes two special flags needed to
support the more intractable development environment. These flags help
the program locate parts that it needs.
@@ -62,7 +61,7 @@ the program locate parts that it needs.
.B -mingw=\fIpath\fP
Tell the program the root of the Mingw compiler tool suite. The
\fBvvp\fP runtime is compiled with this compiler, and this is the
compiler that \fIiverilog-vpi\fP expects to use to compile your source
compiler that \fIiverilog\-vpi\fP expects to use to compile your source
code. This is normally not needed, and if you do use it, it is only
needed once. The compiler will save the \fIpath\fP in the registry for
use later.
@@ -76,7 +75,7 @@ stored in the registry for future use.
.SH "UNIX-ONLY OPTIONS"
The UNIX version of \fIiverilog-vpi\fP includes additional flags to
The UNIX version of \fIiverilog\-vpi\fP includes additional flags to
let Makefile gurus peek at the configuration of the \fIiverilog\fP
installation. This way, Makefiles can be written that handle complex VPI
builds natively, and without hard-coding values that depend on the
@@ -104,9 +103,9 @@ requests a 32bit vpi binary instead of the default 64bit binary.
.P
Example GNU makefile that takes advantage of these flags:
.IP "" 4
CFLAGS = -Wall -O $(CFLAGS_$@)
CFLAGS = \-Wall \-O $(CFLAGS_$@)
.br
VPI_CFLAGS := $(shell iverilog-vpi --cflags)
VPI_CFLAGS := $(shell iverilog-vpi \-\-cflags)
.br
CFLAGS_messagev.o = $(VPI_CFLAGS)
.br
@@ -129,7 +128,7 @@ iverilog(1), vvp(1),
.SH COPYRIGHT
.nf
Copyright \(co 2002 Stephen Williams
Copyright \(co 2002\-2009 Stephen Williams
This document can be freely redistributed according to the terms of the
GNU General Public License version 2.0
+5 -4
View File
@@ -17,17 +17,18 @@
# 59 Temple Place - Suite 330
# Boston, MA 02111-1307, USA
#
#ident "$Id: iverilog-vpi.sh,v 1.17 2007/02/06 05:07:31 steve Exp $"
# These are the variables used for compiling files
CC=@IVCC@
CC="@IVCC@"
CXX=@IVCXX@
CFLAGS="@PIC@ @IVCFLAGS@ -I@INCLUDEDIR@"
SUFFIX=@SUFFIX@
# These are used for linking...
LD=$CC
LDFLAGS="@SHARED@ -L@LIBDIR@"
LDLIBS="-lveriuser -lvpi"
LDLIBS="-lveriuser$SUFFIX -lvpi$SUFFIX"
CCSRC=
CXSRC=
@@ -101,7 +102,7 @@ do
;;
--install-dir)
echo "@LIBDIR@/ivl"
echo "@LIBDIR@/ivl$SUFFIX"
exit
;;
esac

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