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https://github.com/steveicarus/iverilog.git
synced 2026-09-08 04:20:49 +02:00
Report an error when trying to take the select of a real value.
This patch adds checks in various places to prevent the user from
taking a select of a real value (bit, part and indexed selects).
(cherry picked from commit 5852f1eb7a)
This commit is contained in:
@@ -2354,6 +2354,14 @@ NetExpr* PEIdent::elaborate_expr_param_(Design*des,
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if (!name_tail.index.empty())
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use_sel = name_tail.index.back().sel;
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if (par->expr_type() == IVL_VT_REAL &&
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use_sel != index_component_t::SEL_NONE) {
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cerr << get_fileline() << ": error: "
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<< "Can not select part of a real parameter value." << endl;
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des->errors += 1;
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return 0;
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}
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// NOTE TO SELF: This is the way I want to see this code
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// structured. This closely follows the structure of the
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// elaborate_expr_net_ code, which splits all the various
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@@ -2626,6 +2634,14 @@ NetExpr* PEIdent::elaborate_expr_net_word_(Design*des, NetScope*scope,
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if (name_tail.index.size() > 1)
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word_sel = name_tail.index.back().sel;
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if (res->expr_type() == IVL_VT_REAL &&
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word_sel != index_component_t::SEL_NONE) {
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cerr << get_fileline() << ": error: "
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<< "Can not select part of a real array word." << endl;
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des->errors += 1;
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return 0;
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}
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if (word_sel == index_component_t::SEL_PART)
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return elaborate_expr_net_part_(des, scope, res, found_in);
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@@ -2920,6 +2936,14 @@ NetExpr* PEIdent::elaborate_expr_net(Design*des, NetScope*scope,
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if (! path_.back().index.empty())
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use_sel = path_.back().index.back().sel;
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if (node->expr_type() == IVL_VT_REAL &&
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use_sel != index_component_t::SEL_NONE) {
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cerr << get_fileline() << ": error: "
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<< "Can not select part of a real value." << endl;
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des->errors += 1;
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return 0;
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}
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// If this is a part select of a signal, then make a new
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// temporary signal that is connected to just the
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// selected bits. The lsb_ and msb_ expressions are from
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@@ -195,6 +195,15 @@ NetAssign_* PEIdent::elaborate_lval(Design*des,
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if (reg->array_dimensions() > 0)
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return elaborate_lval_net_word_(des, scope, reg);
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// This must be after the array word elaboration above!
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if (reg->data_type() == IVL_VT_REAL &&
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use_sel != index_component_t::SEL_NONE) {
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cerr << get_fileline() << ": error: "
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<< "Can not select part of a real value." << endl;
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des->errors += 1;
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return 0;
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}
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if (use_sel == index_component_t::SEL_PART) {
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NetAssign_*lv = new NetAssign_(reg);
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elaborate_lval_net_part_(des, scope, lv);
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@@ -289,6 +298,14 @@ NetAssign_* PEIdent::elaborate_lval_net_word_(Design*des,
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if (name_tail.index.size() > 1)
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use_sel = name_tail.index.back().sel;
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if (reg->data_type() == IVL_VT_REAL &&
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use_sel != index_component_t::SEL_NONE) {
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cerr << get_fileline() << ": error: "
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<< "Can not select part of a real array word." << endl;
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des->errors += 1;
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return 0;
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}
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if (use_sel == index_component_t::SEL_BIT)
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elaborate_lval_net_bit_(des, scope, lv);
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+15
@@ -460,6 +460,14 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
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/* The array has a part/bit select at the end. */
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if (name_tail.index.size() > sig->array_dimensions()) {
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if (sig->data_type() == IVL_VT_REAL) {
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cerr << get_fileline() << ": error: "
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<< "Can not select part of a real array word."
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<< endl;
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des->errors += 1;
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return 0;
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}
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long midx_tmp, lidx_tmp;
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if (! eval_part_select_(des, scope, sig, midx_tmp, lidx_tmp))
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return 0;
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@@ -475,6 +483,13 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
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lidx = lidx_tmp;
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}
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} else if (!name_tail.index.empty()) {
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if (sig->data_type() == IVL_VT_REAL) {
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cerr << get_fileline() << ": error: "
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<< "Can not select part of a real value." << endl;
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des->errors += 1;
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return 0;
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}
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long midx_tmp, lidx_tmp;
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if (! eval_part_select_(des, scope, sig, midx_tmp, lidx_tmp))
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return 0;
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+3
-1
@@ -625,7 +625,9 @@ void PGBuiltin::elaborate(Design*des, NetScope*scope) const
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return;
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}
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lval_sigs[idx] = pin(idx)->elaborate_lnet(des, scope);
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ivl_assert(*this, lval_sigs[idx]);
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// The only way this should return zero is if an error
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// happened, so for that case just return.
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if (lval_sigs[idx] == 0) return;
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// For now, assume all the outputs are the same width.
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ivl_assert(*this, idx == 0 || lval_sigs[idx]->vector_width() == lval_sigs[0]->vector_width());
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