Spelling fixes

All fixes are in comments, except for one error message (was "iternal error")

Makefile.in

@@ -30,7 +30,7 @@ SHELL = /bin/sh
 # The "suffix" is used as an installation suffix. It modifies certain
 # key install paths/files such that a build and install of Icarus Verilog
 # with the same $(prefix) but a different $(suffix) will not interfere.
-# The normal configuratin leaves suffix empty
+# The normal configuration leaves suffix empty
 suffix = @install_suffix@
 
 prefix = @prefix@

driver/main.c

@@ -1041,7 +1041,7 @@ int main(int argc, char **argv)
 
 	/* If we are planning on opening a dependencies file, then
 	   open and truncate it here. The other phases of compilation
-	   will append to the file, so this is necessray to make sure
+	   will append to the file, so this is necessary to make sure
 	   it starts out empty. */
       if (depfile) {
 	    FILE*fd = fopen(depfile, "w");

elab_expr.cc

@@ -719,7 +719,7 @@ NetExpr* PEBinary::elaborate_expr_base_rshift_(Design*des,
 	    return tmp;
       }
 
-	// Falback, handle the general case.
+	// Fallback, handle the general case.
       if (expr_wid > 0)
 	    lp = pad_to_width(lp, expr_wid, *this);
       tmp = new NetEBShift(op_, lp, rp);
@@ -3499,7 +3499,7 @@ NetExpr*PETernary::elaborate_expr(Design*des, NetScope*scope,
 	// evaluation of ternary expressions, but it doesn't disallow
 	// it. The disadvantage of doing this is that semantic errors
 	// in the unused clause will be missed, but people don't seem
-	// to mind, and do apreciate the optimization available here.
+	// to mind, and do appreciate the optimization available here.
       if (NetEConst*tmp = dynamic_cast<NetEConst*> (con)) {
 	    verinum cval = tmp->value();
 	    ivl_assert(*this, cval.len()==1);

expr_synth.cc

@@ -907,7 +907,7 @@ NetNet* NetEUnary::synthesize(Design*des, NetScope*scope, NetExpr*root)
 	    return sig;
       }
 
-      cerr << get_fileline() << ": iternal error: "
+      cerr << get_fileline() << ": internal error: "
 	   << "NetEUnary::synthesize cannot handle op_=" << op_ << endl;
       des->errors += 1;
       return expr_->synthesize(des, scope, root);

ivl_target.h

@@ -594,7 +594,7 @@ extern double      ivl_const_real(ivl_net_const_t net);
  *
  * The discipline domain will not be IVL_DIS_NONE. The "none" domain
  * is a place-holder internally for incomplete parsing, and is also
- * available for code generaters to use.
+ * available for code generators to use.
  */
 extern const char*ivl_discipline_name(ivl_discipline_t net);
 extern ivl_dis_domain_t ivl_discipline_domain(ivl_discipline_t net);
@@ -1674,7 +1674,7 @@ extern int          ivl_scope_time_units(ivl_scope_t net);
  *
  * ivl_signal_discipline
  *    If the signal has been declared with a domain (Verilog-AMS) then
- *    this function wil return a non-nil ivl_discipline_t.
+ *    this function will return a non-nil ivl_discipline_t.
  *
  * ivl_signal_msb
  * ivl_signal_lsb

lexor.lex

@@ -1155,7 +1155,7 @@ static void process_ucdrive(const char*txt)
       cp += strspn(cp, " \t");
       if (strncmp(cp, "//", 2) != 0 &&
           (size_t)(cp-yytext) != strlen(yytext)) {
-	    VLerror(yylloc, "Invalid `unconnected_dirve directive (extra "
+	    VLerror(yylloc, "Invalid `unconnected_drive directive (extra "
 	                    "garbage after precision).");
 	    return;
       }

tgt-vhdl/expr.cc

@@ -477,7 +477,7 @@ static vhdl_expr *translate_select(ivl_expr_t e)
                                     new vhdl_type(*from->get_type()));
       }
       else if (from_var_ref->get_type()->get_name() != VHDL_TYPE_STD_LOGIC) {
-         // We can use the more idomatic VHDL slice notation on a
+         // We can use the more idiomatic VHDL slice notation on a
          // single variable reference
          vhdl_type integer(VHDL_TYPE_INTEGER);
          from_var_ref->set_slice(base->cast(&integer), ivl_expr_width(e) - 1);

tgt-vhdl/stmt.cc

@@ -747,7 +747,7 @@ static int draw_wait(vhdl_procedural *_proc, stmt_container *container,
    bool is_top_level = container == proc->get_container()
       && container->empty();
 
-   // See if this can be implemented in a more idomatic way before we
+   // See if this can be implemented in a more idiomatic way before we
    // fall back on the generic translation
    if (is_top_level && draw_synthesisable_wait(proc, container, stmt))
       return 0;

tgt-vhdl/vhdl_syntax.hh

@@ -569,7 +569,7 @@ public:
    enum assign_type_t { ASSIGN_BLOCK, ASSIGN_NONBLOCK, ASSIGN_CONST };
    
    // Get the sort of assignment statement to generate for
-   // assignemnts to this declaration
+   // assignments to this declaration
    // For some sorts of declarations it doesn't make sense
    // to assign to it so calling assignment_type just raises
    // an assertion failure
@@ -766,7 +766,7 @@ protected:
 
    // If this is true then the body contains a `wait' statement
    // embedded in it somewhere
-   // If this is the case then we can't use a sensitvity list for
+   // If this is the case then we can't use a sensitivity list for
    // the process
    bool contains_wait_stmt_;
 };

tgt-vvp/eval_expr.c

@@ -1942,7 +1942,7 @@ static struct vector_info draw_number_expr(ivl_expr_t expr, unsigned wid)
 /*
  * This little helper function generates the instructions to pad a
  * vector in place. It is assumed that the calling function has set up
- * the first sub_sidth bits of the dest vector, and the signed_flag is
+ * the first sub_width bits of the dest vector, and the signed_flag is
  * true if the extension is to be signed.
  */
 static void pad_in_place(struct vector_info dest, unsigned sub_width, int signed_flag)

tgt-vvp/eval_real.c

@@ -186,7 +186,7 @@ static int draw_number_real(ivl_expr_t expr)
 	/* If this is a negative number, then arrange for the 2's
 	   complement to be calculated as we scan through the
 	   value. Real values are sign-magnitude, and this negation
-	   gets us a magnitide. */
+	   gets us a magnitude. */
 
       int negate = 0;
       int carry = 0;

vvp/dff.h

@@ -30,7 +30,7 @@
  *
  *   port-0:  D input
  *   port-1:  Clock input
- *   port-2:  Clock Enagle input
+ *   port-2:  Clock Enable input
  *   port-3:  Asynchronous D input.
  */
 class vvp_dff  : public vvp_net_fun_t {

vvp/opcodes.txt

@@ -333,7 +333,7 @@ register to read the repetition count from (signed or unsigned).
 %evctl/i sets the repetition to an immediate unsigned value.
 
 %evctl/c clears the event control information. This is needed if a
-%assign/e may be skiped since the %assign/e statements clear the
+%assign/e may be skipped since the %assign/e statements clear the
 event control information and the other %evctl statements assert
 that this information has been cleared. You can get an assert if
 this information is not managed correctly.

vvp/vthread.cc

@@ -951,7 +951,7 @@ bool of_ASSIGN_V0(vthread_t thr, vvp_code_t cp)
       vvp_net_ptr_t ptr (cp->net, 0);
       if (bit >= 4) {
 	      // If the vector is not a synthetic one, then have the
-	      // scheduler pluck it direcly out of my vector space.
+	      // scheduler pluck it directly out of my vector space.
 	    schedule_assign_plucked_vector(ptr, delay, thr->bits4, bit, wid);
       } else {
 	    vvp_vector4_t value = vthread_bits_to_vector(thr, bit, wid);
@@ -2028,7 +2028,7 @@ static unsigned long* divide_bits(unsigned long*ap, unsigned long*bp, unsigned w
 					 ap[cur_ptr+btop+1]);
 	    }
 
-	      // cur_res is a guestimate of the result this far. It
+	      // cur_res is a guesstimate of the result this far. It
 	      // may be 1 too big. (But it will also be >0) Try it,
 	      // and if the difference comes out negative, then adjust.