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(V0.9) Modified rules for primitive gate port expression widths. 

The IEEE standard states that the port expressions used for arrays
of primitive gates must be the exact width required, but is silent
about the requirements for single instances. The consensus among
other simulators is that for input ports of single instances, the
expression is silently truncated to a single bit.

This patch also fixes a compiler crash if an error is found when
elaborating a primitive gate port expression.
This commit is contained in:
Martin Whitaker 2011-05-30 09:52:36 +01:00 committed by Stephen Williams
parent 409898eb3b
commit 9ac9f36e3c
1 changed files with 10 additions and 2 deletions
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12
elaborate.cc
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@ -737,12 +737,20 @@ void PGBuiltin::elaborate(Design*des, NetScope*scope) const
sig = lval_sigs[idx];
} else {
// If this is an array, the port expression is required
// to be the exact width required (this will be checked
// later). But if this is a single instance, consensus
// is that we just take the LSB of the port expression.
unsigned use_width = array_count * instance_width;
ivl_variable_type_t tmp_type = IVL_VT_NO_TYPE;
bool flag = false;
ex->test_width(des, scope, 0, use_width, tmp_type, flag);
NetExpr*tmp = elab_and_eval(des, scope, ex,
use_width, use_width);
NetExpr*tmp = elab_and_eval(des, scope, ex, -1,
msb_ ? -1 : 1);
if (tmp == 0)
continue;
if (msb_ == 0 && tmp->expr_width() != 1)
tmp = new NetESelect(tmp, make_const_0(1), 1);
sig = tmp->synthesize(des, scope, tmp);
delete tmp;
}