When generating code for a condition expression, i.e. directly
before a %jmp/X statement, try to generate the result into the
flag bit without passing through the vec4 stack. For example, the
%cmpX/X instructions generate results into the flag bits, so it
makes no sense to push these bits into the vec4 stack then pop
them back into the flag bit. So try to handle this case.
These bypass the vec4 stack in some common cases, saving instructions
and vec4 manipulations.
Also, minor improvement to the %flag/set/vec4 statement.
Kill a few warnings.
- Have %pushi/vec4 handle some special cases optimally.
- Eliminate some duplicated method calls in %load/vec4.
- Optimize the vvp_vector4_t::copy_from_ method by inlining
some parts.
Added various error/warning messages for behaviour not supported
in synthesis. Also give correct behaviour when multiple case item
expressions evaluate to the same constant value.
When unsized literals are used in case item expressions, it is likely
that the calculated expression width will be larger than necessary to
unambiguously select the correct case item (particularly when using
"strict" expression elaboration). This patch adds an optimisation
step that prunes the expressions to the minimum necessary width.
If an error is found whilst elaborating a range expression in a signal
declaration, create a dummy range and continue elaboration. This stops
the compiler reporting an error every time that signal is referenced.
When checking that an enumeration value is in range we need to cast it to
a 2-state value so that when we compare it we get a true or false value
instead of an undefined value. Undefined bits in the comparison return
undefined which is not logically false.
If elaboration of the msb or lsb expression in the range of a vector
type specification failed (due to an error in the Verilog code being
compiled), an assertion failure was being triggered when the compiler
attempted to evaluate the expressions. Bypassing the evaluation (and
using a default value) should allow us to recover from the error.
The code to get the correct modpath delay for a given edge had the X and Z
entries swapped.
When putting a delay from the VPI the 2 delay to twelve delay mapping was
incorrect and the to/from X delays were also not being calculated correctly.
Note: I could not find any info about the integer() function, but it is
used in the VHDL standard packages (e.g. math_real, see:
http://www.csee.umbc.edu/portal/help/VHDL/packages/mathpack.vhd)
Real numbers are rounded, this is compatible with ModelSim behavior.
VHDL does not allow to specify the size of returned std_logic_vector,
whereas Verilog requires the size to be known in advance. The size of
the vector is determined by checking the type of expression used in the
return statement.
This adds the runtime support for class properties that are classes
to be arrayed. Add a means to define the dimensions of a property
in the vvp format, and add functions for setting/extracting elements
of a property.
We need the scope where the class is defined so that it can find
types in that containing scope. Note that most definitions cannot
escape into the the lexical scope of the class, but some can.
This goes all the way down to the vvp level, where we create support
for arrays of objects, generate the new code in the -tvvp code
generator, and elaborate the arrays in the first place.
This patch fixes the following enumeration bugs:
When looking for an enumeration look in the current scope and then
recursively in any parent scope.
Add enumeration definitions to a package scope.
The parser always passes a single NULL argument for system tasks. For a
method call which will add a signal to call the method on we need to
ignore this NULL argument.
If an expression contains a division, remainder, or right shift operation,
set the expression min_width to UINT_MAX to flag that the expression width
cannot be pruned. Using UINT_MAX ensures that the min_width won't change
as we continue to elaborate the expression.
Internally, treat the "$" as a special expression type that takes
as an argument the signal that is being indexed. In the vvp target,
use the $last system function to implement this.
This works by translating it to a $size() system function call.
The $size function is already implemented for dynamic queues and
it is easy enough to expand it for queues.
Once a signal/variable of unbounded array type becomes limited in its size, it
is emitted as a packed array. Therefore currently it works only for
bit/logic/reg/wire types.
Like this:
... if (ce0) foo <= foo_in;
... if (ce1) bar <= bar_in;
Note that this is within a block, and represents multiple FF nodes
with different clock enables.
When for example assigning to foo[<x>] within a contitional, and
doing synthesis, we need to create a NetSubstitute device to manage
the l-value bit selects.
Testing with 32-bit clang 3.3, with additional compiler flags
-Wsign-compare -Wundef
this patch eliminates the following warnings:
config.h:100:6: warning: 'UINT64_T_AND_ULONG_SAME' is not defined, evaluates to 0 [-Wundef]
vcd_priv2.cc:233:12: warning: duplicate 'extern' declaration specifier [-Wduplicate-decl-specifier]
parse.cc:6496:9: warning: comparison of 0 <= unsigned expression is always true [-Wtautological-compare]
parse.cc:6499:13: warning: comparison of 0 <= unsigned expression is always true [-Wtautological-compare]
parse.cc:6502:9: warning: comparison of 0 <= unsigned expression is always true [-Wtautological-compare]
parse.cc:6510:53: warning: comparison of integers of different signs: 'const unsigned int' and 'int' [-Wsign-compare]
Changing the vlltype elements from unsigned to int reconciles their
type with the native bison YYLTYPE structure.
Before this patch, WARNING_FLAGS applied to both C and C++,
and WARNING_FLAGS_CXX applied to C++ only.
This patch adds a WARNING_FLAGS_CC that applies to C only.
That change should be generally useful; in particular the C
code is almost ready for -Wstrict-prototypes, which does not
apply to C++.
-Wextra (or -W) used to only apply to C++ via WARNING_FLAGS_CXX.
This patch moves it to WARNING_FLAGS, to apply to both C and C++.
Unfortunately, that triggers a ton of warnings.
For now, cover most of the new warnings up by adding
-Wno-unused -Wno-sign-compare -Wno-type-limits
to WARNING_FLAGS_CC. In the long run, I want to change the C coding
style, and take off these disable-warning flags. But those changes
can dribble in as separate commits; this patch is big enough already.
Actually fix a couple missing-field-initializers in libveriuser/veriusertfs.c.
119 formal void parameters added to keep -Wstrict-prototypes happy.
Process found one real missing prototype in vpi/vcd_priv.h:
EXTERN void vcd_names_delete(struct vcd_names_list_s*tab);
8 such warnings left, all in Tony's code
The only known problems left are in files imported from gtkwave,
if not for them you could turn on -Wsign-compare.
Assumes c99 for c code, so the scope of for-loop indexes can be made sane.
This generates an EQZ LPM device that carries the case-z-ness to
the code generator.
Also add to the vvp code generator support for the EQZ device so
that the synthesis results can be simulated.
Account for the wildcard devices in the sizer.
It shouldn't be possible, but sometimes is, that a NetCondit is
missing input nets during async synthesis. Handle this by generating
a place-holder net and printing a warning.
Second try cleaning up cast-alignment problems surrounding need_result_buf().
Clang gave a bunch of warnings like
vvp/vpi_const.cc:196:34: warning: cast from 'char *' to 'p_vpi_vecval' (aka 't_vpi_vecval *') increases required alignment from 1 to 4 [-Wcast-align]
This version is verbose and changes the prototype for need_result_buf().
But it is semantically (c++) correct, and makes need_result_buf() feel like malloc().
" characters in strings must be escaped when the compiler writes a
quoted string to a vvp script. This patch fixes up a few places where
this wasn't being done.
Better handle the case where the output for some pins comes from
an earlier assignment. This allows for multiple ways to specify
default outputs for some cases: the default: case and pre-assignment.
When conditional ports are blending (by allowing NetPartSelects be
connected together to the outputs) make sure there isn't an accidental
overlap of drivers that invalidates the process.
When a mux (NetCondit) is only writing to a part of the output
vector (and using only a part of the inputs) then blend the mux
output with the previous statement output.
If both conditions of a NetCondit device assign to the same subset
of l-value bits, then generate a smaller NetMux device that only
switches the affected bits.
This is an error in traditional Verilog and a unsupported feature in
SystemVerilog. Fail gracefully with a suitable error/sorry message.
Do the same for task declarations.
In a design, there may be lingering NexusSet objects, or the
nodangle may itself use NexusSet objects. This creates links,
and this should not confuse the functor.
While we are at it, clean up some handling of events structures.
It is possible for an assignment statement to be part of a
grander complex that has lots of outputs, not all handled
by this particular assignment. In that case, the assignment
may need to figure out which output it is supposed to bind to.
This required keeping for-loops as actual things through the
netlist form so that the synthesizer can get at and understand
the parts of the for-loop. This may improve vvp code generation
in the future, but for now continue to present to the vvp code
generation the block-while form.
Some types, i.e. vector types with parameterized dimensions,
may have different elaboration results in different scopes.
Handle those cases in the elaboration caches.
When the clock enable is not generated, don't try to hook it
up then detach it. That will make a mess that needs clean up.
Instead, leave unused ce pins (Enable) unconnected.
Signals are collected in a link map that uses the Link class so that
it doesn't need to save Nexus objects. But naked uses of Link don't
set the node_ and pin_zero_ members. So initialize them to zero so
that Nexus scanners can skip these naked Links.
If statements within blocks can confuse the synthesizer when there
are outputs that are assigned ahead of the if statement. This patch
handles that case.
Some of the SDF warnings were mixing some of the scope path with the
instance name. These are now separated into just scope and instance name.
There was also a place where vpi_get_str() was being called twice in a
single print statement. This is illegal since vpi_get_str() uses a single
buffer and multiple calls will overwrite the buffer.
This function was apparently not well tested, because any use of
acc_handle_object() triggered a use of vpi_handle_by_name that was
buggy.
The implementation was awkwardly written, to parts of it were redone.
The tf_igetlongtime function may pass in any kind of object, so the
scale() function may need to convert an object handle to the handle
for the objects parent scope.
The netparray_t::slice_dimensions bug was the most insidious and
caused all manner of confusion. Also fix some other packed array
and unpacked array (and mixed) indexing calculations.
Get rid of the data_type, signed_flag, and range arguments to the
pform_module_define_port because they add no value within the
parse.y parser. Cleaning these out will hopefully ease the addition
of new functionality.
This can be handled entirely in the parser, where we rewrite the
syntax to me a begin/end block that contains the index variable
declaration and the for loop.
The root cause was that NetESignal::dup_exr() was not copying the calculated
type (signed/unsigned) of the expression.
In passing, found and fixed a similar issue when calculating a blended value
for a constant ternary expression.
%exec_ufunc assumed that because a function can never block, a call to
vthread_run() on the function code would only return when the final %end
instruction had been executed. This is not true if the function contains
a named block, which will be executed via a %fork instruction, allowing
the main function thread to suspend after a %join instruction. The fix
is to break %exec_ufunc into two instructions, the first setting the
function inputs and executing the function code, the second collecting
the function result. This provides the opportunity for the parent thread
to suspend after the %exec_ufunc instruction until all its children have
completed.
The vvp code generator was optimising away adds and subtracts where one
operand was a constant zero. This is not valid for 4-state arithmetic.
It was also optimising away multiplies by a constant zero - but in this
case getting it wrong and effectively multiplying by 1.
For shift operations evaluated at compile time, the compiler was converting
the right operand to a native unsigned long value. If the operand exceeded
the size of an unsigned long, excess bits were discarded, which could lead
to an incorrect result.
The fix I've chosen is to add an as_unsigned() function to the verinum class
which returns the maximum unsigned value if the internal verinum value is
wider than the native unsigned type. This then naturally gives the correct
result for shifts, as the verinum bit width is also an unsigned value.
I've changed the as_ulong() and as_ulong64() functions to do likewise, as
this is more likely to either give the correct behaviour or to give some
indication that an overflow has occurred where these functions are used.
When an expression is elaborated, the compiler converts multiplies with
one constamt zero operand into a constant zero value. This is only valid
if the other operand is not a 4-state variable.
Unsized expressions can expand to extremely large widths. Usually this
is actually a mistake in the source code, but it can lead to the compiler
temporarily using extremely large amounts of memory, or in the worst
case, crashing. This adds a cap on the width of unsized expressions (by
default 65536 bits, but overridable by the user), and causes a warning
message to be output when the cap is reached.
When performing the initial assignment for a procedural continuous
assignment, any previous continuous assignment to the destination
signal must be unlinked first, otherwise the initial value for the
assignment will propagate to any other nets that are driven by the
original source signal.
The verinum arithmetic operators now observe the standard Verilog
rules for calculating the result width if all operands are sized.
If any operand is unsized, the result is lossless, as before.
They also now all observe the standard rules for handling partially
undefined operands (if any operand bit is 'x', the entire result is
'x').
I've also added the unary '-' operator, and renamed v_not() to be
the unary '~' operator. This has allowed some simplification in
other parts of the compiler.
A procedural continuous assignment is supposed to be updated any time
a variable on the RHS changes. Currently this only happens if the RHS
is a simple signal.
In the case that the RHS of a procedural continuous assignment is a simple
vector that is wider than the LHS, changes to the RHS vector cause the
entire vector to be sent to port 1 of the LHS vvp_fun_signal object. This
vector needs to be coerced to the size of the LHS. Note that this is a
stopgap fix until vvp handles arbitrary expressions on the RHS of a
procedural continuous assignment.
Signed vector power operations were being implemented using the double
pow() function. This gave inaccurate results when the operands or
result were not exactly representable by a 64-bit floating point number.
During expression evaluation, the compiler attempts to optimise away
relational operations when one side is constant and all possible values
of the other side would result in the relation being true. This is not
a valid optimisation if the other side is a 4-state variable, as an
'x' or 'z' will result in the relation being unknown.
This changes the verinum pow() function to use the more efficient algorithm
used in the vvp runtime. It will still be slow if the left operand is unsized
and the right operand is large, as it will expand the result vector to avoid
overflow.
The vvp_vector2_t::pow() function is recursive, and performs a multiplication
operation on each step. The multiplication operator was expanding the result
vector to accomodate the maximum possible result value for the given operand
vectors, thus causing the execution time of the power operation to be
exponentially proportional to the exponent value. Both in this case and
in general, it is unnecessary for the multiplication result vector to be
expanded, as the compiler has already determined the required vector width
during elaboration, and sizes the operand vectors to match.
The vvp_vector2_t constructor that takes a vvp_vector4_t value was
documented as creating a NaN value if the supplied vector contained
any X or Z bits, but instead used the standard Verilog 4-state to
2-state conversion semantics (X or Z translate to 0). I've added an
optional second parameter to the constructor to allow the user to
choose which semantics they want, as both are needed.
The link was pointing to a page that said:
This page has been moved to http://iverilog.icarus.com, you will be forwarded there automatically in 3 seconds.
Please update your links.
So now it's updated
If the l-value is an unresolved wire, then elaboration can allow
the assignment as long as it is to bits that are not otherwise
driven. Handle this in some simple cases.
This means using some of the new vec4 infrastructure to get at the
data, instead of using the old thread bit pointers. In the process,
remove the vbit and vwid members that pointed to thread bits. Those
bits no longer exist.
When a module is instantiated multiple times, the enum
types contained within would cause trouble. This fixes
that by elaborating in proper scope context.
When creating a constant zero for implementing a unary minus operation
using a binary subtraction operator, the constant needs to be to exactly
the expression width.
Redsign the handling of the return value, including a rework of
the %vpi_func syntax to carry the needed information.
Add a few more arithmetic operator instructions.
This patchs adds support for the $dimensions() and $unpacked_dimensions()
array functions. Since the argument is only used to get the type information
these functions can always be evaluated at compile time.
For the following functions if the dimension argument is constant or omitted
and the first argument is not dynamic (a string or dynamic array) they will
return the specified information.
$left(), $right(), $high(), $low(), $increment() and $size()
Dynamic information and a variable second argument will be implement in a
future patch.
There were also some subtleties related to using enumerations
from typedefs and using them in multiple places. Fix various
bugs related to those issues.
The standard explicitly states that only object with a full name
can be searched for by name. A port does not have a full name and
hence should be skipped so that a different object (the signal,
etc.) can be returned. This patch adds code to skip ports when
searching for an object handle by name.
This patch fixes some leaks in the object stack when getting various
class properties. With this fix an assert can be added to verify that
the object stack is clean when a thread is exiting.
This allows for syntax like a.b.c where a is a class with member
b, which is a class with member c, and so on. The handling is mostly
for the support of compound objects like classes.
When a thread that has detached children is reaped the detached children
need to be fully detached so they can be reaped correctly. If they are not
fully detached then they may reference a parent that has already been
reaped (memory freed). Found with valgrind.
The code should only look at the real argument that exist any missing
arguments default to not being defined and hence needs to use the
default expression. Found with valgrind.
This gets nested l-values to (but just short of) the ivl_target API.
Now the elaborator can process nested l-values, but I haven't figured
out how to present that at the ivl_target.h API.
It is better to leave the handling of PChainConstructor calls to
the elaboration, instead of stripping them out early. This allows
for handling the arguments of the chain constructor in the correct
scope.
It is more common to find an unsized number on the right hand side
of a binary operator than on the left hand side, particularly for
comparison operations (e.g. x < 10 rather than 10 > x), so testing
the width of the right operand first is less likely to result in
the width needing to be retested. Counting the number of times an
operand width is retested when running the test suite confirms this;
before this change an operand width was retested 4869 times, after
the change an operand width was retested 99 times.
A BUFT is needed to allow a force to override the pull value. This had
already been done for pullup devices, so factor out the common code and
use for both pullup and pulldown.
Currently vvp only applies the pullup/pulldown for tri1/tri0 nets when
the net is not driven. The correct behaviour is to treat the pullup/
pulldown as an extra driver (with pull strength).
For synthesis we remove the output set of signals from the input set to
remove temporaries from the final sensitivity set. The @* construct also
uses the input sensitivity list, but because it can include statements
that cannot be synthesized we should not calculate the output set for this
case. Not find the output set is also a speed enhancement since the output
set was already being ignored later in the code for this case.
To be strictly compliant with the standard and compatible with other
EDA tools, unsized numbers should be treated as having a fixed size
(the same size as an integer). The -gstrict-expr-width option is
extended to allow the user to enable this behaviour.
This option is intended to make it easier to compare results from
Icarus with results from other simulators. For now, the only effect
it has is to change the default format for displaying real numbers
when no format string is supplied.
This includes adding support for returning strings from functions,
adding initializing new darray with array_pattern strings, and
assigning an array_pattern of strings to a preallocated darray.
Also fix up support for initializing array with simple string
expression.
When you have an expression like this (extreme example):
a[idx[1]][idx[2]*4 +: 4] <= #(idx[3]) 4'ha;
where a is a reg array and idx is a reg or net array. The retrieval
of idx[2] was clobbering index register 3, which was set before
evaluating the part offset expression, then used in the %set/av of the
array value. (likewise for idx[1] and idx[3]])
To avoid this issue, this patch adds and uses a new instruction
%ix/mov which simply copies one indexed register to another. When
necessary, expressions are first evaluated into temporary registers to
avoid clobbering, then moved in to place before the %*/av instruction.
Implements page 644 of IEEE 1800-2012.
`` is now overloaded with the Icarus-specific "stringify" expansions.
It is now used as indicated in 1800-2012 when appearing inside a macro
definition, and the Icarus way when not. To do so, it uses the fact
that istack->file is NULL iff we are processing expanded macro text,
which is a bit of hack but works as is.
`" and `\`" on the other hand are treated the same inside and outside
of macro definitions.
When a fork/join contains a task, the task completion may become
confused with the completion of another thread if any of the
threads are embedded in the main thread. So always create threads
for all the fork paths, and joins to match.
In the ASIC universe, it is (probably) OK to replace a DFF CE
with a mux of the D input with the Q output. The idea is that
if the CE is true, the DFF latches D, but if CE is false, the DFF
re-latches the current output.
Turns out that call to eval_expr is redundant, and in degenerate
situations can lead to so many wasteful calls to eval_expr that
elaboration performance suffers dramatically.
The signal bit numbering should be used for signals. This is
necessary for .model ports because the user specified numbers
are part of the interface, but once that is done, it is trivial
to follow it internally as well.
Instead of just translating a generate scope to a named begin/end scope
this patch creates a generate specific scope (vpiScopeGenerate) that is
of the vpiGenScope type. This may not match the standard 100%, but does
allow the FST dumper to denote generate scopes differently than the
other scope types. Most of the VPI code treats a vpiGenScope just like a
named block so only the FST dumper should have different behavior.
Add support for detecting when to add a $signed() or $unsigned() to
create a self-determined context. This makes the test in the test suite
pass, but there could still be issues
Since parameters are now passed by reference use that information to print
the parameter name in a select vs trying to figure it out by searching the
scope looking for a parameter with the same file, line and value information.
Only print the $signed() may need to be removed messages for a select
expression that will actually be cast to signed.
Use the actual parameter information to warn that -pallowsigned=1 is needed
for a parameter when the LSB > MSB.
For variable parameter selects (indexed and bit) pass the value being
selected as a parameter reference instead of just a numeric constant
so it is easy to get the underlying parameter information.
Move the parameter bit select code into its own routine and cleanup
the remaining general code.
This should not effect the VVP code, but the ivl_expr_parameter(<expr>)
routine can be used to get at the actual parameter information in the
vlog95 target.
Static properties are like variables in a named scope.
Detect these variables during elaboration so that the
code generator just sees them as variables.
This implementation works by detecting assignments
to constant properties in elaboration. Allow initializer
assignments to assign to the constant, error all other
assignments, and otherwise treat the constant like any
other property.
Class types that have both implicit construction and
an explicit constructor can blend the implicit and
explicit construction into the "new" function defined
by the user. This doesn't change the behavior any, but
removes a function call and related scope.
The actual signal code is trivial, but the emit expression code needed
to be enhanced to pass a flag that says if one of the arguments in a
binary (except the shifts) or ternary (excluding the condition) context
is unsigned. This information is used to prevent emitting an explicit
$unsigned() for a signal that is used in this context since it will be
implicitly cast to unsigned.
This patch adds support for finding and adding $signed() and $unsigned()
to procedural expressions for the binary, unary and concatenation
operators. Selects have partial support. The select implementation
uncovered limitations in the compiler that need to be fixed before they
will work 100%. Most of the limitations currently generate a message
about the issue.
We need to elaborate expressions so that function calls in
expressions (i.e. ranges) get bound to their proper scope.
This binding is in turn used to emit package scopes. This
is particularly interesting for ports of entities.
If constant functions are exited by a return/disable, fix
the leaked "disable" flag that causes blocks in the next
try at the function to not work.
There are also a lot of debug messages added to help find
this and similar problems.
The VHDL to_unsigned function with to arguments is best handled
in the ivl elaborator, so have it generate an $ivlh_to_unsigned
function call in the vhdlpp code, and implement it in the ivl
core.
Also, implement the 'length attribute as a $bits() call for
similar reasons.
The package emit of types and constants needs to know which names are
from the current type and which are imported from libraries. Rework
the scope handling of those names so that the information is preserved.
For constant bit/part selects, issue a warning if the select is out
of range or an undefined value. In any case, the RHS value should be
discarded, and the actual assignment should be skipped.
If a VPI call with real arguments has no calltf function, we still
need to pop the arguments off the vthread stack. Similarly, if it
has a real result, we need to push a value onto the vthread stack.
For constant word indices, issue a warning if the index is out of
range or an undefined value. In any case, the RHS value should be
discarded, and the actual assignment should be skipped.
Class constructors are the "new" method in a class description.
Elaborate the constructor as an ordinary method, but the only
way to access this method is to implicitly call it. The elaborator
will take the constructor call and generate a naked "new" expression
and implicit constructor method call with the object itself as the
return value.
The changes in COPYING are mostly cosmetic and use <year> vs 19xx, etc.
Also update the tgt-vlog95/Makefile.in copyright to match the formatting
in the FSF version.
If a logical pull device is converted into a CA then it is an assignment
with strength, so just emit the appropriate constant to get the correct
functionality (e.g. 1'b1 for a pull up and 1'b0 for a pull down).
Also add missing file/line information.
There was one section of code in the tgt-vvp back end that was using
deprecated functions. This patch fixes that. The functionality is still
missing (force/assign to part of a vector), but the code now compiles
cleanly (no warnings).
This patch finishes the code needed to translate a SystemVerilog package to a
module with a special name. It also adds code to report that class scopes are
not supported and treats both a class and package as a top level scope.
Rework lexical support for PACKAGE_IDENTIFIER so that the lexor
can help with package scoped identifiers.
Pform package types and package functions up to elaboration.
Add support for case, forever, and repeat statements in constant
functions. Also fix a bug in the constant function implementation
of NetESelect when used for zero/sign extension.
The compiler was treating case and case item expressions as
self-determined. They should be context-sensitive, just like
the operands of a comparison operation.
Emit the elaborated class methods. Also generate root scopes to
represent the classes in order to hold the methods. These scopes
can also in the future be used to implement static properties.
This patch implements the evaluate_function method for the NetDisable
and NetSTask classes. It also makes the checks for a function being
constant work when the function contains nested scopes (named blocks).
Pure functions with constant operands can be evaluated at compile
time rather than at run time. This patch provides a global control
to enable this optimisation. Until constant function support is
complete, by default it is disabled.
If a ternary expression with mixed logic and real operands is
short-circuited and the logic value is selected, that value
should be cast to a real value.
IVL_VT_NO_TYPE is now used to signal an untyped LHS in a parameter
declaration. The parser function that handles specparam declarations
needs to do this too. Also, although it should never happen, make
sure we don't set the expression width in a NetECast object to a
negative number. Make constant evaluation of NetECast objects
observe the expression width.
This patch fixes a few issues/bugs that showed up when testing the
fixes for implicit casts:
1. Make the compile-time implementation of $abs, $min, and $max match
the run-time behaviour (system functions can't be polymorphic).
2. Correctly set the type (signed/unsigned) of the result of an
assignment inside a constant user function (the LHS should not
inherit the type of the RHS).
3. Fix a bug in the verinum(double) constructor (insufficient bits
were allocated in the case where the double value rounded up to
the next power of two).
This patch adds support for bool/bit vector types on the LHS of
a parameter declaration and ensures implicit casts in parameter
declarations are performed where necessary.
This patch adds support for implicit casts to the elaborate_rval_expr()
function. This will handle the majority of cases where an implicit cast
can occur.
A package can have parameters, but it does not have specparams or
keep the order the parameters are defined. This patch skips these
items if the scope is not a Module.
There are limitations with this since the compiler does not pass all
the information that was present in the original source, but it is enough
to get a valid simulation result. It is not enough for timing analysis!
specparams are also incorrectly translated to parameters so they show up
in the wrong place.
If modules instantiations were always handled correctly this would not be
needed, but for now looking for the nexus driver outside the scope is
needed to make some of the tests work.
This was temporarily implemented to just copy definitions to the
local scope, but the better method is to create a PEIdent that has
the package attached to it.
In SystemVerilog a task or function can initialize a variable in a task or
function. In Icarus this is done by creating an initial block that does
the assignment. We can translate this by emitting the initial block in the
enclosing module scope. This is not 100% correct since SystemVerilog
requires the initialization to be done before the other initial/always
blocks are processed. For SystemVerilog the current Icarus behavior is
incorrect, but even if it had a new process type that ran before the other
ones the best I can do for vlog95 is emit it before the normal module
processes which currently works.
In the starting comment say if the conversion was done with signed support.
If there were errors then add a comment at the end of the file that says
how many errors occurred and add a line after this that prevents the file
from running with out an error. This requires the user to see that errors
occurred and remove the offending line if they want to use the file anyway.
For a LPM constant we need to pass the sign information so that the vlog95
code generator can create the correct constant. Also when using the
sub_net_from() routine the numeric constant should have the same sign as
the signal so that it can also be displayed correctly.
Since the vlog95 code generator needs the strength information we do
not want to hide it behind a concat-Z optimization. For now we abort
the optimization, but in the future we could add parts of this back
in (e.g. all the drivers have matching strength then replace with a
normal concat and a buf-Z if the strength are not both strong. The
original buf-Z should be removed to reduce the number of LPM devices).
The Verilog-A abs(), min() and max() functions can be converted if the
expressions do not have side effects. Also note the new, null and class
property operators from SystemVerilog are not supported.
SystemVerilog allows a function to be called without an assignment for
the return value. This patch adds a warning that Icarus does not currently
support this and provides a place to add this functionality later.
This patch implements the evaluate_function method for the NetEBBits,
NetEBDiv, NetEBLogic, NetEBMinMax, and NetEBPow classes. It also
factors out some common code into the NetEBinary class.
Currently, when a variable expression is passed to a system task,
the expression value is stored in thread memory. Values stored
in thread memory cannot safely be passed to $strobe or $monitor,
because the thread memory may get reused or deallocated before
the $strobe or $monitor task actually executes. As a temporary
measure, we just trap this case and terminate with a "sorry"
message. A proper fix would require the expression value to be
calculated at the time the $strobe or $monitor executes, not at
the time it is called.
This is rather a pointless sort of thing, but it does turn from
from time to time, for example when constant literals (with no x or
z bits) are given strengths. So handle .net8/2s and .net8/2u the
same as .net8.s and .net8 objects.
If a strength aware net has an unambiguous HiZ1 strength, VVP treats
it as a logic '1'. It should be treated as a logic 'z'. An ambiguous
HiZ1/HiZ0 strength should also be treated as a logic 'z'.
L-value bit selects were incorrectly converting an undefined index to 0.
L-value part selects were asserting if an undefined index was given.
This patch unifies how all these are handle (including indexed part selects).
The base is set to an undefined value and an appropriate width is used.
A warning message is always printed since this is not a simple out of
range issue. It is the responsibility of the code generator to skip the
assignment, but we always want to execute the R-value since it could have
a side effect.
When VVP compiles a .array statement for a net array, it does not
know the data type, so initialises the array signed_flag to false.
We need to set the signed_flag to the correct value once we know
the data type, to allow the VPI routines to correctly format the
data.
When checking with valgrind clean up the following:
The arguments for invalid task/function calls.
The simulation callback queues (only needed when the runtime aborts).
Call pthread_exit(NULL) just before exiting to cleanup dynamic loading.
The vvp_darray_real class cal be used for static arrays as well
and this is a more general solution anyhow. Kill the now useless
vvp_realarray_t class.
If a signal s driven by multiple non-overlapping NetPartSelect(PV)
objects, then combine them into a single NetConcat object. This
eliminates the need for resolvers in the target.
This provides the ivl_target.h interface for class definitions
and expressions, the vvp code generator support for class objects
and properties, and the vvp run time support. Trivial class objects
now seem to work.
Add properties to the classes, and elaborate expressions that
have class properties. Describe class object property references
all the way down to the stub target.
Create stub class objects at the vvp level and generate the code
to invoke that stub. Implement the routines needed to implement
a test for null object references.
The code that calculated the canonical index for a multi-dimensional
array access did not correctly estimate the index expression width
in the case that the first index value was a constant zero. This
patch fixes the problem, and, in passing, also makes the expression
calculation more efficient if any of the indices are constant zeroes.
This will hopefully improve performance slightly, but also this
intended as a model for what to do when I get around to doing the
same thing to other data types.
Strings, when put into dynamic arrays, are treated as first class
types much line reals. Add the code generator and vvp support for
this situation. Also fix a bug distinguishing between character
selects from strings and select form arrays of strings.
This involves working out the code to get the base type of a select
expression of a darray. Also added the runtime support for darrays
with real value elements.
Clean up the vector4_to_value to use templates and explicit
instantiations. This makes the interface much cleaner for a
wider variety of integral types.
This patch updates the vvp code so it will compile with the valgrind hooks
again. There are still new constructs that need to be cleaned up correctly
and some old constructs were changed enough that the old code no longer
works, but the rest of this can be done as an incremental improvement.
In generate for blocks, there is a genvar that can be used in
expressions within the generate block. Generate this genvar in
the generated output, matched to the generate scope.
Windows and hence mingw does not follow the standard regarding the return
value of vsnprintf(). The mingw code needs to iteratively search for a
buffer large enough to print the output.
The second call to vsnprintf() needs to have a copy of the argument list
so it can run correctly. On some system vsnprintf() destorys the original
argument list.
When sending a string to a system task/function allocate the space needed
to avoid truncating the string vs using a large fixed buffer.
In vvp allocate and use an exactly sized buffer for the MCD print routine if
the fixed buffer is not large enough. Using a fixed buffer keeps normal
printing fast.
defparam assignments found inside a generate block were being stored
in the enclosing module scope. They should be stored in the generate
block scope.
Also removed the genvar list from the PGenerate class, as this is
already declared in the base LexicalScope class.
This patch updates the code to translate the SystemVerilog assignments with
an opcode to the appropriate vlog95. This includes ++ and -- when used in
a statement context. The ++ and -- operators are not currently translated
in an expression context. This translation only occurs in two places:
A simple assignment statement (foo += 2;) and the increment of a for
statement. I still need to check if there are other places where these
operators are allowed.
These two typedefs exactly matched earlier ones in the same scope and
gcc was complaining that they were shadowing the previous definitions.
Since the definitions matched exactly just deleting the second
typedef was acceptable.
SystemVerilog supports using assignments with opcodes (e.g. +=). This
patch checks for these in a few common places and prints a warning
that they are not currently supported. Eventually the simple cases
will be converted.
We can not convert SystemVerilog strings or dynamic arrays to valid vlog95.
This patch adds an error message that they are not supported. There are still
issues with converting some of the dynamic array constructs (the compiler
crashes), but the message is printed before the crash.
When built with MinGW, pow() may not always generate an exact integer
result when supplied with integer operands. Converting the result to an
integer before we use it seems to be enough to work round this issue.
This patch adds support for SystemVerilog packed arrays and adds sorry
messages for generate blocks as well as the new SV final and
fork/join_any/join_none statements.
The compiler doesn't currently check that the width of an indexed
part select is non-zero. If code contains this erroneous case, the
compiler can crash (with an assertion failure). This patch causes
the compiler to output a suitable error message and recover. It
also fixes a potential crash if an illegal expresson is encountered.
The parser does not distinguish between module and UDP instances, so
a UDP delay is handled by the rules used for parsing module parameter
overrides. Although these rules had been relaxed to accept the case of
a simple decimal value (e.g. #10), they did not allow a simple real
value (e.g. #0.1).
This patch implements the $countdrivers system function. It does not
yet support wires connected to islands (and outputs a suitable "sorry"
message when this is detected).
To implement the $countdrivers system function, we need to be able to
find all the driver values for a given wire. Currently, if a wire has
has more than four drivers, the compiler builds a resolver tree out
of 4-input nodes to resolve the driven values, and there is no way at
run time to work back from the output node to the original driver
values. This patch moves the implementation of the resolver tree into
a single vvp functor (using a mechanism similar to wide functors to
support more than 4 inputs), thus gathering all the driver values into
a single place.
Implement through the ivl core to the ivl_target.h API.
Also draft implementation of creating and storing arrays
in the vvp runtime and code generator.
When string[x] is an l-value, generate code to implement something
like the string.putc(x, ...) method.
Also handle when string[x] is the argument of a system task. In that
case resort to treating it as a calculated 8-bit vector, because that
is what it is.
This also advances support for string expressions in general.
Handle assignments to string variables in the code generator by
trying to calculate a string expression. This involves the new
string object thread details.
In vvp, create the .var/str variable for representing strings, and
handle strings in the $display system task.
Add to vvp threads the concept of a stack of strings. This is going to
be how complex objects are to me handled in the future: forth-like
operation stacks. Also add the first two instructions to minimally get
strings to work.
In the parser, handle the variable declaration and make it available
to the ivl_target.h code generator. The vvp code generator can use this
information to generate the code for new vvp support.
The parser had been changed to support null statements in sequential
and parallel blocks (a feature introduced in SystemVerilog), but was
not supported in elaboration, leading to a compiler crash. This patch
fixes this by discarding the null statements during parsing.
Currently, localparam declarations inside generate blocks are
elaborated after any nested generate constructs are elaborated.
This prevents the localparams being used by the nested constructs.
Reversing the elaboration order fixes this bug.
Added: basic vpiPort VPI Objects for vpiModulkes
vpiDirection, vpiPortIndex, vpiName, vpiSize attributes
Since ports do not exist as net-like entities (nets either side
module instance boundaries are in effect connect directly in
the language front-ends internal representation) the port information
is effectively just meta-data passed through t-dll interface and
output as a additional annotation of module scopes in vvp.
Added: vpiLocalParam attribute for vpiParameter VPI objects
Added: support build for 32-bit target on 64-bit host (--with-m32
option to configure.in and minor tweaks to Makefiles and systemc-vpi).
The fork/join list did not adequately support the tree of processes
that can happen in Verilog, so this patch reworks that support to
make it all more natural.
Making the scope type NESTED_MODULE was just plain wrong, because
it didn't really encapsulate the meaning of program blocks OR
nested modules. So instead create nested_module() and program_block()
flags and use those to test scope constraints.
An important advantage of program blocks is its ability to nest
within a module. This winds up also allowing modules to nest, which
is legal but presumably less used feature.
It is common for typedefs of complex types to use further typedefs.
Emit the type definitions depth first so that the types that are used
are defined first. This reduces the need for pre-declaration of types.
When concatenation expressions have aggregate arguments, we need to
get the type of the result down to the aggregate expressions so that
it can know how to interpret the elements.
Elaborate records and emit them as packed SV records. Also handle
record members so handle name prefixes.
While we are at it, handle some cases of array aggregate expressions.
When signals/variables are records, they are often referenced by
their members, using a prefix.name syntax. Parse that syntax and
generate "sorry" messages in elaboration.
A NetScope object currently has two lists of parameters, 'parameters'
and 'localparams'. However, user-declared localparams are stored in
the 'parameters' list, and 'localparams' is only used for adding
genvar values to the parameter list. There seems no good reason to
maintain separate lists, as the lists are merged before being passed
to the target DLL. This is most likely a hang-over from older code.
This patch extends the compiler to support all specparam declarations
allowed by the 1364-2005 standard. For compatibility with other
simulators, it allows specparam values to be used in any constant
expression, but outputs a warning message and disables run-time
annotation of a specparam if it is used in an expression that must
be evaluated at compile time.
SystemVerilog allows a variable to be used as a variable OR
as an unresolved wire. The detection of this case was checking
the references to the affected value, instead of the l-value
references.
(cherry picked from commit cceeaa30f27260cd444015cb39b04353cb858768)
The final step of expression elaboration is to reduce the width of
lossless/unsized constant expressions to the minimum needed to hold
the resulting constant value. This leads to unexpected results if
the user supplies a literal number with redundant digits that gets
passed to a system task that is sensitive to the width (e.g. $display).
This patch prevents width reduction occurring in this case.
When a conditional statement is unnamed, it doesn't create a scope
and we get into "direct" generate scheme elaboration. This direct
elaboration needs to handle case generate schemes.
The IEEE standard does not specify the behaviour of a tranif primitive
when its control input is an 'x' or 'z'. vvp currently treats these as
if the tran was turned off, but it would be better to propagate the
uncertainty to the tran bi-directional ports. For compatibility with
other simulators, we adopt the behaviour specified for MOS primitives.
This is a cleanup in preparation for better support of range lists.
(cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68)
Conflicts:
PTask.h
elab_scope.cc
elab_sig.cc
parse.y
pform.cc
pform.h
pform_types.h
Signed-off-by: Stephen Williams <[email protected]>
The SystemVerilog unbased literals (e.g. '0, '1, etc.) are expected to be
used standalone and cannot take a size. This patch modifies the parsing
code to give a good error message when this is done.
The standard specifies that the size of a vecval should be calculated as
(size - 1)/32 + 1. When size is a PLI_INT32 this is needed to prevent an
overflow, but when the size is unsigned this can be simplified to
(size + 31)/32 since the size must fit into an integer, but we have an
extra significant bit in an unsigned so no overflow can happen.
This patch changes the code to use the correct version of the equation
depending on the context.
The previous patch does this in vvp/vpi_priv.cc
When vpi_put_value() is asked to delay the assignment any pointer data
needs to be duplicated so that the caller can clean up the locally
allocated memory without causing memory access problems.
Also update word calculation to match the next patch.
If a tranif gate has a delay, the vvp code generator needs to generate
a unique label for the island port used for the tranif enable, to
prevent a name collision if the undelayed signal is also connected
to the island.
Also add an assertion in vvp to catch bugs like this.
Class methods belong in a class scope, not the containing module.
So create a lexical scope that carries tasks and functions and
create a PClass to represent classes.
Tasks call arguments may be dropped in favor of default values.
Allow for that in the syntax. This requires a little handling
of the non-SystemVerilog case during elaboration.
Class names can be declared early, before definitions, so that the
name can be used as a type name. This thus allows class definitions
to be separate from the declaration. This creates some complexity in
the parser, since the lexor knows about the class names.
This adds the vector_type_t and real_type_t types to handle
vector and real types in tf_port items. This cleans up a lot
of the parsing for these items.
During parse/pform processing, convert increment statements to
the equivalent compressed assignment statement. This is less weird
for elaboration processing and better expresses what is going on.
The clang compiler does not like using struct to reference a class object.
This patch removes all the struct keywords for __vpiNamedEvent objects
since they are now a class and can be called without a struct/class
qualifier.
This patch also removes all the extra class qualifiers from the rest of
the source code.
This handles a few cases where the non-constant bit selects are
in the final index. This doesn't handle all the cases of packed
arrays, but it handles some common cases.
This gets me to the point where the parser stashes a defined type,
and the lexical analyzer uses the type names to differentiate
IDENTIFIER and TYPE_IDENTIFIER.
Parse typedefs with structs and enums, but give a sorry message,
because they are not yet supported. Rearrange some of the parse
rules for variables in order to increase comonality with the
typedef rules.
When looking for a value change on a part select of an array word,
the callback handle has to save the current value and test it with
the new value to see if there is an actual change. If not, then
suppress the callback.
The clang compiler does not like mixing class and struct references. This
patch updates all the struct __vpiHandle, etc. to use class since that is
how they are now defined.
All the methods that this structure supported are now pulled
into the __vpiHandle class as virtual methods. This includes
the vpi_free_object_ method, which required some extra trickery.
Instead of C-like data structures where the __vpiHandle base is a
leading member, make the __vpiHandle a derived class. Give the base
class a virtual destructor so that dynamic_cast works reliably, and
now pretty much all of the junk for testing if an object really is
of the derived class goes away. Also, problems with casting up to
a vpiHandle become trivial non-issues.
Full vector assigns are able to short circuit the propagation of
the value if it finds that there are no value changes. This patch
supports that behavior in writes to parts as well. Put this change
to use in logic devices as well.
Not all the lex/yacc (flex/bison) targets were using a consistent syntax.
This patch fixes that and explicitly serializes the *.c/*.cc and *.h build.
Not doing this was causing problem when using make -j. The issue appears to
be that if two targets are specified for a rule (e.g. file.cc file.h: file.y)
make does not realize they are both built by the same call so the rule is
executed twice. Once for the .cc target and once for the .h target. This is
not a problem for a serial build. To work around this only use the .c/.cc
file in the main target and then make the .h file depend on the .c/.cc file
as a sub-target.
Rework the nexus emitting code to correctly translate most I/O ports.
Fix a few other expression issues uncovered when port translation was
done correctly. Ignore and warn that the SV ++/-- operators and enum
types are not translatable. More updates of the nexus debug code.
When a black-box item requests a specific footprint, we need to
read a file (<footprint>.fp) that contains the actual details
about that footprint. Support parse of that file and use the
loaded Element to generate the footprint for the item.
On some systems having both %.o: %.c and %.o: %.cc rules confused the
make system. This is directory only has C++ code so remove the %o: %.c
rule. Also the C++ compiler should be used to link C++ object code.
On Ubunto 10.10 (32 bit) tgt-pcb would not build because there were
include file issues. This patch fixes those and uses the C++ include
version where appropriate.
The main .pcb file contains elements, and basic PCB status.
Write out a .pcb file with stub Elements for each of the devices
in the design.
Rearrange the way the files are reported to the code generator
so that we can sensibly express where the output files are.
This is a pretty trivial fix for the code generation of compressed
assign to a memory word. We generated incorect code for the stash
of the calculated word index, causing the assign of the result to
not work properly.
This same change was done in the vpi directory. This patch fixes the
issues in the libveriuser directory. This fixed a fail in the vpi
timescale test under MinGW.
A declaration of the form "parameter signed a = 1.0" causes a
compiler crash. The standard is somewhat contradictory on what
type "a" should have, but testing with other compilers shows a
majority in favour of it being a real value.
The standard allows a parameter (or localparam) declaration of the
form "parameter signed my_param = ...". The parser currently rejects
this. A small adjustment is also required in the parameter evaluation
code to correctly apply the type.
Now we have a code generator that can handle compressed assignments
as they have been re-imagined in elaboration. There are some cases
that are not yet supported, we'll patch them up in due course.
Most people doing real modeling don't want to bring in the whole
Verilog-AMS infrastructure to use wreal nets. This patch adds the
wreal keyword to the xtypes generation so that wreal is available
by default.
This patch adds wreal support when in Verilog-AMS mode. It doesn't add
everything that is shown in the Verilog-A standard.
It adds the following:
Declaring a wreal net.
Declaring a wreal net with an initialization.
Declaring a wreal input/output using ANSI syntax.
Declaring a wreal input/output using the old style.
Declaring wreal inout ports are also allowed and parsed, but the
compiler does not know how to handle this. There are other deviations
from what is shown in the Verilog-A standard, but this should get most
of the syntax people actually use.
An @* with no sensitivities should be treated as something that will
never trigger vs something that will run continuously. This patch makes
this change and adds a warning when an @* has no sensitivities since
this is almost certainly a coding bug.
It is legal for a named block to contain variable definitions and
no statements. This patch fixes this for both style of blocks. It
also organizes the block parsing code to be a bit more clear, adds
an error case for fork/join and changes on check for size() > 0 for
the more efficient ! empty().
To avoid a variables not initialized in the construct this patch modifies
the PSpecPath class to take the polarity and full_flag as arguments to
the constructor.
The --always flag to git describe is harmless in the normal case,
and helpful in some special cases. Also add the --dirty flag to
get extra interesting details.
If a wired and/or net has more than four connections all the other
resolution branches must also be wired and/or. All other nets can
just be tri since tri0/tri1 only needs the final resolution to be
an active pull up/down.
Since synthesis is not currently supported we do not support/generate
sync/async set or clear control inputs. This is further complicated by
the fact that the VVP DFF primitive is not fully implemented.
This patch fixes a compile problem in Cygwin where there are two
definitions for abs() that do not match so the C++ code doesn't know
which one to call. To avoid the whole mess replace the call to abs()
with the appropriate ?: construct.
In a specify block a full connection is defined to only support a single
source and destination path. This patch adds an error message when this
is found, except we skip the error if all the paths are a single bit
wide. This exemption was added to match the functionality found in
NC-Verilog and presumably Verilog-XL.
A message was also added in place of an assert if the source signals was
not found in the current scope.
Both UDPs and system functions use the wide input functor. This patch
modified the code generator to create a local net declaration for the
output net if we have either a delay or modpath connecting the output
to the true output. This is needed so that the wide input can be
cleaned up correctly.
Local real nets were also added to the local net pool when testing with
valgrind. This allows them to be cleaned up at the end.
For a delay we do not know exactly what type we will be propagating
until the initialization event has happened. Because of this we
allocate both a vec4 and a vec8 value. Once the initialization event
has happened we can free the unneeded element(s).
This patch uses the full_flag to verify that the input and output have the
same width for a parallel connection. Icarus always uses a full connection
so this is just a portability issue with other simulators.
The pform dump code was also modified to correctly display the polarity
and full/parallel connection type.
In MinGW, when parameters are passed to vhdlpp by ivlpp, single quotes
are treated as ordinary characters. Use double quotes instead, as is
done in the driver.
Also, MinGW does not have a standard mkdir() function, so we need to
convert calls to mkdir() into calls to _mkdir().
When scaling a time value we would often use the power operator to
create constants 10**-N that were then multiplied with the original
value. The problem with this is that there is some errors in the
representation of the fractional number. It is better to create a
integer value 10**N and then divide the original value by this
exact constant. You still have the calculation error, but the scale
value is now an exactly real value.
Add support for %m, suppression '*' and a maximum field width along with
a number of other fixes/enhancements. There is still no support for
%u, %v or %z.
The fix to get a C99 compliant strtod() in MinGW mistakenly set the
LDFLAGS value rather than appending to it. This meant that a LDFLAGS
supplied by the user on the configure command line would be ignored.
MinGW has reverted to using the Microsoft msvcrt0 implementation
of the strtod() function. This implementation doesn't accept "INF"
"NaN". MinGW does provide a C99 compliant implementation of this
function called __strtod(). We need to force the linker to replace
all references to strtod() with references to __strtod().
This patch adds error messages that forcing a word to/from a variable
array is not currently supported. This is because variable arrays no
longer are fully populated and don't have an access functor for each
word. Forcing a word from/to a net array does work as expected since
each word in a net array is created.
Technically forcing a variable array word is not supported in 1364-2005.
Reading from an array word, which is supported, will be fixed in
development once the expression rework is finished.
The error message printed when forcing a bit/part select l-value was
also improved.
Promote the unsigned values to long to get a good comparison and on a
machine where an unsigned is the same size as a long (32 bit) assert
that the unsigned values are constrained to fit into a long. It's unlikely
the values needed to create invalid results would ever happen, but this
patch makes sure it doesn't go undetected.
Some of the last changes I added to the enumeration next()/prev() code
introduced a memory leak under some situations. This patch fixes the
leak by freeing the iterator before the new one is created.
The name is not currently used, but when it is it makes sense for it to
be in the base class. Also the name cannot be deleted after compiling
since it may be used later.
The VPI object data model diagrams show a one to many relationship
between the "mod path" and "path term" objects. This means that the
correct way to obtain handles to "path term" objects is to use the
vpi_iterate and vpi_scan functions.
Support for the old method of obtaining handles to "path term" objects
using the vpi_handle function is retained for backwards compatibility.
Entity generics are easily implemented as module parameters, so make
it so. Give the parameters their default values from the generic declaration.
Array bounds may use values that cannot be evaluated right away, so
put off their evaluation.
Add an implementation for the enumeration name() method. This currently
only works if the context defines the return width (e.g. the result is
assigned to a variable). It does not work in a self-determined context
(e.g. as an argument to a system function or in a comparison). This is
a limitation in the compiler/code generator/run time not the method
implementation provided here. We may need full string support to make
this work 100%.
The standard defines how to calculate the name for an access function
or iterator if one is not given. It is supposed to be vpi followed by
the words in the name with each word capitalized. For the one to many
(iterator) interface from the enumeration typespec to the individual
constants this is vpiEnumConst not vpiMember.
Rework the actual next() and prev() methods to correctly process the
numeric count argument. Also rework the compiletf routine to give better
error messages and combine the call routine for the two methods.
Add a compiletf routine that checks the arguments and then report that
the name() method is not currently implemented.
We don't currently have the information needed to correctly provide the
base typespec, but in the next() and prev() methods I need to know if
the enumeration is two or four state. This patch sets the base typespec
for four state enumerations to vpiReg and to vpiBitVar for two state
enumerations. This provide enough information to get next() and prev()
working correctly.
This patch adds vpiEnumTypespec to the list so that vpi_get_str(vpiType, ...)
returns an appropriate string when an enum type is passed.
It also adds the initial hook to allow iteration (global) over the UDP
definitions. This along with table traversal will be needed to free the
memory allocated when the UDP definition is created. Ultimately this
will all the UDP test to be valgrind clean.
The PLI tf_getlongsimtime() function is a non-standard function provided
for compatibility with some commercial simulators. To match the behaviour
of those simulators, it should return the raw simulation time, not a
scaled time.
The vpiDecStrVal case for the get_numeric() function needs to use the
existing string width as the minimum result size. -1 can be represented as
a signed value with a width of 1. This gives a display width of -1 which
is too small for the -1 string value. This was creating valgrind issues.
In general the string value should be the minimum so this is a safe change.
If a constant is padded the original constant will be freed and replaced
with a new one. This results in the ce pointer pointing to freed memory.
In reality the second check only needs to be done if the first one is
false so avoid the whole issue by only performing the second check if
the first on is false.
If a wait statement has a constant argument then the mode must be defined
before test_width() is called since the current mode is used in the
PENumber test_width routine.
Add code to allow an enumeration method to be called as a function.
This is only the compiler support. The runtime support is still missing
so only an empty argument call will succeed (e.g. next(), etc.). For now
the rest get a warning message.
Update the line number for a couple cppcheck suppressions and add one for
the pool variable in the vvp directory.
Also move a check for null to the correct place.
This patch makes the code consistently use struct/class in the C++ files,
it removes a couple shadow warnings and where a class pointer is passed to
the C routines, it defines the pointer as a class for C++ and as struct for
C and it removes a namespace std duplication.
This patch updates the $scanf and $printtimescale routines to work with
two-state variables. It also updates the general is_numeric check to
recognize two-state variables as numeric.
Modify the $random code to allow the seed to be either an int, long or
bit that is 32 bits or longer. The 32 bit check is new and also applies
to reg/logic variables.
This patch fixes a few more bugs in the enumeration code.
It add support for saving the file and line information to make
diagnostic messages better.
It updates some of the compiler warning messages to use the file
and line information.
It passes if the enumeration type is signed all the way to the
code generators.
It fixes the parser to correctly have the range after the signed
designation for the vector types.
It adds a warning that vvp does not currently support a negative
two state enumeration value.
We need to print a message and fail if the two \\ characters are not found
in the executable path.
Also update the generation warning to include -g2005-sv.
This is caused by a bug in some simple pattern matching the VHDL target does to try
and produce more idiomatic code in common cases (e.g. FFs with asynchronous resets in
this case). This patch just restricts the kinds of if-statements we use this
optimisation for.
The patch adds necessary error checking to verify that the operands of
increment decrement operator is not number.
Signed-off-by: Prasad Joshi <[email protected]>
Type cast expressions and some function calls are syntactically
identical to array element select, so we can only tell the difference
by looking up the name of the identifier being selected. If it is a
type name, then create an ExpCast instead of an ExpName object.
Also, parse and emit vector part selects.
Add a new IVL_PR_FINAL process type.
Add a flag to NetScope in_final_ which is set when elaborating the
statement of a final procedure.
Add checks during statement elaboration for invalid statements in a
final procedure, similar to checks for statements in functions.
Do a final check to make sure no final blocks have delays.
In the vvp runtime, use "$final" as the flag for the thread created by
the final procedure. During compilation, instead of adding such a
thread to the sched_list, add it to a new schedule_final_list that
mirrors the schedule_init_list, but is run at the end of simulation.
This patch adds support for increment/decrement operators as an
expression. The operations on real and vector slices have been
disabled for now.
These operators can be used as in independent statements. However, the
corresponding support is not added in parser.
Changes since V2:
- Additional error checking in elaboration to deny operation on vector
slices and real (suggested by Martin)
Changes since V1:
- Use 'i' and 'I' for increment (suggested by Cary)
- Evaluate sub-expression once (suggested by Cary and Stev)
- Add necessary checks during elaboration to ensure that the
expression is valid (suggested Stev)
- Proper width handling with vectors (suggested by Martin)
Signed-off-by: Prasad Joshi <[email protected]>
Icarus uses 'i' in the net expressions for a cast to integer. Replacing
it with 'v' would free the character 'i' that can be used for increment
operators. This changes cast operators to become 'v', '2', and 'r'.
Signed-off-by: Prasad Joshi <[email protected]>
Suggested-by: Cary R. <[email protected]>
The vvp target code generator may not elide a BUFZ if the output of
the BUFZ is connected to a net that is the subject of a procedural
force statement.
Named libraries are similar to the work library, but they are not
written to implicitly, or imported implicitly. They are only brought
in by a "library" clause, the the packages within the library are
brought in by a "use" clause.
Technically the sized function is not currently needed by Icarus since
the SFT file handles this type of information, but lets define this so
that things work correctly if we ever switch to using the standard VPI
interface. Also mark this as a system defined function.
Presumably, the user will want the ability to explicitly set the
working library location, so create a +vhdl-work+ plusarg setting
for exactly that purpose.
Port map aspects were held in std::maps. Because
of that, in case of multiple assignments to the same
port, some assignments were lost and in effect vhdlpp
produced correct verilog code from a buggy VHDL.
Std::map was replaced by std::multimap. Thanks to it
we can gather this multiple assignments and detect them
in the elaboration phase.
This patch introduces in ScopeBase separate containers
for declarations coming from the current scope and from
the previous scopes.
Until now, in one scope, all objects were kept in an stl map.
When a scope was created inside other scopes, a shallow
copy of the map was made. This solution was nice for
name shadowing (in new scopes, when a name was
encountered, the old objects were overridden by a new
one), but didn't allow for distinguishing where the objects
were allocated. As a result, it is impossible to know who
the owner is and who should delete them.
In this commit ScopeBase gets two containers: for old
and new objects. If a ScopeBase is made from another
ScopeBase object, all objects from the copied object
go to an old_XXX container, where XXX depends on the
type of the copied objects. When a ScopeBase object
is deleted, the objects from new_XXX are deleted and
the ones from old_XXX are not touched.
This patch adds some complexity to the internals
of ScopeBase, but leaves its interface unchanged.
This is rather a cosmetic change. The patch changes
the container used for stack of scopes from std::list
to std::stack. It suits this particular application
a bit better.
Thanks to valgrind analysis it turned out that
there were objects in the parser that were not being
deleted in a proper way. This patch fixes them all.
Instead of using automatic variables for global
types, I allocate them dynamically. Thanks to it,
all type objects can be treated in the same way,
as all of them are pointers allocated with `new'.
Now we will be able to remove all scopes in the same
manner, no matter if it is a global or local scope,
by deleting all carried pointers.
When writing arrays to the work library, handle the special
case that it is an array of std_logic and write a std_logic_vector
declaration instead. This makes for a more compact description.
When a "use" clause tries to pull a package from the work library,
put together a file name and try to find that package in the
work library directory. If found, parse the package file and
try again to find the package.
Bison and Flex generate different interfaces for reentrant
parsers, so handle that different API. We need this change
because library support is going to reuse the parser to
read in library packages.
This patch adds code to check for a negative or undefined value used in
an enumeration sequence name, it verifies that the count in an enumeration
sequence name is not zero and allows more decimal constant values in the
enumeration sequence name..
isprint() is defined to take an int and if it is defined as a macro then
you can get a warning that a char is being used as an array index. This
patch fixes this warning in tgt-vlog95/msic.c
SystemVerilog extended the assignments operator support to C-like
assignment operators and special bitwise assignment operators.
For example:
a += 1;
a -= 1;
The list of these operators can be found in SV LRM (1800-2009)
section 11.4.1.
NOTE: I fixed a few parts of this. In particular, the PEBShift
class is used for shift operators.
Acked-and-Tested-by: Oswaldo Cadenas <[email protected]>
Signed-off-by: Prasad Joshi <[email protected]>
This function is for the time being used in the
component instatiation. It is checked, whether
an expression is a correct r-value.
To be a correct r-value, it must be either
port name or signal name.
pow(int, int) is ambiguous since it could use the double version from
the math library or the verinum version. This patch makes it obvious that
we want to use the double version.
Build up a work library by writing a VHDL representation of the
package header into a source file. This representation needs to
be accurate enough that later invocations of vhdlpp can read them
with the VHDL parser.
A bit/logic output type in a module initially is defaulted to as a
variable. Depending on how they are used in the module, the type
changes accordingly.
For example
module test(output logic l);
assign l = '0;
endmodule
The variable 'l' would be promoted to a Net data type, when the
'assign' statement is encountered.
Acked-by: Oswaldo Cadenas <[email protected]>
Signed-off-by: Prasad Joshi <[email protected]>
The module declaration should allow initialization of the bit and
logic data types.
For example:
$ cat clkgen.sv
module clkgen(output logic clk = 0, output bit p = 1);
initial begin
#200;
$display("p = %b", p);
$finish;
end
initial forever #10 clk = ~clk;
endmodule
$ iverilog -g 2009 clkgen.sv
$ ./a.out
p = 1
Suggested-by: Oswaldo Cadenas <[email protected]>
Signed-off-by: Prasad Joshi <[email protected]>
SystemVerilog allows passing the 'bit' and 'logic' arguments to a
function. The patch adds support for parsing these function
definitions. The 'bit' data type is treated as boolean, whereas 'logic'
data type remains as logic.
Acked-by: Oswaldo Cadenas <[email protected]>
Signed-off-by: Prasad Joshi <[email protected]>
This patch removes the space between -L and the directory in the vpi
Makefile. It also fixes the line to use the correct variable name
for the LDFLAGS.
The patch allows parsing of function definitions which do not have
explicit data type or range. The default return data type is assumed
to be reg unsigned and the default range is 0.
Signed-off-by: Prasad Joshi <[email protected]>
Verilog allows returning variables of 'reg' type. The icarus verilog
implicitly assumes the default returned type of the function as
'reg unsigned'. The patch allows to explicitly specify the 'reg' return
type.
Signed-off-by: Prasad Joshi <[email protected]>
Verilog allows user to define variables of primitive types. The patch
adds support for defining variables of type 'logic'. The data type
'logic' is the only primitive data type which supports defining ranges.
Signed-off-by: Prasad Joshi <[email protected]>
Verilog allows user to define variables of primitive types. The patch
adds support for defining variables of type 'bit'. The data type 'bit'
is the only primitive data type which supports defining ranges.
Signed-off-by: Prasad Joshi <[email protected]>
Remove an unused variable (desired_vector_width) in elaborate.cc.
Reduce the scope of spin to make it obvious it is only used locally
in elaborate.cc. Initialize sel_type_ in the NetAssign_ constructor
(net_assign.cc). The code doesn't currently require this since
sel_type_ is only used when the base is not zero and it is always
defined when base is not zero, but giving this a default value in
the constructor hedges against accidentally using an undefined
value if someone checks the select type when the base is zero.
The $ivlh_attribute_event system function helps the Verilog runtime
support <name>'event expressions in VHDL. The vhdlpp generates a
call to $ivlh_attribute_event, which in turn uses callbacks to handle
the support.
This is also the start of the vhdl_sys vpi module. This module should
by included whenever VHDL code is parsed.
The compiler was handling bi-directional pass switches using the default
case for primitive gates, where the first port is treated as an output
and the remaining ports are treated as inputs. This patch adds a special
case for pass switches, so that the first two ports are treated as
bi-directional.
When a signal (or port) is assigned by a sequential assignment,
the signal or port becomes a reg, instead of a wire(net). Detect
this distinction during elaboration and generate the correct
signal/port declaration.
The -gno-specify flag should only control the delay and timing checks.
It should not also remove the specparams since they can be used outside
of a specify block.
The IEEE standard states that the port expressions used for arrays
of primitive gates must be the exact width required, but is silent
about the requirements for single instances. The consensus among
other simulators is that for input ports of single instances, the
expression is silently truncated to a single bit.
This patch also fixes a compiler crash if an error is found when
elaborating a primitive gate port expression.
Keep the entity/component/module port declarations in the module port
list of the generated code. This clarifies the generated code and
fixes a couple bugs for more complicated types.
R-value expressions are more general then L-value expressions, in that
the expression type may be a bit more complex. If the R-value expression
is part of an assignment, then elaborate with the constrained type from
the L-value. In other cases, where the expression type is not as obvious,
use expression type probes to figure out the type of the expression and
elaborate using that calculated type.
This patch adds code to properly calculate the type and width of a
specparam when it is used in an expression.
This patch also fixes a compiler crash when an unknown identifier is
used in a delay expression.
Icarus is not actually fast enough to run into this issue in a
reasonable amount of time. I discovered this by thinking about
the algorithm and verified the fix with custom code.
If a relative path name is passed to the Windows LoadModule function,
it is applied in turn to each path in the DLL search path. For the
ivl_dlopen function, we actually want to mimic the Unix behaviour,
where a relative path is relative to the current working directory.
On systems where the KB2264107 security fix has been applied, the
CWD is excluded from the DLL search path, so we no longer get the
required behaviour. This patch reworks the ivl_dlopen function to
give the correct behaviour under Windows.
This patch also adds a flush of the stderr stream after reporting
VPI call errors. This fixes a race between the stdout and stderr
streams when running the regression tests in a MinGW shell.
VHDL doesn't have a direct way to express "always @(posedge...)"
statements, but we do want to detect common paradigms that naturally
translate. This makes for a better translation.
Entity output ports may be used as l-values in a process within
the bound architecture. Detect that case during elaboration and
adjust the signal declaration so that it works in the Verilog pass.
Infrastructure for debug and emit of sequential statements in processes.
This does not properly handle the actual semantics of the behavioral
code, but it provides an infrastructure where we can handle all the
tricky elaboration to come.
Get to the point where our sample program parses completely, and
the sequential statements generate SequentialStmt objects and a
process object in the architecture.
Also add a few missing expression types.
The code should be able to correctly parse any command string and
assign the appropriate values from the file to a structure that will
be used to add the information to the table structure.
snprintf() copies at most N characters, but the string may not be
terminated correctly. This patch uses sizeof() so that the snprintf()
call matches the size of the buffer and adds code to insert a NULL as
the last character of the string.
Added an explicit option prefix="yy" to files that were generated
without an explicit -P.
This makes the lex-generated symbol names self contained without any
help from from build system.
The const fixes for lxt_write.c were never pushed to GTKWave so
they were lost in a later sync with GTKWave. These changes have
now been pushed to GTKWave.
If there are attributes attached to a module port declaration them
pform_bind_attribute() which is called from pform_module_define_port()
will delete the attribute list. They do not need to be deleted locally.
To get the correct definition for _FILE_OFFSET_SIZE we must include
the header that loads this before calling the other system headers.
This patch also fixes a minor spacing issues.
After some more thought I believe it is better for $q_full to return
'bx instead of 2 when $q_full is given an invalid id. This will make
the typical full/not full checks both return false. We still return
an error code in the status variable.
This patch adds preliminary support for implementing the $table_model()
function for Verilog-A. It is not currently functional, but the VPI
interface routines and data file parsing are mostly complete. The big
things left are building the data structures and adding the interpolation
and extrapolation routines.
We also need to fix vvp to identify constant strings/parameters in a
structural context.
This patch adds the ability to print a constant string in a
structural context. It also fixes the argument order for
structural function calls and makes a few improvements in
nexus identification.
This patch adds code to the compiler so that a constant string
in a structural context can maintain the string property. This
is needed but not currently implemented in vvp (it's still
converted to a number). A pending patch for the vlog95 target
does use this new information.
This patch adds support for calculating the average queue wait
time. This is accomplished by keeping two 64 bit values that
represent the high and low total wait time for all previous
queue elements. The current wait time for any elements still
in the queue are added to this total. The wait time total is
then divided by the total number of items added to the queue.
Significant rework of scope management to unify the handling of
types in the ieee library and types/constants/components in packages.
This involved adjusting the parser rules to manage a stack of scopes
and rewriting the IEEE library support to not use global maps for
the loaded types.
If the right hand operand of a shift is a signed vector value, it
is coerced to an unsigned value. This needs to be allowed for when
estimating the width expansion caused by a shift in a lossless
expression.
The power operator defines 2**-1 and -2**-1 to be zero. This patch fixes
both the procedural and continuous assignments to work correctly. It also
fixes a problem in the compiler power code so that the one constant value
always has at least two bits.
This patch adds support for calculating the queue mean inter-arrival
time. This is just the latest add time minus the first add time
divided by the number of intervals (the number of adds minus one).
This patch adds full support for the stochastic tasks/functions except
the mean inter-arrival and average wait statistics are not currently
available. These will be added in a later patch. This implementation
goes a bit beyond the standard and supports the following:
1. The job and inform arguments support 32 bit four state values.
2. The id for all routines, the job and inform arguments for $q_add(),
the statistic code for $q_exam() along with the queue type and
maximum length arguments for $q_initialize() can be less than or
equal to 32 bits. The argument will be sign extended if needed to
fill the internal 32 bit value.
3. The job and inform arguments to $q_remove() and the status argument
for all the routines must be 32 bits, but do not have to be an
integer variable (e.g. a 32 bit register or part select is OK).
4. An undefined bit in the id argument for any of the routines will
return a status of 2 (undefined queue id). Undefined bits are not
automatically converted to zero.
5. Undefined bits in the $q_initialize() queue type and maximum
length arguments or the $q_exam() statistic code argument are also
flagged as an error (are not converted to zero).
6. The $q_full() function returns 2 on error, the other routines that
return a value $q_remove() job/inform arguments and the $q_exam()
statistic value argument will usually return x on error.
7. An invalid statistic code will set the $q_exam() status to 8.
8. The $q_exam() statistic value argument can be 32 bits or larger.
This allows returning large statistical time values.
9. All time values are internally saved in simulation time units.
They will be converted to the calling module's time unit (with
rounding) before they are returned.
10. If a $q_exam() statistical value is too large to fit into the
variable the maximum positive value will be returned and the
status code will be set to 9 (value is too large).
11. If a statistical value is currently undefined $q_exam() will
return 10 (no statistical information) (e.g. using code 5 on an
empty queue).
This patch allows the compiler to perform early elaboration
of functions if they are encountered in expressions that are
elaborated before the function would normally be elaborated.
This makes the function available for constant evaluation.
Suitable error messages are generated if a function that is
used in a constant expression is not a valid constant function.
For now Icarus doesn't support a UDP instantiation with a range.
Instead of generating a warning about the port count being wrong
this patch adds code to calculate the range and print a message
if a range greater than one is found.
This creates the Package class to represent packages, and the
Scope class to represent scopes in general. The library functions
are worked up to support scanning scopes for declarations that are
imported by "use" clauses.
Make sure in a conponent instantiation that the instantiated
component is really declared, and that the ports of the binding
really do match the ports of the declared component. This requires
that we create and save component declarations, and that components
have methods for mapping the ports.
Certain types of expressions involving only constants would produce
ambiguous VHDL output. Fixed by qualifying one of the arguments. E.g.
('0' or '1') = '1'
Which is ambiguous becomes
(std_logic'('0') or '1') = '1'
This fixes the xnor_test test.
Reduce XNOR was implemented incorrectly because of trivial typo
Fixes regression of simple_gen test.
Also extended ivl_lpm_size API call to support all LPM types. This
simplifies some of the VHDL LPM generation code a little.
When a user or system function is called on the RHS of a continuous
assignment, and one of the function arguments is an undeclared
identifier, the compiler reports the error correctly but then
crashes. This patch fixes the crash.
This patch changes the method used to signal that a constant expression
is being elaborated from flags stored in global variables to flags
passed down the call chain. It also generates more informative error
messages when variable references are found in a constant expression.
There has been added additional default attribute to
all 'dump' function calls which is in all cases equal
to 0. Now one can specify how much this debug dumping should
be intended. This should allow people to dump smoothly whole
designs (as it was now) as far as separate units.
This is now the parent who specifies the base indentation
for all components (children). For example, architecture
"decides" how much their signals should be indented.
During elaboration, it is sometimes efficient to collapse a
collections of PV drivers to a net to a single concatenation.
This removes a bunch of resolutions and other nodes, and also
is the only way that 2-value logic should work.
During elaboration, it is sometimes efficient to collapse a
collections of PV drivers to a net to a single concatenation.
This removes a bunch of resolutions and other nodes, and also
is the only way that 2-value logic should work.
This gets us as far as emiting a component instantiation. Very little
error checking/elaboration is done, so there is room for improvement,
but this is a working stub.
This gets us as far as emiting a component instantiation. Very little
error checking/elaboration is done, so there is room for improvement,
but this is a working stub.
Up till now only "global" use clauses were parsed
and as a result libraries were loaded.
Since use clauses can appear not only in global context,
parsing of non-global clauses has been introduced and
selected names are now handled (like name1.name2.name3).
This gets us as far as emiting a component instantiation. Very little
error checking/elaboration is done, so there is room for improvement,
but this is a working stub.
These signals are declared in the architecture and are local to
the module. The Architecture already parsed and stored these signal
declarations, but this patch adds the ability to actually emit these
signals in the generated code.
In the process of doing this, I had to regularize the elaboration
and emit of VTypes, so that it can be used in multiple places, not
just in entity headers (for ports).
I also added support for bit selects of signals. This effected a couple
places in the parser, and expressions in general.
The bison grammar has been extended in order
to parse configuration statements. Parsing
remains very primitive but principal constructs
can be now recognized.
IEEE 1800-2005/9 says "each fixed-size dimension shall be represented by
an address range, such as [1:1024], or a single positive number to
specify the size of a fixed-size unpacked array, as in C. In other
words, [size] becomes the same as [0:size-1]."
This patch implements that translation in the parser. It issues a
warning when doing so when the generation flag is less than 2005-sv.
These signals are declared in the architecture and are local to
the module. The Architecture already parsed and stored these signal
declarations, but this patch adds the ability to actually emit these
signals in the generated code.
In the process of doing this, I had to regularize the elaboration
and emit of VTypes, so that it can be used in multiple places, not
just in entity headers (for ports).
I also added support for bit selects of signals. This effected a couple
places in the parser, and expressions in general.
This patch adds code to make sure a double (Verilog real) constant
is printed correctly. It also adds code to trim any leading escaped
NULLs from an expression string.
In VHDL it is allowed to have multiple architectures
per one entity. The proper architecture should be then
chosen in a configuration block. Now, if many architectures
will be found, then there will be a warning message printed.
FIXME notes are added in order not to forget about changes to
be done
This patch uses the new function (ivl_logic_is_cassign) to determine
if a logical was really the base of a continuous assignment. This
allows creating code that more closely matches the original.
This patch adds code that allows the targets to determine if a logical
gate came from a continuous assignment. This helps some of the targets
generate code that more closely matches the input.
It also reworks/simplifies the synthesis of && and || since the
compiler has already converted the two operands to single bit form
and fixes a mismatched delete from a previous patch.
This patch adds support for correctly handling most unconnected ports.
Most important is top level ports that are the root of the conversion.
This patch also adds support for emitting more signed constructs when
they are requested. $signed() and $unsigned() are still not supported
or recognized as an error when not emitting signed constructs.
This patch changes the module elaboration slightly to allow passing
the appropriate information for unconnected and top level ports. This
allows the vlog95 generator to get the basic structure correct.
These go into the architecture/block of their scope and will be
used by component instantiations to make sure the bindings are
correct and complete.
Also handle signal declarations. The elaborator will use these
to generate module local variables that are used by the architecture.
Also include support for "sorry" messages so that we have a place
to hang unsupported but properly parsed constructs.
In the process of doing this, I also encountered and add parser support
for indexed names. And matching "sorry" messages.
This patch adds a flag -pallowsigned=1 to the vlog95 converter that
tells it to allow signed signals. There is currently no code to check
for and warn/emit the $signed() and $unsigned() system functions. I
need to determine if >>> emitting should also be controlled by the
allow signed flag.
This patch adds support for emitting escaped identifiers and adds
code to correctly emit most module port expressions/definitions.
There are some minor code optimizations/cleanup included as well.
There was a single message when the expression width was larger
than the port width. This patch makes it a bit more clear by
saying that the expression was pruned.
Currently the compiler coerces input ports to inout ports whenever
there is an internal driver connected to the internal port net.
This generates an error if the port is externally connected to
something other than a structural net. This patch modifies the
compiler to ensure port coercion only occurs in valid cases.
This patch ensures that the result of a shift is an undefined value
if the right operand is an undefined value. It also improves the
code generated for right shifts where the right operand is constant
and optimises away shifts where the right operand is a constant 0.
It also fixes a few places where the expression type (signed/unsigned)
was not being set correctly.
The logic_lpm.c file uses the nexus private data pointer as an
unsigned counter. This patch makes the value unsigned long to
avoid a compilation warning on 64 bit systems.
This patch adds support for emitting fixed CA selects (zero based
variable bit and array selects also work), emitting a for statement
as a single statement and fixes for numerous little bugs. It also
adds the start of emitting module port information.
This patch adds some preliminary module port information to the ivl
interface. This may change as I investigate exactly what is needed.
It also fixes a few minor bugs (a missed local variable and spacing)
This patch adds a trace command to the interactive prompt that can be
used to control statement tracing when the code is instrumented (has
%file_line opcodes).
A valarray of an enum does not initialize to 0 so explicitly specify the
value to fill the array with. This was causing the compiler to incorrectly
report that fixed width elements in a concatenation had no size.
The following was done to remove compiler warning when using the native
compiler on OpenSolaris.
Remove the anonymous unions in tgt-vlog95/stmt.c and tgt-vvp/vvp_process.c.
Use UINT_MAX for the maximum unsigned unsigned instead of -1 in
tgt-vvp/draw_net_input.c.
Even though lex defines yywrap() to have no arguments when %option
noyywrp is used it generates a define that takes an argument that is not
used. The compiler warned about this so remove the option and add a
dummy yywrap function.
This patch adds a check on the expression type before adjusting an
unsized expression width up to integer_width. This adjustment should
only be performed for vectorable expressions.
The patch also fixes a few compiler warnings that only show up on
32-bit builds.
This patch adds support for tracing procedural statement execution in vvp.
This is accomplished by adding a new opcode that is inserted before the
code that represents a procedural statement. These opcodes also trigger
a message whenever time advances. By default these opcodes are not added.
To add them, pass the -pfileline=1 flag to the compiler. In the future we
may add support for turning the debug output on and off once the opcodes
have been added with a system task or from the interactive prompt.
The 1364-1995 version of Verilog does not support non zero based
parameters. This patch removes the comment requesting the parameter
MSB/LSB information to denormalize the expression and replaces it
with one stating that we need to keep the compiler normalization.
This patch removes the code that was deleting the signals in an L-value
concat if the concatenation failed to elaborate. This is incorrect since
the signal could be used in another context that is processed later. The
error message when an output/inout port fails to elaborate was also
improved to give the expression that is connected to the port.
This patch adds the rest of the functionality needed to correctly
emit both L-value and R-value procedural variable indexed part
selects as a concatenation of variable bit selects.
This patch modifies the compiler and the ivl interface to pass the
type of indexed part select that is being represented (up/down) in
a procedural L-value or R-value. This is needed by any back end that
wants to correctly denormalize the (zero based) base expression.
This patch adds support to the compiler/ivl interface for getting the
original UDP definition port names. ivl_udp_port() was added to get
this information.
This patch adds partial support of procedural variable indexed part
selects (both R and L-value). The restriction is that this currently
only works on a zero based little endian vector. I need to know if
the select is an up or down select to correctly denormalize the base
expression for the general case.
This patch adds copyright information for the Icarus generated UDPs
(lesser GPL version 2.1). It also prints a note to let the user know
that this copyrighted code is being included in the output file. They
can then remove the primitives if needed. These are likely only
needed when the output is from synthesis. At the moment we only have
a positive edge D-FF. In the future a negative edge FF and D latches
will also be needed.
Add a preliminary gate name and range (zero based) for logic primitives.
Also assert that a logic gate in a continuous assignment has the correct
number of inputs/outputs.
This patch adds code to emit variable real procedural delays by
removing the scaling that is added by the compiler. It also
recognizes that all variable continuous assignment delays are
scaled at run time.
This patch reworks the delay emitting code to handle delay expressions
better. It also encloses the emitted unary operators in parenthesis to
make sequenced unary operators work properly.
It was incorrect to extend emit_expr_signal() to handle a local signal
(a continuous assignment). The only way this should ever happen is
when evaluating a variable delay expression. It is better to do this
checking in the delayx evaluation where we know if we are processing
a delay for a statement or a continuous assignment. This keeps the
emit_expr_signal() routine cleaner and we only allow a CA delay for
a continuous assignment.
This patch fixes the following bugs in the vlog95 converter:
When emitting a signal as an expression, if the signal is local then
emit the expression that is driving the local signal.
The casts need to emit the expression.
When emitting pull devices they have different default strength rules
(pull is the default).
For compatibility pull devices should only have a single output net.
Extend the code that searches for the <var> = <delay> <value> pattern
to also check for an <event>. The previous event code only looks for
the repeat event pattern.
In principle, some of these should be handled by overloaded operator
functions, but these are built in types with natural translations so
do the obvious things.
Implement the parser infrastructure for handling library use clauses,
and use that to handle specific packages of the ieee library. Make
the numeric types come from the numeric_* packages instead of being
built in.
There are internal types that are unbounded arrays. Allow subtype
syntax that creates bounded versions of these arrays, and elaborate
them as vectors at port boundaries. This makes some interesting types
work out.
Also start replacing vhdlint and vhdlreal with int64_t and double,
which are reasonable values for universal_integer and universal_real
from the VHDL standard. I need these cleaned up because the ints in
particular are used for the literal expressions in array index constraints.
Rather then just relying on comparing type names all throughout
elaboration, create type description data structures and use them
during elaboration to handle proper types.
So translate them to lower case so that internally I don't have to
constantly worry about it. Note that even keywords are case insensitive,
so do the translation BEFORE the keyword check.
Rather then leave net types to implicit declarations, write
declarations explicitly. This will become necessary when more
interesting types are supported.
Separate elaboration from code generation in the Entity, and add
to Architectures a code generator to handle some simple cases. At
this point we have the basic structure for the VHDL compiler.
Elaboration will need a parse tree for expressions. Create one for
the expression types that are currently supported. Also add rules
and the keywords for all the remaining binary logical operators.
This patch adds a flag that emits file and line information for
most lines. This can help the user understand where the various
lines came from in the original code. They are printed as
comments so the generated code still runs correctly.
This patch fixes a bunch of objects to have the correct file/line
information. It also adds support for getting file/line information
for events (named events have a definition line).
When emitting a logical device as part of a continuous assignment
we need to use the actual inputs (not the output). We also do not
need to emit anything if the nexus is NULL. Also skip logical gates
that have a local output since they are part of a continuous
assignment and the inputs to a logical gate can be an expression
so emit them as a continuous assignment.
This patch adds the following to the vlog95 converter.
Add support for emitting and calling UDPs.
Generate a UDP for a synthesized DFF.
Add the ability do emit a constant assigned to a net.
This patch adds/fixes the following:
Adds file/line information to a UDP definition.
Prints an error message if a UDP is passed signals wider than 1 bit.
A UDP should supports a range, but the compiler currently does not.
Add scope information for constants.
Fix the Icarus extension UDP table entry element 'h' to use h.
The ivl_udp_init() value is a char not unsigned.
Add FILE_NAME() for a bunch more of the ivl interface objects.
This patch adds code that when it find a select of a constant it looks
for a parameter in the enclosing scope and the module scope that has
the same line, file and value information. If it find one that is
used to rebuild the expression. A more exhaustive search is need to
make this 100% clean.
It also uses the named scope when emitting statement inside a named
begin or fork instead of the enclosing scope.
This patch moves the logic and lpm code to a new file. It refactors
the strength emitting routine and adds support for emitting the
standard tran style of gates.
This patch adds the ability to translate the code produced by the
compiler for a wait statement back into a wait statement. It also
reworks the strength emitting code to only emit a single strength
for the pull gates and fixes a bug in the strength emitting code.
Currently the vvp target emits multiple single bit %mov instructions
to perform sign extension. This patch adds a new %pad instruction
that allows sign extension to be performed with just one instruction.
A NOOP at the end of an existing statement can be represented as ";\n"
(a simple line termination). In general a NOOP represents an empty
begin/end pair.
This patch add the following functionality to the vlog95 generator.
Add support for most CAs. Selects still don't work correctly.
Emitting a named event as an expression.
Enhance the ability to find a signal in a nexus.
Add code to emit a nexus driven by a constant.
Rework the delay/strength code for logic gates/CAs
Refactor some of the number code.
Refactor the variable emitting code to support named blocks.
Translate the compiler code back to <var> = <event> <value>
In the standard a pull device can be given both a 1 and 0 strength.
Only the appropriate one is actually used. This patch adds support
for giving both pull strength to a pull device.
This patch adds support for emitting an array as an expression. This is
used as a system task/function argument.
It partially reworks the real display code to print an appropriate
expression for NaN, inf and -inf. To get other real numbers to always
display correctly we need to build a custom printing routine that adjusts
what is displayed based on the actual bits in the double.
Add the ability to print a real variable delay. They are not scaled by
the compiler.
Since a delayx delay may be variable we must always enclose this type of
delay with parenthesis.
Fix the L-value concatenation to be in the correct order.
Handle the special case that an if with a single if as the true statement
does not loose any associated else clause to the enclosed if. Basically
add a begin/end pair as needed to make things work out correctly.
This patch fixes the following problem in the compiler:
An integer task argument should be marked as an integer port.
An implicit register can be converted to either a reg or an integer.
An old style task port should default to <no type> unless reg or some
other type is provided. ANSI style is always defined. For example:
input ri;
output ro;
inout rio;
real ri, ro, rio;
should define all three task ports to be of type real.
This patch updates the make clean target and modifies the vpath search to
match what is done in the main ivl Makefile since this one has the same
issues it does. It also adds a cppcheck target and removes the redundant
libmisc build target since the vpath already handles this.
This patch adds the ability for the user to change the spacing increment
from the command line using the -pspacing=<num> flag. The is restricted to
be a value between and including 1 and 16.
This patch fixes the ivl build to find files in libmisc using vpath instead
of a separate target. The existing constructs caused build problems after
running a make clean. It also adds an empty checking target to vhdlpp.
This patch adds preliminary support for finding the correct name for
a nexus at a given scope level. It also does the following.
Report that real modulus is not supported.
Fix a bug in the generation of concat expressions.
Add missing generation of unary ! operator.
Add ability to generate > integer delays.
Refactor some of the support code.
Make some of the error messages more descriptive.
Ignore the ALLOC and FREE statements (only used with automatic tasks).
If the left power operator expression is a numeric constant that has a
value 2^n n>0 then we can use a left shift to calculate the result. This
patch adds code to do this. All other power expressions are flagged as a
compilation error.
This patch adds significantly more functionality to the vlog95 back end.
The following are the major additions:
Display unsigned numbers without undefined bits in hex.
Add support for both L-Value and R-value bit and part selects.
Added support for out of scope references.
Added support for emitting logic gates (range not finished, name is invalid).
Added support for emitting initial/always blocks.
Add support for event inter statement delays.
Convert a blocking inter statement delay assign back to the original form.
Added support for rescaling variable delays.
Added support for the disable statement.
Added support for an event trigger statement (event name is missing).
Added support for calling a user task (calling arguments are missing).
Added support for an event based delay statement (@) (event name is missing)
Not all of these are working as expected since there is not currently a
routine to find a nexus name as a function of scope (needed for event names,
logic gate ports, etc.). Since the Icarus compiler generates structural code
the arguments to modules, module instantiations and calling user tasks are
also still missing.
Include the compiler infrastructure to vhdlpp for collecting the
file and line information and attaching it to entities and ports.
Make the parser store the file name during parse.
Create a libmisc library where I can put source files that are
used by multiple programs within the source tree.
Add enough rules to parse a simple VHDL program:
Parse library and use clauses,
Parse entity declarations, and
Parse architecture bodies.
Add some parser infrastructure:
Handle syntax errors with useful error messages,
Include file name and line numbers in parse errors,
Add some parser debug aids.
The original message talks about an unresolved net which may be
something different/more encompassing. This patch explicitly adds
uwire to the message to make it clear to the user that a uwire
could cause this message.
This patch doesn't completely fix the problem, but with it the problem
is at least manageable. The issues was that when the lexor_keyword.gperf
file is updated and you are building outside the source directory the
Makefile would create a local lexor_keyword.cc as expected. The problem
is that it always looked in the source directory for the file. This
patch adds a special vpath rule that says to look in the build directory
first and then in the source directory for lexor_keyword.cc.
This works as expected except for the first time the lexor_keyword.cc
file is generated locally. During the make invocation it compares the
source lexor_keyword.cc file to the gperf file and notices it is out of
date. It then generates a new file in the build directory, but the make
rule is still using the source file which didn't change so it doesn't
rebuild as needed. To get the new file to compile you need to run make
a second time to get the rule to execute using the local version of the
file. This extra make invocation is only needed when the local file is
first created since after that the rule always uses the local file.
I plan to look at resolving the remaining issue, but there is much
subtlety in this since you effectively need to break/rebuild the make
dependency tree to get this to build correctly in a single run.
This patch adds support for using a scope in an expression and calling
a user function. It also fixes an issue in the module name mangling
and calling a system task/function with multiple arguments.
This patch adds support for the various case statements and adds
preliminary support for instantiating modules. The module instantiation,
just like the module definition, is still missing ports. Adding this
will require modification to the compiler to get the port order correct.
Because of defparams and passed parameters any module that has a
parameter must be generated uniquely for each instance since they may not
all be the same. Modules without parameters are only generated once.
For diagnostics and to know what is really going on in the compiler
we need to keep any NULL that is in a verinum string or when
displayed as/converted to a string.
When padding a verinum string if the padding is in multiples of eight
then keep the string property.
This patch fixes a small bug found with the vlog95 back end. A root scope
should define is_cell instead of leaving it undefined. Normally I would
expect a root scope to not be a cell, but I don't think the standard
prohibits this from happening, so copy the value from the definition.
This patch adds the ability to print a delay expression (it is rescaled
to the module timescale) and adds support the following statement types:
nonblocking assignment with a delay (event control is still missing)
condition (if/else)
forever
repeat
while (Icarus translated for loops to while loops)
fork
procedural continuous assign
deassign
force
release
This patch adds support to the vlog95 convert for the ternary operator,
the concat/repeat operator and calling a system function. It also adds
the `celldefine information when appropriate.
This patch adds more support to the Verilog 1995 converter. There is
still a lot that is missing and there is still some implemented
functionality that is not 100%.
It was documented that ivl_scope_port(s)() could be used with tasks,
but the code did not support this. This patch adds that functionality
as documented. It also removes the documentation for ivl_lval_mem()
since that function no longer exists.
It was a poor choice to only add -g2009 for 1800-2009 and ignore the
previous version of System Verilog 1800-2005. This patch adds a
generation for 1800-2005 and also adds `begin_keywords support for
1800-2005. The previous SystemVerilog keywords have been put under
the 1800-2005 generation and the new one from 1800-2009 have also
been added.
When a verinum is displayed as a string we need to make sure that any
character that will be displayed as an octal constant must be converted
correctly. Also change to isprint() instead of isgraph() since it is the
same as isgraph() plus a space.
Cadence allows an ifnone with an edge-sensitive path. Until we understand
exactly what this is and how to implement it this patch adds a warning
that an ifnone with an edge-sensitive path is not supported.
Constant user functions aren't currently supported. A suitable
error message should be output when a user function call is
encountered in a parameter expression. This got lost in the
parameter expression rework.
The compiler currently performs parameter expression elaboration before
performing parameter overrides. This means that the information needed
to correctly determine the expression type and width may not be available
at the time elaboration is performed. This patch reworks the code to
delay elaboration until after all overrides have been performed. It
also provides a new -g option that controls how the width of parameter
expressions is calculated when the parameter itself is unsized.
This patch fixes a few compilation warnings introduced by the
enumeration code. It also updates the ivl.def file so that the
proper routines get exported under windows.
Using reg real [1:0] var you can define a real variable with a
range. This was crashing the run time. This patch catches this
in the compiler and prints an appropriate message.
This gets the enumeration type through to the ivl_target API so
that code generators can do something with it. Generate stub
output with tgt-stub, and generate the proper vvp run time to
make simple enumerations work from end to end.
With warnings turned sufficiently high in gcc, I get:
.../vpi_user.h:568: warning: function declaration isn't a prototype
when building VPI modules. Patch is trivial.
At the moment we only support one real driver. This patch adds a
combined error routine for a uwire or a real net with multiple
drivers. We display the top level net in the hierarchy. It also
reworks the nexus data_type calculation.
System tasks and functions can be defined to have NULL arguments.
This patch makes the @* sensitivity list calculation skip these
NULL (constant) arguments.
This patch adds asserts after new to verify that memory was allocated
correctly and adds a warning if some of the routines are called with
an invalid function name.
Create the v2009.vpi module to include SystemVerilog core
functions, and start out with some of the enum methods.
Add to vvp support for creating enum types, including some
vpi access methods.
The pform propagates the parsed enum base type information
to the elaborator so that the base type can be fully elaborated.
This is necessary to get the types of the enumeration literals
correct.
This patch covers more than it should. It removes many of the -Wextra
warnings in the main ivl directory. It also makes some minor code
improvements, adds support for constant logicals in eval_tree (&&/||),
adds support for correctly sign extending === and !==, it starts to
standardize the eval_tree debug messages and fixes a strength bug
in the target interface (found with -Wextra). The rest of the warnings
and eval_tree() rework will need to come as a second patch.
The files we get from GTKWave are not under our control so we need to
ignore the cppcheck style warnings for them. The random routines are
from the standard so they should not be changed to fix style warnings
either. We also have some weird, but correct pointer subtraction that
cppcheck warns about. This patch adds suppression files for all these
warnings. You must have the latest cppcheck from git since I submitted
a patch that adds the ability to place comments in the suppression file.
In ivl_alloc.h we redefine malloc(), realloc() and calloc() to have
standard error checking. We don't want to do this for anything that
comes from the standard headers. This specifically doesn't work if
a C++ header files does std::malloc, etc.
Also change to -W instead of -Wextra since that is more portable. I
plan to add a check from -Wextra and use it when available since it
is more descriptive.
This patch changes all the iterator code to use a prefix ++ instead
of postfix since it is more efficient (no need for a temporary). It
is likely that the compiler could optimize this away, but lets make
it efficient from the start.
When enum names are used as r-values in expressions, use their
values. Treat the enum names similar to (but not exactly as)
localparams so that they fit into the rest of the elaboration
flow naturally.
I'm adding more uses of the make_range_from_width function, so
it seems like time to get rid of its use of the svector template.
This thread led to a lot of other uses of svector that had to
also be removed.
BOOL values have a specific cast from LOGIC, this node takes care
of it. Also arrange for the elaboration to insert them in the right
planes and for the code generator to generate them.
This patch adds -Wextra to the compilation flags for C++ files in
the vvp and vpi subdirectories. It also fixes all the problems
found while adding -Wextra. This mostly entailed removing some of
the unused arguments, removing the name for others and using the
correct number of initializers.
This patch adds support for running cppcheck from the Makefile. It also
standardizes the order of some of the targets. It renames vpip_format.c
to vpip_format.cc and fixes the size of the array tables to make room
for the trailing NULL. Found when using a C++ compiler.
This patch adds a few missing initializations to various constructors
in the vvp directory. It also enhances the array alias code to copy
more values from the aliased array.
Starting in autoconf 2.68, "the macros AC_PREPROC_IFELSE,
AC_COMPILE_IFELSE, AC_LINK_IFELSE, and AC_RUN_IFELSE now warn if the
first argument failed to use AC_LANG_SOURCE or AC_LANG_PROGRAM to
generate the conftest file contents."
IVL_VT_BOOL variables at the code generator should generate
.var/2x records so that the run time can do 2-value optimizations
and otherwise support atom2 values.
SystemVerilog allows variables to be either variables or unresolved
nets, depending on how they are used. If they are assigned by
procedural code, then they are variables. If they are assigned
by a continuous assignment, they are unresolved nets. Note that
they cannot be both, and when they are unresolved nets they can
only be assigned once.
Create the .var/2u and .var/2s variable records and give them
basic implementations. Make available to VPI the proper types
for the SystemVerilog types that these variables represent.
Follow-up to "Brainless start to const-correct changes"
Still actually does nothing, but now if the #define ICARUS_VPI_CONST
in vpi_user.h is changed to const, Icarus is almost const-correct,
as checked with gcc flags -Wcast-qual -Wwrite-strings.
Choosing when to #define ICARUS_VPI_CONST const is left as an
exercise for the reader.
With these two patches applied, and the const define, there are
still about a dozen const problems left.
Results of running
cd vpi
for f in *.c *.h; do sed -i \
-e "s/_calltf(PLI_BYTE8/_calltf(ICARUS_VPI_CONST PLI_BYTE8/" \
-e "s/_compiletf(PLI_BYTE8/_compiletf(ICARUS_VPI_CONST PLI_BYTE8/" $f; done
and a trivial patch to vpi_user.h to, among other things, make
ICARUS_VPI_CONST blank.
Thus, this patch does absolutely nothing. Will be followed by a
(much shorter) patch that makes it do something. :-)
This is a fix for pr2555831. A separate entity/architecture pair is
generated for each module that is instantiated with a unique
parameter combination.
For example:
-- Generated from Verilog module child (vhdl_tests/generics.v:30)
-- MY_VALUE = 3
entity child is
To make it clear which values were used for this entity.
Conflicts:
tgt-vhdl/scope.cc
This changes the implementation of $display/$write to use VHDL
report statements rather the the std.textio functions. The code
produced is simpler and more like what a real VHDL designed would
write. However it no longer exactly matches the Verilog output as
most VHDL simulators prepend the text with simulation time, entity
name, severity level, etc. There is a corresponding change in
ivtest to support this.
Conflicts:
tgt-vhdl/cast.cc
tgt-vhdl/display.cc
tgt-vhdl/vhdl_syntax.cc
tgt-vhdl/vhdl_target.h
Previous we generated a "wait for 0 ns" statement after
every blocking assignment that wasn't the last statement
in the process. While this implements the Verilog semantics,
it generates excessive waits, and cannot usually be synthesised.
This patch only generates "wait for 0 ns" statements when it
cannot be avoid (e.g. when the target of a blocking assignment
is read in the same process).
An example:
begin
x = 5;
if (x == 2)
y = 7;
end
Becomes:
x <= 5;
wait for 0 ns; -- Required to implement assignment semantics
if x = 2 then
y <= 7; -- No need for wait here, not read
-- wait for 0 ns (previously)
end if;
Conflicts:
tgt-vhdl/process.cc
tgt-vhdl/stmt.cc
tgt-vhdl/vhdl_target.h
Add code to print a warning if the user tries to use the -S flag.
We need this warning since synthesis is not currently being actively
maintained or supported in any branch after V0.8.
An unsized signed constant that is smaller than integer_width needs
to be resized up to either the integer_width or the expression width
whichever is smaller.
Fix all the Icarus files that can be so that we do not have any
signed/unsigned compare warnings. It also removes const as a
return qualifier for two routines in discipline.h.
This patch mimics what was done for vectors, but is simpler since
arrays don't use the endian information. It also needs to address
the fact that .array/port assumes the expression is unsigned so
any signed expression must be padded to make it larger than the
maximum array word when it is converted to unsigned.
This patch modifies all the variable bit and indexed part selects
to use a common routine. This routine determines the minimum
width needed to calculate the result correctly, pads the expression
if needed and then converts the expression to signed if required to
make the calculation correct.
The Cygwin man command requires that you have a / in the path
if you want to avoid looking at the normal search path. This
patch addes ./ before the manual page file name. Which should
work on any system. It also makes the vvp generation create a
PS file like is done in the other Makefiles.
By default we generate normal manual pages. You can then
create PostScript version and from these you can generate a
PDF version.
While checking for an infinite loop in an always block I missed
the case where an if statement does not have a statement. This
was resulting in a segmentation fault.
This is a fix for pr2555831. A separate entity/architecture pair is
generated for each module that is instantiated with a unique
parameter combination.
If someone accidentally makes a parameter depend on itself
we need to report this not crash. This patch fixes the crash
and prints an appropriate string of messages to figure out
the loop. Icarus currently supports forward references of
parameters so more complicated loops can be created. These
are also caught.
To prevent a force from back propagating we need to keep a BUFZ
that represents a continuous assignment between two nets. This
only effects continuous assignments of the form assign out = in.
In general these are fairly rare so keeping them has minimal
impact on the simulation speed.
Add code to print a warning if the user tries to use the -S flag.
We need this warning since synthesis is not currently being actively
maintained or supported in any branch after V0.8.
For example:
-- Generated from Verilog module child (vhdl_tests/generics.v:30)
-- MY_VALUE = 3
entity child is
To make it clear which values were used for this entity.
This changes the implementation of $display/$write to use VHDL
report statements rather the the std.textio functions. The code
produced is simpler and more like what a real VHDL designed would
write. However it no longer exactly matches the Verilog output as
most VHDL simulators prepend the text with simulation time, entity
name, severity level, etc. There is a corresponding change in
ivtest to support this.
Previous we generated a "wait for 0 ns" statement after
every blocking assignment that wasn't the last statement
in the process. While this implements the Verilog semantics,
it generates excessive waits, and cannot usually be synthesised.
This patch only generates "wait for 0 ns" statements when it
cannot be avoid (e.g. when the target of a blocking assignment
is read in the same process).
An example:
begin
x = 5;
if (x == 2)
y = 7;
end
Becomes:
x <= 5;
wait for 0 ns; -- Required to implement assignment semantics
if x = 2 then
y <= 7; -- No need for wait here, not read
-- wait for 0 ns (previously)
end if;
This patch adds a check in the vvp back end that a uwire has
at most one driver. Previously this was just converted (with
a warning message) to a wire just after elaboration.
This patch adds the ability to call a system function as a task for
the SystemVerilog generation (-g2009). The return value is really
calculated, but it is ignored.
E.g. $signed(x) > y with x, y different sizes should be
resize(signed(x), N) > y
Not
signed(resize(x, N)) > y
As this does not treat the sign bit correctly. Was causing
the signed5 test to fail.
Added 'expr_wid' parameter to calls to 'eval_expr()' within
PEBinary::elaborate_eval_expr_base_()'. This makes a specific problem
go away and may even be the correct thing to do.
This patch adds support for a UDP with variable delays. In the process the
intrinsic support for delays was removed from the UDP functor and replaced
with a call to the .delay functor. Both a normal gate and a UDP now use the
same code to generate the delay.
This patch adds checks that the delay count is correct for the
various gates and adds support for a missing variable decay
time. For this case the decay time is the minimum of the rise
and fall times. This is denoted by setting the decay variable
to 0 in the vvp file. vvp notes this and sets an ignore decay
time property in the base delay. This turns off the ability
to set the decay time and the minimum delay calculation will
also update the decay time.
These checks are not needed since we have already verified that
we have a 64 bit immediate value. This is likely old code that
should have been removed when the original functionality was
changed.
This patch pushes delays for tranif gates to the code generator.
We still need to add checks for the number of delays, etc. For
now an error message is printed when a tranif gate is given a
non-zero delay.
This patch modifies the real ternary operator code to support
unlimited tail recursion without overflowing the thread
registers. Head recursion is still limited by the available
registers.
It fixes the thread word checks to use a new define that has
the correct number of thread words (16). It adds a message
instead of just an assert if the thread words are exhausted.
And it also changes some of the error messages to use vvp.tgt
in the message to be consistent with the other messages.
Elaborate conditional assignments with BUFZ devices that do *NOT*
preserve strengths. Add a BUFT (transparent) device that can be
used in those cases where I really need a transparent buffer.
We only need to set the width of a multiple if the width is greater
than zero and if the expression is vectorable. This matches what is
done for addition.
A real delay must be scaled and rounded using the local precision
before it is finally scaled to the simulation time units. This
patch fixes the compiler to do this correctly or generate the
correct code for run time calculated delays. Delays in a CA
already worked correctly. The run time was also fixed to scale
modpath (SDF back annotation) delays correctly.
This patch modifies the vvp main code to cleanup if there was an
error compiling the input file. There are still a few issues, but
this takes care of most of them.
The error routines for task and function definitions were incorrectly
popping the scope. This should not be done since no scope was pushed.
Also assert that the current_task/function is 0 to catch that kind of
error like the other definition rules.
This patch adds two new opcodes and the infrastructure needed to call
system functions as tasks. The normal %vpi_call will generate an error
if a system function is called as a task. %vpi_call/w will generate a
warning and will ignore any value returned by the function. %vpi_call/i
will ignore the system function return value and will not print a
message. Adding this is a feature request and is supported in
SystemVerilog. Next I need to add flags to control this depending on
the compiler generation and possibly other flags.
I may leave the cast to void (%vpi_call/i) functionality unimplemented
for now.
This patch caches the vpi_call error messages (task/function does
not exist, task being called as a function and function being
called as a task). This allows us to display the file name and line
number information for the invalid usage.
When pushing the current file path we need to get past any `define
expansions that have been pushed onto the stack to find the real
file path.
This patch is partially based on a patch submitted by Steve Tell.
This patch avoids a crash when trying to use a parameter/localparam that
has been assigned a value from a constant user function. Icarus does not
currently support constant user functions so it creates a parameter with
a NULL value. This patch fixes a few places where this could crash the
compiler.
You need to probe the expression width before trying to elaborate and
evaluate an expression. The eval_path_component() routine was missing
this and was causing an assert.
The functions (malloc, free, etc.) that used to be provided in
malloc.h are now provided in cstdlib for C++ files and stdlib.h for
C files. Since we require a C99 compliant compiler it makes sense
that malloc.h is no longer needed.
This patch also modifies all the C++ files to use the <c...>
version of the standard C header files (e.g. <cstdlib> vs
<stdlib.h>). Some of the files used the C++ version and others did
not. There are still a few other header changes that could be done,
but this takes care of much of it.
gcc on OpenBSD reported shadow warnings for variables, arguments named
log, time and exp. This patch renanes those variables to logic, timerec
and expr.
This syncs fstapi.c to the latest from GTKWave CVS. This cleans up
most of the issues. I still have two to track down, but I think they
are cppcheck bugs not fstapi.c deficiencies.
The fstHandle is only a uint32_t so to avoid compiler warnings on 64
bit systems cast this to long before casting to a pointer.
Also reformat some of the code to match the rest of the Icarus code.
This patch documents that the lxt2/lx2 dumper supports -speed and
-space options. It adds -speed, -space, -space-speed and
-speed-space options for the fst dumper. Here are results for a
gate level back annotated design using the fst dumper.
<none> 12.88 seconds 3.5 Meg dump file.
-space 12.89 seconds 2.9 Meg dump file.
-speed 12.36 seconds 4.6 Meg dump file.
-<both> 12.84 seconds 3.2 Meg dump file.
We keep a scope list that is checked to verify that we do not try
to dump duplicate scopes or variables. Since the scan_item routine
can not add duplicate scopes we only need to sort the list after
the scan_item routine is called. Calling it every time a scope
was added was creating a significant startup delay for gate level
simulations since the sort routine is called for every scope in
the design (possibly thousands of times).
This mostly matches what was done for the LXT dumper except the
LXT dumper was incorrectly sorting before not after scan_item
was called. This would not catch a duplicate variable just
after a scope was added in a $dumpvars call.
The lxt2 routine was referencing the lxt not the lxt2 versions
of the space/speed flags. This also adds the lx2 version of the
flags. These were already supported in the sys_table.c file.
This patch is a slight modification to files Tony Bybell (the author of
GTKWave) send to me. We still have a few more changes we plan to make,
but this should be functional enough for initial testing. Multi-treading
and speed/size flags will be added shortly.
The make_pair() routine has a PExpr* as the second argument. Not all
compilers can promote a child correctly, so just assign the child type
to a PExpr* when they are created solves this issue.
vpi_config.h defines _FILE_OFFSET_BITS. This must be defined before
any system includes files are processed, so vpi_config.h must be
called first. This patch puts vpi_config.h first. It also removes
direct calls for both vpi_config.h and vpi_user.h when sys_priv.h
is included since it already includes these two files.
It also updates the code to always include vpi_user.h using double
quotes.
Using -xMD generates dependencies for all files including the
system files. This could point to some system .cc files and
was causing GNU make to try to build these files if the
dependency files existed. Using -xMMD generates only the
dependencies outside the system directories.
It's possible that the OpenSolaris make knows how to deal with
this correctly, but Icarus needs GNU make.
This is generating an octal constant but there is no reason to have
three '\' characters. You need two to get the leading '\', but the
last one is not needed.
The SunPro compiler does not support struct definitions inside an
anonymous union. This patch moves the struct definition so that both
gcc and SunPro 12.1 compile this without issue.
gcc supports creating an array with a run time defined size. The
SunPro compiler for OpenSolaris does not. This patch converts the
array creation to use conventional (malloc based) array creation.
This patch is similar to the previous patches and cleans up a single
place in the vvp directory where an enum had a trailing ',' and a
place where a C++ routine needed extern "C".
Some new shadow issues have crept in. This patch fixes these new
issues and adds -Wshadow to the normal warning flags to keep any
new occurrences from happening.
Since the base lxt_write.c and lxt2_write.c files reference <config.h>
instead of "vpi_config.h" all their definitions need to be moved to
the main config.h include file.
This patch updates all the Makefile.in files and configure.in
as follows:
Do not use the -Wall warning flag when using the SunPro compiler.
The SunPro compiler uses -xMD instead of -MD.
There are still more fixes needed before Icarus will compile
on OpenSolaris.
Tran islands must do their calculations using the forced values,
if any. But the output from a port must also be subject to force
filtering. It's a little ugly, but hopefully won't hurt the more
normal case.
The comparison and reduction operators only have a single output bit
that can be delayed.
The comparison of real values always produces a logical value so the
delay type is not dependent on the arguments type.
The repeat expression is evaluated in a self determined context
(expression width == -1). It needs to call probe_expr_width() to
figure out the width needed by the expression before calling
elab_and_eval() to elaborate the expression.
This patch updates the lxt_write.h and lxt2_write.h header files
to the latest ones from GTKWave CVS. It also adds HAVE_INTTYPES_H
to the vpi_config.h.in header.
This patch fixes two places where Icarus under certain conditions
would try to free a NULL iterator value in $dumpvars(). $dumpvars()
can have a NULL argument to indicate that all variables should be
dumped. Under two error conditions the code was trying to free
this NULL argument reference.
The standard does not define if vpi_free_object() can support a
NULL reference. Icarus does not currently allow it (it asserts).
This patch adds support for converting bit based ports to real signals.
You can only do this for single instances. Arrayed instance would
create multiple instances driving the same real signal.
Any real port can be connected to a bit based signal. The only limitation
is that the signal width must be an integer multiple of the instance
count since all the real conversions must have the same width.
Also add an error message for an arrayed instance with real to real
output connections. Again multiple drivers.
This patch also adds errors for inout real and bit based inout ports
driving a real signal. There is no logical way to deal with the full
capabilities of inout and real ports/signals. So for now they are not
allowed.
This patch remove the old VAMS $log function. It could create confusion
with the Verilog $log task. Recent versions of VAMS and 1364-2005 use
$log10 for the base 10 logarithm.
Comparison expressions have sorta-self-determined arguments.
Handle the special cause that some of the arguments may be
themselves unsized, and so expecting to be even wider then
otherwise.
Operands to reduction unary operators are self determined, so
evaluate the operands that way. But this means that binary expressions
in this context should take pains to use their test_width tested
expression width.
This exposed a case where the test_width methods were not called
for self-determined expressions. Fix that too.
It is acceptable to call delete on a NULL object. It's also acceptable
to assign the value to zero if it is already zero. Removing the
superfluous if should produce slightly better code since there is no
conditional to deal with except for what is likely in the delete
implementation, but that should be highly optimized.
This patch cleans up some style issues: no need to check that a value
is defined before freeing or deleting it, use C++ style casts, make
sure to NULL terminate strncpy(), empty() is faster than size() for
size == 0 or size >= 0 checks, re-scope some variables, etc.
When searching for a symbol we do not want to search up the
hierarchical stack if the symbol we are searching for was
prefixed with a hierarchical path.
This patch adds support for iterating over the list of vpiUserSystf
tasks/functions that have vpiUserDefn set. The vpiUserDefn property
is true by default, but you can call vpip_make_systf_system_defined()
to set this property false (will hide the vpiUserSystf object). All
the normal system tasks/functions have been modified to call this
procedure to remove them from the list of vpiUserSystf objects. Only
user defined system tasks or functions should appear in the list.
vpi_compare_objects() is just a simple are the two pointers the
same. This works correctly for the vpiUserSystf objects, but the
other handle objects have not been checked.
This patch changes system tasks and functions to use the vpiUserSystf
property and returns this information when vpi_register_systf() is
called. It also adds the vpiUserDefn property for system tasks and
functions which for now always returns 1 (true). System task and
functions can now get a handle to this information using the
vpiUserSystf property. vpi_systf_info() returns pointers to the
real data so the user will need to be careful when using the pointer
fields (e.g. tfname, user_data, etc.). This is a shallow copy. A deep
copy would require the user to free the various fields and I'm not
certain it is even possible or desirable to copy the user_data for
all cases.
A stub for vpi_compare_objects() was also added since I will need
that when testing the second half of the patch (add iteration over
all the vpiUserSystf objects and add a method to control vpiUserDefn).
The latest gcc with the latest Cygwin complains when passing a char to
the toupper, tolower, isspace, isalnum, isprint, isdigit or isalpha
functions/macros. These functions are defined to take an integer. This
patch adds cast to int as needed to remove the warnings. After this
there are still two warnings related to signed/unsigned comparison in
yy_get_next_buffer() (part of flex).
To ensure the initial propagation of 'x' values at time-0 does not
trigger any events, the propagation of these values needs to be
completed before any statements that wait on events are executed.
vvp has a pre-simulation event queue to handle this, but some
functors defeat this by postponing their output propagation using
the stratified event queue. This patch fixes this by using the
pre-simulation event queue to schedule functor output propagation
until initial value propagation is complete.
To match the behaviour of other simulators, delayed bit-based signals
should have the value 'x' and delayed real valued signals should have
the value 0.0 until the true initial value has propagated. This patch
provides this behaviour.
Under certain circumnstances, the vvp code generator can generate
a .part/pv that directly feeds an input port of a .concat. This
patch adds a recv_vec4_pv method to the vvp_fun_concat class to
handle this case. It also changes the initial value of the stored
vector from X to Z to correctly handle bits which are not driven.
If a net is driven by a simple variable, an initial 'x' value is
propagated to the net at time-0. The same thing should happen if
a net is driven by a variable array word. This patch makes this
happen by scheduling an initial event for each array port attached
to a variable array.
The SDF file format supports zero or more timing specs. Previously
the parser was one or more. Things like tie high/low cells do not
have any delay information so zero or more is needed and matches
the standard.
When building a modpath the source for the modpath must have the
same scope as the modpath. This is required to make the back
annotation work correctly (have the correct names).
This is the initial commit in an effort to build a 1364-1995
back end for Icarus Verilog. It is expected that this back end
will allow the user to write 1364-2005 RTL and then using this
back end (converter) generate functionally equivalent 1364-1995
compatible code. This can be used to support older tools in a
work flow. The primary focus will be simulation equivalence,
though I expect to verify logical equivalence as well.
The vpi_get_value() function should not crash when called during
the compiletf phase. This patch fixes this by returning 'bx for
any vectors in thread space. It also fixes some other minor things
that my test code uncovered. Most of the other objects work as
expected.
This patch enhances elaboration to drop/ignore zero replication
count constants. Not doing this was causing problems later in
the compiler. We still pass non-constant expressions since
both user and system functions must be run for their possible
side effects. Constants can never have a side effect so just
dropping them is acceptable.
This patch adds support to $sdf_annotate to ignore RECREM constructs
in the SDF file. It also adds the ability to not specify all the
values in a rtriple (e.g. 1.1::1.6).
This patch adds support for passing the delay selection to the
VPI interface. It adds a new property to both the vpi_get and
vpi_get_str calls to return the current delay selection. It also
defines three constants for minimum, typical and maximum
delay selections.
This patch adds support for passing the delay selection to vvp.
It adds a new header :ivl_delay_selection "<value>"; that has
the values TYPICAL, MINIMUM or MAXIMUM depending on the -T
flag to iverilog. This information is needed by $sdf_annotate
to select that appropriate value for a triplet when
"TOOL_CONTROL" is specified (default).
This patch mimics what was done for normal assignments to get the
width correct for nonblocking assignments when converting a real
r-value to a l-value vector.
A named event does not have an edge so taking a posedge or negedge
is illegal. This patch adds an error message for this. Before the
edge was being ignored for named events, but this is incompatible
with other tools.
Generate schemes may nest freely, but generate regions
(an anachronistic concept from 1364-2001) cannot nest,
not within schemes or other regions. Have the parser detect
the nesting and print an error message.
Move check of the value $fatal is called with from the compiletf to
the calltf routine, since the value may not be known at compiletf
time. If the value is invalid, it just prints a warning that $fatal
was called with a bad finish_number, and resets it to the default 1.
Changes the compile time check for a numeric argument to a warning.
Also, fixes bug where $fatal called without an argument causes problems.
When selecting bits from unsized literals, we do not put a limit
on the size of the literal, so there is no top above which we
stop getting literal bits.
Icarus does not support interconnect delays so INTERCONNECT is
currently ignored. The SDF parser does not currently support a
bit select as a port_instance. Since we are already ignoring
the INTERCONNECT I added support for bit selects there. This
is probably the most common place to find them.
This is part of the 1800-2009 standard (Section 23.3.2.3) and allows
ports of module instances to be declared like:
modname instance(.foo, .bar);
instead of
modname instead(.foo(foo), .bar(bar));
The only tricky part about this is the implicit port connection shall
not create an implicit net declaration. To make this happen, the path
of least resistance was to add a bool to PEIdent indicating that it
should not implicitely create a net.
This does not rely on the generation flag to be 2009, following the
trend that new port naming convention (like ANSI style ports) work
regardless of the generation.
Added generation flag -g2009 which enables support for 1800-2009
constructs. Added related support such as "1800-2009" in the
`begin_keywords directive.
Keeps 2005 as the default generation for now.
Removed the -gsytem-verilog flag and folded the 1800-2005 stuff into
1800-2009. The rationale behind this is we have so little of
1800-2005 actually implemented that it does not make sense to
distinguish between 1800-2005 and 1800-2009 SystemVerilog extensions,
so we just count them all as the new 1800-2009 Verilog language.
@@ -285,12 +285,12 @@ One might note that the quote from section 4.1.14 says "Unsized
expressions...", so arguably accepting (15+1) or even (16+0) as an
operand to a concatenation is not a violation of the letter of the
law. However, the very next sentence of the quote expresses the
intent, and accepting (15+1) as having a more defined size then (16)
intent, and accepting (15+1) as having a more defined size than (16)
seems to be a violation of that intent.
Whatever a compiler decides the size is, the user has no way to
predict it, and the compiler should not have the right to treat (15+1)
any differently then (16). Therefore, Icarus Verilog takes the
any differently than (16). Therefore, Icarus Verilog takes the
position that such expressions are *unsized* and are not allowed as
operands to concatenations. Icarus Verilog will in general assume that
operations on unsized numbers produce unsized results. There are
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Stephen Williams
Cary R
Maciej Suminski
Martin Whitaker
Larry Doolittle
Todd Strader ([email protected])
Colin
Clifford Wolf
Jared Casper
Arun Persaud
Martin Whitaker
Andrew Stevens
Gordon McGregor
Ole Henrik Jahren
Alexander Klimov
Nick Gasson
Prasad Joshi
Pawel Szostek
Prasad Joshi
Greg Steuck
Pawel Szostek
Joe Auricchio
Patrick Doyle