Commentary/Tests: Describe PARAMNODEFAULT as top.

Fixes #7441.

.bake.toml

@@ -1,4 +1,6 @@
-# mbake configuration file
+# DESCRIPTION: mbake configuration file
+# SPDX-FileCopyrightText: 2025 Wilson Snyder
+# SPDX-License-Identifier: CC0-1.0
 
 [formatter]
 # Indentation settings

.clang-tidy

@@ -1,4 +1,4 @@
-Checks:          '*,-hicpp*,-android-cloexec-fopen,-cert-dcl50-cpp,-cert-env33-c,-cert-err34-c,-cert-err58-cpp,-clang-analyzer-core.UndefinedBinaryOperatorResult,-clang-analyzer-security*,-cppcoreguidelines-avoid-magic-numbers,-cppcoreguidelines-no-malloc,-cppcoreguidelines-owning-memory,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-constant-array-index,-cppcoreguidelines-pro-bounds-pointer-arithmetic,-cppcoreguidelines-pro-type-const-cast,-cppcoreguidelines-pro-type-reinterpret-cast,-cppcoreguidelines-pro-type-static-cast-downcast,-cppcoreguidelines-pro-type-union-access,-cppcoreguidelines-pro-type-vararg,-cppcoreguidelines-special-member-functions,-fuchsia-*,-google-default-arguments,-google-readability-todo,-google-runtime-references,-llvm-header-guard,-llvm-include-order,-misc-string-integer-assignment,-misc-string-literal-with-embedded-nul,-modernize-use-auto,-modernize-use-trailing-return-type,-readability-braces-around-statements,-readability-container-size-empty,-readability-delete-null-pointer,-readability-else-after-return,-readability-implicit-bool-conversion,-readability-named-parameter,-readability-static-accessed-through-instance,-llvmlibc-*,-altera-*'
+Checks:          '*,-hicpp*,-android-cloexec-fopen,-cert-dcl50-cpp,-cert-env33-c,-cert-err34-c,-cert-err58-cpp,-clang-analyzer-core.UndefinedBinaryOperatorResult,-clang-analyzer-security*,-cppcoreguidelines-avoid-magic-numbers,-cppcoreguidelines-no-malloc,-cppcoreguidelines-owning-memory,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-constant-array-index,-cppcoreguidelines-pro-bounds-pointer-arithmetic,-cppcoreguidelines-pro-type-const-cast,-cppcoreguidelines-pro-type-reinterpret-cast,-cppcoreguidelines-pro-type-static-cast-downcast,-cppcoreguidelines-pro-type-union-access,-cppcoreguidelines-pro-type-vararg,-cppcoreguidelines-special-member-functions,-fuchsia-*,-google-default-arguments,-google-readability-todo,-google-runtime-references,-llvm-header-guard,-llvm-include-order,-misc-string-integer-assignment,-misc-string-literal-with-embedded-nul,-modernize-use-auto,-modernize-use-trailing-return-type,-readability-braces-around-statements,-readability-container-size-empty,-readability-delete-null-pointer,-readability-else-after-return,-readability-implicit-bool-conversion,-readability-named-parameter,-readability-static-accessed-through-instance,-llvmlibc-*,-altera-*,-boost-use-ranges'
 WarningsAsErrors: ''
 HeaderFilterRegex: ''
 FormatStyle:     none

.codecov.yml

@@ -1,10 +1,10 @@
 ---
 # DESCRIPTION: codecov.io config
 #
-# Copyright 2020-2025 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2020-2026 Wilson Snyder
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 ####################
 # Validate:

.github/dependabot.yml

@@ -6,3 +6,6 @@ updates:
     directory: "/"
     schedule:
       interval: "weekly"
+    groups:
+      everything:
+        patterns: ["*"]

.github/workflows/build-test.yml

@@ -138,11 +138,11 @@ jobs:
       CCACHE_DIR: ${{ github.workspace }}/.ccache
       CCACHE_LIMIT_MULTIPLE: 0.95
     steps:
-      - uses: actions/checkout@v5
+      - uses: actions/checkout@v6
         with:
           path: repo
       - name: Cache $CCACHE_DIR
-        uses: actions/cache@v4
+        uses: actions/cache@v5
         with:
           path: ${{ env.CCACHE_DIR }}
           key: msbuild-msvc-cmake
@@ -155,7 +155,7 @@ jobs:
       - name: Zip up repository
         run: Compress-Archive -LiteralPath install -DestinationPath verilator.zip
       - name: Upload zip archive
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v7
         with:
           path: ${{ github.workspace }}/repo/verilator.zip
           name: verilator-win.zip

.github/workflows/contributor.yml

@@ -16,5 +16,5 @@ jobs:
     name: "'docs/CONTRIBUTORS' was signed"
     runs-on: ubuntu-24.04
     steps:
-      - uses: actions/checkout@v5
+      - uses: actions/checkout@v6
       - run: test_regress/t/t_dist_contributors.py

.github/workflows/coverage.yml

@@ -74,10 +74,10 @@ jobs:
     runs-on: ubuntu-24.04
     steps:
       - name: Checkout
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
 
       - name: Download code coverage data
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v8
         with:
           pattern: code-coverage-*
           path: obj_coverage
@@ -90,7 +90,7 @@ jobs:
           find obj_coverage -type f | paste -sd, | sed "s/^/files=/" >> "$GITHUB_OUTPUT"
 
       - name: Upload to codecov.io
-        uses: codecov/codecov-action@v5
+        uses: codecov/codecov-action@v6
         with:
           disable_file_fixes: true
           disable_search: true
@@ -110,10 +110,11 @@ jobs:
         run: |
           echo 'set man-db/auto-update false' | sudo debconf-communicate >/dev/null
           sudo dpkg-reconfigure man-db
+          sudo apt install lcov || \
           sudo apt install lcov
 
       - name: Download repository archive
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v8
         with:
           name: ${{ needs.build.outputs.archive }}
           path: ${{ github.workspace }}
@@ -124,7 +125,7 @@ jobs:
           ls -lsha
 
       - name: Download code coverage data
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v8
         with:
           pattern: code-coverage-*
           path: repo/obj_coverage
@@ -169,14 +170,14 @@ jobs:
           fi
 
       - name: Upload report
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v7
         with:
           path: repo/obj_coverage
           name: coverage-report
 
       - name: Upload notification
         if: ${{ github.event_name == 'pull_request' }}
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v7
         with:
           path: repo/notification
           name: coverage-pr-notification
@@ -192,7 +193,7 @@ jobs:
       # Creating issues requires elevated privilege
       - name: Generate access token
         id: generate-token
-        uses: actions/create-github-app-token@v2.1.4
+        uses: actions/create-github-app-token@v3.1.1
         with:
           app-id: ${{ vars.VERILATOR_CI_ID }}
           private-key: ${{ secrets.VERILATOR_CI_KEY }}

.github/workflows/docker.yml

@@ -39,7 +39,7 @@ jobs:
 
     steps:
       - name: Checkout
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
 
       - name: Extract context variables
         run: |
@@ -54,7 +54,7 @@ jobs:
 
       - name: Docker meta
         id: docker_meta
-        uses: docker/metadata-action@v5
+        uses: docker/metadata-action@v6
         with:
           images: |
             ${{ vars.DOCKER_HUB_NAMESPACE }}/${{ env.image_name }}
@@ -64,21 +64,21 @@ jobs:
             type=raw,value=latest,enable=${{ inputs.add_latest_tag == true }}
 
       - name: Set up QEMU
-        uses: docker/setup-qemu-action@v3
+        uses: docker/setup-qemu-action@v4
 
       - name: Set up Docker Buildx
-        uses: docker/setup-buildx-action@v3
+        uses: docker/setup-buildx-action@v4
         with:
           buildkitd-flags: --debug
 
       - name: Login to Docker Hub
-        uses: docker/login-action@v3
+        uses: docker/login-action@v4
         with:
           username: ${{ secrets.DOCKER_HUB_USER }}
           password: ${{ secrets.DOCKER_HUB_ACCESS_TOKEN }}
 
       - name: Build and Push to Docker
-        uses: docker/build-push-action@v6
+        uses: docker/build-push-action@v7
         if: startsWith(github.ref, 'refs/tags/v') || github.event_name == 'workflow_dispatch'
         with:
           context: ${{ env.build_context }}

.github/workflows/format.yml

@@ -21,23 +21,24 @@ jobs:
       CI_COMMIT: ${{ github.sha }}
     steps:
       - name: Checkout
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
         with:
           token: ${{ secrets.GITHUB_TOKEN }}
       - name: Install packages for build
         env:
           CI_BUILD_STAGE_NAME: build
         run: |
-          bash ci/ci-install.bash &&
-          sudo apt-get install clang-format-18 yapf3 &&
-          sudo pip3 install gersemi mbake &&
-          git config --global user.email "[email protected]" &&
+          sudo apt install clang-format-18 || \
+          sudo apt install clang-format-18
+          git config --global user.email "[email protected]"
           git config --global user.name "github action"
       - name: Format code
         run: |
-          autoconf &&
-          ./configure &&
-          make -j 2 format CLANGFORMAT=clang-format-18 &&
+          autoconf
+          ./configure
+          make venv
+          source .venv/bin/activate
+          make -j 2 format CLANGFORMAT=clang-format-18
           git status
       - name: Push
         run: |-

.github/workflows/no-pulls.yml

@@ -0,0 +1,15 @@
+---
+# Block PRs against stable branch
+name: "Check PR not against 'stable'"
+on:
+  pull_request:
+    branches: [stable]
+
+jobs:
+  block-pr:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Fail and block PR
+        run: |-
+          echo "Error: Pull requests directly to 'stable' are not allowed. Please PR against 'master'."
+          exit 1

.github/workflows/pages.yml

@@ -6,11 +6,8 @@ name: Pages
 
 on:
   push:
-    branches:
-      - master
-    paths:
-      - "ci/**"
-      - ".github/workflows"
+    branches: [master]
+    paths: ["ci/**", ".github/workflows"]
   workflow_dispatch:
   workflow_run:
     workflows: ["Code coverage"]
@@ -41,7 +38,7 @@ jobs:
       coverage-pr-run-ids: ${{ steps.build.outputs.coverage-pr-run-ids }}
     steps:
       - name: Checkout
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
       - name: Build pages
         id: build
         env:
@@ -64,7 +61,7 @@ jobs:
       url: ${{ steps.deployment.outputs.page_url }}
     steps:
       - name: Deploy to GitHub Pages
-        uses: actions/deploy-pages@v4
+        uses: actions/deploy-pages@v5
 
   notify:
     name: Notify
@@ -73,11 +70,11 @@ jobs:
     if: ${{ github.repository == 'verilator/verilator' }}
     steps:
       - name: Checkout
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
       # Use the Verilator CI app to post the comment
       - name: Generate access token
         id: generate-token
-        uses: actions/create-github-app-token@v2.1.4
+        uses: actions/create-github-app-token@v3.1.1
         with:
           app-id: ${{ vars.VERILATOR_CI_ID }}
           private-key: ${{ secrets.VERILATOR_CI_KEY }}

.github/workflows/reusable-build.yml

@@ -61,14 +61,14 @@ jobs:
       CCACHE_MAXSIZE: 1000M  # Per build matrix entry (* 5 = 5000M in total)
     steps:
       - name: Checkout
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
         with:
           path: repo
           ref: ${{ inputs.sha }}
           fetch-depth: ${{ inputs.dev-gcov && '0' || '1' }}  # Coverage flow needs full history
 
       - name: Cache $CCACHE_DIR
-        uses: actions/cache@v4
+        uses: actions/cache@v5
         env:
           CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache
         with:
@@ -93,7 +93,7 @@ jobs:
           echo "archive=$ARCHIVE" >> "$GITHUB_OUTPUT"
 
       - name: Upload repository archive
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v7
         with:
           path: ${{ github.workspace }}/${{ steps.create-archive.outputs.archive }}
           name: ${{ steps.create-archive.outputs.archive }}

.github/workflows/reusable-lint-py.yml

@@ -27,20 +27,25 @@ jobs:
     name: Sub-lint | Python
     steps:
       - name: Checkout
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
         with:
           path: repo
 
       - name: Install packages for build
         run: ./ci/ci-install.bash
 
-    # We use specific version numbers, otherwise a Python package
-    # update may add a warning and break our build
-      - name: Install packages for lint
-        run: sudo pip3 install mypy==1.18.2 pylint==3.0.2 ruff==0.1.3 clang sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe ruff
-
       - name: Configure
-        run: autoconf && ./configure --enable-longtests --enable-ccwarn
+        run: |
+          autoconf
+          ./configure --enable-longtests --enable-ccwarn
+
+      - name: Install python dependencies
+        run: |
+          sudo apt install python3-clang || \
+          sudo apt install python3-clang
+          make venv
 
       - name: Lint
-        run: make -k lint-py
+        run: |-
+          source .venv/bin/activate
+          make -k lint-py

.github/workflows/reusable-rtlmeter-build.yml

@@ -34,18 +34,20 @@ jobs:
           echo "path-exclude /usr/share/doc/*"  | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc
           echo "path-exclude /usr/share/man/*"  | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc
           echo "path-exclude /usr/share/info/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc
+          sudo apt update || \
           sudo apt update
-          sudo apt install ccache mold help2man libfl-dev libgoogle-perftools-dev libsystemc-dev
+          sudo apt install ccache mold help2man libfl-dev libjemalloc-dev libsystemc-dev || \
+          sudo apt install ccache mold help2man libfl-dev libjemalloc-dev libsystemc-dev
 
       - name: Use saved ccache
-        uses: actions/cache@v4
+        uses: actions/cache@v5
         with:
           path: ccache
           key: rtlmeter-build-ccache-${{ inputs.runs-on }}-${{ inputs.cc }}-${{ github.run_id }}-${{ github.run_attempt }}
           restore-keys: rtlmeter-build-ccache-${{ inputs.runs-on }}-${{ inputs.cc }}
 
       - name: Checkout
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
         with:
           path: repo
           fetch-depth: 0 # Required for 'git describe' used for 'verilator --version'
@@ -68,7 +70,7 @@ jobs:
         run: tar --posix -c -z -f verilator-rtlmeter.tar.gz install
 
       - name: Upload Verilator installation archive
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v7
         with:
           path: verilator-rtlmeter.tar.gz
           name: verilator-rtlmeter-${{ inputs.runs-on }}-${{ inputs.cc }}

.github/workflows/reusable-rtlmeter-run.yml

@@ -58,11 +58,13 @@ jobs:
           echo "path-exclude /usr/share/doc/*"  | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc
           echo "path-exclude /usr/share/man/*"  | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc
           echo "path-exclude /usr/share/info/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc
+          sudo apt update || \
           sudo apt update
-          sudo apt install ccache mold libfl-dev libgoogle-perftools-dev libsystemc-dev
+          sudo apt install ccache mold libfl-dev libjemalloc-dev libsystemc-dev || \
+          sudo apt install ccache mold libfl-dev libjemalloc-dev libsystemc-dev
 
       - name: Download Verilator installation archive
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v8
         with:
           name: verilator-rtlmeter-${{ inputs.runs-on }}-${{ inputs.cc }}
 
@@ -73,14 +75,14 @@ jobs:
 
       - name: Use saved ccache
         if: ${{ env.CCACHE_DISABLE == 0 }}
-        uses: actions/cache@v4
+        uses: actions/cache@v5
         with:
           path: ${{ env.CCACHE_DIR }}
           key: rtlmeter-run-ccache-${{ inputs.runs-on }}-${{ inputs.cc }}-${{ inputs.cases }}-${{ inputs.compileArgs }}-${{ github.run_id }}-${{ github.run_attempt }}
           restore-keys: rtlmeter-run-ccache-${{ inputs.runs-on }}-${{ inputs.cc }}-${{ inputs.cases }}-${{ inputs.compileArgs }}
 
       - name: Checkout RTLMeter
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
         with:
           repository: "verilator/rtlmeter"
           path: rtlmeter
@@ -115,7 +117,7 @@ jobs:
           ./rtlmeter report --steps '*' --metrics '*' ../results-${{ steps.results.outputs.hash }}.json
 
       - name: Upload results
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v7
         with:
           path: results-${{ steps.results.outputs.hash }}.json
           name: rtlmeter-${{ inputs.tag }}-results-${{ steps.results.outputs.hash }}
@@ -124,5 +126,5 @@ jobs:
 
       - name: Report status
         working-directory: rtlmeter
-        run: | # This will fail the job if any of the runs failed
+        run: |-  # This will fail the job if any of the runs failed
           ./rtlmeter run --verbose --cases='${{inputs.cases}}' --compileArgs='${{inputs.compileArgs}}' --executeArgs='${{inputs.executeArgs}}'

.github/workflows/reusable-test.yml

@@ -55,7 +55,7 @@ jobs:
     steps:
 
       - name: Download repository archive
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v8
         with:
           name: ${{ inputs.archive }}
           path: ${{ github.workspace }}
@@ -67,7 +67,7 @@ jobs:
           ls -lsha
 
       - name: Cache $CCACHE_DIR
-        uses: actions/cache@v4
+        uses: actions/cache@v5
         env:
           CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache2
         with:
@@ -77,14 +77,18 @@ jobs:
             ${{ env.CACHE_KEY }}-
 
       - name: Install test dependencies
-        run: ./ci/ci-install.bash
+        run: |
+          ./ci/ci-install.bash
+          make venv
 
       - name: Test
         id: run-test
         continue-on-error: true
         env:
           TESTS: ${{ inputs.suite }}
-        run: ./ci/ci-script.bash
+        run: |
+          source .venv/bin/activate
+          ./ci/ci-script.bash
 
       - name: Combine code coverage data
         if: ${{ inputs.dev-gcov }}
@@ -95,11 +99,13 @@ jobs:
 
       - name: Upload code coverage data
         if: ${{ inputs.dev-gcov }}
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v7
         with:
           path: ${{ github.workspace }}/repo/obj_coverage/verilator-${{ inputs.suite }}.info
           name: code-coverage-${{ inputs.suite }}
 
       - name: Fail job if a test failed
         if: ${{ steps.run-test.outcome == 'failure' && !cancelled() }}
-        run: exit 1
+        run: |-
+          echo "Click on '> Tests' arrow above (or on other steps), to expand it, and see the failure reasons"
+          exit 1

.github/workflows/rtlmeter-pr-results.yml

@@ -20,13 +20,13 @@ jobs:
       pull-requests: write
     steps:
       - name: Download report
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v8
         with:
           name: rtlmeter-pr-results
           run-id: ${{ github.event.workflow_run.id }}
           github-token: ${{ secrets.GITHUB_TOKEN }}
       - name: Download PR number
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v8
         with:
           name: pr-number
           run-id: ${{ github.event.workflow_run.id }}
@@ -34,7 +34,7 @@ jobs:
       # Use the Verilator CI app to post the comment
       - name: Generate access token
         id: generate-token
-        uses: actions/create-github-app-token@v2.1.4
+        uses: actions/create-github-app-token@v3.1.1
         with:
           app-id: ${{ vars.VERILATOR_CI_ID }}
           private-key: ${{ secrets.VERILATOR_CI_KEY }}

.github/workflows/rtlmeter.yml

@@ -11,6 +11,8 @@ on:
     - cron: '0 2 * * *'  # Daily, starting at 02:00 UTC
   pull_request:
     types: [opened, synchronize, reopened, labeled, unlabeled]
+  push:
+    branches: ['ci-rtlmeter/**']
 
 permissions:
   contents: read
@@ -35,7 +37,8 @@ jobs:
         && vars.ENABLE_SCHEDULED_JOBS == 'true') ||
       (github.event_name == 'pull_request'
         && contains(github.event.pull_request.labels.*.name, 'pr: rtlmeter')) ||
-      (github.event_name == 'workflow_dispatch')
+      (github.event_name == 'workflow_dispatch') ||
+      (github.event_name == 'push')
     runs-on: ubuntu-24.04
     steps:
       - name: Startup
@@ -75,11 +78,10 @@ jobs:
       matrix:
         cases:
           - "BlackParrot:1x1:*"
-          - "BlackParrot:2x2:*"
           - "BlackParrot:4x4:*"
+          - "Caliptra:default:*"
           - "NVDLA:*"
           - "OpenPiton:1x1:*"
-          - "OpenPiton:2x2:*"
           - "OpenPiton:4x4:*"
           - "OpenTitan:*"
           - "VeeR-EH1:asic*"
@@ -120,11 +122,10 @@ jobs:
       matrix:
         cases:
           - "BlackParrot:1x1:*"
-          - "BlackParrot:2x2:*"
           - "BlackParrot:4x4:*"
+          - "Caliptra:default:*"
           - "NVDLA:*"
           - "OpenPiton:1x1:*"
-          - "OpenPiton:2x2:*"
           - "OpenPiton:4x4:*"
           - "OpenTitan:*"
           - "VeeR-EH1:asic*"
@@ -165,11 +166,9 @@ jobs:
       matrix:
         cases:
           - "BlackParrot:1x1:* !-hier"
-          - "BlackParrot:2x2:* !-hier"
           - "BlackParrot:4x4:* !-hier"
           - "NVDLA:* !-hier"
           - "OpenPiton:1x1:* !-hier"
-          - "OpenPiton:2x2:* !-hier"
           - "OpenPiton:4x4:* !-hier"
           - "OpenPiton:8x8:* !-hier"
           - "OpenPiton:16x16:dhry !-hier"
@@ -188,7 +187,7 @@ jobs:
         tag: [gcc, clang, gcc-hier]
     steps:
       - name: Checkout RTLMeter
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
         with:
           repository: "verilator/rtlmeter"
           path: rtlmeter
@@ -196,7 +195,7 @@ jobs:
         working-directory: rtlmeter
         run: make venv
       - name: Download all results
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v8
         with:
           pattern: rtlmeter-${{ matrix.tag }}-results-*
           path: all-results-${{ matrix.tag }}
@@ -206,7 +205,7 @@ jobs:
         run: |
           ./rtlmeter collate ../all-results-${{ matrix.tag }}/*.json > ../all-results-${{ matrix.tag }}.json
       - name: Upload combined results
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v7
         with:
           path: all-results-${{ matrix.tag }}.json
           name: all-results-${{ matrix.tag }}
@@ -225,20 +224,20 @@ jobs:
     runs-on: ubuntu-24.04
     steps:
       - name: Download combined results
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v8
         with:
           pattern: all-results-*
           path: results
           merge-multiple: true
       - name: Upload published results
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v7
         with:
           path: results/*.json
           name: published-results
       # Pushing to verilator/verilator-rtlmeter-results requires elevated permissions
       - name: Generate access token
         id: generate-token
-        uses: actions/create-github-app-token@v2.1.4
+        uses: actions/create-github-app-token@v3.1.1
         with:
           app-id: ${{ vars.VERILATOR_CI_ID }}
           private-key: ${{ secrets.VERILATOR_CI_KEY }}
@@ -246,7 +245,7 @@ jobs:
           repositories: verilator-rtlmeter-results
           permission-contents: write
       - name: Checkout verilator-rtlmeter-results
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
         with:
           repository: "verilator/verilator-rtlmeter-results"
           token: ${{ steps.generate-token.outputs.token }}
@@ -279,7 +278,7 @@ jobs:
       actions: read
     steps:
       - name: Checkout RTLMeter
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
         with:
           repository: "verilator/rtlmeter"
           path: rtlmeter
@@ -287,7 +286,7 @@ jobs:
         working-directory: rtlmeter
         run: make venv
       - name: Download combined results
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v8
         with:
           pattern: all-results-*
           path: all-results
@@ -306,7 +305,7 @@ jobs:
           DATE=$(gh run --repo ${{ github.repository }} view $ID --json createdAt --jq ".createdAt")
           echo "date=$DATE" >> $GITHUB_OUTPUT
       - name: Download scheduled run results
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v8
         with:
           name: published-results
           path: nightly-results
@@ -372,14 +371,14 @@ jobs:
           done
           cat report.txt
       - name: Upload report
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v7
         with:
           path: report.txt
           name: rtlmeter-pr-results
       - name: Save PR number
         run: echo ${{ github.event.number }} > pr-number.txt
       - name: Upload PR number
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v7
         with:
           path: pr-number.txt
           name: pr-number
@@ -395,7 +394,7 @@ jobs:
       # Creating issues requires elevated privilege
       - name: Generate access token
         id: generate-token
-        uses: actions/create-github-app-token@v2.1.4
+        uses: actions/create-github-app-token@v3.1.1
         with:
           app-id: ${{ vars.VERILATOR_CI_ID }}
           private-key: ${{ secrets.VERILATOR_CI_KEY }}

.gitignore

@@ -17,6 +17,7 @@
 *.pdf
 /Makefile
 /.ccache
+/.venv/
 /artifact/
 README
 TAGS

Artistic

@@ -1,197 +0,0 @@
-Artistic License 2.0
-
-Copyright (c) 2000-2006, The Perl Foundation.
-
-Everyone is permitted to copy and distribute verbatim copies of this
-license document, but changing it is not allowed.
-
-Preamble
-********
-
-This license establishes the terms under which a given free software
-Package may be copied, modified, distributed, and/or redistributed.  The
-intent is that the Copyright Holder maintains some artistic control over
-the development of that Package while still keeping the Package
-available as open source and free software.
-
-You are always permitted to make arrangements wholly outside of this
-license directly with the Copyright Holder of a given Package.  If the
-terms of this license do not permit the full use that you propose to
-make of the Package, you should contact the Copyright Holder and seek a
-different licensing arrangement.
-
-Definitions
-***********
-
-"Copyright Holder" means the individual(s) or organization(s) named in
-the copyright notice for the entire Package.
-
-"Contributor" means any party that has contributed code or other
-material to the Package, in accordance with the Copyright Holder's
-procedures.
-
-"You" and "your" means any person who would like to copy, distribute, or
-modify the Package.
-
-"Package" means the collection of files distributed by the Copyright
-Holder, and derivatives of that collection and/or of those files.  A
-given Package may consist of either the Standard Version, or a Modified
-Version.
-
-"Distribute" means providing a copy of the Package or making it
-accessible to anyone else, or in the case of a company or organization,
-to others outside of your company or organization.
-
-"Distributor Fee" means any fee that you charge for Distributing this
-Package or providing support for this Package to another party.  It does
-not mean licensing fees.
-
-"Standard Version" refers to the Package if it has not been modified, or
-has been modified only in ways explicitly requested by the Copyright
-Holder.
-
-"Modified Version" means the Package, if it has been changed, and such
-changes were not explicitly requested by the Copyright Holder.
-
-"Original License" means this Artistic License as Distributed with the
-Standard Version of the Package, in its current version or as it may be
-modified by The Perl Foundation in the future.
-
-"Source" form means the source code, documentation source, and
-configuration files for the Package.
-
-"Compiled" form means the compiled bytecode, object code, binary, or any
-other form resulting from mechanical transformation or translation of
-the Source form.
-
-Permission for Use and Modification Without Distribution
-********************************************************
-
-(1) You are permitted to use the Standard Version and create and use
-Modified Versions for any purpose without restriction, provided that you
-do not Distribute the Modified Version.
-
-Permissions for Redistribution of the Standard Version
-******************************************************
-
-(2) You may Distribute verbatim copies of the Source form of the
-Standard Version of this Package in any medium without restriction,
-either gratis or for a Distributor Fee, provided that you duplicate all
-of the original copyright notices and associated disclaimers.  At your
-discretion, such verbatim copies may or may not include a Compiled form
-of the Package.
-
-(3) You may apply any bug fixes, portability changes, and other
-modifications made available from the Copyright Holder.  The resulting
-Package will still be considered the Standard Version, and as such will
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-Distribution of Modified Versions of the Package as Source
-**********************************************************
-
-(4) You may Distribute your Modified Version as Source (either gratis or
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-Modified Version) provided that you clearly document how it differs from
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-the user installing or running the Standard Version.  In addition, the
-Modified Version must bear a name that is different from the name of the
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-
-(c) allow anyone who receives a copy of the Modified Version to make the
-Source form of the Modified Version available to others under
-
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-
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-be made freely available in that license fees are prohibited but
-Distributor Fees are allowed.
-
-Distribution of Compiled Forms of the Standard Version or Modified
-******************************************************************
-Versions without the Source
-***************************
-
-(5) You may Distribute Compiled forms of the Standard Version without
-the Source, provided that you include complete instructions on how to
-get the Source of the Standard Version.  Such instructions must be valid
-at the time of your distribution.  If these instructions, at any time
-while you are carrying out such distribution, become invalid, you must
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-you provide valid instructions or cease distribution within thirty days
-after you become aware that the instructions are invalid, then you do
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-
-(6) You may Distribute a Modified Version in Compiled form without the
-Source, provided that you comply with Section 4 with respect to the
-Source of the Modified Version.
-
-Aggregating or Linking the Package
-**********************************
-
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-Modified Version) with other packages and Distribute the resulting
-aggregation provided that you do not charge a licensing fee for the
-Package.  Distributor Fees are permitted, and licensing fees for other
-components in the aggregation are permitted.  The terms of this license
-apply to the use and Distribution of the Standard or Modified Versions
-as included in the aggregation.
-
-(8) You are permitted to link Modified and Standard Versions with other
-works, to embed the Package in a larger work of your own, or to build
-stand-alone binary or bytecode versions of applications that include the
-Package, and Distribute the result without restriction, provided the
-result does not expose a direct interface to the Package.
-
-Items That are Not Considered Part of a Modified Version
-********************************************************
-
-(9) Works (including, but not limited to, modules and scripts) that
-merely extend or make use of the Package, do not, by themselves, cause
-the Package to be a Modified Version.  In addition, such works are not
-considered parts of the Package itself, and are not subject to the terms
-of this license.
-
-General Provisions
-******************
-
-(10) Any use, modification, and distribution of the Standard or Modified
-Versions is governed by this Artistic License.  By using, modifying or
-distributing the Package, you accept this license.  Do not use, modify,
-or distribute the Package, if you do not accept this license.
-
-(11) If your Modified Version has been derived from a Modified Version
-made by someone other than you, you are nevertheless required to ensure
-that your Modified Version complies with the requirements of this
-license.
-
-(12) This license does not grant you the right to use any trademark,
-service mark, tradename, or logo of the Copyright Holder.
-
-(13) This license includes the non-exclusive, worldwide, free-of-charge
-patent license to make, have made, use, offer to sell, sell, import and
-otherwise transfer the Package with respect to any patent claims
-licensable by the Copyright Holder that are necessarily infringed by the
-Package.  If you institute patent litigation (including a cross-claim or
-counterclaim) against any party alleging that the Package constitutes
-direct or contributory patent infringement, then this Artistic License
-to you shall terminate on the date that such litigation is filed.
-
-(14) Disclaimer of Warranty: THE PACKAGE IS PROVIDED BY THE COPYRIGHT
-HOLDER AND CONTRIBUTORS "AS IS' AND WITHOUT ANY EXPRESS OR IMPLIED
-WARRANTIES.  THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-PARTICULAR PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED TO THE EXTENT
-PERMITTED BY YOUR LOCAL LAW.  UNLESS REQUIRED BY LAW, NO COPYRIGHT
-HOLDER OR CONTRIBUTOR WILL BE LIABLE FOR ANY DIRECT, INDIRECT,
-INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING IN ANY WAY OUT OF THE USE
-OF THE PACKAGE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

CITATION.cff

@@ -1,3 +1,4 @@
+---
 # See https://citation-file-format.github.io/
 cff-version: 1.2.0
 title: Verilator
@@ -14,14 +15,14 @@ authors:
     family-names: Wasson
   - given-names: Duane
     family-names: Galbi
+  - given-names: Geza
+    family-names: Lore
   - name: 'et al'
 repository-code: 'https://github.com/verilator/verilator'
 url: 'https://verilator.org'
 abstract: >-
   The Verilator package converts Verilog and SystemVerilog hardware
   description language (HDL) designs into a fast C++ or SystemC model
-  that, after compiling, can be executed.  Verilator is not a
+  that, after compiling, can be executed.  Verilator is not only a
   traditional simulator but a compiler.
-license:
-  - LGPL-3.0-only
-  - Artistic-2.0
+license: [LGPL-3.0-only, Artistic-2.0]

CMakeLists.txt

@@ -4,10 +4,10 @@
 #
 #*****************************************************************************
 #
-# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2003-2025 Wilson Snyder
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 #****************************************************************************/
@@ -16,7 +16,7 @@ cmake_minimum_required(VERSION 3.15)
 cmake_policy(SET CMP0091 NEW) # Use MSVC_RUNTIME_LIBRARY to select the runtime
 project(
     Verilator
-    VERSION 5.042
+    VERSION 5.047
     HOMEPAGE_URL https://verilator.org
     LANGUAGES CXX
 )

Changes

@@ -8,6 +8,404 @@ The changes in each Verilator version are described below.  The
 contributors that suggested or implemented a given issue are shown in []. Thanks!
 
 
+Verilator 5.047 devel
+==========================
+
+**Important:**
+
+* Support jemalloc as the default allocator on Linux (#7250). [Yangyu Chen]
+  For better performance, `apt install libjemalloc-dev` or equivalent before running ./configure.
+
+**Other:**
+
+* Support inout inside SV interface (#3466) (#7134). [Nick Brereton]
+* Support `##0` cycle delays (#4263) (#7298). [Yilou Wang]
+* Support array reduction methods with 'with' clause in constraints (#6455) (#6999). [Rahul Behl]
+* Support constraint imperfect distributions (#6811) (#7168). [Yilou Wang]
+* Support disable task by name (#6853) (#7136). [Nick Brereton]
+* Support procedural concurrent assertion simple cases (#6944).
+* Support force assignments to array elements of real type (#7048). [Ryszard Rozak, Antmicro Ltd.]
+* Support VPI array indexing in signal names (#7097) (#7187) (#7214) (#7289). [Christian Hecken, Heidelberg University]
+* Support soft constraint solving (#7124) (#7166). [Yilou Wang]
+* Support constraints on fixed-size array of class object members (#7170) (#7183). [Yilou Wang]
+* Support Z non-blocking assignment (#7192) (#496) (#7197). [Nick Brereton]
+* Support constraint `with` item.index array reduction (#7198). [Rahul Behl]
+* Support constant expressions without parentheses in `PATHPULSE$` (#7199). [Pawel Kojma, Antmicro Ltd.]
+* Support $sformat with runtime format string (#7212).
+* Support dist and solve...before inside foreach constraints (#7245) (#7253). [Yilou Wang]
+* Support array and struct info metadata in FST traces (#7255). [Geza Lore, Testorrent USA, Inc.]
+* Support dynamic array .size in inline randomize() with constraints (#7258) (#7266). [Yilou Wang]
+* Support defparam with more than one dot (#7262). [Artur Bieniek, Antmicro Ltd.]
+* Support modport export/import task prototypes and out-of-block definitions (#7277). [Yilou Wang]
+* Support very wide $display arguments (#7280). [Jakub Michalski]
+* Support named sequence declarations and instances in assertions  (#7283). [Yilou Wang]
+* Support `##` delay on implication RHS in SVA properties (#7284). [Yilou Wang]
+* Support boolean and/or in sequence expressions (#7285). [Yilou Wang]
+* Support property-local variables and sequence match items (#7286). [Yilou Wang]
+* Support 'until' property (partial #7290) (#7399). [Ryszard Rozak, Antmicro Ltd.]
+* Support array map() method (#7307) (#7316) (#7344). [Wei-Lun Chiu]
+* Support SVA goto repetition `[->N]` in concurrent assertions (#7310). [Yilou Wang]
+* Support consecutive repetition `[\*N]` in SVA properties (#7311). [Yilou Wang]
+* Support `##[*]`, `##[+]`, `##[M:N]`, `##[M:$]` cycle delays in assertions (#7312) (#7377). [Yilou Wang]
+* Support rise/fall delays (#7368). [Artur Bieniek, Antmicro Ltd.]
+* Support sequence intersect operator (#7374). [Yilou Wang]
+* Support sequence 'throughout' operator (#7378). [Yilou Wang]
+* Support sequence consecutive repetition `[*N:M]`, `[+]`, and `[*]` (#7379). [Yilou Wang]
+* Support sequence `first_match` operator (#7392). [Yilou Wang]
+* Support nonconsecutive repetition [=N] in sequence expressions (#7397). [Yilou Wang]
+* Support per-process RNG for process::srandom() and object seeding (#7408) (#7415) (#7408). [Yilou Wang]
+* Support 2**n expressions in constraint randomization (#7422). [Yilou Wang]
+* Support `until_with` property (#7290 partial) (#7436). [Ryszard Rozak, Antmicro Ltd.]
+* Add VPI callback support to --main (#7145).
+* Add V3LiftExpr pass to lower impure expressions and calls (#7141) (#7164). [Geza Lore, Testorrent USA, Inc.]
+* Add --func-recursion-depth CLI option (#7175) (#7179).
+* Add `+verilator+solver+file` (#7242).
+* Add MacOS support for address sanitizer memory limit (#7308). [Marco Bartoli]
+* Deprecate `--structs-packed` (#7222).
+* Improve assignment-compatibility type check (#2843) (#5666) (#7052). [Pawel Kojma, Antmicro Ltd.]
+* Improve error message when variable used as data type (#7318). [Ryszard Rozak, Antmicro Ltd.]
+* Improve E_UNSUPPORTED warning messages (#7329). [Eunseo Song]
+* Change array tracing to dump left index to right index (#7205). [Geza Lore, Testorrent USA, Inc.]
+* Change `--converge-limit` default to 10000 (#7209).
+* Remove DFG extract optimization pass (#7394). [Geza Lore, Testorrent USA, Inc.]
+* Optimize trace code for faster compiles on repeated types (#6707) (#6832). [Todd Strader]
+* Optimize size of trace declaration object code (#7150). [Szymon Gizler, Antmicro Ltd.]
+* Optimize function call return value temporaries (#7152). [Geza Lore, Testorrent USA, Inc.]
+* Optimize conditional merging across some impure statements (#7159). [Geza Lore, Testorrent USA, Inc.]
+* Optimize reuse of existing associative terms in DfgPeephole. [Geza Lore, Testorrent USA, Inc.]
+* Optimize duplicate vertices and multiplexers in DfgPeephole (#7305). [Geza Lore, Testorrent USA, Inc.]
+* Optimize commutative vertex operands in DFG for better combining. [Geza Lore, Testorrent USA, Inc.]
+* Optimize DFG peephole until a fixed point (#7309). [Geza Lore, Testorrent USA, Inc.]
+* Optimize comparisons with identical operands and $countones in DFG. [Geza Lore, Testorrent USA, Inc.]
+* Optimize more patterns in DfgPeephole (#7332). [Geza Lore, Testorrent USA, Inc.]
+* Optimize read references in DFG (#7354). [Geza Lore, Testorrent USA, Inc.]
+* Optimize DFG only once, after scoping (#7362). [Geza Lore, Testorrent USA, Inc.]
+* Optimize more DFG peephole patterns (#7423). [Geza Lore, Testorrent USA, Inc.]
+* Fix recursive default assignment for sub-arrays (#4589) (#7202). [Julian Carrier]
+* Fix virtual interface member trigger convergence (#5116) (#7323). [Yilou Wang]
+* Fix shift width mismatch in constraint solver SMT emission (#5420) (#7265). [Yilou Wang]
+* Fix returning wrong type from static function in parameterized class (#5479) (#7387) (#7411) (#7418). [em2machine]
+* Fix randomize size+element queue constraints (#5582) (#7225). [Rahul Behl, Testorrent USA, Inc.]
+* Fix null assignment to virtual interfaces (#5974) (#5990). [Maxim Fonarev]
+* Fix typedef scope resolution for parameterized class aliases (#5977) (#7319). [Nick Brereton]
+* Fix lambda coroutines (#6106) (#7135). [Nick Brereton]
+* Fix super constructor calls with local variables (#6214) (#6933). [Igor Zaworski, Antmicro Ltd.]
+* Fix parameter default comparison when value contains type cast (#6281) (#7369) (#6281). [Yilou Wang]
+* Fix `local::` false error in randomize() with on parameterized class (#6680) (#7293). [Yilou Wang]
+* Fix false recursive definition error (#6769) (#7118). [Alex Zhou]
+* Fix port assignment to large arrays (#6904).
+* Fix interface localparam dependencies and arbitrary nesting (#6936) (#7128) (#7188) (#7190). [em2machine]
+* Fix parameterized class typedef as interface type parameter (#7000) (#7006). [Leela Pakanati]
+* Fix errant integer promotion (#7012). [Todd Strader]
+* Fix randc solver hang with wide variables (#7068) (#7248). [Yilou Wang]
+* Fix coroutine trace setters (#7078 repair) (#7296). [Igor Zaworski, Antmicro Ltd.]
+* Fix vpi_put_value not updating forced read value (#7092) (#7395) (#7092). [Christian Hecken, Heidelberg University]
+* Fix scheduling non-determinism (#7120) (#7162) (#7165). [Geza Lore, Testorrent USA, Inc.]
+* Fix parameters inside std::randomize `with` clause  (#7140). [Kamil Danecki, Antmicro Ltd.]
+* Fix forcing unpacked variables (#7149). [Ryszard Rozak, Antmicro Ltd.]
+* Fix wide conditional short circuiting (#7155).
+* Fix eliminating assignments to DPI-read variables (#7158). [Geza Lore, Testorrent USA, Inc.]
+* Fix std::randomize() in static function with static class members (#7167) (#7169). [Yilou Wang]
+* Fix resolving default/non-default type parameters (#7171) (#7346) (#7380) (#7385) (#7398) (#7406) (#7398). [em2machine]
+* Fix recursive constant function in $unit scope (#7173) (#7174).
+* Fix class extend references between queues (#7195).
+* Fix library/hier_block tracing when top name is empty (#7200). [Geza Lore, Testorrent USA, Inc.]
+* Fix virtual interface select from sub-interface instance (#7203) (#7370) (#7203). [Yilou Wang]
+* Fix VPI force of bit-selected signals (#7211) (#7301). [Christian Hecken]
+* Fix `$finish` to immediately stop executing code from non-final blocks (#7213 partial) (#7390).
+* Fix wrong $bits() for parameterized interface struct typedefs (#7218) (#7219). [em2machine]
+* Fix `dist` operator inside constraint if blocks (#7221) (#7224). [Rahul Behl, Testorrent USA, Inc.]
+* Fix array reduction in constraints crashing with class inheritance (#7226) (#7263). [Yilou Wang]
+* Fix soft cross-object constraint priority inversion (#7228) (#7233). [Yilou Wang]
+* Fix internal error when derived class calls this.randomize() with inherited rand members (#7229) (#7234). [Yilou Wang]
+* Fix enum range constraints missing for rand variables in sub-objects (#7230) (#7235). [Yilou Wang]
+* Fix vpi_put_value release on non-continuous signal (#7231) (#7241). [Christian Hecken]
+* Fix functions in generate block resulting in 'Broken link in node' (#7236) (#7367). [em2machine]
+* Fix tracing of typedefed 1D packed arrays with --trace-structs (#7237). [Geza Lore, Testorrent USA, Inc.]
+* Fix rand variable used as array index in constraint evaluated as constant (#7238) (#7247). [Yilou Wang]
+* Fix --hierarchical dropping arguments in -f/-F files (#7240). [Clara Sparks]
+* Fix `final` asserts and $stop (#7249). [Artur Bieniek, Antmicro Ltd.]
+* Fix MacOS clang PCH compile error with -o flag (#7251) (#7327). [Eunseo Song]
+* Fix vpi_put_value with vpiIntVal on VlWide data (#7256). [Christian Hecken]
+* Fix streaming with descending unpacked arrays and unpacked-to-queue (#7287). [Yilou Wang]
+* Fix MacOs lexer compile error (#7314) (#7315). [Tracy Narine]
+* Fix linking shared library with its dependencies (#7320). [Artur Bieniek, Antmicro Ltd.]
+* Fix modport selection of virtual interface handle (#7321). [Yilou Wang]
+* Fix false ASSIGNIN on interface input ports driven from outside (#7322). [Yilou Wang]
+* Fix static initialization order for packages with class hierarchies (#7324). [Yilou Wang]
+* Fix sensitivity of signals to unrelated interface members (#7336). [Artur Bieniek, Antmicro Ltd.]
+* Fix `disable iff` imply-delay statement linking (#7337). [Nick Brereton]
+* Fix lost `$stop` on implied assertion `$error` failures.
+* Fix wait() hang when interface uses process calls and VIF function (#7342). [Yilou Wang]
+* Fix error on illegal nand/nor binary operators (#7353).
+* Fix simple array assignment unrolling in slice optimization (#7359). [Geza Lore, Testorrent USA, Inc.]
+* Fix missing temporary for DfgSplicePacked (#7361). [Geza Lore, Testorrent USA, Inc.]
+* Fix virtual interface function calls binding to wrong instance (#7363). [Yilou Wang]
+* Fix false ASSIGNIN on interface input port connections (#7365). [Yilou Wang]
+* Fix string `inside` queue (#7373).
+* Fix subclass with rand_mode(0) getting randomized (#7376) (#7383). [Yilou Wang]
+* Fix VPI access to Verilog `force`-ed signals (#7381). [Christian Hecken, Heidelberg University]
+* Fix sampling of hierarchical references (#7386). [Ryszard Rozak, Antmicro Ltd.]
+* Fix virtual class inheritance false error (#7403) (#7405). [Nikolay Puzanov]
+* Fix CMake compiler coroutine flags (#7404). [Shogo Yamazaki]
+* Fix delete inside foreach skipping elements (#7407) (#7410)
+* Fix std::randomize in parameterized-derived class (#7409) (#7416). [Yilou Wang]
+* Fix virtual interface implied comparison with null (#7421). [Alex Solomatnikov]
+* Fix inline constraint on array-indexed randomize target (#7431) (#7434). [Yilou Wang]
+* Fix modification of members of object with const handle (#7433). [Kamil Danecki, Antmicro Ltd.]
+
+
+Verilator 5.046 2026-02-28
+==========================
+
+**Important:**
+
+* Support #0 delays with IEEE-1800 compliant semantics (#7079). [Geza Lore, Testorrent USA, Inc.]
+  This may require `-no-sched-zero-delay` to maintain performance vs. previous versions.
+
+**Other:**
+
+* Add IEEE 4-state type lint checks (#3645 partial) (#6895). [Jose Drowne]
+* Add VERILATOR_NUMA_STRATEGY environment variable (#6826) (#6880). [Yangyu Chen]
+* Add decoded Verilog name in JSON output (#6919) (#6995). [Oleh Maksymenko]
+* Add parsing of solve-before inside foreach (#6934). [Pawel Kojma, Antmicro Ltd.]
+* Add error when accessing a non-static class field from a static function (#6948). [Artur Bieniek, Antmicro Ltd.]
+* Add VerilatedContext::useNumaAssign and set on threads() call (#6954). [Yangyu Chen]
+* Add coverage type information to verilator_coverage annotation output (#7131) (#7133) (#7148).
+* Add --max-replication option (#7139). [Todd Strader]
+* Support modport expression syntax + nested (#2601) (#5581) (#7005). [Leela Pakanati]
+* Support nested interface as port connection (#5066) (#6986). [Leela Pakanati]
+* Support solve..before constraints (#5647) (#7123). [Yilou Wang]
+* Support structure initial values (#6130).
+* Support proper automatic/static initialization, and remove STATICVAR warning (#6405) (#7086).
+* Support vpi_put/vpi_get forcing of signals (#5933) (#6704). [Christian Hecken, Heidelberg University]
+* Support detailed failure info for constraint violations (#6617) (#6883). [Yilou Wang]
+* Support `unique` constraints (on 1D static arrays) (#6810) (#6878). [Srinivasan Venkataramanan]
+* Support complex expressions as std::randomize arguments (#6860). [Jakub Wasilewski, Antmicro Ltd.]
+* Support dynamic array elements in std::randomize (#6896). [Ryszard Rozak, Antmicro Ltd.]
+* Support unbounded '$' in inside range expressions (#6935) (#6938). [Wei-Lun Chiu]
+* Support `extern module` as a forward-declaration that is ignored.
+* Support `foreach` with nested dots (#6991). [Krzysztof Bieganski, Antmicro Ltd.]
+* Support signed multiplication in constraints (#7008). [Pawel Kojma, Antmicro Ltd.]
+* Support constraint_mode() on static constraints (#7027) (#7038). [Yilou Wang]
+* Support some system functions in constraint blocks (#7028) (#7036). [Yilou Wang]
+* Support std::randomize() for queue, dynamic array, and associative array variables (#7044). [Yilou Wang]
+* Support inherited and nested pre/post_randomize callbacks (#7049) (#7053). [Yilou Wang]
+* Support `$get_initial_random_seed` (#7056) (#7069). [Srinivasan Venkataramanan]
+* Support unique constraint on explicit array element subsets (#7057) (#7064). [Yilou Wang]
+* Support force assignments to unpacked structs (#7060). [Ryszard Rozak, Antmicro Ltd.]
+* Support function calls with random arguments in constraints (#7061) (#7083). [Yilou Wang]
+* Support power expressions with constant exponent in constraints (#7073). [Kamil Danecki]
+* Support `disable iff` with sequences (#7090). [Ryszard Rozak, Antmicro Ltd.]
+* Support `this` keyword inside inline randomize() with {} constraint blocks (#7102) (#7113). [Yilou Wang]
+* Support constraint dynamic array reduction methods without 'with' clause (#7104) (#7108). [Yilou Wang]
+* Remove deprecated `--xml-only`.
+* Remove deprecated `--make cmake`.
+* Change JSON dumps to not include booleans that are false (#6977).
+* Change metacomment extra underscore error to BADVLTPRAGMA warning (#6968). [Geza Lore, Testorrent USA, Inc.]
+* Change INITIALSTATIC to also report on processes, per IEEE (#7020).
+* Change automatic variables to not be traced.
+* Change type definition error to show type chain with source context (#7151).
+* Optimize string temporaries to not be localized (#6969). [Geza Lore, Testorrent USA, Inc.]
+* Optimize wide word shifts by multiple of word size (#6970). [Geza Lore, Testorrent USA, Inc.]
+* Optimize concatenations that produce unused bits in DFG (#6971). [Geza Lore, Testorrent USA, Inc.]
+* Optimize more wide operation temporaries with substitution (#6972). [Geza Lore, Testorrent USA, Inc.]
+* Optimize right shifts as clean (#6981). [Geza Lore, Testorrent USA, Inc.]
+* Optimize temporary insertion for concatenations in DFG (#7013). [Geza Lore, Testorrent USA, Inc.]
+* Optimize removing redundant variables during DFG Peephole pass (#7076). [Geza Lore, Testorrent USA, Inc.]
+* Optimize additional DFG peephole Shift and Concat patterns (#7077). [Geza Lore, Testorrent USA, Inc.]
+* Optimize logic and variable removal early in DFG (#7081). [Geza Lore, Testorrent USA, Inc.]
+* Optimize straight line code in DFG always (#7084). [Geza Lore, Testorrent USA, Inc.]
+* Optimize always blocks using local temporary variables in DFG (#7085). [Geza Lore, Testorrent USA, Inc.]
+* Optimize functions inlined from packages in DFG (#7091). [Geza Lore, Testorrent USA, Inc.]
+* Optimize continuous assignments with function on RHS in DFG (#7096). [Geza Lore, Testorrent USA, Inc.]
+* Fix MULTIDRIVEN with task and default driver (#4045) (#6858). [em2machine]
+* Fix parameterized virtual interface references that have no model references (#4286).
+* Fix hierarchical interface/modport issues (#5941) (#6997). [Leela Pakanati]
+* Fix extending class by a typedef (#6679) (#6855). [Alex Zhou]
+* Fix variable reference lookup for module-level variables (#6741) (#6882). [Yilou Wang]
+* Fix false CASEOVERLAP case item expression lint (#6825) (#6886). [Luca Colagrande]
+* Fix virtual interface triggers (#6844). [Igor Zaworski, Antmicro Ltd.]
+* Fix use-after-free error (#6846). [Matthew Ballance]
+* Fix dynamic scheduler temporary variable locations (#6859) (#6926). [Igor Zaworski, Antmicro Ltd.]
+* Fix dynamic array elements passed to ref argument (#6877). [Ryszard Rozak, Antmicro Ltd.]
+* Fix large debug_str for emitted Syms headers (#6889). [Bartłomiej Chmiel, Antmicro Ltd.]
+* Fix `disable iff` in simple properties (#6890). [Ryszard Rozak, Antmicro Ltd.]
+* Fix #0 delays to control fork scheduling (#6891). [Artur Bieniek, Antmicro Ltd.]
+* Fix member-selected randomization assignments (#6892). [Yilou Wang]
+* Fix WIDTHEXTEND suppression on add/sub with single-bit signal. [Dan Katz]
+* Fix segfault in V3Slice (#6899). [Pawel Kojma, Antmicro Ltd.]
+* Fix unpacked array concatenation function arguments (#6900). [Pawel Kojma, Antmicro Ltd.]
+* Fix signedness of packed array (#6901) (#6902). [Yutetsu TAKATSUKASA]
+* Fix assignment of queue from unpacked array (#6906).
+* Fix `foreach` with mid-index empty commas (#6910).
+* Fix internal error when fork under always expression (#6911).
+* Fix error when calling non-static method (#6916). [Artur Bieniek, Antmicro Ltd.]
+* Fix memory leak in vpi_put_value and vpi_get_value (#6917). [Christian Hecken, Heidelberg University]
+* Fix interface internal type reference (#6920) (#6966). [Todd Strader]
+* Fix segfault after assignment pattern XOR error (#6928) (#6931). [emmettifelts]
+* Fix delayed initial assignment (#6929). [Todd Strader]
+* Fix event triggering (#6932) (#7072) (#7101). [Igor Zaworski, Antmicro Ltd.]
+* Fix `--top-module` with underscores (#6940). [Christopher Batten]
+* Fix variable randomization to better differ by seed (#6945) (#6956). [Rodrigo Batista de Moraes]
+* Fix null pointer dereference in class member trigger expressions (#6946). [Cameron Waite]
+* Fix type assignments for arrays of parameter types (#6955). [Todd Strader]
+* Fix accessing non-rand struct member in constraints (#6960). [Pawel Kojma, Antmicro Ltd.]
+* Fix associative array of events causes C++ compile error (#6962).
+* Fix UNUSED / UNDRIVEN for unused functions (#6967). [Todd Strader]
+* Fix non-inlined function return value clearing (#6982).
+* Fix parameterized class typedef as interface type parameter (#6983) (#6984). [Leela Pakanati]
+* Fix virtual interface not found internal error (#7010). [Igor Zaworski, Antmicro Ltd.]
+* Fix multidimensional dynamic array elements passed to ref argument (#7023). [Ryszard Rozak, Antmicro Ltd.]
+* Fix randomize() null pointer dereference (#7026). [Artur Bieniek, Antmicro Ltd.]
+* Fix randc cyclic behavior broken with constraints (#7029) (#7035). [Yilou Wang]
+* Fix inline foreach constraints on dynamic arrays of class objects (#7030) (#7037). [Yilou Wang]
+* Fix rand_mode() on nested object variables causing Z3 solver error (#7031) (#7034). [Yilou Wang]
+* Fix non-member identifiers used inside constraints (#7033). [Pawel Kojma, Antmicro Ltd.]
+* Fix tracing without module inlining to match with inlining (#7041). [Geza Lore, Testorrent USA, Inc.]
+* Fix scope tree in traces in hierarchical mode (#7042). [Geza Lore, Testorrent USA, Inc.]
+* Fix rand_mode()/constraint_mode() when used as function arguments (#7051) (#7055). [Yilou Wang]
+* Fix constraint_mode()/rand_mode() in constructor being overwritten (#7054). [Yilou Wang]
+* Fix enum variables in constraint solver producing invalid enum values (#7058) (#7065). [Yilou Wang]
+* Fix randomize() on null object handle crashing instead of returning 0 (#7059) (#7066). [Yilou Wang]
+* Fix inside operator crash with impure expression and unsized range literals (#7063) (#7067). [Yilou Wang]
+* Fix constant propagating DPI-written variables (#7074). [Geza Lore, Testorrent USA, Inc.]
+* Fix conditional expressions in constraints (#7087). [Ryszard Rozak, Antmicro Ltd.]
+* Fix UNSUPPORTED on $sampled in sensitivity list (#7093). [Ryszard Rozak, Antmicro Ltd.]
+* Fix time to not advance after `$finish` (#7095).
+* Fix associative array size() constraint generating invalid resize() call (#7103) (#7112). [Yilou Wang]
+* Fix `new` shallow copy to preserve polymorphic runtime type (#7105) (#7109). [Yilou Wang]
+* Fix circular class reference %p-printing causing infinite recursion (#7106).
+* Fix too-short bit pack returning wrong value (#7111).
+* Fix randomize of real (#7115). [Srinivasan Venkataramanan]
+* Fix inlining of C functions with reloop locals (#7132). [Geza Lore, Testorrent USA, Inc.]
+* Fix segfault in EmitCSyms (#7142) (#7143). [Gilberto Abram]
+
+
+Verilator 5.044 2026-01-01
+==========================
+
+**Important:**
+
+* This is the last release supporting the deprecated `--xml-only` and
+  `--make cmake` options.
+* Change `--lint-only` and `--json-only` to imply `--timing` (#6790).
+
+**Other:**
+
+* Add `--unroll-limit` option (#6654) (#6668). [Geza Lore, Fractile Ltd.]
+* Add `-fno-inline-funcs-eager` option to disable excessive inlining (#6682). [Geza Lore, Fractile Ltd.]
+* Add `-param`/`-port` options to `public_flat*` control directives (#6685). [Geza Lore, Fractile Ltd.]
+* Add `--top` specifying `config` name (#6710). [Dan Ruelas-Petrisko]
+* Add `sc_biguint` pragma (#6712). [Jakub Wasilewski, Antmicro Ltd.]
+* Add `make venv` target (#6775). [Geza Lore]
+* Add SUPERNFIRST error on super.new on non-first statement (#6784). [Artur Bieniek]
+* Add fargs for reusability of `--dump-inputs` output (#6812). [Geza Lore]
+* Add `--quiet-build` to suppress make/compiler informationals.
+* Support `std::randomize(){...}` (#4706) (#6573). [Yilou Wang]
+* Support force assignments to unpacked array elements (partial #4735) (#6787). [Ryszard Rozak, Antmicro Ltd.]
+* Support `config' (#5891) (#6714) (#6717) (#6745) (#6764). [Dan Ruelas-Petrisko]
+* Support unpacked struct in localparam (#6053 partial) (#6708). [Jonathan Drolet]
+* Support `randsequence` (#6131).
+* Support array reference arguments into 'std::randomize()' (#6384) (#6719). [Yilou Wang]
+* Support basic global constraints (#6551) (#6552). [Yilou Wang]
+* Support SystemC time resolution with step 10/100 (#6633) (#6715). [Aliaksei Chapyzhenka]
+* Support `this.randomize()` with constraints (#6634). [Artur Bieniek, Antmicro Ltd.]
+* Support multi-expression sequences (#6639). [Bartłomiej Chmiel, Antmicro Ltd.]
+* Support `#1step` delay as statement  (#6671). [Pawel Kojma, Antmicro Ltd.]
+* Support clocking output delay `1step` (#6681). [Ondrej Ille]
+* Support parsing of dotted `bins_expression` (#6683). [Pawel Kojma, Antmicro Ltd.]
+* Support constant expression cycle delays in sequences (#6691). [Ryszard Rozak, Antmicro Ltd.]
+* Support general global constraints (#6709) (#6711). [Yilou Wang]
+* Support complex std::randomize patterns (#6736) (#6737). [Yilou Wang]
+* Support `rand_mode` in global constraint gathering (#6740) (#6752). [Yilou Wang]
+* Support reduction or in constraints (#6840). [Pawel Kojma, Antmicro Ltd.]
+* Support vpiSigned (#6868) (#6870). [Kaleb Barrett]
+* Optimize away calls to empty functions (#6626). [Geza Lore]
+* Optimize redundant headers in Syms implementation files. [Geza Lore, Fractile Ltd.]
+* Optimize constructor/destructor VerilatedModules (#6660). [Geza Lore, Fractile Ltd.]
+* Optimize repeated function call during symbol table initialization (#6665). [Geza Lore, Fractile Ltd.]
+* Optimize functions reading external parameters as pure (#6684). [Geza Lore, Fractile Ltd.]
+* Optimize `$past` delayed variable reuse (#6689). [Geza Lore, Fractile Ltd.]
+* Optimize combinational loops through sign extension (#6724). [Geza Lore]
+* Optimize trace initialization code size (#6749). [Geza Lore]
+* Optimize combinational cycles in DFG (#6744) (#6746) (#6744). [Geza Lore]
+* Optimize inlining small C functions and add `-inline-cfuncs` (#6815). [Jose Drowne]
+* Fix generate function(s) inside of generate blocks (#1011) (#6789). [em2machine]
+* Fix typedef derived from type defined inside interface (#3441) (#6776). [em2machine]
+* Fix warning lint directive ordering and consistency (#4185) (#5368) (#5610) (#6876).
+* Fix extern function that returns parameterized class (#4924).
+* Fix type deduction for variable parameterized classes (#6281) (#6813). [em2machine]
+* Fix randomize called within func/task (#6144) (#6753). [Yilou Wang]
+* Fix pre/post_randomize on extended classes (#6467). [Alex Solomatnikov]
+* Fix expression short circuiting (#6483). [Todd Strader]
+* Fix resized lvalues with warning suppressed (#6497) (#6816). [Alex Solomatnikov]
+* Fix unsupported `if` virtual interface warning (#6558) (#6861). [Krzysztof Bieganski, Antmicro Ltd.]
+* Fix expression coverage of system calls (#6592). [Todd Strader]
+* Fix `--timing` with `--x-initial-edge` (#6603) (#6631). [Krzysztof Bieganski, Antmicro Ltd.]
+* Fix merging of impure assignments in gate optimization (#6629) (#6630). [Geza Lore]
+* Fix determining Verilator revision when within git submodules without tags.
+* Fix initial random values for verilator-created variables (#6611). [Todd Strader]
+* Fix parsing of `with` clause inside covergroups (#6618). [Pawel Kojma, Antmicro Ltd.]
+* Fix slice memory overflow on large output arrays (#6636) (#6638). [Jens Yuechao Liu]
+* Fix localparam type assignment from interface type parameters (#6637) (#6732). [em2machine]
+* Fix memory usage statistics on MacOS (#6644). [Geza Lore, Fractile Ltd.]
+* Fix command line statistics with --stats (#6645) (#6646). [Geza Lore, Fractile Ltd.]
+* Fix slow compilation of generated sampled value code (#6652). [Geza Lore, Fractile Ltd.]
+* Fix non-deterministic output when splitting Syms file. [Geza Lore, Fractile Ltd.]
+* Fix crash on DFG driver lookup (#6649). [Geza Lore]
+* Fix ccache-report with PCH files. [Geza Lore, Fractile Ltd.]
+* Fix parameterized class function (#6659) (#6802). [em2machine]
+* Fix local interface parameter hierarchical access (#6661) (#6666). [Paul Swirhun]
+* Fix splitting of Syms constructor/destructor bodies (#6662). [Geza Lore, Fractile Ltd.]
+* Fix long C++ compilation due to VerilatedScope constructors (#6664). [Geza Lore, Fractile Ltd.]
+* Fix large array initialization (#6669). [Artur Bieniek, Antmicro Ltd.]
+* Fix `--expand-limit` not respected for expressions (#6670). [Geza Lore, Fractile Ltd.]
+* Fix `free` name collision (#6675). [Todd Strader]
+* Fix bounds checking in non-inlined function (#6677). [Geza Lore, Fractile Ltd.]
+* Fix stream operator widening (#6693) (#6697). [Jean-Nicolas Strauss]
+* Fix multitop cross references (#6699).
+* Fix DFG independent bits analysis performance (#6713) (#6743). [Geza Lore]
+* Fix deleting linked node error in V3Randomize (#6718). [Igor Zaworski, Antmicro Ltd.]
+* Fix runtime worker thread stack sizes on MacOS (#6721). [Geza Lore]
+* Fix X handling in UDPs (#6722) (#6723). [Michael Bikovitsky]
+* Fix `--prof-exec` using `--lib-create`. [Geza Lore]
+* Fix fork scheduling semantics (#6730). [Artur Bieniek, Antmicro Ltd.]
+* Fix JSON output case statements (#6733).
+* Fix internal fault when cross-class calling with DPI (#6735) (#6742). [Matthew Ballance]
+* Fix write variable placement for global constraints (#6740) (#6750) (#6797). [Yilou Wang]
+* Fix JSON dump missing output ports (#6751) (#6831). [Oleh Maksymenko]
+* Fix resolution of specialized typedefs (#6754) (#6808) (#6834). [em2machine]
+* Fix UNSUPPORTED on force / release with complex selects (#6755). [Ryszard Rozak, Antmicro Ltd.]
+* Fix select assignment expansion (#6757). [Geza Lore]
+* Fix `--lib-create` with multi-bit clocks (#6759). [Geza Lore]
+* Fix DFG reusing volatile variables. [Geza Lore]
+* Fix DFG assertion on out-of-bounds selects. [Geza Lore]
+* Fix process reference giving no return statement error (#6767) (#6823). [Krzysztof Bieganski, Antmicro Ltd.]
+* Fix class param static not found again error (#6768).
+* Fix crash when super.new() called without a base class (#6772). [Matthew Ballance]
+* Fix class-in-class extends with parameters (#6773).
+* Fix enum item references in class extends with parameters.
+* Fix reordering of function body inlined on RHS of <= NBA (#6780). [Geza Lore]
+* Fix clang `-Wno-vla-cxx-extension` warning for UVM DPI tests (#6782)
+* Fix `disable iff` in simple properties (#6783). [Ryszard Rozak, Antmicro Ltd.]
+* Fix input sampling of clocking block signals (#6788). [Pawel Kojma, Antmicro Ltd.]
+* Fix O(n*2) analysis in const-bit-op-tree (#6791). [Geza Lore]
+* Fix member select of variable without randmode (#6800) (#6833). [Yilou Wang]
+* Fix duplicate name error with interface initial blocks (#6804) (#6805). [Thomas Dybdahl Ahle]
+* Fix nested struct within parameter port list (#6818) (#6824). [Luca Colagrande]
+* Fix setting thread count in VerilatedContext (#6826 partial) (#6841). [Yangyu Chen]
+* Fix firing array selects of events (#6829). [Amal Araweelo Almis]
+* Fix false IMPLICITSTATIC on localparam (#6835). [Geza Lore]
+* Fix randcase under fork (#6843). [Amal Araweelo Almis]
+* Fix JSON missing `signed` indication (#6845).
+* Fix class reference throwing cannot detect changes error (#6851).
+* Fix `randc` on extended class (#6852).
+* Fix typedef `::` class reference error (#6862).
+* Fix missing include on FreeBSD (#6864).
+* Fix `--Wwarn-lint` to be inverse of `--Wno-lint`.
+
+
 Verilator 5.042 2025-11-02
 ==========================
 
@@ -39,6 +437,7 @@ Verilator 5.042 2025-11-02
 * Support modports referencing clocking blocks (#4555) (#6436). [Ryszard Rozak, Antmicro Ltd.]
 * Support class package reference on pattern keys (#5653). [Todd Strader]
 * Support digits in `$sscanf` field width formats (#6083). [Iztok Jeras]
+* Support assert under assert (#6146). [Alex Solomatnikov]
 * Support pure functions in sensitivity lists (#6393). [Krzysztof Bieganski, Antmicro Ltd.]
 * Support simple alias statements (#6339) (#6501). [Ryszard Rozak, Antmicro Ltd.]
 * Support simple cycle delay sequence expressions inside properties (#6508). [Bartłomiej Chmiel, Antmicro Ltd.]
@@ -236,6 +635,8 @@ Verilator 5.040 2025-08-30
 * Fix wide select expansion and substitution (#6341) (#6345). [Geza Lore]
 * Fix upcasting class type parameters (#6344). [Krzysztof Bieganski, Antmicro Ltd.]
 * Fix undefined weak link for Apple GCC etc (#6348). [Congcong Cai]
+* Fix emitting unbounded parameters (#6912).
+* Fix syntax error on unsupported defparam array (#6915).
 
 
 Verilator 5.038 2025-07-08
@@ -445,6 +846,7 @@ Verilator 5.034 2025-02-24
 * Optimize labels as final `if` block statements (#5744).
 * Optimize empty function definition bodies (#5750).
 * Optimize splitting trigger computation and dump (#5798). [Geza Lore]
+* Optimize some DFG multiplexers (#6822). [Yangyu Chen]
 * Fix error message when call task as a function (#3089). [Matthew Ballance]
 * Fix force VPI public signal visibility (#5225). [Frédéric Requin]
 * Fix VPI iteration over hierarchy (#5314) (#5731). [Natan Kreimer]
@@ -5394,9 +5796,9 @@ Verilator 0.0 1994-07-08
 Copyright
 =========
 
-Copyright 2001-2025 by Wilson Snyder. This program is free software; you
-can redistribute it and/or modify it under the terms of either the GNU
-Lesser General Public License Version 3 or the Perl Artistic License
-Version 2.0.
+This program is free software; you can redistribute it and/or modify it
+under the terms of either the GNU Lesser General Public License Version 3
+or the Perl Artistic License Version 2.0.
 
+SPDX-FileCopyrightText: 2001-2025 Wilson Snyder
 SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

LICENSE

@@ -1,165 +1,304 @@
-                   GNU LESSER GENERAL PUBLIC LICENSE
-                       Version 3, 29 June 2007
+GNU LESSER GENERAL PUBLIC LICENSE
+Version 3, 29 June 2007
 
- Copyright (C) 2007 Free Software Foundation, Inc. <https://fsf.org/>
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
+Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
 
+Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed.
 
-  This version of the GNU Lesser General Public License incorporates
-the terms and conditions of version 3 of the GNU General Public
-License, supplemented by the additional permissions listed below.
+This version of the GNU Lesser General Public License incorporates the terms and conditions of version 3 of the GNU General Public License, supplemented by the additional permissions listed below.
 
-  0. Additional Definitions.
+0. Additional Definitions.
 
-  As used herein, "this License" refers to version 3 of the GNU Lesser
-General Public License, and the "GNU GPL" refers to version 3 of the GNU
-General Public License.
+As used herein, "this License" refers to version 3 of the GNU Lesser General Public License, and the "GNU GPL" refers to version 3 of the GNU General Public License.
 
-  "The Library" refers to a covered work governed by this License,
-other than an Application or a Combined Work as defined below.
+"The Library" refers to a covered work governed by this License, other than an Application or a Combined Work as defined below.
 
-  An "Application" is any work that makes use of an interface provided
-by the Library, but which is not otherwise based on the Library.
-Defining a subclass of a class defined by the Library is deemed a mode
-of using an interface provided by the Library.
+An "Application" is any work that makes use of an interface provided by the Library, but which is not otherwise based on the Library. Defining a subclass of a class defined by the Library is deemed a mode of using an interface provided by the Library.
 
-  A "Combined Work" is a work produced by combining or linking an
-Application with the Library.  The particular version of the Library
-with which the Combined Work was made is also called the "Linked
-Version".
+A "Combined Work" is a work produced by combining or linking an Application with the Library.  The particular version of the Library with which the Combined Work was made is also called the "Linked Version".
 
-  The "Minimal Corresponding Source" for a Combined Work means the
-Corresponding Source for the Combined Work, excluding any source code
-for portions of the Combined Work that, considered in isolation, are
-based on the Application, and not on the Linked Version.
+The "Minimal Corresponding Source" for a Combined Work means the Corresponding Source for the Combined Work, excluding any source code for portions of the Combined Work that, considered in isolation, are based on the Application, and not on the Linked Version.
 
-  The "Corresponding Application Code" for a Combined Work means the
-object code and/or source code for the Application, including any data
-and utility programs needed for reproducing the Combined Work from the
-Application, but excluding the System Libraries of the Combined Work.
+The "Corresponding Application Code" for a Combined Work means the object code and/or source code for the Application, including any data and utility programs needed for reproducing the Combined Work from the Application, but excluding the System Libraries of the Combined Work.
 
-  1. Exception to Section 3 of the GNU GPL.
+1. Exception to Section 3 of the GNU GPL.
+You may convey a covered work under sections 3 and 4 of this License without being bound by section 3 of the GNU GPL.
 
-  You may convey a covered work under sections 3 and 4 of this License
-without being bound by section 3 of the GNU GPL.
+2. Conveying Modified Versions.
+If you modify a copy of the Library, and, in your modifications, a facility refers to a function or data to be supplied by an Application that uses the facility (other than as an argument passed when the facility is invoked), then you may convey a copy of the modified version:
 
-  2. Conveying Modified Versions.
+     a) under this License, provided that you make a good faith effort to ensure that, in the event an Application does not supply the function or data, the facility still operates, and performs whatever part of its purpose remains meaningful, or
 
-  If you modify a copy of the Library, and, in your modifications, a
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+     b) under the GNU GPL, with none of the additional permissions of this License applicable to that copy.
 
-   a) under this License, provided that you make a good faith effort to
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+3. Object Code Incorporating Material from Library Header Files.
+The object code form of an Application may incorporate material from a header file that is part of the Library.  You may convey such object code under terms of your choice, provided that, if the incorporated material is not limited to numerical parameters, data structure layouts and accessors, or small macros, inline functions and templates (ten or fewer lines in length), you do both of the following:
 
-   b) under the GNU GPL, with none of the additional permissions of
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+If the Program specifies that a proxy can decide which future versions of the GNU General Public License can be used, that proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Program.
+
+Later license versions may give you additional or different permissions. However, no additional obligations are imposed on any author or copyright holder as a result of your choosing to follow a later version.
+
+15. Disclaimer of Warranty.
+THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+16. Limitation of Liability.
+IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+
+17. Interpretation of Sections 15 and 16.
+If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, reviewing courts shall apply local law that most closely approximates an absolute waiver of all civil liability in connection with the Program, unless a warranty or assumption of liability accompanies a copy of the Program in return for a fee.
+
+END OF TERMS AND CONDITIONS
+
+How to Apply These Terms to Your New Programs
+
+If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms.
+
+To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively state the exclusion of warranty; and each file should have at least the “copyright” line and a pointer to where the full notice is found.
+
+     <one line to give the program's name and a brief idea of what it does.>
+     Copyright (C) <year>  <name of author>
+
+     This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.
+
+     This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+
+     You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program does terminal interaction, make it output a short notice like this when it starts in an interactive mode:
+
+     <program>  Copyright (C) <year>  <name of author>
+     This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+     This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, your program's commands might be different; for a GUI interface, you would use an “about box”.
+
+You should also get your employer (if you work as a programmer) or school, if any, to sign a “copyright disclaimer” for the program, if necessary. For more information on this, and how to apply and follow the GNU GPL, see <http://www.gnu.org/licenses/>.
+
+The GNU General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. But first, please read <http://www.gnu.org/philosophy/why-not-lgpl.html>.

LICENSES/Apache-2.0.txt

@@ -0,0 +1,73 @@
+Apache License
+Version 2.0, January 2004
+http://www.apache.org/licenses/
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+1. Definitions.
+
+"License" shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document.
+
+"Licensor" shall mean the copyright owner or entity authorized by the copyright owner that is granting the License.
+
+"Legal Entity" shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that entity. For the purposes of this definition, "control" means (i) the power, direct or indirect, to cause the direction or management of such entity, whether by contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the outstanding shares, or (iii) beneficial ownership of such entity.
+
+"You" (or "Your") shall mean an individual or Legal Entity exercising permissions granted by this License.
+
+"Source" form shall mean the preferred form for making modifications, including but not limited to software source code, documentation source, and configuration files.
+
+"Object" form shall mean any form resulting from mechanical transformation or translation of a Source form, including but not limited to compiled object code, generated documentation, and conversions to other media types.
+
+"Work" shall mean the work of authorship, whether in Source or Object form, made available under the License, as indicated by a copyright notice that is included in or attached to the work (an example is provided in the Appendix below).
+
+"Derivative Works" shall mean any work, whether in Source or Object form, that is based on (or derived from) the Work and for which the editorial revisions, annotations, elaborations, or other modifications represent, as a whole, an original work of authorship. For the purposes of this License, Derivative Works shall not include works that remain separable from, or merely link (or bind by name) to the interfaces of, the Work and Derivative Works thereof.
+
+"Contribution" shall mean any work of authorship, including the original version of the Work and any modifications or additions to that Work or Derivative Works thereof, that is intentionally submitted to Licensor for inclusion in the Work by the copyright owner or by an individual or Legal Entity authorized to submit on behalf of the copyright owner. For the purposes of this definition, "submitted" means any form of electronic, verbal, or written communication sent to the Licensor or its representatives, including but not limited to communication on electronic mailing lists, source code control systems, and issue tracking systems that are managed by, or on behalf of, the Licensor for the purpose of discussing and improving the Work, but excluding communication that is conspicuously marked or otherwise designated in writing by the copyright owner as "Not a Contribution."
+
+"Contributor" shall mean Licensor and any individual or Legal Entity on behalf of whom a Contribution has been received by Licensor and subsequently incorporated within the Work.
+
+2. Grant of Copyright License. Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable copyright license to reproduce, prepare Derivative Works of, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form.
+
+3. Grant of Patent License. Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable (except as stated in this section) patent license to make, have made, use, offer to sell, sell, import, and otherwise transfer the Work, where such license applies only to those patent claims licensable by such Contributor that are necessarily infringed by their Contribution(s) alone or by combination of their Contribution(s) with the Work to which such Contribution(s) was submitted. If You institute patent litigation against any entity (including a cross-claim or counterclaim in a lawsuit) alleging that the Work or a Contribution incorporated within the Work constitutes direct or contributory patent infringement, then any patent licenses granted to You under this License for that Work shall terminate as of the date such litigation is filed.
+
+4. Redistribution. You may reproduce and distribute copies of the Work or Derivative Works thereof in any medium, with or without modifications, and in Source or Object form, provided that You meet the following conditions:
+
+     (a) You must give any other recipients of the Work or Derivative Works a copy of this License; and
+
+     (b) You must cause any modified files to carry prominent notices stating that You changed the files; and
+
+     (c) You must retain, in the Source form of any Derivative Works that You distribute, all copyright, patent, trademark, and attribution notices from the Source form of the Work, excluding those notices that do not pertain to any part of the Derivative Works; and
+
+     (d) If the Work includes a "NOTICE" text file as part of its distribution, then any Derivative Works that You distribute must include a readable copy of the attribution notices contained within such NOTICE file, excluding those notices that do not pertain to any part of the Derivative Works, in at least one of the following places: within a NOTICE text file distributed as part of the Derivative Works; within the Source form or documentation, if provided along with the Derivative Works; or, within a display generated by the Derivative Works, if and wherever such third-party notices normally appear. The contents of the NOTICE file are for informational purposes only and do not modify the License. You may add Your own attribution notices within Derivative Works that You distribute, alongside or as an addendum to the NOTICE text from the Work, provided that such additional attribution notices cannot be construed as modifying the License.
+
+     You may add Your own copyright statement to Your modifications and may provide additional or different license terms and conditions for use, reproduction, or distribution of Your modifications, or for any such Derivative Works as a whole, provided Your use, reproduction, and distribution of the Work otherwise complies with the conditions stated in this License.
+
+5. Submission of Contributions. Unless You explicitly state otherwise, any Contribution intentionally submitted for inclusion in the Work by You to the Licensor shall be under the terms and conditions of this License, without any additional terms or conditions. Notwithstanding the above, nothing herein shall supersede or modify the terms of any separate license agreement you may have executed with Licensor regarding such Contributions.
+
+6. Trademarks. This License does not grant permission to use the trade names, trademarks, service marks, or product names of the Licensor, except as required for reasonable and customary use in describing the origin of the Work and reproducing the content of the NOTICE file.
+
+7. Disclaimer of Warranty. Unless required by applicable law or agreed to in writing, Licensor provides the Work (and each Contributor provides its Contributions) on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, including, without limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. You are solely responsible for determining the appropriateness of using or redistributing the Work and assume any risks associated with Your exercise of permissions under this License.
+
+8. Limitation of Liability. In no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been advised of the possibility of such damages.
+
+9. Accepting Warranty or Additional Liability. While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability.
+
+END OF TERMS AND CONDITIONS
+
+APPENDIX: How to apply the Apache License to your work.
+
+To apply the Apache License to your work, attach the following boilerplate notice, with the fields enclosed by brackets "[]" replaced with your own identifying information. (Don't include the brackets!)  The text should be enclosed in the appropriate comment syntax for the file format. We also recommend that a file or class name and description of purpose be included on the same "printed page" as the copyright notice for easier identification within third-party archives.
+
+Copyright [yyyy] [name of copyright owner]
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.

LICENSES/Artistic-2.0.txt

@@ -0,0 +1,85 @@
+The Artistic License 2.0
+
+Copyright (c) 2000-2006, The Perl Foundation.
+
+Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed.
+
+Preamble
+
+This license establishes the terms under which a given free software Package may be copied, modified, distributed, and/or redistributed. The intent is that the Copyright Holder maintains some artistic control over the development of that Package while still keeping the Package available as open source and free software.
+
+You are always permitted to make arrangements wholly outside of this license directly with the Copyright Holder of a given Package.  If the terms of this license do not permit the full use that you propose to make of the Package, you should contact the Copyright Holder and seek a different licensing arrangement.
+
+Definitions
+
+     "Copyright Holder" means the individual(s) or organization(s) named in the copyright notice for the entire Package.
+
+     "Contributor" means any party that has contributed code or other material to the Package, in accordance with the Copyright Holder's procedures.
+
+     "You" and "your" means any person who would like to copy, distribute, or modify the Package.
+
+     "Package" means the collection of files distributed by the Copyright Holder, and derivatives of that collection and/or of those files. A given Package may consist of either the Standard Version, or a Modified Version.
+
+     "Distribute" means providing a copy of the Package or making it accessible to anyone else, or in the case of a company or organization, to others outside of your company or organization.
+
+     "Distributor Fee" means any fee that you charge for Distributing this Package or providing support for this Package to another party.  It does not mean licensing fees.
+
+     "Standard Version" refers to the Package if it has not been modified, or has been modified only in ways explicitly requested by the Copyright Holder.
+
+     "Modified Version" means the Package, if it has been changed, and such changes were not explicitly requested by the Copyright Holder.
+
+     "Original License" means this Artistic License as Distributed with the Standard Version of the Package, in its current version or as it may be modified by The Perl Foundation in the future.
+
+     "Source" form means the source code, documentation source, and configuration files for the Package.
+
+     "Compiled" form means the compiled bytecode, object code, binary, or any other form resulting from mechanical transformation or translation of the Source form.
+
+Permission for Use and Modification Without Distribution
+
+(1) You are permitted to use the Standard Version and create and use Modified Versions for any purpose without restriction, provided that you do not Distribute the Modified Version.
+
+Permissions for Redistribution of the Standard Version
+
+(2) You may Distribute verbatim copies of the Source form of the Standard Version of this Package in any medium without restriction, either gratis or for a Distributor Fee, provided that you duplicate all of the original copyright notices and associated disclaimers.  At your discretion, such verbatim copies may or may not include a Compiled form of the Package.
+
+(3) You may apply any bug fixes, portability changes, and other modifications made available from the Copyright Holder.  The resulting Package will still be considered the Standard Version, and as such will be subject to the Original License.
+
+Distribution of Modified Versions of the Package as Source
+
+(4) You may Distribute your Modified Version as Source (either gratis or for a Distributor Fee, and with or without a Compiled form of the Modified Version) provided that you clearly document how it differs from the Standard Version, including, but not limited to, documenting any non-standard features, executables, or modules, and provided that you do at least ONE of the following:
+
+     (a) make the Modified Version available to the Copyright Holder of the Standard Version, under the Original License, so that the Copyright Holder may include your modifications in the Standard Version.
+     (b) ensure that installation of your Modified Version does not prevent the user installing or running the Standard Version. In addition, the Modified Version must bear a name that is different from the name of the Standard Version.
+     (c) allow anyone who receives a copy of the Modified Version to make the Source form of the Modified Version available to others under
+
+          (i) the Original License or
+          (ii) a license that permits the licensee to freely copy, modify and redistribute the Modified Version using the same licensing terms that apply to the copy that the licensee received, and requires that the Source form of the Modified Version, and of any works derived from it, be made freely available in that license fees are prohibited but Distributor Fees are allowed.
+
+Distribution of Compiled Forms of the Standard Version or Modified Versions without the Source
+
+(5)  You may Distribute Compiled forms of the Standard Version without the Source, provided that you include complete instructions on how to get the Source of the Standard Version.  Such instructions must be valid at the time of your distribution.  If these instructions, at any time while you are carrying out such distribution, become invalid, you must provide new instructions on demand or cease further distribution. If you provide valid instructions or cease distribution within thirty days after you become aware that the instructions are invalid, then you do not forfeit any of your rights under this license.
+
+(6)  You may Distribute a Modified Version in Compiled form without the Source, provided that you comply with Section 4 with respect to the Source of the Modified Version.
+
+Aggregating or Linking the Package
+
+(7)  You may aggregate the Package (either the Standard Version or Modified Version) with other packages and Distribute the resulting aggregation provided that you do not charge a licensing fee for the Package.  Distributor Fees are permitted, and licensing fees for other components in the aggregation are permitted. The terms of this license apply to the use and Distribution of the Standard or Modified Versions as included in the aggregation.
+
+(8) You are permitted to link Modified and Standard Versions with other works, to embed the Package in a larger work of your own, or to build stand-alone binary or bytecode versions of applications that include the Package, and Distribute the result without restriction, provided the result does not expose a direct interface to the Package.
+
+Items That are Not Considered Part of a Modified Version
+
+(9) Works (including, but not limited to, modules and scripts) that merely extend or make use of the Package, do not, by themselves, cause the Package to be a Modified Version.  In addition, such works are not considered parts of the Package itself, and are not subject to the terms of this license.
+
+General Provisions
+
+(10)  Any use, modification, and distribution of the Standard or Modified Versions is governed by this Artistic License. By using, modifying or distributing the Package, you accept this license. Do not use, modify, or distribute the Package, if you do not accept this license.
+
+(11)  If your Modified Version has been derived from a Modified Version made by someone other than you, you are nevertheless required to ensure that your Modified Version complies with the requirements of this license.
+
+(12)  This license does not grant you the right to use any trademark, service mark, tradename, or logo of the Copyright Holder.
+
+(13)  This license includes the non-exclusive, worldwide, free-of-charge patent license to make, have made, use, offer to sell, sell, import and otherwise transfer the Package with respect to any patent claims licensable by the Copyright Holder that are necessarily infringed by the Package. If you institute patent litigation (including a cross-claim or counterclaim) against any party alleging that the Package constitutes direct or contributory patent infringement, then this Artistic License to you shall terminate on the date that such litigation is filed.
+
+(14)  Disclaimer of Warranty:
+THE PACKAGE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS IS" AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES. THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED TO THE EXTENT PERMITTED BY YOUR LOCAL LAW. UNLESS REQUIRED BY LAW, NO COPYRIGHT HOLDER OR CONTRIBUTOR WILL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING IN ANY WAY OUT OF THE USE OF THE PACKAGE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

LICENSES/BSD-2-Clause.txt

@@ -0,0 +1,9 @@
+Copyright (c) <year> <owner>
+
+Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

LICENSES/BSD-3-Clause.txt

@@ -0,0 +1,11 @@
+Copyright (c) <year> <owner>.
+
+Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

LICENSES/CC0-1.0.txt

@@ -0,0 +1,121 @@
+Creative Commons Legal Code
+
+CC0 1.0 Universal
+
+    CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE
+    LEGAL SERVICES. DISTRIBUTION OF THIS DOCUMENT DOES NOT CREATE AN
+    ATTORNEY-CLIENT RELATIONSHIP. CREATIVE COMMONS PROVIDES THIS
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+    REGARDING THE USE OF THIS DOCUMENT OR THE INFORMATION OR WORKS
+    PROVIDED HEREUNDER, AND DISCLAIMS LIABILITY FOR DAMAGES RESULTING FROM
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+
+Statement of Purpose
+
+The laws of most jurisdictions throughout the world automatically confer
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+
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+
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+
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+applied by Affirmer to the Work. Should any part of the License for any
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+partial invalidity or ineffectiveness shall not invalidate the remainder
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+will not (i) exercise any of his or her remaining Copyright and Related
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+
+4. Limitations and Disclaimers.
+
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+    party to this document and has no duty or obligation with respect to
+    this CC0 or use of the Work.

LICENSES/ISC.txt

@@ -0,0 +1,8 @@
+ISC License:
+
+Copyright (c) 2004-2010 by Internet Systems Consortium, Inc. ("ISC")
+Copyright (c) 1995-2003 by Internet Software Consortium
+
+Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.
+
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LICENSES/LGPL-3.0-only.txt

@@ -0,0 +1,304 @@
+GNU LESSER GENERAL PUBLIC LICENSE
+Version 3, 29 June 2007
+
+Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
+
+Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed.
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+GNU GENERAL PUBLIC LICENSE
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+Each version is given a distinguishing version number. If the Program specifies that a certain numbered version of the GNU General Public License “or any later version” applies to it, you have the option of following the terms and conditions either of that numbered version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of the GNU General Public License, you may choose any version ever published by the Free Software Foundation.
+
+If the Program specifies that a proxy can decide which future versions of the GNU General Public License can be used, that proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Program.
+
+Later license versions may give you additional or different permissions. However, no additional obligations are imposed on any author or copyright holder as a result of your choosing to follow a later version.
+
+15. Disclaimer of Warranty.
+THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+16. Limitation of Liability.
+IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+
+17. Interpretation of Sections 15 and 16.
+If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, reviewing courts shall apply local law that most closely approximates an absolute waiver of all civil liability in connection with the Program, unless a warranty or assumption of liability accompanies a copy of the Program in return for a fee.
+
+END OF TERMS AND CONDITIONS
+
+How to Apply These Terms to Your New Programs
+
+If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms.
+
+To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively state the exclusion of warranty; and each file should have at least the “copyright” line and a pointer to where the full notice is found.
+
+     <one line to give the program's name and a brief idea of what it does.>
+     Copyright (C) <year>  <name of author>
+
+     This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.
+
+     This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+
+     You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program does terminal interaction, make it output a short notice like this when it starts in an interactive mode:
+
+     <program>  Copyright (C) <year>  <name of author>
+     This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+     This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, your program's commands might be different; for a GUI interface, you would use an “about box”.
+
+You should also get your employer (if you work as a programmer) or school, if any, to sign a “copyright disclaimer” for the program, if necessary. For more information on this, and how to apply and follow the GNU GPL, see <http://www.gnu.org/licenses/>.
+
+The GNU General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. But first, please read <http://www.gnu.org/philosophy/why-not-lgpl.html>.

LICENSES/LicenseRef-Altera-No-Warranty.txt

@@ -0,0 +1,7 @@
+This Verilog file was developed by Altera Corporation.  It may be
+freely copied and/or distributed at no cost.  Any persons using this
+file for any purpose do so at their own risk, and are responsible for
+the results of such use.  Altera Corporation does not guarantee that
+this file is complete, correct, or fit for any particular purpose.
+NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED.  This notice must
+accompany any copy of this file.

LICENSES/LicenseRef-IEEE-1800.txt

@@ -0,0 +1,22 @@
+This license is used on IEEE files where there is a permitted use of
+standards, including copying strictly necessary to implement normative
+interfaces defined by the standard. Refer to IEEE SA Operations Manual
+Clause 6.1 and IEEE Standards Permission policies.
+
+--
+
+Copyright 2024 by The Institute of Electrical and Electronics Engineers, Inc.
+All rights reserved.
+
+IEEE, 802, and POSIX are registered trademarks in the U.S. Patent &
+Trademark Office, owned by The Institute of Electrical and Electronics
+Engineers, Incorporated.
+
+IEEE draft and approved standards are copyrighted by IEEE under US and
+international copyright laws.  They are made available by IEEE and are
+adopted for a wide variety of both public and private uses. These include
+both use, by reference, in laws and regulations, and use in private
+self-regulation, standardization, and the promotion of engineering
+practices and methods. By making these documents available for use and
+adoption by public authorities and private users, neither IEEE nor its
+licensors waive any rights in copyright to the documents.

LICENSES/MIT.txt

@@ -0,0 +1,18 @@
+MIT License
+
+Copyright (c) <year> <copyright holders>
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of this software and
+associated documentation files (the "Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the
+following conditions:
+
+The above copyright notice and this permission notice shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT
+LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
+EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+USE OR OTHER DEALINGS IN THE SOFTWARE.

LICENSES/Unlicense.txt

@@ -0,0 +1,10 @@
+This is free and unencumbered software released into the public domain.
+
+Anyone is free to copy, modify, publish, use, compile, sell, or distribute this software, either in source code form or as a compiled binary, for any purpose, commercial or non-commercial, and by any means.
+
+In jurisdictions that recognize copyright laws, the author or authors of this software dedicate any and all copyright interest in the software to the public domain. We make this dedication for the benefit of the public at large and to the detriment of our heirs and
+successors. We intend this dedication to be an overt act of relinquishment in perpetuity of all present and future rights to this software under copyright law.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+For more information, please refer to <http://unlicense.org/>

Makefile.in

@@ -7,10 +7,10 @@
 #
 #*****************************************************************************
 #
-# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 #****************************************************************************/
@@ -398,9 +398,12 @@ CPPCHECK_RUNTIME_CPP = $(wildcard $(srcdir)/include/*.cpp)
 CPPCHECK_VLC_CPP = $(wildcard $(srcdir)/src/Vlc*.cpp)
 CPPCHECK_EXAMPLES_CPP = $(wildcard $(srcdir)/examples/*/*.cpp)
 CHECK_CPP = $(CPPCHECK_VERILATOR_CPP) $(CPPCHECK_RUNTIME_CPP) $(CPPCHECK_VLC_CPP) $(CPPCHECK_EXAMPLES_CPP)
-CHECK_H = $(wildcard \
+CHECK_H = $(filter-out \
+  $(srcdir)/src/config_package.h \
+  $(srcdir)/src/config_rev.h, \
+  $(wildcard \
   $(srcdir)/include/*.h \
-  $(srcdir)/src/*.h )
+  $(srcdir)/src/*.h ))
 CHECK_YL = $(wildcard \
   $(srcdir)/src/*.y \
   $(srcdir)/src/*.l )
@@ -441,7 +444,9 @@ cppcheck:
 CLANGTIDY = clang-tidy
 CLANGTIDY_FLAGS = -config='' \
   -header-filter='.*' \
-  -checks='-fuchsia-*,-cppcoreguidelines-avoid-c-arrays,-cppcoreguidelines-init-variables,-cppcoreguidelines-avoid-goto,-modernize-avoid-c-arrays,-readability-magic-numbers,-readability-simplify-boolean-expr,-cppcoreguidelines-macro-usage' \
+  -checks='*,-abseil-*,-fuchsia-*,-cppcoreguidelines-avoid-c-arrays,-cppcoreguidelines-init-variables,-cppcoreguidelines-avoid-goto,-modernize-avoid-c-arrays,-readability-magic-numbers,-readability-simplify-boolean-expr,-cppcoreguidelines-macro-usage' \
+
+# Good checks: -checks='-*,bugprone-assignment-in-if-condition,google-build-using-namespace,google-readability-casting,modernize-use-default-member-init,modernize-use-emplace,modernize-use-equals-default,modernize-use-equals-delete,modernize-use-nullptr,performance-faster-string-find,readability-isolate-declaration,readability-redundant-control-flow,readability-redundant-member-init,readability-redundant-string-cstr,readability-uppercase-literal-suffix
 
 CLANGTIDY_DEP = $(subst .cpp,.cpp.tidy,$(CHECK_CPP))
 CLANGTIDY_DEFS = -DVL_DEBUG=1 -DVL_CPPCHECK=1
@@ -460,23 +465,19 @@ analyzer-include:
 	-rm -rf examples/*/obj*
 	scan-build $(MAKE) -k examples
 
-format:
-	$(MAKE) -j 5 format-c format-cmake format-exec format-py
-
-CLANGFORMAT = clang-format-18
-CLANGFORMAT_FLAGS = -i
-CLANGFORMAT_FILES = $(CHECK_CPP) $(CHECK_H) $(CHECK_YL) test_regress/t/*.c* test_regress/t/*.h
-
-format-c clang-format:
-	$(CLANGFORMAT) --version
-	@$(CLANGFORMAT) --version | fgrep 'version 18' > /dev/null \
-	|| echo "*** You are not using clang-format-18, indents may differ from master's ***"
-	$(CLANGFORMAT) $(CLANGFORMAT_FLAGS) $(CLANGFORMAT_FILES)
-
-YAMLFIX = YAMLFIX_WHITELINES=1 YAMLFIX_LINE_LENGTH=200 YAMLFIX_preserve_quotes=true yamlfix
-
-yamlfix:
-	$(YAMLFIX) .
+# Bash/sh files
+BASH_FILES = \
+  ci/ci-install.bash \
+  ci/ci-pages-notify.bash \
+  ci/ci-pages.bash \
+  ci/ci-script.bash \
+  ci/docker/run/hooks/post_push \
+  ci/docker/run/verilator-docker \
+  ci/docker/run/verilator-wrap.sh \
+  nodist/fuzzer/all \
+  nodist/fuzzer/run \
+  nodist/fuzzer/setup_root \
+  nodist/fuzzer/setup_user \
 
 # CMake files
 CMAKE_FILES = \
@@ -495,6 +496,12 @@ MAKE_FILES = \
   src/Makefile*.in \
   test_regress/Makefile* \
 
+# Perl programs
+PERL_PROGRAMS = \
+  bin/redirect \
+  bin/verilator \
+  bin/verilator_coverage \
+
 # Python programs, subject to format and lint
 PY_PROGRAMS = \
   bin/verilator_ccache_report \
@@ -502,25 +509,29 @@ PY_PROGRAMS = \
   bin/verilator_gantt \
   bin/verilator_includer \
   bin/verilator_profcfunc \
-  examples/json_py/vl_file_copy \
-  examples/json_py/vl_hier_graph \
-  docs/guide/conf.py \
   docs/bin/vl_sphinx_extract \
   docs/bin/vl_sphinx_fix \
-  src/astgen \
-  src/bisonpre \
-  src/config_rev \
-  src/flexfix \
-  src/vlcovgen \
-  src/.gdbinit.py \
-  test_regress/*.py \
-  test_regress/t/*.pf \
+  docs/guide/conf.py \
+  examples/json_py/vl_file_copy \
+  examples/json_py/vl_hier_graph \
   nodist/clang_check_attributes \
   nodist/dot_importer \
   nodist/fuzzer/actual_fail \
   nodist/fuzzer/generate_dictionary \
   nodist/install_test \
+  nodist/lint_py_test_filter \
   nodist/log_changes \
+  nodist/uvm_pkg_packer \
+  nodist/verilator_bisect \
+  nodist/verilator_saif_diff \
+  src/.gdbinit.py \
+  src/astgen \
+  src/bisonpre \
+  src/config_rev \
+  src/flexfix \
+  src/vlcovgen \
+  test_regress/*.py \
+  test_regress/t/*.pf \
 
 # Python files, subject to format but not lint
 PY_FILES = \
@@ -530,26 +541,71 @@ PY_FILES = \
 # Python files, test_regress tests
 PY_TEST_FILES = test_regress/t/*.py
 
-YAPF = yapf3
+# YAML files
+YAML_FILES = \
+  .*.yaml \
+  .*.yml \
+  .github/*.yml \
+  .github/*/*.yml \
+  CITATION.cff \
+
+######################################################################
+# Format
+
+format:
+	$(MAKE) -j 5 format-c format-cmake format-exec format-py format-yaml
+
+BEAUTYSH = beautysh
+BEAUTYSH_FLAGS = --indent-size 2
+
+format-bash:
+	$(BEAUTYSH) --version
+	$(BEAUTYSH) $(BEAUTYSH_FLAGS) $(BASH_FILES)
+
+CLANGFORMAT = clang-format-18
+CLANGFORMAT_FLAGS = -i
+CLANGFORMAT_FILES = $(CHECK_CPP) $(CHECK_H) $(CHECK_YL) test_regress/t/*.c* test_regress/t/*.h
+
+format-c clang-format:
+	$(CLANGFORMAT) --version
+	@$(CLANGFORMAT) --version | fgrep 'version 18' > /dev/null \
+	|| echo "*** You are not using clang-format-18, indents may differ from master's ***"
+	$(CLANGFORMAT) $(CLANGFORMAT_FLAGS) $(CLANGFORMAT_FILES)
+
+GERSEMI = gersemi
+GERSEMI_FLAGS = -i --no-warn-about-unknown-commands
+
+format-cmake:
+	$(GERSEMI) --version
+	$(GERSEMI) $(GERSEMI_FLAGS) $(CMAKE_FILES)
+
+MBAKE = mbake
+MBAKE_FLAGS = format --config ./.bake.toml
+
+format-exec:
+	-chmod a+x test_regress/t/t_*.py
+	-chmod a-x test_regress/t/*.v
+
+format-make mbake:
+	$(MBAKE) --version
+	$(MBAKE) $(MBAKE_FLAGS) $(MAKE_FILES)
+
+YAPF = yapf
 YAPF_FLAGS = -i --parallel
 
 format-py yapf:
 	$(YAPF) --version
 	$(YAPF) $(YAPF_FLAGS) $(PY_FILES)
 
-GERSEMI = gersemi
-GERSEMI_FLAGS = -i --no-warn-about-unknown-commands
+YAMLFIX = YAMLFIX_WHITELINES=1 YAMLFIX_LINE_LENGTH=200 YAMLFIX_preserve_quotes=true yamlfix
+YAMLFIX_FLAGS =
 
-format-cmake:
-	$(GERSEMI) $(GERSEMI_FLAGS) $(CMAKE_FILES)
+format-yaml yamlfix:
+	$(YAMLFIX) --version
+	$(YAMLFIX) $(YAMLFIX_FLAGS) $(YAML_FILES)
 
-MBAKE = mbake
-MBAKE_FLAGS = format --config ./.bake.toml
-
-format-make:
-	$(MBAKE) $(MBAKE_FLAGS) $(MAKE_FILES)
-
-format-yaml: yamlfix
+######################################################################
+# Lint
 
 MYPY = mypy
 MYPY_FLAGS = --strict --no-error-summary
@@ -583,9 +639,6 @@ lint-py-pylint-tests:
 lint-py-ruff:
 	$(RUFF) $(RUFF_FLAGS) $(PY_PROGRAMS)
 
-format-exec:
-	-chmod a+x test_regress/t/*.py
-
 ######################################################################
 # Configure
 
@@ -781,7 +834,7 @@ clean mostlyclean distclean maintainer-clean::
 
 distclean maintainer-clean::
 	rm -f *.info* *.1 $(INFOS) $(INFOS_OLD) $(VL_INST_MAN_FILES)
-	rm -f Makefile config.status config.cache config.log TAGS
+	rm -f Makefile config.status config.cache config.log configure~ TAGS
 	rm -f verilator_bin* verilator_coverage_bin*
 	rm -f bin/verilator_bin* bin/verilator_coverage_bin*
 	rm -f include/verilated.mk include/verilated_config.h
@@ -806,3 +859,21 @@ preexist:
 
 maintainer-dist: preexist tag
 	svnorcvs release $(DISTTAGNAME)
+
+######################################################################
+# Python venv
+
+VENV_PATH ?= .venv
+
+.PHONY: venv
+venv:
+	# Create virtual environment using the python3 picked up by configure
+	[ -e $(VENV_PATH) ] || @PYTHON3@ -m venv --system-site-packages $(VENV_PATH)
+	# Install python3 dependencies, with explicit retry
+	$(VENV_PATH)/bin/pip3 install -r python-dev-requirements.txt || \
+	$(VENV_PATH)/bin/pip3 install -r python-dev-requirements.txt
+	@echo
+	@echo "Installed Python virtual environment, in:"
+	@echo "  $(VENV_PATH)"
+	@echo "To activate, run:"
+	@echo "  source $(VENV_PATH)/bin/activate"

README.rst

@@ -1,22 +1,24 @@
 .. Github doesn't render images unless absolute URL
 .. Do not know of a conditional tag, "only: github" nor "github display" works
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 |badge1| |badge2| |badge3| |badge4| |badge5| |badge7| |badge8|
 
 .. |badge1| image:: https://img.shields.io/badge/Website-Verilator.org-181717.svg
-    :target: https://verilator.org
+   :target: https://verilator.org
 .. |badge2| image:: https://img.shields.io/badge/License-LGPL%20v3-blue.svg
-    :target: https://www.gnu.org/licenses/lgpl-3.0
+   :target: https://www.gnu.org/licenses/lgpl-3.0
 .. |badge3| image:: https://img.shields.io/badge/License-Artistic%202.0-0298c3.svg
-    :target: https://opensource.org/licenses/Artistic-2.0
+   :target: https://opensource.org/licenses/Artistic-2.0
 .. |badge4| image:: https://repology.org/badge/tiny-repos/verilator.svg?header=distro%20packages
-    :target: https://repology.org/project/verilator/versions
+   :target: https://repology.org/project/verilator/versions
 .. |badge5| image:: https://img.shields.io/docker/pulls/verilator/verilator
-    :target: https://hub.docker.com/r/verilator/verilator
+   :target: https://hub.docker.com/r/verilator/verilator
 .. |badge7| image:: https://github.com/verilator/verilator/workflows/build/badge.svg
-    :target: https://github.com/verilator/verilator/actions?query=workflow%3Abuild
+   :target: https://github.com/verilator/verilator/actions?query=workflow%3Abuild
 .. |badge8| image:: https://img.shields.io/github/actions/workflow/status/verilator/verilator/rtlmeter.yml?branch=master&event=schedule&label=benchmarks
-    :target: https://verilator.github.io/verilator-rtlmeter-results
+   :target: https://verilator.github.io/verilator-rtlmeter-results
 
 
 Welcome to Verilator
@@ -28,7 +30,7 @@ Welcome to Verilator
         * Accepts Verilog or SystemVerilog
         * Performs lint code-quality checks
         * Compiles into multithreaded C++, or SystemC
-        * Creates XML to front-end your own tools
+        * Creates JSON to front-end your own tools
      - |Logo|
    * - |verilator multithreaded performance|
      - **Fast**
@@ -54,36 +56,38 @@ Welcome to Verilator
 What Verilator Does
 ===================
 
-Verilator is invoked with parameters similar to GCC or Synopsys's VCS.  It
+Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It
 "Verilates" the specified Verilog or SystemVerilog code by reading it,
 performing lint checks, and optionally inserting assertion checks and
 coverage-analysis points. It outputs single- or multithreaded .cpp and .h
 files, the "Verilated" code.
 
-These Verilated C++/SystemC files are then compiled by a C++ compiler
-(gcc/clang/MSVC++), optionally along with a user's own C++/SystemC wrapper
-file, to instantiate the Verilated model. Executing the resulting
-executable performs the design simulation. Verilator also supports linking
-Verilated generated libraries, optionally encrypted, into other simulators.
+Verilator can automatically generate a simulator executable (using
+``--binary``), or users can write their own C++/SystemC wrapper to
+instantiate the model. The resulting Verilated executable performs the
+design simulation. Verilator also supports linking Verilator-generated
+libraries, optionally encrypted, into other simulators.
 
-Verilator may not be the best choice if you are expecting a full-featured
-replacement for a closed-source Verilog simulator, need SDF annotation,
-mixed-signal simulation, or are doing a quick class project (we recommend
-`Icarus Verilog`_ for classwork).  However, if you are looking for a path
-to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of
-designs, Verilator is the tool for you.
+Verilator supports all design constructs, most verification constructs,
+intra-assignment delays (e.g, `#10`), and events. Tristate-bus (`z`) and
+unknowns (`x`) are handled in limited contexts, in a special manor for
+performance. It currently may not be the best choice if you are expecting a
+full-featured replacement for a closed-source Verilog simulator, performing
+SDF annotation, or mixed-signal simulation. However, if you are looking for
+a path to migrate SystemVerilog to C++/SystemC, or want high-speed
+simulation, Verilator is the tool for you.
 
 
 Performance
 ===========
 
-Verilator does not directly translate Verilog HDL to C++ or SystemC. Rather,
-Verilator compiles your code into a much faster optimized and optionally
-thread-partitioned model, which is in turn wrapped inside a C++/SystemC
-module. The results are a compiled Verilog model that executes even on a
-single thread over 10x faster than standalone SystemC, and on a single
-thread is about 100 times faster than interpreted Verilog simulators such
-as `Icarus Verilog`_. Another 2-10x speedup might be gained from
+Verilator does not directly translate Verilog HDL to C++ or SystemC.
+Rather, Verilator compiles your code into a much faster optimized and
+optionally thread-partitioned model, which is in turn wrapped inside a
+C++/SystemC module. The results are a compiled Verilog model that executes
+even on a single thread over 10x faster than standalone SystemC, and on a
+single thread is about 100 times faster than interpreted Verilog simulators
+such as `Icarus Verilog`_. Another 2-10x speedup might be gained from
 multithreading (yielding 200-1000x total over interpreted simulators).
 
 Verilator has typically similar or better performance versus closed-source
@@ -101,8 +105,8 @@ For more information:
 - `Verilator installation and package directory structure
   <https://verilator.org/install>`_
 
-- `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_,
-  or `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_
+- `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_, or
+  `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_
 
 - `Subscribe to Verilator announcements
   <https://github.com/verilator/verilator-announce>`_
@@ -132,6 +136,10 @@ organizations; please see `Verilator Commercial Support
 Related Projects
 ================
 
+- `Cocotb <https://www.cocotb.org/>`_ - A coroutine-based cosimulation
+  library for writing testbenches in Python which officially supports
+  Verilator.
+
 - `GTKwave <https://gtkwave.sourceforge.net/>`_ - Waveform viewer for
   Verilator traces.
 
@@ -145,16 +153,16 @@ Related Projects
 Open License
 ============
 
-Verilator is Copyright 2003-2025 by Wilson Snyder. (Report bugs to
+Verilator is Copyright 2003-2026 by Wilson Snyder. (Report bugs to
 `Verilator Issues <https://verilator.org/issues>`_.)
 
 Verilator is free software; you can redistribute it and/or modify it under
 the terms of either the GNU Lesser General Public License Version 3 or the
 Perl Artistic License Version 2.0. See the documentation for more details.
 
-.. _CHIPS Alliance: https://chipsalliance.org
-.. _Icarus Verilog: https://steveicarus.github.io/iverilog
-.. _Linux Foundation: https://www.linuxfoundation.org
+.. _chips alliance: https://chipsalliance.org
+.. _icarus verilog: https://steveicarus.github.io/iverilog
+.. _linux foundation: https://www.linuxfoundation.org
 .. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png
 .. |verilator multithreaded performance| image:: https://www.veripool.org/img/verilator_multithreaded_performance_bg-min.png
 .. |verilator usage| image:: https://www.veripool.org/img/verilator_usage_400x200-min.png

REUSE.toml

@@ -0,0 +1,60 @@
+# DESCRIPTION: Verilator default licensing for "reuse lint"
+
+version = 1
+
+[[annotations]]
+path = [
+    "**/.gitattributes",
+    "**/.gitignore",
+    ".clang-format",
+    ".clang-tidy",
+    ".codacy.yml",
+    ".devcontainer/devcontainer.json",
+    ".github/**",
+    ".pre-commit-hooks.yaml",
+    ".style.yapf",
+    "CITATION.cff",
+    "CPPLINT.cfg",
+    "docs/CONTRIBUTORS",
+    "docs/spelling.txt",
+    "docs/verilated.dox",
+    "examples/**/*.vc",
+    "install-sh",
+    "test_regress/.gdbinit",
+    "test_regress/input.vc",
+    "test_regress/input.xsim.vc",
+    "test_regress/t/*.dat",
+    "test_regress/t/*.gprof",
+    "test_regress/t/*.mem",
+    "test_regress/t/*.out",
+    "test_regress/t/*.tree",
+    "test_regress/t/*.vc",
+    "test_regress/t/t_lint_bsspace_bad.v",
+    "verilator.pc.in",
+]
+SPDX-FileCopyrightText = "2003-2026 Wilson Snyder"
+SPDX-License-Identifier = "CC0-1.0"
+
+[[annotations]]
+path = [
+    "docs/_static/**",
+    "docs/gen/*.rst",
+    "docs/guide/figures/**",
+]
+SPDX-FileCopyrightText = "2003-2026 Wilson Snyder"
+SPDX-License-Identifier = "LGPL-3.0-only OR Artistic-2.0"
+
+[[annotations]]
+path = "test_regress/t/uvm/**"
+SPDX-FileCopyrightText = [
+    "2010-2017 Mentor Graphics Corporation",
+    "2010-2013 Synopsys, Inc.",
+    "2010-2018 Cadence Design Systems, Inc.",
+    "2013 NVIDIA Corporation",
+]
+SPDX-License-Identifier = "Apache-2.0"
+
+[[annotations]]
+path = "include/gtkwave/lz4.*"
+SPDX-FileCopyrightText = "2011-2023 Yann Collet"
+SPDX-License-Identifier = "BSD-2-Clause"

bin/redirect

@@ -1,10 +1,10 @@
 #!/usr/bin/env perl
 ######################################################################
 #
-# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################

bin/verilator

@@ -1,10 +1,10 @@
 #!/usr/bin/env perl
 ######################################################################
 #
-# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################
@@ -42,6 +42,7 @@ if ($#ARGV < 0) {
 }
 
 # Insert debugging options up front
+# (VERILATOR_TEST_FLAGS is not a documented nor official supported feature)
 push @ARGV, (split ' ', $ENV{VERILATOR_TEST_FLAGS} || "");
 
 # We sneak a look at the flags so we can do some pre-environment checks
@@ -148,7 +149,7 @@ if ($opt_gdb) {
         . verilator_bin()
         . " " . join(' ', @quoted_sw));
 } else {
-    # Normal, non gdb
+    # Normal, non-gdb
     run(ulimit_stack_unlimited() . aslr(1) . verilator_bin() . " " . join(' ', @quoted_sw));
 }
 
@@ -212,14 +213,22 @@ sub ulimit_stack_unlimited {
     # AddressSanitizer doesn't work with 'ulimit -s unlimted'
     if (`${\(verilator_bin())} --get-supported DEV_ASAN` eq "1\n") {
         # Use host 'physical memory / #cores / 8' instead
-        open(my $fh, "<", "/proc/meminfo") || die "Can't read host memory for asan";
-        while (<$fh>) {
-            if (m/MemTotal:\s+(\d+)\s+kB/) {
-                $limit = int(int($1)/`nproc`/8);
-                last;
+        if ($^O eq "darwin") {
+            my $membytes = `sysctl -n hw.memsize`;
+            chomp $membytes;
+            my $ncpu = `sysctl -n hw.ncpu`;
+            chomp $ncpu;
+            $limit = int(int($membytes / 1024) / $ncpu / 8);
+        } else {
+            open(my $fh, "<", "/proc/meminfo") || die "Can't read host memory for asan";
+            while (<$fh>) {
+                if (m/MemTotal:\s+(\d+)\s+kB/) {
+                    $limit = int(int($1)/`nproc`/8);
+                    last;
+                }
             }
+            close($fh);
         }
-        close($fh);
     }
     system("ulimit -s $limit 2>/dev/null");
     my $status = $?;
@@ -344,6 +353,7 @@ detailed descriptions of these arguments.
      -CFLAGS <flags>            C++ compiler arguments for makefile
     --compiler <compiler-name>  Tune for specified C++ compiler
     --compiler-include          Include additional header in the precompiled one
+    --constraint-array-limit <size>   Maximum array size for constraint array reduction
     --converge-limit <loops>    Tune convergence settle time
     --coverage                  Enable all coverage
     --coverage-expr             Enable expression coverage
@@ -389,6 +399,7 @@ detailed descriptions of these arguments.
      -f <file>                  Parse arguments from a file
      -FI <file>                 Force include of a file
     --flatten                   Force inlining of all modules, tasks and functions
+    --func-recursion-depth <value>  Maximum recursive constant function depth
     --future0 <option>          Ignore an option for compatibility
     --future1 <option>          Ignore an option with argument for compatibility
      -fno-<optimization>        Disable internal optimization stage
@@ -408,6 +419,8 @@ detailed descriptions of these arguments.
      -I<dir>                    Directory to search for includes
     --if-depth <value>          Tune IFDEPTH warning
      +incdir+<dir>              Directory to search for includes
+    --inline-cfuncs <value>     Inline CFuncs with <=value nodes (0=off)
+    --inline-cfuncs-product <value>  Inline CFuncs if size*calls <= value
     --inline-mult <value>       Tune module inlining
     --instr-count-dpi <value>   Assumed dynamic instruction count of DPI imports
      -j <jobs>                  Parallelism for --build-jobs/--verilate-jobs
@@ -419,6 +432,7 @@ detailed descriptions of these arguments.
     --l2-name <value>           Verilog scope name of the top module
     --language <lang>           Default language standard to parse
      -LDFLAGS <flags>           Linker pre-object arguments for makefile
+     -libmap                    Specify library mapping file
     --lib-create <name>         Create a DPI library
      +libext+<ext>+[ext]...     Extensions for finding modules
      +librescan                 Ignored for compatibility
@@ -473,15 +487,18 @@ detailed descriptions of these arguments.
     --public-params             Mark all parameters as public_flat
      -pvalue+<name>=<value>     Overwrite toplevel parameter
     --quiet                     Minimize additional printing
+    --quiet-build               Don't print build progress
     --quiet-exit                Don't print the command on failure
     --quiet-stats               Don't print statistics
     --relative-includes         Resolve includes relative to current file
     --reloop-limit <value>      Minimum iterations for forming loops
+    --replication-limit <value> Replication concatenation limit (default: 8k)
     --report-unoptflat          Extra diagnostics for UNOPTFLAT
     --rr                        Run Verilator and record with rr
     --runtime-debug             Enable model runtime debugging
     --savable                   Enable model save-restore
     --sc                        Create SystemC output
+    --sched-zero-delay          Specify #0 delay support
     --no-skip-identical         Disable skipping identical output
     --stats                     Create statistics file
     --stats-vars                Provide statistics on variables
@@ -489,7 +506,6 @@ detailed descriptions of these arguments.
     --no-std-package            Prevent parsing standard package
     --no-std-waiver             Prevent parsing standard lint waivers
     --no-stop-fail              Do not call $stop when assertion fails
-    --structs-packed            Convert all unpacked structures to packed structures
      -sv                        Enable SystemVerilog parsing
      +systemverilogext+<ext>    Synonym for +1800-2023ext+<ext>
     --threads <threads>         Enable multithreading
@@ -517,6 +533,7 @@ detailed descriptions of these arguments.
      -U<var>                    Undefine preprocessor define
     --no-unlimited-stack        Don't disable stack size limit
     --unroll-count <loops>      Tune maximum loop iterations
+    --unroll-limit <loops>      Maximum loop iterations before assuming infinite loop
     --unroll-stmts <stmts>      Tune maximum loop body size
     --unused-regexp <regexp>    Tune UNUSED lint signals
      -V                         Verbose version and config
@@ -546,8 +563,6 @@ detailed descriptions of these arguments.
     --x-assign <mode>           Assign non-initial Xs to this value
     --x-initial <mode>          Assign initial Xs to this value
     --x-initial-edge            Enable initial X->0 and X->1 edge triggers
-    --xml-only                  Create XML parser output
-    --xml-output                XML output filename
      -y <dir>                   Directory to search for modules
 
 This is a short summary of the simulation runtime arguments, i.e. for the
@@ -570,15 +585,17 @@ description of these arguments.
      +verilator+quiet                      Minimize additional printing
      +verilator+rand+reset+<value>         Set random reset technique
      +verilator+seed+<value>               Set random seed
+     +verilator+solver+file+<filename>     Set random solver log filename
      +verilator+V                          Show verbose version and config
      +verilator+version                    Show version and exit
+     +verilator+wno+unsatconstr+<value>    Disable constraint warnings
 
 
 =head1 DISTRIBUTION
 
 The latest version is available from L<https://verilator.org>.
 
-Copyright 2003-2025 by Wilson Snyder. This program is free software; you can
+Copyright 2003-2026 by Wilson Snyder. This program is free software; you can
 redistribute it and/or modify the Verilator internals under the terms of
 either the GNU Lesser General Public License Version 3 or the Perl Artistic
 License Version 2.0.

bin/verilator_ccache_report

@@ -17,18 +17,15 @@ parser = argparse.ArgumentParser(
 
     For documentation see
     https://verilator.org/guide/latest/exe_verilator_ccache_report.html""",
-    epilog="""Copyright 2002-2025 by Wilson Snyder. This program is free software; you
-can redistribute it and/or modify it under the terms of either the GNU
-Lesser General Public License Version 3 or the Perl Artistic License
-Version 2.0.
+    epilog="""This program is free software; you can redistribute it and/or modify it
+under the terms of either the GNU Lesser General Public License Version 3
+or the Perl Artistic License Version 2.0.
 
-SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
+SPDX-FileCopyrightText: 2002-2026 Wilson Snyder
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+""")
 
-parser.add_argument('-o',
-                    type=argparse.FileType('w'),
-                    metavar="OUTFILE",
-                    required=True,
-                    help='output file')
+parser.add_argument('-o', type=pathlib.Path, metavar="OUTFILE", required=True, help='output file')
 parser.add_argument('logdir', type=pathlib.Path, help='log directory')
 
 args = parser.parse_args()
@@ -58,34 +55,35 @@ for logfile in args.logdir.iterdir():
                 elapsed[obj] = toDateTime(match.group(1)) - start
                 results[obj] = match.group(2)
 
-args.o.write("#" * 80 + "\n")
-args.o.write("ccache report (from verilator_ccache_report) :\n")
+with args.o.open("w") as ofd:
+    ofd.write("#" * 80 + "\n")
+    ofd.write("ccache report (from verilator_ccache_report) :\n")
 
-if not results:
-    args.o.write("\nAll object files up to date\n")
-else:
-    args.o.write("\nCompiled object files:\n")
-    wnames = max(len(_) for _ in results) + 1
-    wresults = max(len(_) for _ in results.values()) + 1
-    for k in sorted(results.keys()):
-        args.o.write("{:{wnames}} : {:{wresults}} : {}s\n".format(k,
-                                                                  results[k],
-                                                                  elapsed[k].total_seconds(),
-                                                                  wnames=wnames,
-                                                                  wresults=wresults))
+    if not results:
+        ofd.write("\nAll object files up to date\n")
+    else:
+        ofd.write("\nCompiled object files:\n")
+        wnames = max(len(_) for _ in results) + 1
+        wresults = max(len(_) for _ in results.values()) + 1
+        for k in sorted(results.keys()):
+            ofd.write("{:{wnames}} : {:{wresults}} : {}s\n".format(k,
+                                                                   results[k],
+                                                                   elapsed[k].total_seconds(),
+                                                                   wnames=wnames,
+                                                                   wresults=wresults))
 
-    args.o.write("\nSummary:\n")
-    counts = collections.Counter(_ for _ in results.values())
-    total = sum(counts.values())
-    for k in sorted(counts.keys()):
-        c = counts[k]
-        args.o.write("{:{width}}| {} ({:.2%})\n".format(k, c, c / total, width=wresults))
+        ofd.write("\nSummary:\n")
+        counts = collections.Counter(_ for _ in results.values())
+        total = sum(counts.values())
+        for k in sorted(counts.keys()):
+            c = counts[k]
+            ofd.write("{:{width}}| {} ({:.2%})\n".format(k, c, c / total, width=wresults))
 
-    args.o.write("\nLongest:\n")
-    longest = sorted(list(elapsed.items()), key=lambda kv: -kv[1].total_seconds())
-    for i, (k, v) in enumerate(longest):
-        args.o.write("{:{width}}| {}s\n".format(k, v.total_seconds(), width=wnames))
-        if i > 4:
-            break
+        ofd.write("\nLongest:\n")
+        longest = sorted(list(elapsed.items()), key=lambda kv: -kv[1].total_seconds())
+        for i, (k, v) in enumerate(longest):
+            ofd.write("{:{width}}| {}s\n".format(k, v.total_seconds(), width=wnames))
+            if i > 4:
+                break
 
-args.o.write("#" * 80 + "\n")
+    ofd.write("#" * 80 + "\n")

bin/verilator_coverage

@@ -1,10 +1,10 @@
 #!/usr/bin/env perl
 ######################################################################
 #
-# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder
 #
 ######################################################################
 
@@ -52,7 +52,7 @@ if (! GetOptions (
     pod2usage(-exitstatus => 2, -verbose => 0);
 }
 
-# Normal, non gdb
+# Normal, non-gdb
 run(verilator_coverage_bin()
     . " " . join(' ', @Opt_Verilator_Sw));
 
@@ -192,11 +192,12 @@ L<https://verilator.org/guide/latest/exe_verilator_coverage.html>.
 
 The latest version is available from L<https://verilator.org>.
 
-Copyright 2003-2025 by Wilson Snyder. This program is free software; you
+Copyright 2003-2026 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify the Verilator internals under the terms
 of either the GNU Lesser General Public License Version 3 or the Perl
 Artistic License Version 2.0.
 
+SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 =head1 SEE ALSO

bin/verilator_difftree

@@ -110,12 +110,13 @@ It performs a diff between two files, or all files common between two
 directories, ignoring irrelevant pointer differences.
 
 Exit status is 0 if inputs are the same, 1 if different, 2 if trouble.""",
-    epilog="""Copyright 2005-2025 by Wilson Snyder. This program is free software; you
-can redistribute it and/or modify it under the terms of either the GNU
-Lesser General Public License Version 3 or the Perl Artistic License
-Version 2.0.
+    epilog="""This program is free software; you can redistribute it and/or modify it
+under the terms of either the GNU Lesser General Public License Version 3
+or the Perl Artistic License Version 2.0.
 
-SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
+SPDX-FileCopyrightText: 2005-2026 Wilson Snyder
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+""")
 
 parser.add_argument('--debug', action='store_const', const=9, help='enable debug')
 parser.add_argument('--no-lineno',

bin/verilator_gantt

@@ -613,12 +613,13 @@ Verilator_gantt creates a visual representation to help analyze Verilator
 
 For documentation see
 https://verilator.org/guide/latest/exe_verilator_gantt.html""",
-    epilog="""Copyright 2018-2025 by Wilson Snyder. This program is free software; you
-can redistribute it and/or modify it under the terms of either the GNU
-Lesser General Public License Version 3 or the Perl Artistic License
-Version 2.0.
+    epilog="""This program is free software; you can redistribute it and/or modify it
+under the terms of either the GNU Lesser General Public License Version 3
+or the Perl Artistic License Version 2.0.
 
-SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
+SPDX-FileCopyrightText: 2018-2026 Wilson Snyder
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+""")
 
 parser.add_argument('--debug', action='store_true', help='enable debug')
 parser.add_argument('--no-vcd', help='disable creating vcd', action='store_true')

bin/verilator_includer

@@ -2,11 +2,11 @@
 # mypy: disallow-untyped-defs
 # pylint: disable=C0114,C0209
 #
-# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify the Verilator internals under the terms
-# of either the GNU Lesser General Public License Version 3 or the Perl
-# Artistic License Version 2.0.
+# This program is free software; you can redistribute it and/or modify the
+# Verilator internals under the terms of either the GNU Lesser General
+# Public License Version 3 or the Perl Artistic License Version 2.0.
 #
+# SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 ######################################################################
 

bin/verilator_profcfunc

@@ -173,12 +173,13 @@ in each Verilog block.
 
 For documentation see
 https://verilator.org/guide/latest/exe_verilator_profcfunc.html""",
-    epilog="""Copyright 2002-2025 by Wilson Snyder. This program is free software; you
-can redistribute it and/or modify it under the terms of either the GNU
-Lesser General Public License Version 3 or the Perl Artistic License
-Version 2.0.
+    epilog="""This program is free software; you can redistribute it and/or modify it
+under the terms of either the GNU Lesser General Public License Version 3
+or the Perl Artistic License Version 2.0.
 
-SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
+SPDX-FileCopyrightText: 2002-2026 Wilson Snyder
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+""")
 
 parser.add_argument('--debug', action='store_const', const=9, help='enable debug')
 parser.add_argument('filename', help='input gprof output to process')

ci/ci-install.bash

@@ -1,11 +1,7 @@
 #!/usr/bin/env bash
 # DESCRIPTION: Verilator: CI dependency install script
 #
-# Copyright 2020 by Geza Lore. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-#
+# SPDX-FileCopyrightText: 2020 Geza Lore
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ################################################################################
@@ -34,7 +30,7 @@ elif [ "$CI_OS_NAME" = "osx" ]; then
 elif [ "$CI_OS_NAME" = "freebsd" ]; then
   MAKE=gmake
 else
-  fatal "Unknown os: '$CI_OS_NAME'"
+  fatal "Unknown CI_OS_NAME: '$CI_OS_NAME'"
 fi
 
 if [ "$CI_OS_NAME" = "linux" ]; then
@@ -47,7 +43,7 @@ fi
 install-vcddiff() {
   TMP_DIR="$(mktemp -d)"
   git clone https://github.com/veripool/vcddiff "$TMP_DIR"
-  git -C "${TMP_DIR}" checkout dca845020668887fd13498c772939814d9264fd5
+  git -C "${TMP_DIR}" checkout 4db0d84a27e8f148b127e916fc71d650837955c5
   "$MAKE" -C "${TMP_DIR}"
   sudo cp "${TMP_DIR}/vcddiff" /usr/local/bin
 }
@@ -60,28 +56,32 @@ if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then
   if [ "$CI_OS_NAME" = "linux" ]; then
     sudo apt-get update ||
     sudo apt-get update
-    sudo apt-get install ccache help2man libfl-dev ||
-    sudo apt-get install ccache help2man libfl-dev
+    sudo apt-get install --yes ccache help2man libfl-dev ||
+    sudo apt-get install --yes ccache help2man libfl-dev
     if [[ ! "$CI_RUNS_ON" =~ "ubuntu-22.04" ]]; then
       # Some conflict of libunwind verison on 22.04, can live without it for now
-      sudo apt-get install libgoogle-perftools-dev ||
-      sudo apt-get install libgoogle-perftools-dev
+      sudo apt-get install --yes libjemalloc-dev ||
+      sudo apt-get install --yes libjemalloc-dev
     fi
-    if [[ "$CI_RUNS_ON" =~ "ubuntu-20.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]]; then
-      sudo apt-get install libsystemc libsystemc-dev ||
-      sudo apt-get install libsystemc libsystemc-dev
+    if [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-26.04" ]]; then
+      if [[ ! "$CI_RUNS_ON" =~ "-riscv" ]]; then
+        sudo apt-get install --yes libsystemc libsystemc-dev ||
+        sudo apt-get install --yes libsystemc libsystemc-dev
+      fi
     fi
-    if [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]]; then
-      sudo apt-get install bear mold ||
-      sudo apt-get install bear mold
+    if [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-26.04" ]]; then
+      sudo apt-get install --yes bear mold ||
+      sudo apt-get install --yes bear mold
     fi
   elif [ "$CI_OS_NAME" = "osx" ]; then
+    brew update ||
     brew update
+    brew install ccache perl gperftools autoconf bison flex help2man ||
     brew install ccache perl gperftools autoconf bison flex help2man
   elif [ "$CI_OS_NAME" = "freebsd" ]; then
     sudo pkg install -y autoconf bison ccache gmake perl5
   else
-    fatal "Unknown os: '$CI_OS_NAME'"
+    fatal "Unknown CI_OS_NAME: '$CI_OS_NAME'"
   fi
 
   if [ -n "$CCACHE_DIR" ]; then
@@ -96,16 +96,18 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
     sudo apt-get update ||
     sudo apt-get update
     # libfl-dev needed for internal coverage's test runs
-    sudo apt-get install gdb gtkwave lcov libfl-dev ccache jq z3 ||
-    sudo apt-get install gdb gtkwave lcov libfl-dev ccache jq z3
+    sudo apt-get install --yes gdb gtkwave lcov libfl-dev ccache jq z3 ||
+    sudo apt-get install --yes gdb gtkwave lcov libfl-dev ccache jq z3
     # Required for test_regress/t/t_dist_attributes.py
-    if [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]]; then
-      sudo apt-get install python3-clang mold ||
-      sudo apt-get install python3-clang mold
+    if [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-26.04" ]]; then
+      sudo apt-get install --yes python3-clang mold ||
+      sudo apt-get install --yes python3-clang mold
     fi
-    if [[ "$CI_RUNS_ON" =~ "ubuntu-20.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]]; then
-      sudo apt-get install libsystemc-dev ||
-      sudo apt-get install libsystemc-dev
+    if [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-26.04" ]]; then
+      if [[ ! "$CI_RUNS_ON" =~ "-riscv" ]]; then
+        sudo apt-get install --yes libsystemc libsystemc-dev ||
+        sudo apt-get install --yes libsystemc libsystemc-dev
+      fi
     fi
   elif [ "$CI_OS_NAME" = "osx" ]; then
     brew update
@@ -115,7 +117,7 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
     # fst2vcd fails with "Could not open '<input file>', exiting."
     sudo pkg install -y ccache gmake perl5 python3 jq z3
   else
-    fatal "Unknown os: '$CI_OS_NAME'"
+    fatal "Unknown CI_OS_NAME: '$CI_OS_NAME'"
   fi
   # Common installs
   install-vcddiff
@@ -124,5 +126,5 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
 else
   ##############################################################################
   # Unknown build stage
-  fatal "Unknown build stage: '$CI_BUILD_STAGE_NAME'"
+  fatal "Unknown CI_BUILD_STAGE_NAME: '$CI_BUILD_STAGE_NAME'"
 fi

ci/ci-pages-notify.bash

@@ -1,11 +1,7 @@
 #!/usr/bin/env bash
 # DESCRIPTION: Verilator: CI script for 'pages.yml', notifies PRs
 #
-# Copyright 2025 by Geza Lore. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-#
+# SPDX-FileCopyrightText: 2025 Geza Lore
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 # Notify PRs via comment that their coverage reports are available

ci/ci-pages.bash

@@ -1,11 +1,7 @@
 #!/usr/bin/env bash
 # DESCRIPTION: Verilator: CI script for 'pages.yml', builds the GitHub Pages
 #
-# Copyright 2025 by Geza Lore. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-#
+# SPDX-FileCopyrightText: 2025 Geza Lore
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 # This scipt build the content of the GitHub Pages for the repository.

ci/ci-script.bash

@@ -1,11 +1,7 @@
 #!/usr/bin/env bash
 # DESCRIPTION: Verilator: CI main job script
 #
-# Copyright 2020 by Geza Lore. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-#
+# SPDX-FileCopyrightText: 2020 Geza Lore
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ################################################################################
@@ -33,7 +29,7 @@ elif [ "$CI_OS_NAME" = "freebsd" ]; then
   export MAKE=gmake
   NPROC=$(sysctl -n hw.ncpu)
 else
-  fatal "Unknown os: '$CI_OS_NAME'"
+  fatal "Unknown CI_OS_NAME: '$CI_OS_NAME'"
 fi
 NPROC=$(expr $NPROC '+' 1)
 
@@ -94,18 +90,18 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
 
   TEST_REGRESS=test_regress
   if [ "$CI_RELOC" == 1 ]; then
-     # Testing that the installation is relocatable.
-     "$MAKE" install
-     mkdir -p "$RELOC_DIR"
-     mv "$INSTALL_DIR" "$RELOC_DIR/relocated-install"
-     export VERILATOR_ROOT="$RELOC_DIR/relocated-install/share/verilator"
-     TEST_REGRESS="$RELOC_DIR/test_regress"
-     mv test_regress "$TEST_REGRESS"
-     NODIST="$RELOC_DIR/nodist"
-     mv nodist "$NODIST"
-     # Feeling brave?
-     find . -delete
-     ls -la .
+    # Testing that the installation is relocatable.
+    "$MAKE" install
+    mkdir -p "$RELOC_DIR"
+    mv "$INSTALL_DIR" "$RELOC_DIR/relocated-install"
+    export VERILATOR_ROOT="$RELOC_DIR/relocated-install/share/verilator"
+    TEST_REGRESS="$RELOC_DIR/test_regress"
+    mv test_regress "$TEST_REGRESS"
+    NODIST="$RELOC_DIR/nodist"
+    mv nodist "$NODIST"
+    # Feeling brave?
+    find . -delete
+    ls -la .
   fi
 
   # Run the specified test
@@ -196,7 +192,7 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
       "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=9/10
       ;;
     *)
-      fatal "Unknown test: $TESTS"
+      fatal "Unknown TESTS: $TESTS"
       ;;
   esac
 
@@ -208,5 +204,5 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
 else
   ##############################################################################
   # Unknown build stage
-  fatal "Unknown build stage: '$CI_BUILD_STAGE_NAME'"
+  fatal "Unknown CI_BUILD_STAGE_NAME: '$CI_BUILD_STAGE_NAME'"
 fi

ci/ci-win-compile.ps1

@@ -1,10 +1,6 @@
 # DESCRIPTION: Verilator: CI Windows Power Shell - Compile Verilator
 #
-# Copyright 2024 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-#
+# SPDX-FileCopyrightText: 2024 Wilson Snyder
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 ################################################################################
 

ci/ci-win-test.ps1

@@ -1,10 +1,6 @@
 # DESCRIPTION: Verilator: CI Windows Power Shell - Verilate a test
 #
-# Copyright 2024 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-#
+# SPDX-FileCopyrightText: 2024 Wilson Snyder
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 ################################################################################
 

ci/docker/buildenv/Dockerfile

@@ -1,9 +1,9 @@
 # DESCRIPTION: Dockerfile for env to build and fully test Verilator
 #
-# Copyright 2020 by Stefan Wallentowitz. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2020 Stefan Wallentowitz
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 FROM ubuntu:24.04
@@ -37,7 +37,7 @@ RUN apt-get update \
                         libfl2 \
                         libfl-dev \
                         libclang-rt-18-dev \
-                        libgoogle-perftools-dev \
+                        libjemalloc-dev \
                         libsystemc \
                         libsystemc-dev \
                         numactl \

ci/docker/buildenv/README.rst

@@ -1,7 +1,7 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Verilator Build Docker Container:
+.. _verilator build docker container:
 
 Verilator Build Docker Container
 ================================
@@ -9,11 +9,11 @@ Verilator Build Docker Container
 This Verilator Build Docker Container is set up to compile and test a
 Verilator build. It uses the following parameters:
 
--  Source repository (default: https://github.com/verilator/verilator)
+- Source repository (default: https://github.com/verilator/verilator)
 
--  Source revision (default: master)
+- Source revision (default: master)
 
--  Compiler (GCC 13.3.0, clang 18.1.3, default: 13.3.0)
+- Compiler (GCC 13.3.0, clang 18.1.3, default: 13.3.0)
 
 The container is published as ``verilator/verilator-buildenv`` on `docker
 hub
@@ -37,8 +37,9 @@ To change the compiler use the `-e` switch to pass environment variables:
 
    docker run -ti -e CXX=clang++-18 verilator/verilator-buildenv test
 
-The tests, that involve numactl are not working due to security restrictions.
-To run those too, add the CAP_SYS_NICE capability during the start of the container:
+The tests, that involve numactl are not working due to security
+restrictions. To run those too, add the CAP_SYS_NICE capability during the
+start of the container:
 
 ::
 

ci/docker/buildenv/build.sh

@@ -1,10 +1,10 @@
 #!/bin/bash -e
 # DESCRIPTION: Build Verilator (inside container)
 #
-# Copyright 2020 by Stefan Wallentowitz. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2020 Stefan Wallentowitz
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 : "${REPO:=https://github.com/verilator/verilator}"

ci/docker/run/Dockerfile

@@ -1,9 +1,9 @@
 # DESCRIPTION: Dockerfile for image to run Verilator inside
 #
-# Copyright 2020 by Stefan Wallentowitz. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2020 Stefan Wallentowitz
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 FROM ubuntu:24.04
@@ -22,7 +22,7 @@ RUN apt-get update \
                         help2man \
                         libfl2 \
                         libfl-dev \
-                        libgoogle-perftools-dev \
+                        libjemalloc-dev \
                         numactl \
                         perl \
                         perl-doc \

ci/docker/run/README.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 Verilator Executable Docker Container
@@ -11,12 +11,12 @@ easily as a docker image, e.g.:
 
    docker run -ti verilator/verilator:latest --version
 
-This will pull the container from `docker hub
-<https://hub.docker.com/r/verilator/verilator>`_, run the latest Verilator and print
-Verilator's version.
+This will pull the container from `Docker Hub
+<https://hub.docker.com/r/verilator/verilator>`_, run the latest Verilator
+and print Verilator's version.
 
-Containers are automatically built and pushed to docker hub for all released versions, so you may
-easily compare results across versions, e.g.:
+Containers are automatically built and pushed to docker hub for all
+released versions, so you may easily compare results across versions, e.g.:
 
 ::
 
@@ -38,7 +38,7 @@ or
    ./verilator-docker 4.030 --cc test.v
 
 If you prefer not to use ``verilator-docker`` you must give the container
-access to your files as a volume with appropriate user rights.  For example
+access to your files as a volume with appropriate user rights. For example
 to Verilate test.v:
 
 ::
@@ -68,9 +68,9 @@ Internals
 The Dockerfile builds Verilator and removes the tree when completed to
 reduce the image size. The entrypoint is a wrapper script
 (``verilator-wrap.sh``). That script 1. calls Verilator, and 2. copies the
-Verilated runtime files to the ``obj_dir`` or the ``-Mdir``
-respectively. This allows the user to have the files to they may later
-build the C++ output with the matching runtime files. The wrapper also
-patches the Verilated Makefile accordingly.
+Verilated runtime files to the ``obj_dir`` or the ``-Mdir`` respectively.
+This allows the user to have the files to they may later build the C++
+output with the matching runtime files. The wrapper also patches the
+Verilated Makefile accordingly.
 
 A hook is also defined and run by Docker Hub via automated builds.

ci/docker/run/hooks/build

@@ -1,10 +1,10 @@
 #!/bin/bash
 # DESCRIPTION: Docker hub hook to pass SOURCE_COMMIT
 #
-# Copyright 2020 by Stefan Wallentowitz. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2020 Stefan Wallentowitz
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 docker build --build-arg SOURCE_COMMIT=${SOURCE_COMMIT} -f $DOCKERFILE_PATH -t $IMAGE_NAME .

ci/docker/run/hooks/post_push

@@ -1,13 +1,13 @@
 #!/bin/bash
 # DESCRIPTION: Docker hub hook to tag the latest release (stable)
 #
-# Copyright 2020 by Stefan Wallentowitz. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2020 Stefan Wallentowitz
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 if [ "$SOURCE_BRANCH"="stable" ]; then
-    docker tag $IMAGE_NAME $DOCKER_REPO:latest
-    docker push $DOCKER_REPO:latest
+  docker tag $IMAGE_NAME $DOCKER_REPO:latest
+  docker push $DOCKER_REPO:latest
 fi

ci/docker/run/verilator-docker

@@ -1,10 +1,10 @@
 #!/bin/bash
 # DESCRIPTION: Wrap a verilator call to run a docker container
 #
-# Copyright 2020 by Stefan Wallentowitz. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2020 Stefan Wallentowitz
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 docker pull verilator/verilator:$1 >/dev/null

ci/docker/run/verilator-wrap.sh

@@ -2,30 +2,30 @@
 # DESCRIPTION: Wrap a Verilator call and copy vlt includes
 #              (inside docker container)
 #
-# Copyright 2020 by Stefan Wallentowitz. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2020 Stefan Wallentowitz
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 perl /usr/local/bin/verilator "$@"
 status=$?
 if [ $status -ne 0 ]; then
-    exit $status
+  exit $status
 fi
 
 # Check if user set an obj_dir
 obj_dir=$(echo " $@" | grep -oP '\s--Mdir\s*\K\S+')
 if [ "$obj_dir" == "" ]; then
-    obj_dir="obj_dir"
+  obj_dir="obj_dir"
 fi
 
 # If the run was successful: Copy required files to allow build without this container
 if [ -e ${obj_dir} ]; then
-    # Copy files required for the build
-    mkdir -p ${obj_dir}/vlt
-    cp -r /usr/local/share/verilator/bin ${obj_dir}/vlt
-    cp -r /usr/local/share/verilator/include ${obj_dir}/vlt
-    # Point Makefile to that folder
-    sed -i 's/VERILATOR_ROOT = \/usr\/local\/share\/verilator/VERILATOR_ROOT = vlt/g' ${obj_dir}/*.mk
+  # Copy files required for the build
+  mkdir -p ${obj_dir}/vlt
+  cp -r /usr/local/share/verilator/bin ${obj_dir}/vlt
+  cp -r /usr/local/share/verilator/include ${obj_dir}/vlt
+  # Point Makefile to that folder
+  sed -i 's/VERILATOR_ROOT = \/usr\/local\/share\/verilator/VERILATOR_ROOT = vlt/g' ${obj_dir}/*.mk
 fi

configure.ac

@@ -1,8 +1,9 @@
 # DESCRIPTION: Process this file with autoconf to produce a configure script.
 #
-# Copyright 2003-2025 by Wilson Snyder. Verilator is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU Lesser
-# General Public License Version 3 or the Perl Artistic License Version 2.0.
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 # When releasing, also update header of Changes file, and CMakeLists.txt,
@@ -11,7 +12,7 @@
 # Then 'make maintainer-dist'
 #AC_INIT([Verilator],[#.### YYYY-MM-DD])
 #AC_INIT([Verilator],[#.### devel])
-AC_INIT([Verilator],[5.042 2025-11-02],
+AC_INIT([Verilator],[5.047 devel],
         [https://verilator.org],
         [verilator],[https://verilator.org])
 
@@ -63,8 +64,8 @@ AC_ARG_ENABLE([dev-asan],
               [AS_HELP_STRING([--enable-dev-asan],
                               [Enable compiling Verilator with ASAN
                                AddressSanitizer for memory error detection.
-                               This disables tcmalloc.  Does not affect
-                               Verilated models using ASAN.])],
+                               This disables tcmalloc and jemalloc.  Does not
+                               affect Verilated models using ASAN.])],
               [case "${enableval}" in
                 yes) CFG_WITH_DEV_ASAN=yes ;;
                 no)  CFG_WITH_DEV_ASAN=no ;;
@@ -92,6 +93,27 @@ else
   AC_MSG_RESULT($CFG_WITH_TCMALLOC)
 fi
 
+# Flag to enable linking Verilator with jemalloc if available
+AC_MSG_CHECKING(whether to use jemalloc)
+AC_ARG_ENABLE([jemalloc],
+              [AS_HELP_STRING([--enable-jemalloc],
+                              [Use libjemalloc for faster dynamic memory
+                               management in Verilator binary. Preferred over
+                               tcmalloc when both are available
+                               @<:@default=check@:>@])],
+              [case "${enableval}" in
+                yes) CFG_WITH_JEMALLOC=yes ;;
+                no)  CFG_WITH_JEMALLOC=no ;;
+                *)   AC_MSG_ERROR([bad value '${enableval}' for --enable-jemalloc]) ;;
+               esac],
+              [CFG_WITH_JEMALLOC=check;])
+if test "$CFG_WITH_DEV_ASAN" = "yes"; then
+  CFG_WITH_JEMALLOC=no
+  AC_MSG_RESULT("disabled by --enable-dev-asan")
+else
+  AC_MSG_RESULT($CFG_WITH_JEMALLOC)
+fi
+
 # Flag to enable code coverage build with gcov
 AC_MSG_CHECKING(whether to build for gcov code coverage collection)
 AC_ARG_ENABLE([dev-gcov],
@@ -472,9 +494,11 @@ fi
 AC_SUBST(HAVE_DEV_ASAN)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Qunused-arguments)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Wno-shadow)
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Wno-unnecessary-virtual-specifier)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Wno-unused-parameter)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Xclang -fno-pch-timestamp)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-faligned-new)
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-exceptions)
 AC_SUBST(CFG_CXXFLAGS_SRC)
 
 # Flags for compiling Verilator parser always (in addition to above CFG_CXXFLAGS_SRC)
@@ -530,10 +554,12 @@ m4_foreach([cflag],[
         [-Wno-tautological-bitwise-compare],
         [-Wno-tautological-compare],
         [-Wno-uninitialized],
+        [-Wno-unnecessary-virtual-specifier],
         [-Wno-unused-but-set-parameter],
         [-Wno-unused-but-set-variable],
         [-Wno-unused-parameter],
-        [-Wno-unused-variable]],[
+        [-Wno-unused-variable],
+        [-Wno-vla-cxx-extension]],[
     _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_NO_UNUSED,cflag)
     # CMake will test what flags work itself, so pass all flags through to it
     CFG_CXX_FLAGS_CMAKE="$CFG_CXX_FLAGS_CMAKE cflag"
@@ -564,8 +590,10 @@ if test "$CFG_ENABLE_PARTIAL_STATIC" = "yes"; then
   _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_SRC, -static-libstdc++)
   _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_SRC, -Xlinker -gc-sections)
   LTCMALLOC="-Wl,--whole-archive -l:libtcmalloc_minimal.a -Wl,--no-whole-archive"
+  LJEMALLOC="-Wl,--whole-archive -l:libjemalloc.a -Wl,--no-whole-archive"
 else
   LTCMALLOC=-ltcmalloc_minimal
+  LJEMALLOC=-ljemalloc
 fi
 AC_SUBST(CFG_LDFLAGS_SRC)
 AC_SUBST(CFG_LDFLAGS_VERILATED)
@@ -581,11 +609,38 @@ _MY_LDLIBS_CHECK_OPT(CFG_LIBS, -latomic)
 _MY_LDLIBS_CHECK_OPT(CFG_LIBS, -lbcrypt)
 _MY_LDLIBS_CHECK_OPT(CFG_LIBS, -lpsapi)
 
+# Check if jemalloc is available based on --enable-jemalloc
+# jemalloc is preferred over tcmalloc when both are available
+CFG_HAVE_JEMALLOC=no
+_MY_LDLIBS_CHECK_IFELSE(
+  $LJEMALLOC,
+  [if test "$CFG_WITH_JEMALLOC" != "no"; then
+    CFG_LIBS="$LJEMALLOC $CFG_LIBS";
+    CFG_HAVE_JEMALLOC=yes;
+    # If using jemalloc, add some extra options to make the compiler not assume
+    # it is using its own versions of the standard library functions
+    _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-malloc)
+    _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-calloc)
+    _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-realloc)
+    _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-free)
+    AC_DEFINE([HAVE_JEMALLOC],[1],[Defined if have jemalloc])
+   fi],
+  [if test "$CFG_WITH_JEMALLOC" = "yes"; then
+    AC_MSG_ERROR([--enable-jemalloc was given but test for ${LJEMALLOC} failed])
+   fi])
+AC_SUBST(HAVE_JEMALLOC)
+
 # Check if tcmalloc is available based on --enable-tcmalloc
+# Only use tcmalloc if jemalloc was not found/enabled
+if test "$CFG_HAVE_JEMALLOC" = "yes"; then
+  AC_MSG_NOTICE([jemalloc found, skipping tcmalloc check])
+else
+CFG_HAVE_TCMALLOC=no
 _MY_LDLIBS_CHECK_IFELSE(
   $LTCMALLOC,
   [if test "$CFG_WITH_TCMALLOC" != "no"; then
     CFG_LIBS="$LTCMALLOC $CFG_LIBS";
+    CFG_HAVE_TCMALLOC=yes;
     # If using tcmalloc, add some extra options to make the compiler not assume
     # it is using its own versions of the standard library functions
     _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-malloc)
@@ -597,6 +652,7 @@ _MY_LDLIBS_CHECK_IFELSE(
   [if test "$CFG_WITH_TCMALLOC" = "yes"; then
     AC_MSG_ERROR([--enable-tcmalloc was given but test for ${LTCMALLOC} failed])
    fi])
+fi
 AC_SUBST(HAVE_TCMALLOC)
 AC_SUBST(CFG_LIBS)
 

docs/CONTRIBUTING.rst

@@ -1,3 +1,6 @@
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
 Contributing to Verilator
 =========================
 
@@ -23,8 +26,8 @@ Did you find a Verilator bug?
     demonstrating the bug and expected behavior that is not occurring.
 
   - The ideal example works against other simulators, and is in the
-    test_regress/t test format, as described in
-    `Verilator Internals Documentation
+    test_regress/t test format, as described in `Verilator Internals
+    Documentation
     <https://github.com/verilator/verilator/blob/master/docs/internals.rst>`__.
 
 
@@ -38,18 +41,18 @@ Did you write a patch that fixes a Verilator bug?
   <https://github.com/verilator/verilator/pulls>`__.
 
 - See the coding conventions, and other developer information in
-  ``docs/internals.rst`` in the distribution, or as rendered at
-  `Verilator Internals Documentation
+  ``docs/internals.rst`` in the distribution, or as rendered at `Verilator
+  Internals Documentation
   <https://github.com/verilator/verilator/blob/master/docs/internals.rst>`__.
 
-- Verilator uses GitHub Actions to provide continuous integration.  You
-  may want to enable Actions on your GitHub branch to ensure your changes
-  keep the tests passing.
+- Verilator uses GitHub Actions to provide continuous integration. You may
+  want to enable Actions on your GitHub branch to ensure your changes keep
+  the tests passing.
 
-- Your source-code contributions must be certified as open source,
-  under the `Developer Certificate of
-  Origin <https://developercertificate.org/>`__. On your first
-  contribution, you must either:
+- Your source-code contributions must be certified as open source, under
+  the `Developer Certificate of Origin
+  <https://developercertificate.org/>`__. On your first contribution, you
+  must either:
 
   - Have your patch include the addition of your name to `docs/CONTRIBUTORS
     <CONTRIBUTORS>`__ (preferred).
@@ -75,9 +78,9 @@ Did you write a patch that fixes a Verilator bug?
 Do you have questions on Verilator?
 -----------------------------------
 
-- Please see FAQ section and rest of the `Verilator
-  manual <https://verilator.org/verilator_doc.html>`__, or `Verilator
-  manual (PDF) <https://verilator.org/verilator_doc.pdf>`__.
+- Please see FAQ section and rest of the `Verilator manual
+  <https://verilator.org/verilator_doc.html>`__, or `Verilator manual (PDF)
+  <https://verilator.org/verilator_doc.pdf>`__.
 
 - Ask any question in the `Verilator forum
   <https://verilator.org/forum>`__.

docs/CONTRIBUTORS

@@ -12,6 +12,7 @@ Aidan McNay
 Aleksander Kiryk
 Alex Chadwick
 Alex Solomatnikov
+Alex Zhou
 Aliaksei Chapyzhenka
 Ameya Vikram Singh
 Andrea Calabrese
@@ -25,10 +26,12 @@ Anthony Moore
 Arkadiusz Kozdra
 Arthur Rosa
 Artur Bieniek
+AUDIY
 Aylon Chaim Porat
 Bartłomiej Chmiel
 Brian Li
 Cameron Kirk
+Cameron Waite
 Chih-Mao Chen
 Chris Bachhuber
 Chris Randall
@@ -38,7 +41,7 @@ Chuxuan Wang
 Chykon
 Congcong Cai
 Conor McCullough
-Dan Petrisko
+Dan Ruelas-Petrisko
 Daniel Bates
 Danny Oler
 Dave Sargeant
@@ -57,6 +60,7 @@ Driss Hafdi
 Edgar E. Iglesias
 Eric Müller
 Eric Rippey
+Eunseo Song
 Ethan Sifferman
 Eyck Jentzsch
 Fabian Keßler-Schulz
@@ -95,7 +99,9 @@ Iru Cai
 Ivan Vnučec
 Iztok Jeras
 Jake Merdich
+Jakub Michalski
 Jakub Wasilewski
+jalcim
 James Bailey
 James Hanlon
 James Hutchinson
@@ -105,6 +111,8 @@ Jamey Hicks
 Jamie Iles
 Jan Van Winkel
 Jean Berniolles
+Jean-Nicolas Strauss
+Jens Yuechao Liu
 Jeremy Bennett
 Jesse Taube
 Jevin Sweval
@@ -123,15 +131,18 @@ John Wehle
 Jonathan Drolet
 Jonathan Schröter
 Jordan McConnon
+Jose Drowne
 Jose Loyola
 Josep Sans
 Joseph Nwabueze
 Josh Redford
+Julian Carrier
 Julian Daube
 Julie Schwartz
 Julien Margetts
 Justin Thiel
 Kaleb Barrett
+Kamil Danecki
 Kamil Rakoczy
 Kanad Kanhere
 Kefa Chen
@@ -148,6 +159,7 @@ Krzysztof Sychla
 Kuba Ober
 Lan Zongwei
 Larry Doolittle
+Leela Pakanati
 Liam Braun
 Luca Colagrande
 Ludwig Rogiers
@@ -155,6 +167,7 @@ Lukasz Dalek
 Maarten De Braekeleer
 Maciej Sobkowski
 Marcel Chang
+Marco Bartoli
 Marco Widmer
 Mariusz Glebocki
 Markus Krause
@@ -166,6 +179,7 @@ Mateusz Gancarz
 Matt Stroud
 Matthew Ballance
 Max Wipfli
+Maxim Fonarev
 Michael Bedford Taylor
 Michael Bikovitsky
 Michael Killough
@@ -183,6 +197,7 @@ Nathan Graybeal
 Nathan Kohagen
 Nathan Myers
 Nick Brereton
+Nikolay Puzanov
 Nolan Poe
 Oleh Maksymenko
 Patrick Stewart
@@ -190,6 +205,7 @@ Paul Bowen-Huggett
 Paul Swirhun
 Paul Wright
 Pawel Jewstafjew
+Pawel Kojma
 Pawel Sagan
 Pengcheng Xu
 Peter Birch
@@ -205,6 +221,7 @@ Piotr Binkowski
 Qingyao Sun
 Quentin Corradi
 Rafal Kapuscik
+Rahul Behl
 Rasfunk
 Raynard Qiao
 Ricardo Barbedo
@@ -213,6 +230,7 @@ Risto Pejašinović
 Robert Balas
 Robin Heinemann
 Rodrigo Batista de Moraes
+Rowan Goemans
 Rupert Swarbrick
 Ryan Ziegler
 Ryszard Rozak
@@ -222,6 +240,7 @@ Sebastien Van Cauwenberghe
 Sergey Fedorov
 Sergi Granell
 Seth Pellegrino
+Shogo Yamazaki
 Shou-Li Hsu
 Srinivasan Venkataramanan
 Stefan Wallentowitz
@@ -230,6 +249,8 @@ Steven Hugg
 Szymon Gizler
 Sören Tempel
 Teng Huang
+Thomas Aldrian
+Thomas Dybdahl Ahle
 Tim Hutt
 Tim Snyder
 Tobias Jensen
@@ -240,6 +261,7 @@ Tom Manner
 Tomasz Gorochowik
 Topa Topino
 Toru Niina
+Tracy Narine
 Trung Nguyen
 Tudor Timi
 Tymoteusz Blazejczyk
@@ -251,7 +273,9 @@ Varun Koyyalagunta
 Vassilis Papaefstathiou
 Veripool API Bot
 Victor Besyakov
+Vikash Patel
 Vito Gamberini
+Wei-Lun Chiu
 William D. Jones
 Wilson Snyder
 Xi Zhang
@@ -270,8 +294,11 @@ Zhen Yan
 Zhou Shen
 Zhouyi Shen
 Zixi Li
+apocelipes
 dependabot[bot]
 february cozzocrea
 sumpster
+em2machine
+emmettifelts
 Àlex Torregrosa
 Ícaro Lima

docs/Makefile

@@ -5,10 +5,10 @@
 #
 # Code available from: https://verilator.org
 #
-# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################

docs/README.rst

@@ -1,3 +1,6 @@
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
 Verilator Documentation
 =======================
 
@@ -10,8 +13,8 @@ For formatted documentation see:
 - `Verilator installation and package directory structure
   <https://verilator.org/install>`_
 
-- `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_,
-  or `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_
+- `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_, or
+  `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_
 
 - `Subscribe to Verilator announcements
   <https://github.com/verilator/verilator-announce>`_

docs/bin/vl_sphinx_extract

@@ -37,12 +37,13 @@ parser = argparse.ArgumentParser(
     allow_abbrev=False,
     formatter_class=argparse.RawDescriptionHelpFormatter,
     description="""Read a file and extract documentation data.""",
-    epilog=""" Copyright 2021-2025 by Wilson Snyder.  This package is free software;
-you can redistribute it and/or modify it under the terms of either the GNU
-Lesser General Public License Version 3 or the Perl Artistic License
-Version 2.0.
+    epilog="""This program is free software; you can redistribute it and/or modify it
+under the terms of either the GNU Lesser General Public License Version 3
+or the Perl Artistic License Version 2.0.
 
-SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
+SPDX-FileCopyrightText: 2021-2026 Wilson Snyder
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+""")
 
 parser.add_argument('--debug', action='store_const', const=9, help='enable debug')
 parser.add_argument('path', help='path to extract from')

docs/bin/vl_sphinx_fix

@@ -52,12 +52,13 @@ parser = argparse.ArgumentParser(
     allow_abbrev=False,
     formatter_class=argparse.RawDescriptionHelpFormatter,
     description="""Post-process Sphinx HTML.""",
-    epilog=""" Copyright 2021-2025 by Wilson Snyder.  This package is free software;
-you can redistribute it and/or modify it under the terms of either the GNU
-Lesser General Public License Version 3 or the Perl Artistic License
-Version 2.0.
+    epilog="""This program is free software; you can redistribute it and/or modify it
+under the terms of either the GNU Lesser General Public License Version 3
+or the Perl Artistic License Version 2.0.
 
-SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
+SPDX-FileCopyrightText: 2021-2026 Wilson Snyder
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+""")
 
 parser.add_argument('--debug', action='store_const', const=9, help='enable debug')
 parser.add_argument('path', help='path to edit')

docs/gen/ex_ASSIGNEQEXPR_faulty.rst

@@ -1,9 +1,11 @@
 .. comment: generated by t_lint_assigneqexpr_bad
 .. code-block:: sv
    :linenos:
-   :emphasize-lines: 3
+   :emphasize-lines: 3,5
 
      assign d_o =  // Note = not == below
          (
-         c_o = 1  // <--- Warning: ASSIGNEQEXPR
+         e_o = 1  // <--- Warning: ASSIGNEQEXPR
          ) ? 1 : (
+         e_o = 0  // <--- Warning: ASSIGNEQEXPR
+         ) ? b_i : 0;

docs/gen/ex_DIDNOTCONVERGE_msg.rst

@@ -2,4 +2,4 @@
 .. code-block::
 
    -V{t#,#}         'stl' region trigger index 0 is active: @([hybrid] a)
-   %Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after 100 tries
+   %Error-DIDNOTCONVERGE: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after '--converge-limit' of 10000 tries

docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst

@@ -1,4 +1,4 @@
 .. comment: generated by t_lint_didnotconverge_nodbg_bad
 .. code-block::
 
-   %Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after 100 tries
+   %Error-DIDNOTCONVERGE: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after '--converge-limit' of 10000 tries

docs/gen/ex_FUNCTIMECTL_faulty.rst

@@ -4,4 +4,4 @@
    :emphasize-lines: 2
 
      function void calls_timing_ctl;
-       @e; // <--- Bad IEEE 1800-2023 13.4 time-controlling
+       @e;  // <--- Bad IEEE 1800-2023 13.4 time-controlling

docs/gen/ex_PINMISSING_faulty.rst

@@ -4,8 +4,8 @@
    :emphasize-lines: 2
 
    module t;
-      sub sub();  // <--- Warning
-   endmodule
-   module sub
-     (output port);
+     sub sub ();  // <--- Warning
    endmodule
+   module sub (
+       output port
+   );

docs/gen/ex_PINMISSING_msg.rst

@@ -1,4 +1,4 @@
 .. comment: generated by t_lint_pinmissing_bad
 .. code-block::
 
-   %Warning-PINMISSING: example.v:1:8 Instance has missing pin: 'port'
+   %Warning-PINMISSING: example.v:1:7 Instance has missing pin: 'port'

docs/gen/ex_SUPERNFIRST_faulty.rst

@@ -0,0 +1,8 @@
+.. comment: generated by t_class_new_supernfirst_bad
+.. code-block:: sv
+   :linenos:
+   :emphasize-lines: 3
+
+     function new();
+       int x = $random();
+       super.new(build_coverage(x), x);  // <--- BAD, must be first statement

docs/gen/ex_SUPERNFIRST_msg.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_class_new_supernfirst_bad
+.. code-block::
+
+   %Error-SUPERNFIRST: example.v:1:11 'super.new' must be first statement in a 'function new' (IEEE 1800-2023 8.15)

docs/guide/changes.rst

@@ -1,16 +1,17 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ****************
 Revision History
 ****************
 
-.. COMMENT above header must use ### so there is an extra level of headers
+..
+   COMMENT above header must use *** so there is an extra level of headers
    here so the index won't show the huge list of revisions when clicking on
    "Revision History" in the sidebar.
 
 Changes are contained in the :file:`Changes` file of the distribution, and
-also summarized below.  To subscribe to new versions, see `Verilator
+also summarized below. To subscribe to new versions, see `Verilator
 Announcements <https://github.com/verilator/verilator-announce>`_.
 
 .. include:: ../_build/gen/Changes

docs/guide/conf.py

@@ -1,7 +1,7 @@
 # pylint: disable=C0103,C0114,C0116,C0301,E0402,W0622
 #
 # Configuration file for Verilator's Sphinx documentation builder.
-# Copyright 2003-2025 by Wilson Snyder.
+# SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 # This file only contains overridden options. For a full list:
@@ -81,7 +81,7 @@ if 'VERILATOR_SPHINX_EXTENSIONS' in os.environ:
 # directories to ignore when looking for source files.
 # This pattern also affects html_static_path and html_extra_path.
 exclude_patterns = [
-    '_build', 'Thumbs.db', '.DS_Store', 'internals.rst', 'xml.rst', 'gen/ex_*', 'CONTRIBUTING.rst'
+    '_build', 'Thumbs.db', '.DS_Store', 'internals.rst', 'gen/ex_*', 'CONTRIBUTING.rst'
 ]
 
 # Warn about refs

docs/guide/connecting.rst

@@ -1,7 +1,7 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Connecting:
+.. _connecting:
 
 ******************************
 Connecting to Verilated Models
@@ -11,13 +11,13 @@ Structure of the Verilated Model
 ================================
 
 Verilator outputs a :file:`{prefix}.h` header file which defines a class
-named :code:`{prefix}` which represents the generated model the user is
-supposed to instantiate.  This model class defines the interface of the
+named ``{prefix}`` which represents the generated model the user is
+supposed to instantiate. This model class defines the interface of the
 Verilated model.
 
 Verilator will additionally create a :file:`{prefix}.cpp` file, together
-with additional .h and .cpp files for internals.  See the :file:`examples`
-directory in the kit for examples.  See :ref:`Files Read/Written` for
+with additional .h and .cpp files for internals. See the :file:`examples`
+directory in the kit for examples. See :ref:`Files Read/Written` for
 information on all the files Verilator might output.
 
 The output of Verilator will contain a :file:`{prefix}.mk` file that may be
@@ -32,91 +32,89 @@ model:
   equivalents.
 
 * Public top level module instances are exposed as pointers to allow access
-  to :code:`/* verilator public */` items.
+  to ``/* verilator public */`` items.
 
-* The root of the design hierarchy (as in SystemVerilog :code:`$root`) is
-  exposed via the :code:`rootp` member pointer to allow access to model
-  internals, including :code:`/* verilator public_flat */` items.
+* The root of the design hierarchy (as in SystemVerilog ``$root``) is
+  exposed via the ``rootp`` member pointer to allow access to model
+  internals, including ``/* verilator public_flat */`` items.
 
 
-.. _Porting from pre 4.210:
+.. _porting from pre 4.210:
 
 Model interface changes in version 4.210
-------------------------------------------
+----------------------------------------
 
 Starting from version 4.210, the model class is an interface object.
 
 Up until Verilator version 4.204 inclusive, the generated model class was
 also the instance of the top level instance in the design hierarchy (what
-you would refer to with :code:`$root` in SystemVerilog).  This meant that
-all internal variables that were implemented by Verilator in the root scope
-were accessible as members of the model class itself.  Note there were often
-many such variable due to module inlining, including
-:code:`/* verilator public_flat */` items.
+you would refer to with ``$root`` in SystemVerilog). This meant that all
+internal variables that were implemented by Verilator in the root scope
+were accessible as members of the model class itself. Note there were often
+many such variable due to module inlining, including ``/* verilator
+public_flat */`` items.
 
 This means that user code that accesses internal signals in the model
-(likely including :code:`/* verilator public_flat */` signals, as they are
+(likely including ``/* verilator public_flat */`` signals, as they are
 often inlined into the root scope) will need to be updated as follows:
 
 * No change required for accessing top level IO signals. These are directly
   accessible in the model class via references.
 
-* No change required for accessing :code:`/* verilator public */` items.
-  These are directly accessible via sub-module pointers in the model class.
+* No change required for accessing ``/* verilator public */`` items. These
+  are directly accessible via sub-module pointers in the model class.
 
 * Accessing any other internal members, including
-  :code:`/* verilator public_flat */` items requires the following changes:
+  ``/* verilator public_flat */`` items requires the following changes:
 
   * Additionally include :file:`{prefix}___024root.h`. This header defines
-    type of the :code:`rootp` pointer within the model class. Note the
-    :code:`__024` substring is the Verilator escape sequence for the
-    :code:`$` character, i.e.: :code:`rootp` points to the Verilated
-    SystemVerilog :code:`$root` scope.
+    type of the ``rootp`` pointer within the model class. Note the
+    ``__024`` substring is the Verilator escape sequence for the ``$``
+    character, i.e.: ``rootp`` points to the Verilated SystemVerilog
+    ``$root`` scope.
 
-  * Replace :code:`modelp->internal->member` references with
-    :code:`modelp->rootp->internal->member` references, which
-    contain one additional indirection via the :code:`rootp` pointer.
+  * Replace ``modelp->internal->member`` references with
+    ``modelp->rootp->internal->member`` references, which contain one
+    additional indirection via the ``rootp`` pointer.
 
 
-.. _Connecting to C++:
+.. _connecting to c++:
 
 Connecting to C++
 =================
 
-In C++ output mode (:vlopt:`--cc`), the Verilator generated model class is a
-simple C++ class.  The user must write a C++ wrapper and main loop for the
+In C++ output mode (:vlopt:`--cc`), the Verilator generated model class is
+a simple C++ class. The user must write a C++ wrapper and main loop for the
 simulation, which instantiates the model class, and link with the Verilated
 model.
 
 Refer to ``examples/make_tracing_c`` in the distribution for a detailed
 commented example.
 
-Top level IO signals are read and written as members of the model.  You
-call the model's :code:`eval()` method to evaluate the model.  When the
-simulation is complete call the model's :code:`final()` method to execute
-any SystemVerilog final blocks, and complete any assertions. If using
-:vlopt:`--timing`, there are two additional functions for checking if
-there are any events pending in the simulation due to delays, and for
-retrieving the simulation time of the next delayed event. See
-:ref:`Evaluation Loop`.
-
+Top level IO signals are read and written as members of the model. You call
+the model's ``eval()`` method to evaluate the model. When the simulation is
+complete call the model's ``final()`` method to execute any SystemVerilog
+final blocks, and complete any assertions. If using :vlopt:`--timing`,
+there are two additional functions for checking if there are any events
+pending in the simulation due to delays, and for retrieving the simulation
+time of the next delayed event. See :ref:`Evaluation Loop`.
 
 
 Connecting to SystemC
 =====================
 
 In SystemC output mode (:vlopt:`--sc`), the Verilator generated model class
-is a SystemC SC_MODULE.  This module will attach directly into a SystemC
+is a SystemC SC_MODULE. This module will attach directly into a SystemC
 netlist as an instantiation.
 
 The SC_MODULE gets the same pinout as the Verilog module, with the
-following type conversions: Pins of a single bit become bool.  Pins 2-32
-bits wide become uint32_t's.  Pins 33-64 bits wide become sc_bv's or
-uint64_t's depending on the :vlopt:`--no-pins64` option.  Wider pins
-become sc_bv's.  (Uints simulate the fastest so are used where possible.)
+following type conversions: Pins of a single bit become bool. Pins 2-32
+bits wide become uint32_t's. Pins 33-64 bits wide become sc_bv's or
+uint64_t's depending on the :vlopt:`--no-pins64` option. Wider pins become
+sc_bv's. (Uints simulate the fastest so are used where possible.)
 
 Model internals, including lower level sub-modules are not pure SystemC
-code.  This is a feature, as using the SystemC pin interconnect scheme
+code. This is a feature, as using the SystemC pin interconnect scheme
 everywhere would reduce performance by an order of magnitude.
 
 
@@ -124,41 +122,42 @@ Verilated API
 =============
 
 The API to a Verilated model is the C++ headers in the include/ directory
-in the distribution.  These headers use Doxygen comments, `///` and `//<`,
+in the distribution. These headers use Doxygen comments, `///` and `//<`,
 to indicate and document those functions that are part of the Verilated
 public API.
 
 Process-Level Clone APIs
---------------------------
+------------------------
 
-Modern operating systems support process-level clone (a.k.a copying, forking)
-with system call interfaces in C/C++, e.g., :code:`fork()` in Linux.
+Modern operating systems support process-level clone (a.k.a copying,
+forking) with system call interfaces in C/C++, e.g., ``fork()`` in Linux.
 
 However, after cloning a parent process, some resources cannot be inherited
-in the child process. For example, in POSIX systems, when you fork a process,
-the child process inherits all the memory of the parent process. However,
-only the thread that called fork is replicated in the child process. Other
-threads are not.
+in the child process. For example, in POSIX systems, when you fork a
+process, the child process inherits all the memory of the parent process.
+However, only the thread that called fork is replicated in the child
+process. Other threads are not.
 
-Therefore, to support the process-level clone mechanisms, Verilator supports
-:code:`prepareClone()` and :code:`atClone()` APIs to allow the user to manually
-re-construct the model in the child process. The two APIs handle all necessary
-resources required for releasing and re-initializing before and after cloning.
+Therefore, to support the process-level clone mechanisms, Verilator
+supports ``prepareClone()`` and ``atClone()`` APIs to allow the user to
+manually re-construct the model in the child process. The two APIs handle
+all necessary resources required for releasing and re-initializing before
+and after cloning.
 
-The two APIs are supported in the verilated models. Here is an example of usage
-with Linux :code:`fork()` and :code:`pthread_atfork` APIs:
+The two APIs are supported in the verilated models. Here is an example of
+usage with Linux ``fork()`` and ``pthread_atfork`` APIs:
 
 .. code-block:: C++
 
-    // static function pointers to fit pthread_atfork
-    static auto prepareClone = [](){ topp->prepareClone(); };
-    static auto atClone = [](){ topp->atClone(); };
+   // static function pointers to fit pthread_atfork
+   static auto prepareClone = [](){ topp->prepareClone(); };
+   static auto atClone = [](){ topp->atClone(); };
 
-    // in main function, register the handlers:
-    pthread_atfork(prepareClone, atClone, atClone);
+   // in main function, register the handlers:
+   pthread_atfork(prepareClone, atClone, atClone);
 
 For better flexibility, you can also manually call the handlers before and
-after :code:`fork()`.
+after ``fork()``.
 
 With the process-level clone APIs, users can create process-level snapshots
 for the verilated models. While the Verilator save/restore option provides
@@ -170,7 +169,7 @@ Direct Programming Interface (DPI)
 ==================================
 
 Verilator supports SystemVerilog Direct Programming Interface import and
-export statements.  Only the SystemVerilog form ("DPI-C") is supported, not
+export statements. Only the SystemVerilog form ("DPI-C") is supported, not
 the original Synopsys-only DPI.
 
 DPI Example
@@ -181,76 +180,76 @@ Verilog, put in our.v:
 
 .. code-block::
 
-    import "DPI-C" function int add (input int a, input int b);
+   import "DPI-C" function int add (input int a, input int b);
 
-    initial begin
-      $display("%x + %x = %x", 1, 2, add(1,2));
-    endtask
+   initial begin
+     $display("%x + %x = %x", 1, 2, add(1,2));
+   endtask
 
 Then after Verilating, Verilator will create a file Vour__Dpi.h with the
 prototype to call this function:
 
 .. code-block:: C++
 
-     extern int add(int a, int b);
+   extern int add(int a, int b);
 
 From the sc_main.cpp file (or another .cpp file passed to the Verilator
 command line, or the link), you'd then:
 
 .. code-block:: C++
 
-     #include "svdpi.h"
-     #include "Vour__Dpi.h"
-     int add(int a, int b) { return a+b; }
+   #include "svdpi.h"
+   #include "Vour__Dpi.h"
+   int add(int a, int b) { return a+b; }
 
 
 DPI System Task/Functions
 -------------------------
 
 Verilator extends the DPI format to allow using the same scheme to
-efficiently add system functions.  Use a dollar-sign prefixed system
+efficiently add system functions. Use a dollar-sign prefixed system
 function name for the import, but note it must be escaped.
 
 .. code-block:: sv
 
-    export "DPI-C" function integer \$myRand;
+   export "DPI-C" function integer \$myRand;
 
-    initial $display("myRand=%d", $myRand());
+   initial $display("myRand=%d", $myRand());
 
 Going the other direction, you can export Verilog tasks so they can be
 called from C++:
 
 .. code-block:: sv
 
-    export "DPI-C" task publicSetBool;
+   export "DPI-C" task publicSetBool;
 
-    task publicSetBool;
-      input bit in_bool;
-      var_bool = in_bool;
-    endtask
+   task publicSetBool;
+     input bit in_bool;
+     var_bool = in_bool;
+   endtask
 
 Then after Verilating, Verilator will create a file Vour__Dpi.h with the
 prototype to call this function:
 
 .. code-block:: C++
 
-     extern void publicSetBool(svBit in_bool);
+   extern void publicSetBool(svBit in_bool);
 
 From the sc_main.cpp file, you'd then:
 
 .. code-block:: C++
 
-     #include "Vour__Dpi.h"
-     publicSetBool(value);
+   #include "Vour__Dpi.h"
+   publicSetBool(value);
 
-Or, alternatively, call the function under the design class.  This isn't
-DPI compatible but is easier to read and better supports multiple designs.
+Or, alternatively, call the function under the design class. This isn't DPI
+compatible but is easier to read and better supports multiple designs.
 
 .. code-block:: C++
 
-     #include "Vour__Dpi.h"
-     Vour::publicSetBool(value);
-     // or top->publicSetBool(value);
+   #include "Vour__Dpi.h"
+   Vour::publicSetBool(value);
+   // or top->publicSetBool(value);
 
 Note that if the DPI task or function accesses any register or net within
 the RTL, it will require a scope to be set. This can be done using the
@@ -263,11 +262,11 @@ with respect to that top level module, then the scope could be set with
 
 .. code-block:: C++
 
-     #include "svdpi.h"
-     ...
-     const svScope scope = svGetScopeFromName("TOP.dut");
-     assert(scope);  // Check for nullptr if scope not found
-     svSetScope(scope);
+   #include "svdpi.h"
+   ...
+   const svScope scope = svGetScopeFromName("TOP.dut");
+   assert(scope);  // Check for nullptr if scope not found
+   svSetScope(scope);
 
 (Remember that Verilator adds a "TOP" to the top of the module hierarchy.)
 
@@ -282,24 +281,24 @@ DPI Imports that access signals
 
 If a DPI import accesses a signal through the VPI Verilator will not be
 able to know what variables are accessed and may schedule the code
-inappropriately.  Ideally pass the values as inputs/outputs so the VPI is
-not required.  Alternatively a workaround is to use a non-inlined task as a
+inappropriately. Ideally pass the values as inputs/outputs so the VPI is
+not required. Alternatively a workaround is to use a non-inlined task as a
 wrapper:
 
 .. code-block::
 
-     logic din;
+   logic din;
 
-     // This DPI function will read "din"
-     import "DPI-C" context function void dpi_that_accesses_din();
+   // This DPI function will read "din"
+   import "DPI-C" context function void dpi_that_accesses_din();
 
-     always @(...)
-       dpi_din_args(din);
+   always @(...)
+     dpi_din_args(din);
 
-     task dpi_din_args(input din);
-       // verilator no_inline_task
-       dpi_that_accesses_din();
-     endtask
+   task dpi_din_args(input din);
+     // verilator no_inline_task
+     dpi_that_accesses_din();
+   endtask
 
 
 DPI Display Functions
@@ -309,8 +308,8 @@ Verilator allows writing $display like functions using this syntax:
 
 .. code-block::
 
-    import "DPI-C" function void
-          \$my_display(input string formatted /*verilator sformat*/ );
+   import "DPI-C" function void
+     \$my_display(input string formatted /*verilator sformat*/ );
 
 The :option:`/*verilator&32;sformat*/` metacomment indicates that this
 function accepts a $display like format specifier followed by any number of
@@ -320,14 +319,14 @@ arguments to satisfy the format.
 DPI Context Functions
 ---------------------
 
-Verilator supports IEEE DPI Context Functions.  Context imports pass the
+Verilator supports IEEE DPI Context Functions. Context imports pass the
 simulator context, including calling scope name, and filename and line
-number to the C code.  For example, in Verilog:
+number to the C code. For example, in Verilog:
 
 .. code-block::
 
-    import "DPI-C" context function int dpic_line();
-    initial $display("This is line %d, again, line %d\n", `line, dpic_line());
+   import "DPI-C" context function int dpic_line();
+   initial $display("This is line %d, again, line %d\n", `line, dpic_line());
 
 This will call C++ code which may then use the svGet\* functions to read
 information, in this case the line number of the Verilog statement that
@@ -335,22 +334,22 @@ invoked the dpic_line function:
 
 .. code-block:: C++
 
-    int dpic_line() {
-        // Get a scope:  svScope scope = svGetScope();
+   int dpic_line() {
+       // Get a scope:  svScope scope = svGetScope();
 
-        const char* scopenamep = svGetNameFromScope(scope);
-        assert(scopenamep);
+       const char* scopenamep = svGetNameFromScope(scope);
+       assert(scopenamep);
 
-        const char* filenamep = "";
-        int lineno = 0;
-        if (svGetCallerInfo(&filenamep, &lineno)) {
-            printf("dpic_line called from scope %s on line %d\n",
-               scopenamep, lineno);
-            return lineno;
-        } else {
-            return 0;
-        }
-    }
+       const char* filenamep = "";
+       int lineno = 0;
+       if (svGetCallerInfo(&filenamep, &lineno)) {
+           printf("dpic_line called from scope %s on line %d\n",
+              scopenamep, lineno);
+           return lineno;
+       } else {
+           return 0;
+       }
+   }
 
 See the IEEE Standard for more information.
 
@@ -359,13 +358,12 @@ DPI Header Isolation
 --------------------
 
 Verilator places the IEEE standard header files such as svdpi.h into a
-separate include directory, vltstd (VeriLaTor STandarD).  When compiling
+separate include directory, vltstd (VeriLaTor STandarD). When compiling
 most applications $VERILATOR_ROOT/include/vltstd would be in the include
-path along with the normal $VERILATOR_ROOT/include.  However, when
-compiling Verilated models into other simulators which have their own
-svdpi.h and similar standard files with different contents, the vltstd
-directory should not be included to prevent picking up incompatible
-definitions.
+path along with the normal $VERILATOR_ROOT/include. However, when compiling
+Verilated models into other simulators which have their own svdpi.h and
+similar standard files with different contents, the vltstd directory should
+not be included to prevent picking up incompatible definitions.
 
 
 Public Functions
@@ -378,24 +376,23 @@ are slightly faster, but less compatible.
 Verification Procedural Interface (VPI)
 =======================================
 
-Verilator supports a limited subset of the VPI.  This subset allows
+Verilator supports a limited subset of the VPI. This subset allows
 inspection, examination, value change callbacks, and depositing of values
 to public signals only.
 
 VPI is enabled with the Verilator :vlopt:`--vpi` option.
 
 To access signals via the VPI, Verilator must be told exactly which signals
-are to be accessed.  This is done using the Verilator public pragmas
+are to be accessed. This is done using the Verilator public pragmas
 documented below.
 
 Verilator has an important difference from an event based simulator; signal
 values that are changed by the VPI will not immediately propagate their
-values, instead the top level header file's :code:`eval()` method must be
-called.  Normally this would be part of the normal evaluation (i.e. the
-next clock edge), not as part of the value change.  This makes the
-performance of VPI routines extremely fast compared to event based
-simulators, but can confuse some test-benches that expect immediate
-propagation.
+values, instead the top level header file's ``eval()`` method must be
+called. Normally this would be part of the normal evaluation (i.e. the next
+clock edge), not as part of the value change. This makes the performance of
+VPI routines extremely fast compared to event based simulators, but can
+confuse some test-benches that expect immediate propagation.
 
 Note the VPI by its specified implementation will always be much slower
 than accessing the Verilator values by direct reference
@@ -405,132 +402,131 @@ while the direct references are evaluated by the compiler and result in
 only a couple of instructions.
 
 For signal callbacks to work the main loop of the program must call
-:code:`VerilatedVpi::callValueCbs()`.
+``VerilatedVpi::callValueCbs()``.
 
-Verilator also tracks when the model state has been modified via the VPI with
-an :code:`evalNeeded` flag.  This flag can be checked with :code:`VerilatedVpi::evalNeeded()`
-and it can be cleared with :code:`VerilatedVpi::clearEvalNeeded()`.  Used together
-it is possible to skip :code:`eval()` calls if no model state has been changed
-since the last :code:`eval()`.
+Verilator also tracks when the model state has been modified via the VPI
+with an ``evalNeeded`` flag. This flag can be checked with
+``VerilatedVpi::evalNeeded()`` and it can be cleared with
+``VerilatedVpi::clearEvalNeeded()``. Used together it is possible to skip
+``eval()`` calls if no model state has been changed since the last
+``eval()``.
 
-Any data written via :code:`vpi_put_value` with :code:`vpiInertialDelay` will
-be deferred for later.  These delayed values can be flushed to the model with
-:code:`VerilatedVpi::doInertialPuts()`.
+Any data written via ``vpi_put_value`` with ``vpiInertialDelay`` will be
+deferred for later. These delayed values can be flushed to the model with
+``VerilatedVpi::doInertialPuts()``.
 
 
-.. _VPI Example:
+.. _vpi example:
 
 VPI Example
 -----------
 
 In the below example, we have readme marked read-only, and writeme marked
-read-write which if written from outside the model will have the same semantics
-as if it was a top level input.
+read-write which if written from outside the model will have the same
+semantics as if it was a top level input.
 
 .. code-block:: bash
 
-     cat >our.v <<'EOF'
-       module our #(
-          parameter WIDTH /*verilator public_flat_rd*/ = 32
-       ) (input clk);
-          reg [WIDTH-1:0] readme   /*verilator public_flat_rd*/;
-          reg [WIDTH-1:0] writeme  /*verilator public_flat_rw*/;
-          initial $finish;
-       endmodule
-     EOF
+   cat >our.v <<'EOF'
+     module our #(
+        parameter WIDTH /*verilator public_flat_rd*/ = 32
+     ) (input clk);
+       reg [WIDTH-1:0] readme   /*verilator public_flat_rd*/;
+       reg [WIDTH-1:0] writeme  /*verilator public_flat_rw*/;
+       initial $finish;
+     endmodule
+   EOF
 
 There are many online tutorials and books on the VPI, but an example that
 accesses the above signal "readme" would be:
 
 .. code-block:: bash
 
-     cat >sim_main.cpp <<'EOF'
-       #include "Vour.h"
-       #include "verilated.h"
-       #include "verilated_vpi.h"  // Required to get definitions
+   cat >sim_main.cpp <<'EOF'
+     #include "Vour.h"
+     #include "verilated.h"
+     #include "verilated_vpi.h"  // Required to get definitions
 
-       uint64_t main_time = 0;   // See comments in first example
-       double sc_time_stamp() { return main_time; }
+     uint64_t main_time = 0;   // See comments in first example
+     double sc_time_stamp() { return main_time; }
 
-       void read_and_check() {
-           vpiHandle vh1 = vpi_handle_by_name((PLI_BYTE8*)"TOP.our.readme", NULL);
-           if (!vh1) vl_fatal(__FILE__, __LINE__, "sim_main", "No handle found");
-           const char* name = vpi_get_str(vpiName, vh1);
-           const char* type = vpi_get_str(vpiType, vh1);
-           const int size = vpi_get(vpiSize, vh1);
-           printf("register name: %s, type: %s, size: %d\n", name, type, size);  // Prints "register name: readme, type: vpiReg, size: 32"
+     void read_and_check() {
+         vpiHandle vh1 = vpi_handle_by_name((PLI_BYTE8*)"TOP.our.readme", NULL);
+         if (!vh1) vl_fatal(__FILE__, __LINE__, "sim_main", "No handle found");
+         const char* name = vpi_get_str(vpiName, vh1);
+         const char* type = vpi_get_str(vpiType, vh1);
+         const int size = vpi_get(vpiSize, vh1);
+         printf("register name: %s, type: %s, size: %d\n", name, type, size);  // Prints "register name: readme, type: vpiReg, size: 32"
 
-           s_vpi_value v;
-           v.format = vpiIntVal;
-           vpi_get_value(vh1, &v);
-           printf("Value of %s: %d\n", name, v.value.integer);  // Prints "Value of readme: 0"
-       }
+         s_vpi_value v;
+         v.format = vpiIntVal;
+         vpi_get_value(vh1, &v);
+         printf("Value of %s: %d\n", name, v.value.integer);  // Prints "Value of readme: 0"
+     }
 
-       int main(int argc, char** argv) {
-           Verilated::commandArgs(argc, argv);
-           const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
-           const std::unique_ptr<Vour> top{new Vour{contextp.get()}};
+     int main(int argc, char** argv) {
+         Verilated::commandArgs(argc, argv);
+         const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+         const std::unique_ptr<Vour> top{new Vour{contextp.get()}};
 
-           contextp->internalsDump();  // See scopes to help debug
-           while (!contextp->gotFinish()) {
-               top->eval();
-               VerilatedVpi::callValueCbs();  // For signal callbacks
-               read_and_check();
-           }
-           return 0;
-       }
-     EOF
+         contextp->internalsDump();  // See scopes to help debug
+         while (!contextp->gotFinish()) {
+             top->eval();
+             VerilatedVpi::callValueCbs();  // For signal callbacks
+             read_and_check();
+         }
+         return 0;
+     }
+   EOF
 
 
-.. _Evaluation Loop:
+.. _evaluation loop:
 
 Wrappers and Model Evaluation Loop
 ==================================
 
 When using SystemC, evaluation of the Verilated model is managed by the
-SystemC kernel, and for the most part can be ignored.  When using C++, the
-user must call :code:`eval()`, or :code:`eval_step()` and
-:code:`eval_end_step()`.
+SystemC kernel, and for the most part can be ignored. When using C++, the
+user must call ``eval()``, or ``eval_step()`` and ``eval_end_step()``.
 
 1. When there is a single design instantiated at the C++ level that needs
-to evaluate within a given context, call :code:`designp->eval()`.
+to evaluate within a given context, call ``designp->eval()``.
 
 2. When there are multiple designs instantiated at the C++ level that need
-to evaluate within a context, call :code:`first_designp->eval_step()` then
-:code:`->eval_step()` on all other designs.  Then call
-:code:`->eval_end_step()` on the first design then all other designs.  If
-there is only a single design, you would call :code:`eval_step()` then
-:code:`eval_end_step()`; in fact :code:`eval()` described above is just a
-wrapper which calls these two functions.
+to evaluate within a context, call ``first_designp->eval_step()`` then
+``->eval_step()`` on all other designs. Then call ``->eval_end_step()`` on
+the first design then all other designs. If there is only a single design,
+you would call ``eval_step()`` then ``eval_end_step()``; in fact ``eval()``
+described above is just a wrapper which calls these two functions.
 
 3. If using delays and :vlopt:`--timing`, there are two additional methods
 the user should call:
 
-   * :code:`designp->eventsPending()`, which returns :code:`true` if there are
-     any delayed events pending,
-   * :code:`designp->nextTimeSlot()`, which returns the simulation time of the
+   * ``designp->eventsPending()``, which returns ``true`` if there are any
+     delayed events pending,
+   * ``designp->nextTimeSlot()``, which returns the simulation time of the
      next delayed event. This method can only be called if
-     :code:`designp->eventsPending()` returned :code:`true`.
+     ``designp->eventsPending()`` returned ``true``.
 
-Call :code:`eventsPending()` to check if you should continue with the
-simulation, and then :code:`nextTimeSlot()` to move simulation time forward.
-:vlopt:`--main` can be used with :vlopt:`--timing` to generate a basic example
-of a timing-enabled eval loop.
+Call ``eventsPending()`` to check if you should continue with the
+simulation, and then ``nextTimeSlot()`` to move simulation time forward.
+:vlopt:`--main` can be used with :vlopt:`--timing` to generate a basic
+example of a timing-enabled eval loop.
 
-When :code:`eval()` (or :code:`eval_step()`) is called Verilator looks for
-changes in clock signals and evaluates related sequential always blocks,
-such as computing always_ff @ (posedge...) outputs. With :vlopt:`--timing`, it
+When ``eval()`` (or ``eval_step()``) is called Verilator looks for changes
+in clock signals and evaluates related sequential always blocks, such as
+computing always_ff @ (posedge...) outputs. With :vlopt:`--timing`, it
 resumes any delayed processes awaiting the current simulation time. Then
 Verilator evaluates combinational logic.
 
 Note combinatorial logic is not computed before sequential always blocks
 are computed (for speed reasons). Therefore it is best to set any non-clock
-inputs up with a separate :code:`eval()` call before changing clocks.
+inputs up with a separate ``eval()`` call before changing clocks.
 
 Alternatively, if all always_ff statements use only the posedge of clocks,
 or all inputs go directly to always_ff statements, as is typical, then you
 can change non-clock inputs on the negative edge of the input clock, which
-will be faster as there will be fewer :code:`eval()` calls.
+will be faster as there will be fewer ``eval()`` calls.
 
 For more information on evaluation, see :file:`docs/internals.rst` in the
 distribution.
@@ -540,18 +536,18 @@ Verilated and VerilatedContext
 ==============================
 
 Multiple C++ Verilated models may be part of the same simulation context,
-that is share a VPI interface, sense of time, and common settings.  This
+that is share a VPI interface, sense of time, and common settings. This
 common simulation context information is stored in a ``VerilatedContext``
-structure.  If a ``VerilatedContext`` is not created prior to creating a
-model, a default global one is created automatically.  SystemC requires
+structure. If a ``VerilatedContext`` is not created prior to creating a
+model, a default global one is created automatically. SystemC requires
 using only the single, default VerilatedContext.
 
 The ``Verilated::`` methods, including the ``Verilated::commandArgs`` call
 shown above, call VerilatedContext methods using the default global
-VerilatedContext.  (Technically they operate on the last one used by a
-given thread.)  If you are using multiple simulation contexts you should
-not use the Verilated:: methods, and instead always use VerilatedContext
-methods called on the appropriate VerilatedContext object.
+VerilatedContext. (Technically they operate on the last one used by a given
+thread.) If you are using multiple simulation contexts you should not use
+the Verilated:: methods, and instead always use VerilatedContext methods
+called on the appropriate VerilatedContext object.
 
 For methods available under Verilated and VerilatedContext see
 :file:`include/verilated.h` in the distribution.

docs/guide/contributing.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *******************************
@@ -19,50 +19,50 @@ Reporting Bugs
 
 First, check the :ref:`Language Limitations` section.
 
-Next, try the :vlopt:`--debug` option.  This will enable additional
-internal assertions, and may help identify the problem.
+Next, try the :vlopt:`--debug` option. This will enable additional internal
+assertions, and may help identify the problem.
 
 Finally, reduce your code to the smallest possible routine that exhibits
-the bug (see: :ref:`Minimizing bug-inducing code`).  Even better, create
-a test in the :file:`test_regress/t` directory, as follows:
+the bug (see: :ref:`Minimizing bug-inducing code`). Even better, create a
+test in the :file:`test_regress/t` directory, as follows:
 
 .. code-block:: bash
 
-       cd test_regress
-       cp -p t/t_EXAMPLE.py t/t_BUG.py
-       cp -p t/t_EXAMPLE.v t/t_BUG.v
+   cd test_regress
+   cp -p t/t_EXAMPLE.py t/t_BUG.py
+   cp -p t/t_EXAMPLE.v t/t_BUG.v
 
 There are many hints on how to write a good test in the
 :file:`test_regress/driver.py` documentation which can be seen by running:
 
 .. code-block:: bash
 
-       cd $VERILATOR_ROOT  # Need the original distribution kit
-       test_regress/driver.py --help
+   cd $VERILATOR_ROOT  # Need the original distribution kit
+   test_regress/driver.py --help
 
 Edit :file:`t/t_BUG.py` to suit your example; you can do anything you want
 in the Verilog code there; just make sure it retains the single clk input
-and no outputs.  Now, the following should fail:
+and no outputs. Now, the following should fail:
 
 .. code-block:: bash
 
-       cd $VERILATOR_ROOT  # Need the original distribution kit
-       cd test_regress
-       t/t_BUG.py  # Run on Verilator
-       t/t_BUG.py --debug # Run on Verilator, passing --debug to Verilator
-       t/t_BUG.py --vcs  # Run on VCS simulator
-       t/t_BUG.py --nc|--iv|--ghdl  # Likewise on other simulators
+   cd $VERILATOR_ROOT  # Need the original distribution kit
+   cd test_regress
+   t/t_BUG.py  # Run on Verilator
+   t/t_BUG.py --debug # Run on Verilator, passing --debug to Verilator
+   t/t_BUG.py --vcs  # Run on VCS simulator
+   t/t_BUG.py --nc|--iv|--ghdl  # Likewise on other simulators
 
 The test driver accepts a number of options, many of which mirror the main
 Verilator options. For example the previous test could have been run with
-debugging enabled.  The full set of test options can be seen by running
+debugging enabled. The full set of test options can be seen by running
 :command:`driver.py --help` as shown above.
 
 Finally, report the bug at `Verilator Issues
-<https://verilator.org/issues>`_.  The bug will become publicly visible; if
+<https://verilator.org/issues>`_. The bug will become publicly visible; if
 this is unacceptable, mail the bug report to ``[email protected]``.
 
-.. _Minimizing bug-inducing code:
+.. _minimizing bug-inducing code:
 
 Minimizing bug-inducing code
 ============================
@@ -73,12 +73,12 @@ caused by a complex interaction of many parts of the design, and it is not
 clear which parts are necessary to reproduce the bug. In these cases, an
 Open Source tool called `sv-bugpoint
 <https://github.com/antmicro/sv-bugpoint>`_ can be used to automatically
-reduce a SystemVerilog design to the smallest possible reproducer.
-It can be used to automatically reduce a design with hundreds of thousands of
+reduce a SystemVerilog design to the smallest possible reproducer. It can
+be used to automatically reduce a design with hundreds of thousands of
 lines to a minimal test case while preserving the bug-inducing behavior.
 
 With :vlopt:`--debug` or :vlopt:`--dump-inputs`, Verilator will write a
-*{prefix}*\ __inputs\ .vpp file which has all of the individual input files
+*{prefix}*\ __inputs.vpp file which has all of the individual input files
 combined and pre-processed, this is often useful as the input design into
 `sv-bugpoint`.
 
@@ -88,4 +88,5 @@ information on how to use `sv-bugpoint`.
 
 .. Contributing
 .. ============
+
 .. include:: ../CONTRIBUTING.rst

docs/guide/contributors.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ************************
@@ -28,10 +28,11 @@ Alliance <https://chipsalliance.org>`_, and `Antmicro Ltd
 
 Previous major corporate sponsors of Verilator, by providing significant
 contributions of time or funds include: Antmicro Ltd., Atmel Corporation,
-Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd., Hicamp
-Systems, Intel Corporation, Marvell Inc., Mindspeed Technologies Inc.,
-MicroTune Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus
-Networks Inc., SiCortex Inc, Shunyao CAD, and Western Digital Inc.
+Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd., Fractile
+Ltd., Hicamp Systems, Intel Corporation, Marvell Inc., Mindspeed Technologies
+Inc., MicroTune Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus
+Networks Inc., SiCortex Inc, Shunyao CAD, Tenstorrent USA, Inc. and Western
+Digital Inc.
 
 The contributors of major functionality are: Jeremy Bennett, Krzysztof
 Bieganski, Byron Bradley, Lane Brooks, John Coiner, Duane Galbi, Arkadiusz
@@ -41,133 +42,158 @@ Paul Wasson, Jie Xu, and Wilson Snyder.
 Some of the people who have provided ideas, and feedback for Verilator
 include:
 
-David Addison, Tariq B. Ahmad, Nikana Anastasiadis, John David Anglin,
-Frederic Antonin, Hans Van Antwerpen, Vasu Arasanipalai, Jens Arm, Rohan
-Arshid, Valentin Atepalikhin, Philip Axer, Gökçe Aydos, Chris Bachhuber,
-Filip Badáň, Adam Bagley, Sharad Bagri, James Bailey, Robert Balas, Marco
-Balboni, Matthew Ballance, Ricardo Barbedo, Andrew Bardsley, Ilya Barkov,
-Matthew Barr, Geoff Barrett, Kaleb Barrett, Daniel Bates, Julius Baxter,
-Michael Berman, Jean Berniolles, Victor Besyakov, Narayan Bhagavatula,
-Moinak Bhattacharyya, Kritik Bhimani, David Biancolin, Krzysztof Bieganski,
-Michael Bikovitsky, David Binderman, Piotr Binkowski, Johan Björk, David
-Black, Tymoteusz Blazejczyk, Scott Bleiweiss, David van der Bokke, Daniel
-Bone, Guy Bonneau, Krzysztof Boroński, Gregg Bouchard, Christopher
-Boumenot, Paul Bowen-Huggett, Nick Bowler, Bryan Brady, Maarten De
-Braekeleer, Liam Braun, Charlie Brej, J Briquet, John Brownlee, KC
-Buckenmaier, Gijs Burghoorn, Jeff Bush, Lawrence Butcher, Tony Bybell, Iru
-Cai, Ted Campbell, Anthony Campos, Chris Candler, Lauren Carlson, Gregory
-Carver, Donal Casey, Sebastien Van Cauwenberghe, Alex Chadwick, Greg
-Chadwick, Marcel Chang, Aliaksei Chapyzhenka, Chih-Mao Chen, Guokai Chen,
-Kefa Chen, Terry Chen, Yangyu Chen, Yi-Chung Chen, Yurii Cherkasov,
-Hennadii Chernyshchyk, Enzo Chi, Bartłomiej Chmiel, Robert A. Clark, Ryan
-Clarke, Allan Cochrane, Keith Colbert, Quentin Corradi, Nassim Corteggiani,
-Gianfranco Costamagna, February Cozzocrea, Sean Cross, George Cuan, Michal
-Czyz, Joe DErrico, Jim Dai, Lukasz Dalek, Laurens van Dam, Gunter
-Dannoritzer, Ashutosh Das, Julian Daube, Greg Davill, Bernard Deadman,
-Peter Debacker, Josse Van Delm, John Demme, Mike Denio, John Deroo, Philip
-Derrick, Aadi Desai, John Dickol, Ruben Diez, Danny Ding, Jacko Dirks, Ivan
-Djordjevic, Brad Dobbie, Paul Donahue, Jonathon Donaldson, Anthony Donlon,
-Caleb Donovick, Larry Doolittle, Leendert van Doorn, Sebastian Dressler,
-Jonathan Drolet, Justin Yao Du, Maciej Dudek, Alex Duller, Jeff Dutton,
-Tomas Dzetkulic, Usuario Eda, Charles Eddleston, Chandan Egbert, Joe Eiler,
-Ahmed El-Mahmoudy, Trevor Elbourne, Mats Engstrom, Robert Farrell, Julien
-Faucher, Olivier Faure, Eugene Feinberg, Eugen Fekete, Fabrizio Ferrandi,
-Udi Finkelstein, Brian Flachs, Bill Flynn, Andrea Foletto, Alex Forencich,
-Aurelien Francillon, Bob Fredieu, Manuel Freiberger, Mostafa Gamal, Vito
-Gamberini, Mostafa Garnal, Benjamin Gartner, Christian Gelinek, Richard E
-George, Peter Gerst, Glen Gibb, Michael Gielda, Barbara Gigerl, Nimrod
-Gileadi, Shankar Giri, Dan Gisselquist, Szymon Gizler, Petr Gladkikh, Sam
-Gladstone, Mariusz Glebocki, Embedded Go, Andrew Goessling, Amir Gonnen,
-Chitlesh Goorah, Tomasz Gorochowik, Kai Gossner, Tarik Graba, Sergi
-Granell, Al Grant, Nathan Graybeal, Alexander Grobman, Qian Gu, Xuan Guo,
-Prabhat Gupta, Deniz Güzel, Driss Hafdi, Abdul Hameed, Neil Hamilton, James
-Hanlon, Tang Haojin, Øyvind Harboe, Jannis Harder, David Harris, Junji
-Hashimoto, Thomas Hawkins, Mitch Hayenga, Harald Heckmann, Robert Henry,
-Stephen Henry, Sebastian Hesselbarth, David Hewson, Jamey Hicks, Joel
-Holdsworth, Andrew Holme, Peter Holmes, Hiroki Honda, Alex Hornung,
-Pierre-Henri Horrein, David Horton, Peter Horvath, Jae Hossell, Kuoping
-Hsu, Shou-Li Hsu, Teng Huang, Steven Hugg, Alan Hunter, James Hutchinson,
-Tim Hutt, Ehab Ibrahim, Edgar E. Iglesias, Shahid Ikram, Jamie Iles, Fuad
-Ismail, Vighnesh Iyer, Ben Jackson, Daniel Jacques, Shareef Jalloq, Marlon
-James, Krzysztof Jankowski, Eyck Jentzsch, HyungKi Jeong, Iztok Jeras,
-Pawel Jewstafjew, Alexandre Joannou, James Johnson, Christophe Joly, Justin
-Jones, William D. Jones, Abe Jordan, Larry Darryl Lee Jr., Franck Jullien,
-James Jung, Mike Kagen, Arthur Kahlich, Kaalia Kahn, Guy-Armand Kamendje,
-Vasu Kandadi, Yoshitomo Kaneda, Kanad Kanhere, Patricio Kaplan, Pieter
-Kapsenberg, Rafal Kapuscik, Ralf Karge, Per Karlsson, Dan Katz, Sol
-Katzman, Ian Kennedy, Ami Keren, Fabian Keßler, Michael Killough, Sun Kim,
-Jonathan Kimmitt, Olof Kindgren, Kevin Kiningham, Cameron Kirk, Dan
-Kirkham, Aleksander Kiryk, Sobhan Klnv, Gernot Koch, Jack Koenig, Soon Koh,
-Nathan Kohagen, Steve Kolecki, Brett Koonce, Will Korteland, Andrei
-Kostovski, Wojciech Koszek, Varun Koyyalagunta, Arkadiusz Kozdra, Markus
-Krause, David Kravitz, Adam Krolnik, Roland Kruse, Mahesh Kumashikar,
-Andreas Kuster, Sergey Kvachonok, Charles Eric LaForest, Kevin Laeufer, Ed
-Lander, Steve Lang, Pierre Laroche, Stephane Laurent, Walter Lavino,
-Christian Leber, David Ledger, Alex Lee, Larry Lee, Yoda Lee, Michaël
-Lefebvre, Dag Lem, Igor Lesik, John Li, Kay Li, Zixi Li, Davide Libenzi,
-Nandor Licker, Eivind Liland, Ícaro Lima, Kevin Lin, Yu-Sheng Lin, Charlie
-Lind, Andrew Ling, Jiuyang Liu, Joey Liu, Paul Liu, Derek Lockhart, Jake
-Longo, Geza Lore, Arthur Low, Jose Loyola, Stefan Ludwig, Dan Lussier,
-Konstantin Lübeck, Fred Ma, Liwei Ma, Duraid Madina, Oleh Maksymenko, Affe
-Mao, Julien Margetts, Chick Markley, Alexis Marquet, Mark Marshall, Alfonso
-Martinez, Unai Martinez-Corral, Adrien Le Masle, Yves Mathieu, Vladimir
-Matveyenko, Patrick Maupin, Stan Mayer, Jordan McConnon, Conor McCullough,
-Jason McMullan, Elliot Mednick, Yuan Mei, Andy Meier, Luiza de Melo,
-Rodrigo A. Melo, Benjamin Menküc, Jake Merdich, David Metz, Wim Michiels,
+Gilberto Abram, David Addison, Joey Ah-kiow, Thomas Dybdahl Ahle, Tariq B.
+Ahmad, Thomas Aldrian, Omar Alkhatib, Amal Araweelo Almis, Nikana
+Anastasiadis, John David Anglin, Frederic Antonin, Hans Van Antwerpen, Vasu
+Arasanipalai, Jens Arm, Rohan Arshid, Valentin Atepalikhin, Philip Axer,
+Gökçe Aydos, Chris Bachhuber, Filip Badáň, Adam Bagley, Sharad Bagri, James
+Bailey, Robert Balas, Marco Balboni, Matthew Ballance, Ricardo Barbedo,
+Andrew Bardsley, Ilya Barkov, Matthew Barr, Geoff Barrett, Kaleb Barrett,
+Daniel Bates, Julius Baxter, Jeremy Bennett, Michael Berman, Jean
+Berniolles, Victor Besyakov, Narayan Bhagavatula, Moinak Bhattacharyya,
+Kritik Bhimani, David Biancolin, Krzysztof Bieganski, Artur Bieniek,
+Michael Bikovitsky, David Binderman, Piotr Binkowski, Peter Birch, Johan
+Björk, David Black, Tymoteusz Blazejczyk, Scott Bleiweiss, Joel Bodenmann,
+David van der Bokke, Daniel Bone, Guy Bonneau, Pierre-Yves Le Borgne,
+Krzysztof Boroński, Gregg Bouchard, Christopher Boumenot, Paul
+Bowen-Huggett, Nick Bowler, Byron Bradley, Bryan Brady, Maarten De
+Braekeleer, Liam Braun, Charlie Brej, Nick Brereton, J Briquet, Lane
+Brooks, John Brownlee, KC Buckenmaier, Gijs Burghoorn, Jeff Bush, Lawrence
+Butcher, Tony Bybell, Congcong Cai, Iru Cai, Ted Campbell, Anthony Campos,
+Chris Candler, Lauren Carlson, Gregory Carver, Donal Casey, Sebastien Van
+Cauwenberghe, Alex Chadwick, Greg Chadwick, Marcel Chang, Aliaksei
+Chapyzhenka, Chih-Mao Chen, Guokai Chen, Kefa Chen, Terry Chen, Yangyu
+Chen, Yi-Chung Chen, Yurii Cherkasov, Hennadii Chernyshchyk, Enzo Chi,
+Bartłomiej Chmiel, Sergey Chusov, Robert A. Clark, Ryan Clarke, Allan
+Cochrane, John Coiner, Luca Colagrande, Keith Colbert, Quentin Corradi,
+Nassim Corteggiani, Gianfranco Costamagna, February Cozzocrea, Sean Cross,
+George Cuan, RJ Cunningham, Michal Czyz, Joe DErrico, Jim Dai, Lukasz
+Dalek, Laurens van Dam, Gunter Dannoritzer, Ashutosh Das, Julian Daube,
+Greg Davill, Bernard Deadman, Peter Debacker, Josse Van Delm, John Demme,
+Mike Denio, John Deroo, Philip Derrick, Aadi Desai, John Dickol, Ruben
+Diez, Danny Ding, Jacko Dirks, Ivan Djordjevic, Brad Dobbie, Paul Donahue,
+Jonathon Donaldson, Anthony Donlon, Caleb Donovick, Larry Doolittle,
+Leendert van Doorn, Sebastian Dressler, Connor Driscoll, Jonathan Drolet,
+Jose Drowne, Justin Yao Du, Maciej Dudek, Alex Duller, Jeff Dutton, Tomas
+Dzetkulic, Usuario Eda, Charles Eddleston, Chandan Egbert, Joe Eiler, Ahmed
+El-Mahmoudy, Trevor Elbourne, Schuyler Eldridge, Ahmed Elzeftawi, Mats
+Engstrom, Augustin Fabre, Robert Farrell, Julien Faucher, Olivier Faure,
+Sergey Fedorov, Eugene Feinberg, Eugen Fekete, Fabrizio Ferrandi, Adrian
+Fiergolski, Udi Finkelstein, Brian Flachs, Bill Flynn, Andrea Foletto,
+Maxim Fonarev, Alex Forencich, Aurelien Francillon, Marco Frank, Bob
+Fredieu, Manuel Freiberger, Stephane Gagnon, Duane Galbi, Mostafa Gamal,
+Vito Gamberini, Mateusz Gancarz, Mostafa Garnal, Benjamin Gartner,
+Christian Gelinek, Richard E George, Peter Gerst, Glen Gibb, Michael
+Gielda, Barbara Gigerl, Nimrod Gileadi, Shankar Giri, Dan Gisselquist,
+Szymon Gizler, Petr Gladkikh, Sam Gladstone, Mariusz Glebocki, Embedded Go,
+Andrew Goessling, Emil Goh, Amir Gonnen, Chitlesh Goorah, Tomasz
+Gorochowik, Kai Gossner, Toshiki Goto, Tarik Graba, Sergi Granell, Al
+Grant, Nathan Graybeal, Alexander Grobman, Dominick Grochowina, Qian Gu,
+Karol Gugala, Xuan Guo, Prabhat Gupta, Oscar Gustafsson, Deniz Güzel, Driss
+Hafdi, Abdul Hameed, Neil Hamilton, Ali Hammoud, James Hanlon, Tang Haojin,
+Øyvind Harboe, Jannis Harder, David Harris, Junji Hashimoto, Thomas
+Hawkins, Mitch Hayenga, Christian Hecken, Harald Heckmann, Robin Heinemann,
+Robert Henry, Stephen Henry, Sebastian Hesselbarth, David Hewson, Jamey
+Hicks, Joel Holdsworth, Andrew Holme, Peter Holmes, Hiroki Honda, Steve
+Hoover, Alex Hornung, Pierre-Henri Horrein, David Horton, Peter Horvath,
+Jae Hossell, Kuoping Hsu, Shou-Li Hsu, Teng Huang, Steven Hugg, Alan
+Hunter, James Hutchinson, Tim Hutt, Ehab Ibrahim, Edgar E. Iglesias, Shahid
+Ikram, Jamie Iles, Ondrej Ille, Ron K. Irvine, Fuad Ismail, Vighnesh Iyer,
+Ben Jackson, Daniel Jacques, Shareef Jalloq, Marlon James, Krzysztof
+Jankowski, Moubarak Jeje, Tobias Jensen, Eyck Jentzsch, HyungKi Jeong,
+Iztok Jeras, Pawel Jewstafjew, Aditya Ranjan Jha, Xie Jiacheng, Alexandre
+Joannou, James Johnson, Christophe Joly, Justin Jones, William D. Jones,
+Kees Jongenburger, Abe Jordan, Larry Darryl Lee Jr., Franck Jullien, James
+Jung, Yoshitomo KANEDA, Mike Kagen, Arthur Kahlich, Kaalia Kahn, G-A.
+Kamendje, Guy-Armand Kamendje, Vasu Kandadi, Kanad Kanhere, Patricio
+Kaplan, Pieter Kapsenberg, Rafal Kapuscik, Ralf Karge, Per Karlsson, Dan
+Katz, Sol Katzman, Amirreza Kazemi, Ian Kennedy, Ami Keren, Fabian
+Keßler-Schulz, John Khoo, Michael Killough, Sun Kim, Jonathan Kimmitt, Olof
+Kindgren, Kevin Kiningham, Cameron Kirk, Dan Kirkham, Aleksander Kiryk,
+Sobhan Klnv, Gernot Koch, Jack Koenig, Soon Koh, Nathan Kohagen, Pawel
+Kojma, Steve Kolecki, Brett Koonce, Will Korteland, Andrei Kostovski,
+Wojciech Koszek, Varun Koyyalagunta, Arkadiusz Kozdra, Markus Krause, David
+Kravitz, Natan Kreimer, Adam Krolnik, Roland Kruse, Jan Kubalek, Mahesh
+Kumashikar, Andreas Kuster, Sergey Kvachonok, Charles Eric LaForest, Kevin
+Laeufer, Ed Lander, Steve Lang, Pierre Laroche, Stephane Laurent, Walter
+Lavino, Christian Leber, David Ledger, Alex Lee, Larry Lee, Yoda Lee,
+Michaël Lefebvre, Dag Lem, Igor Lesik, Brian Li, John Li, Kay Li, Zixi Li,
+Davide Libenzi, Matt Liberty, Nandor Licker, Eivind Liland, Ícaro Lima,
+Jian Nan Lin, Kevin Lin, Yu-Sheng Lin, Charlie Lind, Andrew Ling, Jens
+Yuechao Liu, Jiuyang Liu, Joey Liu, Paul Liu, Derek Lockhart, Jake Longo,
+Geza Lore, Arthur Low, Jose Loyola, Stefan Ludwig, Martin Lueker-Boden, Dan
+Lussier, Konstantin Lübeck, Fred Ma, Liwei Ma, Duraid Madina, Oleh
+Maksymenko, Alexander Mann, Affe Mao, Rémi Marche, Julien Margetts, Chick
+Markley, Alexis Marquet, Mark Marshall, Alfonso Martinez, Unai
+Martinez-Corral, Adrien Le Masle, Yves Mathieu, Vladimir Matveyenko,
+Patrick Maupin, Stan Mayer, Jordan McConnon, Conor McCullough, Jason
+McMullan, Elliot Mednick, Yuan Mei, Andy Meier, Luiza de Melo, Rodrigo A.
+Melo, Benjamin Menküc, Niraj Menon, Jake Merdich, David Metz, Wim Michiels,
 Miodrag Milanović, Darryl Miles, Kevin Millis, Andrew Miloradovsky, David
-Moberg, Wai Sum Mong, Peter Monsson, Anthony Moore, Sean Moore, Stuart
-Morris, Dennis Muhlestein, John Murphy, Matt Myers, Nathan Myers, Richard
-Myers, Alex Mykyta, Eric Müller, Dimitris Nalbantis, Peter Nelson, Felix
-Neumärker, Bob Newgard, Cong Van Nguyen, Rachit Nigam, Toru Niina, Paul
-Nitza, Yossi Nivin, Pete Nixon, Lisa Noack, Mark Nodine, Michael Nolan,
-Andrew Nolte, Joseph Nwabueze, Kevin Nygaard, Kuba Ober, Krzysztof
-Obłonczek, Andreas Olofsson, Baltazar Ortiz, Aleksander Osman, Don Owen,
-Tim Paine, Deepa Palaniappan, James Pallister, Vassilis Papaefstathiou,
-Sanggyu Park, Brad Parker, Risto Pejašinović, Seth Pellegrino, Morten Borup
-Petersen, Dan Petrisko, Wesley Piard, Maciej Piechotka, David Pierce, Cody
-Piersall, T. Platz, Michael Platzer, Dominic Plunkett, Nolan Poe, David
-Poole, Michael Popoloski, Roman Popov, Aylon Chaim Porat, Oron Port, Rich
-Porter, Rick Porter, Stefan Post, Niranjan Prabhu, Damien Pretet, Harald
-Pretl, Bill Pringlemeir, Usha Priyadharshini, Mark Jackson Pulver, Prateek
-Puri, Han Qi, Jiacheng Qian, Marshal Qiao, Raynard Qiao, Yujia Qiao, Jasen
-Qin, Frank Qiu, Nandu Raj, Kamil Rakoczy, Danilo Ramos, Drew Ranck, Chris
-Randall, Anton Rapp, Josh Redford, Odd Magne Reitan, Frédéric Requin,
-Dustin Richmond, Samuel Riedel, Alberto Del Rio, Eric Rippey, Narcis Rodas,
-Oleg Rodionov, Ludwig Rogiers, Paul Rolfe, Michail Rontionov, Arjen
-Roodselaar, Arthur Rosa, Tobias Rosenkranz, Yernagula Roshit, Ryszard
-Rozak, Huang Rui, Graham Rushton, Jan Egil Ruud, Denis Rystsov, Pawel
-Sagan, Robert Sammelson, Adrian Sampson, John Sanguinetti, Josep Sans, Luca
-Sasselli, Martin Scharrer, Martin Schmidt, Jonathan Schröter, Julie
+Moberg, Wai Sum Mong, Peter Monsson, Anthony Moore, Sean Moore, Javier
+Mora, Rodrigo Batista de Moraes, Stuart Morris, Dennis Muhlestein, John
+Murphy, Matt Myers, Nathan Myers, Richard Myers, Alex Mykyta, Shivaram
+Mysore, Eric Müller, Dimitris Nalbantis, Jitesh Nayak, Peter Nelson, Yuri
+Nenakhov, Felix Neumärker, Bob Newgard, Cong Van Nguyen, Trung Nguyen,
+Rachit Nigam, Toru Niina, Paul Nitza, Yossi Nivin, Pete Nixon, Lisa Noack,
+Mark Nodine, Petr Nohavica, Michael Nolan, Andrew Nolte, Mateusz
+Nurczyński, Joseph Nwabueze, Kevin Nygaard, Thomas O'Keeffe, Kuba Ober,
+Krzysztof Obłonczek, Danny Oler, Andreas Olofsson, Baltazar Ortiz,
+Aleksander Osman, Don Owen, Tim Paine, Deepa Palaniappan, James Pallister,
+Vassilis Papaefstathiou, Sanggyu Park, Brad Parker, Risto Pejašinović, Seth
+Pellegrino, Joel Peltonen, Morten Borup Petersen, Dan Petrisko, Thanh Tung
+Pham, Wesley Piard, Maciej Piechotka, David Pierce, Cody Piersall,
+T. Platz, Michael Platzer, Dominic Plunkett, Nolan Poe, Tuomas Poikela,
+George Polack, David Poole, Michael Popoloski, Roman Popov, Aylon Chaim
+Porat, Oron Port, Rich Porter, Rick Porter, Stefan Post, Niranjan Prabhu,
+Damien Pretet, Harald Pretl, Bill Pringlemeir, Usha Priyadharshini, Mark
+Jackson Pulver, Prateek Puri, Nikolay Puzanov, Han Qi, Jiacheng Qian,
+Marshal Qiao, Raynard Qiao, Yujia Qiao, Jasen Qin, Frank Qiu, Nandu Raj,
+Kamil Rakoczy, Danilo Ramos, Drew Ranck, Chris Randall, Anton Rapp, Josh
+Redford, Odd Magne Reitan, Frédéric Requin, Wajahat Riaz, Dustin Richmond,
+Samuel Riedel, Alberto Del Rio, Eric Rippey, Narcis Rodas, Oleg Rodionov,
+Ludwig Rogiers, Paul Rolfe, Michail Rontionov, Arjen Roodselaar, Arthur
+Rosa, Tobias Rosenkranz, Yernagula Roshit, Diego Roux, Ryszard Rozak, Dan
+Ruelas-Petrisko, Luca Rufer, Huang Rui, Graham Rushton, Jan Egil Ruud,
+Denis Rystsov, Pawel Sagan, Robert Sammelson, Adrian Sampson, John
+Sanguinetti, Josep Sans, Dave Sargeant, Luca Sasselli, Philippe Sauter,
+Martin Scharrer, Parker Schless, Martin Schmidt, Jonathan Schröter, Julie
 Schwartz, Galen Seitz, Sam Shahrestani, Joseph Shaker, Mark Shaw, Salman
-Sheikh, Zhou Shen, Hao Shi, James Shi, Michael Shinkarovsky, Rafael
-Shirakawa, Jeffrey Short, S Shuba, Fan Shupei, Ethan Sifferman, Anderson
-Ignacio da Silva, Rodney Sinclair, Ameya Vikram Singh, Sanjay Singh, Frans
-Skarman, Nate Slager, Steven Slatter, Mladen Slijepcevic, Brian Small,
-Garrett Smith, Gus Smith, Tim Snyder, Maciej Sobkowski, Stan Sokorac, Alex
-Solomatnikov, Flavien Solt, Wei Song, Trefor Southwell, Martin Stadler, Art
-Stamness, David Stanford, Krzysztof Starecki, Baruch Sterin, John
-Stevenson, Pete Stevenson, Patrick Stewart, Rob Stoddard, Tood Strader,
-John Stroebel, Ray Strouble, Sven Stucki, Howard Su, Udaya Raj Subedi,
-Emerson Suguimoto, Gene Sullivan, Qingyao Sun, Renga Sundararajan, Kuba
+Sheikh, Zhou Shen, Zhouyi Shen, Hao Shi, James Shi, Michael Shinkarovsky,
+Rafael Shirakawa, Jeffrey Short, S Shuba, Fan Shupei, Ethan Sifferman,
+Anderson Ignacio da Silva, Rodney Sinclair, Ameya Vikram Singh, Sanjay
+Singh, Frans Skarman, Nate Slager, Steven Slatter, Mladen Slijepcevic,
+Brian Small, Garrett Smith, Gus Smith, Rachel Smith, Tim Snyder, Maciej
+Sobkowski, Stan Sokorac, Alex Solomatnikov, Flavien Solt, Wei Song, Trefor
+Southwell, Martin Stadler, Art Stamness, David Stanford, Krzysztof
+Starecki, Baruch Sterin, John Stevenson, Pete Stevenson, Patrick Stewart,
+Rob Stoddard, Tood Strader, Jean-Nicolas Strauss, John Stroebel, Ray
+Strouble, Matt Stroud, Sven Stucki, Howard Su, Udaya Raj Subedi, Emerson
+Suguimoto, Gene Sullivan, Qingyao Sun, Renga Sundararajan, Kuba
 Sunderland-Ober, Gustav Svensk, Rupert Swarbrick, Jevin Sweval, Paul
-Swirhun, Shinya T-Y, Thierry Tambe, Jesse Taube, Drew Taussig, Christopher
-Taylor, Greg Taylor, Jose Tejada, Sören Tempel, Peter Tengstrand, Wesley
+Swirhun, Krzysztof Sychla, Shinya T-Y, Yutetsu Takatsukasa, Thierry Tambe,
+Jesse Taube, Drew Taussig, Christopher Taylor, David Taylor, Greg Taylor,
+Michael Bedford Taylor, Jose Tejada, Sören Tempel, Peter Tengstrand, Wesley
 Terpstra, Rui Terra, Stefan Thiede, Justin Thiel, Gary Thomas, Ian
-Thompson, Kevin Thompson, Mike Thyer, Hans Tichelaar, Tudor Timi, Viktor
-Tomov, Steve Tong, Topa Topino, Àlex Torregrosa, Topa Tota, Michael
-Tresidder, Lenny Truong, David Turner, Neil Turton, Hideto Ueno, Mike
-Urbach, Joel Vandergriendt, Srini Vemuri, Srinivasan Venkataramanan, Yuri
-Victorovich, Ivan Vnučec, Bogdan Vukobratovic, Holger Waechtler, Philipp
-Wagner, Stefan Wallentowitz, Johannes Walter, CY Wang, Chuxuan Wang, Shawn
-Wang, Yilou Wang, Zhanglei Wang, Greg Waters, Thomas Watts, Eugene Weber,
-John Wehle, Tianrui Wei, David Welch, Thomas J Whatson, Martin Whitaker,
-Marco Widmer, Leon Wildman, Daniel S. Wilkerson, Daniel Wilkerson, Gerald
-Williams, Trevor Williams, Don Williamson, Jan Van Winkel, Jeff Winston,
-Joshua Wise, Clifford Wolf, Johan Wouters, Paul Wright, Tobias Wölfel,
-Junyi Xi, Ding Xiaoliang, Liu Xiaoyi, Jinyan Xu, Mandy Xu, Pengcheng Xu,
-Shanshan Xu, Yan Xu, Yinan Xu, SU YANG, Felix Yan, Jiaxun Yang, Luke Yang,
-Amir Yazdanbakhsh, Chentai (Seven) Yuan, Florian Zaruba, Mat Zeno, Keyi
-Zhang, Xi Zhang, Huanghuang Zhou, Yike Zhou, Jiamin Zhu, Ryan Ziegler.
+Thompson, Kevin Thompson, Mike Thyer, Jerry Tianchen, Hans Tichelaar, Tudor
+Timi, Viktor Tomov, Steve Tong, Topa Topino, Àlex Torregrosa, Topa Tota,
+Michael Tresidder, Lenny Truong, David Turner, Neil Turton, Hideto Ueno,
+Ethan Uppal, Mike Urbach, Joel Vandergriendt, Srini Vemuri, Srinivasan
+Venkataramanan, Yuri Victorovich, Ivan Vnučec, Andrew Voznytsa, Bogdan
+Vukobratovic, Holger Waechtler, Justin Wagner, Philipp Wagner, Stefan
+Wallentowitz, Johannes Walter, CY Wang, Chuxuan Wang, Shawn Wang, Yilou
+Wang, Zhanglei Wang, Jakub Wasilewski, Paul Wasson, Greg Waters, Thomas
+Watts, Eugene Weber, John Wehle, Tianrui Wei, Yin Weijie, David Welch,
+Thomas J Whatson, Martin Whitaker, Marco Widmer, Leon Wildman, Daniel S.
+Wilkerson, Daniel Wilkerson, Gerald Williams, Trevor Williams, Don
+Williamson, Jan Van Winkel, Jeff Winston, Max Wipfli, Joshua Wise, Clifford
+Wolf, Johan Wouters, Paul Wright, Tobias Wölfel, Domenic Wüthrich, Junyi
+Xi, Ding Xiaoliang, Liu Xiaoyi, Jie Xu, Jinyan Xu, Mandy Xu, Pengcheng Xu,
+Shanshan Xu, Yan Xu, Yinan Xu, Felix Yan, Zhen Yan, Jiaxun Yang, Luke Yang,
+Su Yang, Amir Yazdanbakhsh, Law Heng Yi, Ibrahim Burak Yorulmaz, Chentai
+(Seven) Yuan, Florian Zaruba, Igor Zaworski, Mat Zeno, Keyi Zhang, Xi
+Zhang, Alex Zhou, Huanghuang Zhou, Yike Zhou, Jiamin Zhu, Ryan Ziegler, Lan
+Zongwei.
 
 Thanks to them, and all those we've missed mentioning above, and to those
 whom have wished to remain anonymous.
@@ -177,24 +203,24 @@ Historical Origins
 ==================
 
 Verilator was conceived in 1994 by Paul Wasson at the Core Logic Group at
-Digital Equipment Corporation.  The Verilog code that was converted to C
-was then merged with a C-based CPU model of the Alpha processor and
-simulated in a C-based environment called CCLI.
+Digital Equipment Corporation. The Verilog code that was converted to C was
+then merged with a C-based CPU model of the Alpha processor and simulated
+in a C-based environment called CCLI.
 
 In 1995 Verilator started being used for Multimedia and Network Processor
-development inside Digital.  Duane Galbi took over the active development
-of Verilator, and added several performance enhancements, and CCLI was
-still being used as the shell.
+development inside Digital. Duane Galbi took over the active development of
+Verilator, and added several performance enhancements, and CCLI was still
+being used as the shell.
 
 In 1998, through the efforts of existing DECies, mainly Duane Galbi,
-Digital graciously agreed to release the source code.  (Subject to the code
+Digital graciously agreed to release the source code. (Subject to the code
 not being resold, which is compatible with the GNU Public License.)
 
-In 2001, Wilson Snyder took the kit, added a SystemC mode, and called
-it Verilator2.  This was the first packaged public release.
+In 2001, Wilson Snyder took the kit, added a SystemC mode, and called it
+Verilator2. This was the first packaged public release.
 
 In 2002, Wilson Snyder created Verilator 3.000 by rewriting Verilator from
-scratch in C++.  This added many optimizations, yielding about a 2-5x
+scratch in C++. This added many optimizations, yielding about a 2-5x
 performance gain.
 
 In 2009, major SystemVerilog and DPI language support was added.

docs/guide/control.rst

@@ -0,0 +1,348 @@
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+.. _verilator control files:
+
+=======================
+Verilator Control Files
+=======================
+
+In addition to the command line, warnings and other features for the
+:command:`verilator` command may be controlled with Verilator Control
+Files, not to be confused with IEEE Configurations blocks
+(`config...endconfig`). Typically named with the `.vlt` extension, what
+makes it a Verilator Control File is the :option:`\`verilator_config`
+directive. These files, when named `.vlt`, are read before source code
+files; if this behavior is undesired, name the control file with a `.v` or
+other suffix.
+
+An example:
+
+.. code-block:: sv
+
+   `verilator_config
+   lint_off -rule WIDTH
+   lint_off -rule CASEX  -file "silly_vendor_code.v"
+
+This disables WIDTH warnings globally, and CASEX for a specific file.
+
+Verilator control files are fed through the normal Verilog preprocessor
+prior to parsing, so "\`ifdef", "\`define", and comments may be used as if
+the control file was standard Verilog code.
+
+Note that file or line-specific control only applies to files read after
+the control file. It is therefore recommended to pass the control file to
+Verilator as the first file.
+
+The grammar of control commands is as follows:
+
+.. option:: `verilator_config
+
+   Take the remaining text and treat it as Verilator Control File commands.
+   See :ref:`Verilator Control Files`.
+
+.. option:: clock_enable -module "<modulename>" -var "<signame>"
+
+   Deprecated and has no effect (ignored).
+
+   In versions before 5.000:
+
+   Indicates that the signal is used to gate a clock, and the user takes
+   responsibility for ensuring there are no races related to it.
+
+   Same as :option:`/*verilator&32;clock_enable*/` metacomment.
+
+
+   .. t_dist_docs_style ignore no_clocker
+
+.. option:: clocker -module "<modulename>" [-function "<funcname>"] -var "<signame>"
+
+.. option:: clocker -module "<modulename>" [-task "<taskname>"] -var "<signame>"
+
+.. option:: no_clocker -module "<modulename>" [-function "<funcname>"] -var "<signame>"
+
+.. option:: no_clocker -module "<modulename>" [-task "<taskname>"] -var "<signame>"
+
+   Deprecated and has no effect (ignored).
+
+   In versions before 5.042:
+
+   Indicates whether the signal is used as clock or not. Verilator uses
+   this information to mark the signal and any derived signals as clocker.
+   See :vlopt:`--clk`.
+
+   Same as :option:`/*verilator&32;clocker*/` metacomment.
+
+.. option:: coverage_block_off -file "<filename>" -line <lineno>
+
+.. option:: coverage_block_off -module "<modulename>" -block "<blockname>"
+
+   Specifies the entire begin/end block should be ignored for coverage
+   analysis purposes. It can either be specified as a named block or as a
+   filename and line number.
+
+   Same as :option:`/*verilator&32;coverage_block_off*/` metacomment.
+
+.. option:: coverage_off [-file "<filename>" [-lines <line> [ - <line> ]]]
+
+.. option:: coverage_on  [-file "<filename>" [-lines <line> [ - <line> ]]]
+
+   Enable/disable coverage for the specified filename (or wildcard with
+   '\*' or '?', or all files if omitted) and range of line numbers (or all
+   lines if omitted). Often used to ignore an entire module for coverage
+   analysis purposes.
+
+.. option:: forceable -module "<modulename>" -var "<signame>"
+
+   Generate public `<signame>__VforceEn` and `<signame>__VforceVal` signals
+   that can force/release a signal from C++ code. The force control
+   signals are created as :option:`public_flat` signals.
+
+   Same as :option:`/*verilator&32;forceable*/` metacomment.
+
+.. option:: full_case -file "<filename>" -lines <lineno>
+
+   Same as ``//synthesis full_case``. When these synthesis directives
+   are discovered, Verilator will either formally prove the directive to be
+   true, or, failing that, will insert the appropriate code to detect
+   failing cases at simulation runtime and print an "Assertion failed"
+   error message.
+
+.. option:: hier_block -module "<modulename>"
+
+   Specifies that the module is an unit of hierarchical Verilation. Note
+   that the setting is ignored unless the :vlopt:`--hierarchical` option is
+   specified. See :ref:`Hierarchical Verilation`.
+
+.. option:: hier_params -module "<modulename>"
+
+   Specifies that the module contains parameters a :vlopt:`--hierarchical` block. This option
+   is used internally to specify parameters for deparametrized hier block instances.
+   This option should not be used directly.
+   See :ref:`Hierarchical Verilation`.
+
+.. option:: hier_workers -hier-dpi "<function_name>" -workers <worker_count>
+
+   Specifies how many threads need to be used for scheduling hierarchical DPI
+   tasks. This data is inserted internally during :vlopt:`--hierarchical`,
+   based on value specified in `hier_workers -module`. This option
+   should not be used directly. See :ref:`Hierarchical Verilation`.
+
+.. option:: hier_workers -module "<module_name>" -workers <worker_count>
+
+   Specifies how many threads need to be used for scheduling given module with
+   :option:`/*verilator&32;hier_block*/` metacomment. This number needs to be
+   smaller than :vlopt:`--threads` to fit in a thread schedule.
+   See :ref:`Hierarchical Verilation`.
+
+.. option:: inline -module "<modulename>"
+
+   Specifies the module may be inlined into any modules that use this
+   module. Same as :option:`/*verilator&32;inline_module*/` metacomment.
+
+   .. t_dist_docs_style ignore no_inline
+
+.. option:: no_inline -module "<modulename>"
+
+   Specifies the module should not be inlined into any modules that use
+   this module. Same as :option:`/*verilator&32;no_inline_module*/`
+   metacomment.
+
+.. option:: no_inline [-module "<modulename>"] -function "<funcname>"
+
+.. option:: no_inline [-module "<modulename>"] -task "<taskname>"
+
+   Specify the function or task should not be inlined into where it is
+   used. This may reduce the size of the final executable when a task is
+   used a very large number of times. For this flag to work, the task and
+   tasks below it must be pure; they cannot reference any variables outside
+   the task itself.
+
+   Same as :option:`/*verilator&32;no_inline_task*/` metacomment.
+
+.. option:: isolate_assignments -module "<modulename>" -function "<fname>"
+
+.. option:: isolate_assignments -module "<modulename>" [-function "<funcname>"] -var "<signame>"
+
+.. option:: isolate_assignments -module "<modulename>" [-task "<taskname>"] -var "<signame>"
+
+   Used to indicate that the assignments to this signal in any blocks
+   should be isolated into new blocks. Same as
+   :option:`/*verilator&32;isolate_assignments*/` metacomment.
+
+.. option:: lint_off [-rule <message>] [-file "<filename>" [-lines <line> [ - <line>]]]
+
+.. option:: lint_off [-rule <message>] [-file "<filename>"] [-contents "<wildcard>"] [-match "<wildcard>"]
+
+.. option:: lint_on  [-rule <message>] [-file "<filename>" [-lines <line> [ - <line>]]]
+
+   Enable/disables the specified lint warning, in the specified filename
+   (or wildcard with '\*' or '?', or all files if omitted) and range of
+   line numbers (or all lines if omitted).
+
+   If the ``-rule`` is omitted, all lint warnings (see list in
+   :vlopt:`-Wno-lint`) are enabled/disabled.
+
+   If ``-contents`` is provided, the input files must contain the given
+   wildcard (with '\*' or '?'), and are waived in case they match, provided
+   the ``-rule``, ``-file``, and ``-contents`` also match. The wildcard
+   should be designed to match a single line; it is unspecified if the
+   wildcard is allowed to match across multiple lines. The input contents
+   does not include :vlopt:`--std <--no-std>` standard files, nor control
+   files (with ``verilator_config``). Typical use for this is to match a
+   version number present in the Verilog sources, so that the waiver will
+   only apply to that version of the sources.
+
+   If ``-match`` is provided, the linter warnings are matched against the
+   given wildcard (with '\*' or '?'), and are waived in case they match,
+   provided the ``-rule``, ``-file``, and ``-contents`` also match. The
+   wildcard is compared across the entire multi-line message; see
+   :vlopt:`--waiver-multiline`.
+
+   When there are overlapping conflicting lint_on/lint_off directives, they
+   are resolved in the following priority order:
+
+   * All lint_on/lint_off without a ``-file``, or with a ``-file "\*"``,
+     are processed in order of parsing.
+   * All lint_on/lint_off with ``-file "non-\*"`` are processed in order of
+     parsing.
+   * All lint_off with ``--match`` in order of parsing.
+
+   If a warning is disabled with lint_off, it will not be printed, even if
+   the source contains a lint_on metacomment. The control file directives
+   and metacomments are interpreted separately and do not interact. A
+   warning is emitted only if not disabled either in a control file or via
+   metacomments.
+
+   Before version 4.026, ``-rule`` was named ``-msg``, and
+   ``-msg`` remained a deprecated alias until Version 5.000.
+
+.. option:: parallel_case -file "<filename>" -lines <lineno>
+
+   Same as ``//synthesis parallel_case``. When these synthesis
+   directives are discovered, Verilator will either formally prove the
+   directive to be true, or, failing that, will insert the appropriate code
+   to detect failing cases at simulation runtime and print an "Assertion
+   failed" error message.
+
+.. option:: profile_data -hier-dpi "<function_name>" -cost <cost_value>
+
+   Internal profiling data inserted during :vlopt:`--hierarchical`; specifies
+   execution cost of a hierarchical DPI wrappers for modules with
+   :option:`/*verilator&32;hier_block*/` metacomment. See
+   :ref:`Hierarchical Verilation`.
+
+.. option:: profile_data -mtask "<mtask_hash>" -cost <cost_value>
+
+   Feeds profile-guided optimization data into the Verilator algorithms in
+   order to improve model runtime performance. This option is not expected
+   to be used by users directly. See :ref:`Thread PGO`.
+
+.. option:: public [-module "<modulename>"] [-task/-function "<taskname>"] [-var "<signame>"]
+
+.. option:: public_flat [-module "<modulename>"] [-task/-function "<taskname>"] [(-param | -port | -var) "<signame>"]
+
+.. option:: public_flat_rd [-module "<modulename>"] [-task/-function "<taskname>"] [(-param | -port | -var) "<signame>"]
+
+.. option:: public_flat_rw [-module "<modulename>"] [-task/-function "<taskname>"] [(-param | -port | -var) "<signame>"] ["@(edge)"]
+
+   Sets the specified signal to be public. Same as
+   :option:`/*verilator&32;public*/` or
+   :option:`/*verilator&32;public_flat*/`, etc., metacomments. See also
+   :ref:`VPI Example`.
+
+   Using ``-port`` only selects matching ports, ``-param`` matches
+   parameters and localparams, and ``-var`` matches any signal (including
+   ports, parameters, and regular variables or nets). In all three, the
+   following ``<signame>`` can contain ``*`` and ``?`` wildcard
+   characters that match any substring or any single character respectively.
+
+.. option:: sc_biguint -module "<modulename>" -var "<signame>"
+
+   Sets the input/output signal to be of ``sc_biguint<{width}>`` type.
+   This metacomment works for signals of any width.
+   Same as :option:`/*verilator&32;sc_biguint*/` metacomment.
+
+.. option:: sc_bv -module "<modulename>" -var "<signame>"
+
+   Sets the port to be of ``sc_bv<{width}>`` type, instead of bool,
+   uint32_t, or uint64_t. Same as :option:`/*verilator&32;sc_bv*/`
+   metacomment.
+
+.. option:: sformat [-module "<modulename>"] [-function "<funcname>"] -var "<signame>"
+
+.. option:: sformat [-module "<modulename>"] [-task "<taskname>"] -var "<signame>"
+
+   Must be applied to the final argument of type ``input string`` of a
+   function or task to indicate that the function or task should pass all
+   remaining arguments through $sformatf. This allows the creation of DPI
+   functions with $display-like behavior. See the
+   :file:`test_regress/t/t_dpi_display.v` file for an example.
+
+   Same as :option:`/*verilator&32;sformat*/` metacomment.
+
+.. option:: split_var [-module "<modulename>"] [-function "<funcname>"] -var "<varname>"
+
+.. option:: split_var [-module "<modulename>"] [-task "<taskname>"] -var "<varname>"
+
+   Break the variable into multiple pieces typically to resolve UNOPTFLAT
+   performance issues. Typically the variables to attach this to are
+   recommended by Verilator itself; see :option:`UNOPTFLAT`.
+
+   Same as :option:`/*verilator&32;split_var*/` metacomment.
+
+.. option:: timing_off [-file "<filename>" [-lines <line> [ - <line>]]]
+
+.. option:: timing_on  [-file "<filename>" [-lines <line> [ - <line>]]]
+
+   Enables/disables timing constructs for the specified file and lines.
+   When disabled, all timing control constructs in the specified source
+   code locations are ignored the same way as with the
+   :option:`--no-timing`, and code:`fork`/``join*`` blocks are
+   converted into ``begin``/``end`` blocks.
+
+   Similar to :option:`/*verilator&32;timing_on*/`,
+   :option:`/*verilator&32;timing_off*/` meta-comments, but interpreted
+   independently. If either a control file, or meta-comments disable timing
+   constructs, they will be disabled.
+
+   .. t_dist_docs_style ignore tracing_on
+
+.. option:: tracing_off [-file "<filename>" [-lines <line> [ - <line> ]]]
+
+.. option:: tracing_on  [-file "<filename>" [-lines <line> [ - <line> ]]]
+
+.. option:: tracing_off [-scope "<scopename>" [-levels <levels> ]]
+
+.. option:: tracing_on  [-scope "<scopename>" [-levels <levels> ]]
+
+   Enable/disable waveform tracing for all future signals declared in
+   all files.
+
+   With ``-file``, enable/disable waveform tracing in the specified
+   filename (or wildcard with '\*' or '?'), and ``-line`` range of line
+   numbers (or all lines if omitted).
+
+   For tracing_off with ``-file``, instances below any module in the
+   files/ranges specified will also not be traced. To overcome this
+   feature, use tracing_on on the upper module declaration and on any
+   cells, or use the ``-scope`` flavor of the command.
+
+   With ``-scope`` enable/disable waveform tracing for the specified scope
+   (or wildcard with '\*' or '?'), and optional ``--levels`` number of
+   levels below. These controls only operate after other
+   file/line/module-based controls have indicated the signal should be
+   traced. Matching is performed on the shortest prefix first, such that
+   ``tracing_on -scope "a.b" tracing_off -scope "a"`` will turn it on for
+   "a.b" and off for everything else "a.*".
+
+   With ``-levels`` (used with ``-scope``), the number of levels below that
+   scope which the rule is to match, where 0 means all levels below, 1 the
+   exact level as the provided scope, and 2 means an additional level of
+   children below the provided scope, etc.
+
+.. option:: verilator_lib -module "<modulename>"
+
+   Internal use only. Marks the specified module as being a stub for a library
+   created by :vlopt:`--lib-create` (including when created with
+   :vlopt:`--hierarchical`). Required for special internal processing.

docs/guide/copyright.rst

@@ -1,14 +1,13 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *********
 Copyright
 *********
 
-The latest version of Verilator is available from `https://verilator.org
-<https://verilator.org>`_.
+The latest version of Verilator is available from https://verilator.org.
 
-Copyright 2003-2025 by Wilson Snyder. This program is free software; you
+Copyright 2003-2026 by Wilson Snyder. Verilator is free software; you
 can redistribute it and/or modify the Verilator internals under the terms
 of either the GNU Lesser General Public License Version 3 or the Perl
 Artistic License Version 2.0.

docs/guide/deprecations.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 Deprecations
@@ -7,22 +7,25 @@ Deprecations
 The following deprecated items are scheduled for future removal:
 
 C++14 compiler support
-  Verilator currently requires a C++20 or newer compiler for timing, and a
-  C++14 or newer compiler for both compiling Verilator and compiling
-  Verilated models with --no-timing.
+   Verilator currently requires a C++20 or newer compiler for timing, and a
+   C++14 or newer compiler for both compiling Verilator and compiling
+   Verilated models with --no-timing.
 
-  Verilator will require C++20 or newer compilers for both compiling
-  Verilator and compiling all Verilated models no sooner than May 2025.
-  (Likely to be removed shortly after GitHub removes Ubuntu 20.04
-  continuous-integration action runners, which are used to test the older
-  C++ standard).
+   Verilator will require C++20 or newer compilers for both compiling
+   Verilator and compiling all Verilated models no sooner than May 2025.
+   (Although this date has expired, this change is currently on hold until
+   the Ubuntu LTS versions of GCC and clang use C++20 by default, estimated
+   May 2028.)
 
-XML output
-  Verilator currently supports XML parser output (enabled with `--xml-only`).
-  Support for `--xml-*` options will be deprecated no sooner than January 2026.
+`--structs-packed` option
+   The :vlopt:`--structs-packed` option was introduced when Verilator was
+   first implementing unpacked structs. That feature has been stable now
+   for multiple years, so :vlopt:`--structs-packed` should no longer be
+   used. Thus :vlopt:`--structs-packed` will change to a no-operation flag
+   and the related :option:`UNPACKED` warning will never be issued no
+   sooner than September 2026.
 
---make cmake
-  The `--make cmake` options is deprecated and will be removed no sooner than
-  January 2026. Use `--make json` instead. Note that the CMake integration
-  shipping with Verilator (verilator-config.mk) already uses `--make json` so
-  no changes are necessary if using that.
+tcmalloc support
+   Verilator currently supports the default malloc, tcmalloc, or jemalloc.
+   As jemalloc has better performance, support for tcmalloc may be removed
+   no sooner than January 2027.

docs/guide/environment.rst

@@ -1,6 +1,8 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
+.. _Environment:
+
 Environment
 ===========
 
@@ -10,14 +12,14 @@ associated programs.
 .. option:: LD_LIBRARY_PATH
 
    A generic Linux/OS variable specifying what directories have shared
-   object (.so) files.  This path should include SystemC and other
-   shared objects needed at simulation runtime.
+   object (.so) files. This path should include SystemC and other shared
+   objects needed at simulation runtime.
 
 .. option:: MAKE
 
    Names the executable of the make command invoked when using the
-   :vlopt:`--build` option.  Some operating systems may require "gmake" to
-   this variable to launch GNU make.  If this variable is not specified,
+   :vlopt:`--build` option. Some operating systems may require "gmake" to
+   this variable to launch GNU make. If this variable is not specified,
    "make" is used.
 
 .. option:: MAKEFLAGS
@@ -29,33 +31,33 @@ associated programs.
 .. option:: OBJCACHE
 
    Optionally specifies a caching or distribution program to place in front
-   of all runs of the C++ compiler.  For example, "ccache" or "sccache".  If using
-   :command:`distcc` or :command:`icecc`/:command:`icecream`, they would
-   generally be run under :command:`ccache`; see the documentation for
-   those programs.  If OBJCACHE is not set, and at configure time ccache
+   of all runs of the C++ compiler. For example, "ccache" or "sccache". If
+   using :command:`distcc` or :command:`icecc`/:command:`icecream`, they
+   would generally be run under :command:`ccache`; see the documentation
+   for those programs. If OBJCACHE is not set, and at configure time ccache
    was present, ccache will be used as a default.
 
 .. option:: SYSTEMC
 
-   Deprecated.  Used only if :option:`SYSTEMC_INCLUDE` or
-   :option:`SYSTEMC_LIBDIR` is not set.  If set, specifies the directory
-   containing the SystemC distribution.  If not specified, it will come
-   from a default optionally specified at configure time (before Verilator
-   was compiled).
+   Deprecated. Used only if :option:`SYSTEMC_INCLUDE` or
+   :option:`SYSTEMC_LIBDIR` is not set. If set, specifies the directory
+   containing the SystemC distribution. If not specified, it will come from
+   a default optionally specified at configure time (before Verilator was
+   compiled).
 
 .. option:: SYSTEMC_ARCH
 
-   Deprecated.  Used only if :option:`SYSTEMC_LIBDIR` is not set.
-   Specifies the architecture name used by the SystemC kit.  This is the
-   part after the dash in the "lib-{...}" directory name created by a
-   :command:`make` in the SystemC distribution.  If not set, Verilator will
-   try to intuit the proper setting, or use the default optionally
-   specified at configure time (before Verilator was compiled).
+   Deprecated. Used only if :option:`SYSTEMC_LIBDIR` is not set. Specifies
+   the architecture name used by the SystemC kit. This is the part after
+   the dash in the "lib-{...}" directory name created by a :command:`make`
+   in the SystemC distribution. If not set, Verilator will try to intuit
+   the proper setting, or use the default optionally specified at configure
+   time (before Verilator was compiled).
 
 .. option:: SYSTEMC_CXX_FLAGS
 
    Specifies additional flags that are required to be passed to GCC when
-   building the SystemC model.  System 2.3.0 may need this set to
+   building the SystemC model. System 2.3.0 may need this set to
    "-pthread".
 
 .. option:: SYSTEMC_INCLUDE
@@ -67,27 +69,41 @@ associated programs.
 
 .. option:: SYSTEMC_LIBDIR
 
-   If set, specifies the directory containing the libsystemc.a library.  If
+   If set, specifies the directory containing the libsystemc.a library. If
    not specified, it will come from a default optionally specified at
    configure time (before Verilator was compiled), or computed from
    SYSTEMC/lib-SYSTEMC_ARCH.
 
 .. option:: VERILATOR_BIN
 
-   If set, specifies an alternative name of the ``verilator`` binary.  May
+   If set, specifies an alternative name of the ``verilator`` binary. May
    be used for debugging and selecting between multiple operating system
    builds.
 
 .. option:: VERILATOR_COVERAGE_BIN
 
    If set, specifies an alternative name of the ``verilator_coverage``
-   binary.  May be used for debugging and selecting between multiple
+   binary. May be used for debugging and selecting between multiple
    operating system builds.
 
 .. option:: VERILATOR_GDB
 
    If set, the command to run when using the :vlopt:`--gdb` option, such as
-   "ddd".  If not specified, it will use "gdb".
+   "ddd". If not specified, it will use "gdb".
+
+.. option:: VERILATOR_NUMA_STRATEGY
+
+   If set, controls NUMA assignment strategy for Verilator's thread pool
+   for Verilated simulations at runtime.
+   Possible values are:
+
+   * Empty(``""``) or ``"default"``: Enables NUMA assignment that prioritizes
+     assigning Verilator threads to physical cores.
+
+   * ``"none"``: Disables NUMA assignment. Let the operating system handle
+     thread scheduling.
+
+   Other values may be supported in future releases.
 
 .. option:: VERILATOR_ROOT
 
@@ -110,7 +126,7 @@ associated programs.
 
    If you are using a pre-compiled Verilator package, you should not need
    to set ``VERILATOR_ROOT`` - the value embedded in the binary should be
-   correct.  In fact this option *does not work* with Verilator packages
+   correct. In fact this option *does not work* with Verilator packages
    that have been installed with ``make install``. If a Verilator package
    has been installed using ``./configure --prefix=/some/path && make
    install`` and then moved to another location, you cannot use
@@ -121,13 +137,15 @@ associated programs.
 .. option:: VERILATOR_SOLVER
 
    If set, the command to run as a constrained randomization backend, such
-   as :command:`cvc4 --lang=smt2 --incremental`.  If not specified, it will use
-   the one supplied or found during configure, or :command:`z3 --in` if empty.
+   as :command:`cvc4 --lang=smt2 --incremental`. If not specified, it will
+   use the one supplied or found during configure, or :command:`z3 --in` if
+   empty.
 
 .. option:: VERILATOR_VALGRIND
 
-   If set, the command to run when using the :vlopt:`--valgrind` option, such as
-   "valgrind --tool=callgrind".  If not specified, it will use "valgrind".
+   If set, the command to run when using the :vlopt:`--valgrind` option,
+   such as "valgrind --tool=callgrind". If not specified, it will use
+   "valgrind".
 
 
 Make Variables
@@ -146,7 +164,7 @@ set by passing them to make e.g. ``make CXX=my-gcc ...``.
 
    Optionally overrides the default compiler binary used by the Verilated
    makefiles. If CXX is not set, the version found at configure time is
-   used.  Note the default flags passed to the compiler are determined at
+   used. Note the default flags passed to the compiler are determined at
    configuration time, so changing the CXX compiler version using this
    variable, as opposed to passing it at configuration time, may not give
    desired results.
@@ -155,7 +173,7 @@ set by passing them to make e.g. ``make CXX=my-gcc ...``.
 
    Optionally overrides the default linker binary used by the Verilated
    makefiles. If LINK is not set, the version found at configure time is
-   used.  Note the default flags passed to the linker are determined at
+   used. Note the default flags passed to the linker are determined at
    configuration time, so changing the LINK version using this variable, as
    opposed to passing it at configuration time, may not give desired
    results.

docs/guide/example_binary.rst

@@ -1,14 +1,14 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Example Create-Binary Execution:
+.. _example create-binary execution:
 
 Example Create-Binary Execution
 ===============================
 
-We'll compile this SystemVerilog example into a Verilated simulation binary.  For
-an example that discusses the next level of detail see :ref:`Example C++
-Execution`.
+We'll compile this SystemVerilog example into a Verilated simulation
+binary. For an example that discusses the next level of detail see
+:ref:`Example C++ Execution`.
 
 .. include:: example_common_install.rst
 
@@ -16,20 +16,20 @@ Now, let's create an example Verilog file:
 
 .. code-block:: bash
 
-     mkdir test_our
-     cd test_our
+   mkdir test_our
+   cd test_our
 
-     cat >our.v <<'EOF'
-       module our;
-          initial begin $display("Hello World"); $finish; end
-       endmodule
-     EOF
+   cat >our.v <<'EOF'
+     module our;
+        initial begin $display("Hello World"); $finish; end
+     endmodule
+   EOF
 
 Now we run Verilator on our little example.
 
 .. code-block:: bash
 
-     verilator --binary -j 0 -Wall our.v
+   verilator --binary -j 0 -Wall our.v
 
 Breaking this command down:
 
@@ -39,8 +39,7 @@ Breaking this command down:
 #. :vlopt:`-j` `0` to Verilate using use as many CPU threads as the machine
    has.
 
-#. :vlopt:`-Wall` so Verilator has stronger lint warnings
-   enabled.
+#. :vlopt:`-Wall` so Verilator has stronger lint warnings enabled.
 
 #. An finally, :command:`our.v`, which is our SystemVerilog design file.
 
@@ -48,16 +47,16 @@ And now we run it:
 
 .. code-block:: bash
 
-     obj_dir/Vour
+   obj_dir/Vour
 
 And we get as output:
 
 .. code-block:: bash
 
-     Hello World
-     - our.v:2: Verilog $finish
+   Hello World
+   - our.v:2: Verilog $finish
 
 You're better off using a Makefile to run the steps for you, so when your
-source changes, it will automatically run all of the appropriate steps.  To
-aid this, Verilator can create a makefile dependency file.  For examples
+source changes, it will automatically run all of the appropriate steps. To
+aid this, Verilator can create a makefile dependency file. For examples
 that do this, see the :file:`examples` directory in the distribution.

docs/guide/example_cc.rst

@@ -1,12 +1,12 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Example C++ Execution:
+.. _example c++ execution:
 
 Example C++ Execution
 =====================
 
-We'll compile this example into C++.  For an extended and commented version
+We'll compile this example into C++. For an extended and commented version
 of what this C++ code is doing, see
 :file:`examples/make_tracing_c/sim_main.cpp` in the distribution.
 
@@ -16,34 +16,34 @@ Now, let's create an example Verilog and C++ wrapper file:
 
 .. code-block:: bash
 
-     mkdir test_our
-     cd test_our
+   mkdir test_our
+   cd test_our
 
-     cat >our.v <<'EOF'
-       module our;
-          initial begin $display("Hello World"); $finish; end
-       endmodule
-     EOF
+   cat >our.v <<'EOF'
+     module our;
+        initial begin $display("Hello World"); $finish; end
+     endmodule
+   EOF
 
-     cat >sim_main.cpp <<'EOF'
-       #include "Vour.h"
-       #include "verilated.h"
-       int main(int argc, char** argv) {
-           VerilatedContext* contextp = new VerilatedContext;
-           contextp->commandArgs(argc, argv);
-           Vour* top = new Vour{contextp};
-           while (!contextp->gotFinish()) { top->eval(); }
-           delete top;
-           delete contextp;
-           return 0;
-       }
-     EOF
+   cat >sim_main.cpp <<'EOF'
+     #include "Vour.h"
+     #include "verilated.h"
+     int main(int argc, char** argv) {
+         VerilatedContext* contextp = new VerilatedContext;
+         contextp->commandArgs(argc, argv);
+         Vour* top = new Vour{contextp};
+         while (!contextp->gotFinish()) { top->eval(); }
+         delete top;
+         delete contextp;
+         return 0;
+     }
+   EOF
 
 Now we run Verilator on our little example;
 
 .. code-block:: bash
 
-     verilator --cc --exe --build -j 0 -Wall sim_main.cpp our.v
+   verilator --cc --exe --build -j 0 -Wall sim_main.cpp our.v
 
 Breaking this command down:
 
@@ -60,8 +60,7 @@ Breaking this command down:
 #. :vlopt:`-j 0 <-j>` to Verilate using use as many CPU threads as the
    machine has.
 
-#. :vlopt:`-Wall` so Verilator has stronger lint warnings
-   enabled.
+#. :vlopt:`-Wall` so Verilator has stronger lint warnings enabled.
 
 #. And finally, :command:`our.v` which is our SystemVerilog design file.
 
@@ -70,7 +69,7 @@ Once Verilator completes we can see the generated C++ code under the
 
 .. code-block:: bash
 
-     ls -l obj_dir
+   ls -l obj_dir
 
 (See :ref:`Files Read/Written` for descriptions of some of the files that
 were created.)
@@ -79,16 +78,16 @@ And now we run it:
 
 .. code-block:: bash
 
-     obj_dir/Vour
+   obj_dir/Vour
 
 And we get as output:
 
 .. code-block:: bash
 
-     Hello World
-     - our.v:2: Verilog $finish
+   Hello World
+   - our.v:2: Verilog $finish
 
 You're better off using a Makefile to run the steps for you, so when your
-source changes, it will automatically run all of the appropriate steps.  To
-aid this, Verilator can create a makefile dependency file.  For examples
+source changes, it will automatically run all of the appropriate steps. To
+aid this, Verilator can create a makefile dependency file. For examples
 that do this, see the :file:`examples` directory in the distribution.

docs/guide/example_common_install.rst

@@ -1,16 +1,16 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-First you need Verilator installed, see :ref:`Installation`.  In brief, if
+First you need Verilator installed, see :ref:`Installation`. In brief, if
 you installed Verilator using the package manager of your operating system,
 or did a :command:`make install` to place Verilator into your default path,
 you do not need anything special in your environment, and should not have
-VERILATOR_ROOT set.  However, if you installed Verilator from sources and
+VERILATOR_ROOT set. However, if you installed Verilator from sources and
 want to run Verilator out of where you compiled Verilator, you need to
 point to the kit:
 
 .. code-block:: bash
 
-     # See above; don't do this if using an OS-distributed Verilator
-     export VERILATOR_ROOT=/path/to/where/verilator/was/installed
-     export PATH=$VERILATOR_ROOT/bin:$PATH
+   # See above; don't do this if using an OS-distributed Verilator
+   export VERILATOR_ROOT=/path/to/where/verilator/was/installed
+   export PATH=$VERILATOR_ROOT/bin:$PATH

docs/guide/example_dist.rst

@@ -1,42 +1,52 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Examples in the Distribution:
+.. _examples in the distribution:
 
 Examples in the Distribution
 ============================
 
-See the ``examples/`` directory that is part of the distribution, and
-is installed (in an OS-specific place, often in e.g.
-``/usr/local/share/verilator/examples``).  These examples include:
+See the ``examples/`` directory that is part of the distribution, and is
+installed (in an OS-specific place, often in e.g.
+``/usr/local/share/verilator/examples``). These examples include:
 
 examples/make_hello_binary
    Example GNU-make simple Verilog->binary conversion
+
 examples/make_hello_c
    Example GNU-make simple Verilog->C++ conversion
+
 examples/make_hello_sc
    Example GNU-make simple Verilog->SystemC conversion
+
 examples/make_tracing_c
    Example GNU-make Verilog->C++ with tracing
+
 examples/make_tracing_sc
    Example GNU-make Verilog->SystemC with tracing
+
 examples/make_protect_lib
    Example using --protect-lib
+
 examples/cmake_hello_c
    Example building make_hello_c with CMake
+
 examples/cmake_hello_sc
    Example building make_hello_sc with CMake
+
 examples/cmake_tracing_c
    Example building make_tracing_c with CMake
+
 examples/cmake_tracing_sc
    Example building make_tracing_sc with CMake
+
 examples/cmake_protect_lib
    Example building make_protect_lib with CMake
 
 To run an example copy the example to a new directory and run it.
 
-::
+.. code-block:: bash
 
-      cp -rp {path_to}/examples/make_hello_c make_hello_c
-      cd make_hello_c
-      make
+   cp -rp {path_to}/examples/make_hello_c make_hello_c
+   cd make_hello_c
+   make

docs/guide/example_sc.rst

@@ -1,7 +1,7 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Example SystemC Execution:
+.. _example systemc execution:
 
 Example SystemC Execution
 =========================
@@ -15,58 +15,58 @@ Now, let's create an example Verilog, and SystemC wrapper file:
 
 .. code-block:: bash
 
-     mkdir test_our_sc
-     cd test_our_sc
+   mkdir test_our_sc
+   cd test_our_sc
 
-     cat >our.v <<'EOF'
-       module our (clk);
-          input clk;  // Clock is required to get initial activation
-          always @(posedge clk)
-             begin $display("Hello World"); $finish; end
-       endmodule
-     EOF
+   cat >our.v <<'EOF'
+     module our (clk);
+        input clk;  // Clock is required to get initial activation
+        always @(posedge clk)
+           begin $display("Hello World"); $finish; end
+     endmodule
+   EOF
 
-     cat >sc_main.cpp <<'EOF'
-       #include "Vour.h"
-       using namespace sc_core;
-       int sc_main(int argc, char** argv) {
-           Verilated::commandArgs(argc, argv);
-           sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true};
-           Vour* top = new Vour{"top"};
-           top->clk(clk);
-           while (!Verilated::gotFinish()) { sc_start(1, SC_NS); }
-           delete top;
-           return 0;
-       }
-     EOF
+   cat >sc_main.cpp <<'EOF'
+     #include "Vour.h"
+     using namespace sc_core;
+     int sc_main(int argc, char** argv) {
+         Verilated::commandArgs(argc, argv);
+         sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true};
+         Vour* top = new Vour{"top"};
+         top->clk(clk);
+         while (!Verilated::gotFinish()) { sc_start(1, SC_NS); }
+         delete top;
+         return 0;
+     }
+   EOF
 
 Now we run Verilator on our little example:
 
 .. code-block:: bash
 
-     verilator --sc --exe -Wall sc_main.cpp our.v
+   verilator --sc --exe -Wall sc_main.cpp our.v
 
 This example does not use --build, therefore we need to explicitly compile
 it:
 
 .. code-block:: bash
 
-     make -j -C obj_dir -f Vour.mk Vour
+   make -j -C obj_dir -f Vour.mk Vour
 
 And now we run it:
 
 .. code-block:: bash
 
-     obj_dir/Vour
+   obj_dir/Vour
 
 And we get, after the SystemC banner, the same output as the C++ example:
 
 .. code-block:: bash
 
-     SystemC 2.3.3-Accellera
+   SystemC 2.3.3-Accellera
 
-     Hello World
-     - our.v:4: Verilog $finish
+   Hello World
+   - our.v:4: Verilog $finish
 
 Really, you're better off using a Makefile to run the steps for you so when
 your source changes it will automatically run all of the appropriate steps.

docs/guide/examples.rst

@@ -1,7 +1,7 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Examples:
+.. _examples:
 
 ========
 Examples

docs/guide/exe_sim.rst

@@ -1,14 +1,14 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Simulation Runtime Arguments:
+.. _simulation runtime arguments:
 
 Simulation Runtime Arguments
 ============================
 
 The following are the arguments that may be passed to a Verilated
 executable, provided that executable calls
-:code:`VerilatedContext*->commandArgs(argc, argv)`.
+``VerilatedContext*->commandArgs(argc, argv)``.
 
 All simulation runtime arguments begin with "+verilator", so that the
 user's executable may skip over all "+verilator" arguments when parsing its
@@ -18,15 +18,16 @@ Summary:
 
    .. include:: ../_build/gen/args_verilated.rst
 
+Options:
 
 .. option:: +verilator+coverage+file+<filename>
 
    When a model was Verilated using :vlopt:`--coverage`, sets the filename
-   to write coverage data into.  Defaults to :file:`coverage.dat`.
+   to write coverage data into. Defaults to :file:`coverage.dat`.
 
 .. option:: +verilator+debug
 
-   Enable simulation runtime debugging.  Equivalent to
+   Enable simulation runtime debugging. Equivalent to
    :vlopt:`+verilator+debugi+4 <+verilator+debugi+\<value\>>`.
 
    To be useful, the model typically must first be compiled with debug
@@ -50,12 +51,12 @@ Summary:
 .. option:: +verilator+noassert
 
    Disable assert checking per runtime argument. This is the same as
-   calling :code:`VerilatedContext*->assertOn(false)` in the model.
+   calling ``VerilatedContext*->assertOn(false)`` in the model.
 
 .. option:: +verilator+prof+exec+file+<filename>
 
    When a model was Verilated using :vlopt:`--prof-exec`, sets the
-   simulation runtime filename to dump to.  Defaults to
+   simulation runtime filename to dump to. Defaults to
    :file:`profile_exec.dat`.
 
 .. option:: +verilator+prof+exec+start+<value>
@@ -72,9 +73,9 @@ Summary:
    When a model was Verilated using :vlopt:`--prof-exec`, after $time
    reaches :vlopt:`+verilator+prof+exec+start+\<value\>`, Verilator will
    warm up the profiling for this number of eval() calls, then will capture
-   the profiling of this number of eval() calls.  Defaults to 2, which
-   makes sense for a single-clock-domain module where it's typical to want
-   to capture one posedge eval() and one negedge eval().
+   the profiling of this number of eval() calls. Defaults to 2, which makes
+   sense for a single-clock-domain module where it's typical to want to
+   capture one posedge eval() and one negedge eval().
 
 .. option:: +verilator+prof+threads+file+<filename>
 
@@ -94,7 +95,7 @@ Summary:
 .. option:: +verilator+prof+vlt+file+<filename>
 
    When a model was Verilated using :vlopt:`--prof-pgo`, sets the
-   profile-guided optimization data runtime filename to dump to.  Defaults
+   profile-guided optimization data runtime filename to dump to. Defaults
    to :file:`profile.vlt`.
 
 .. option:: +verilator+quiet
@@ -104,17 +105,23 @@ Summary:
 
 .. option:: +verilator+rand+reset+<value>
 
-   When a model was Verilated using
-   :vlopt:`--x-initial unique <--x-initial>`, sets the simulation runtime
-   initialization technique.  0 = Reset to zeros. 1 = Reset to all-ones.  2
-   = Randomize.  See :ref:`Unknown States`.
+   When a model was Verilated using :vlopt:`--x-initial unique
+   <--x-initial>`, sets the simulation runtime initialization technique. 0
+   = Reset to zeros. 1 = Reset to all-ones. 2 = Randomize. See
+   :ref:`Unknown States`.
 
 .. option:: +verilator+seed+<value>
 
    For $random and :vlopt:`--x-initial unique <--x-initial>`, set the
-   simulation runtime random seed value.  If zero or not specified picks a
+   simulation runtime random seed value. If zero or not specified picks a
    value from the system random number generator.
 
+.. option:: +verilator+solver+file+<filename>
+
+   If specified, when the randomization solver is used, open the given
+   filename for writing, and log all random solver commands and responses
+   to it.
+
 .. option:: +verilator+V
 
    Shows the verbose version, including configuration information.
@@ -122,3 +129,11 @@ Summary:
 .. option:: +verilator+version
 
    Displays program version and exits.
+
+.. option:: +verilator+wno+unsatconstr+<value>
+
+   Disable unsatisfied constraint warnings at simulation runtime. When set to
+   1, warnings about unsatisfied constraints during ``randomize()`` calls will
+   not be displayed. Defaults to 0 (warnings enabled). This can also be
+   controlled via the C++ API using
+   ``Verilated::threadContextp()->warnUnsatConstr(false)``.

docs/guide/exe_verilator_coverage.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 verilator_coverage
@@ -7,7 +7,7 @@ verilator_coverage
 Verilator_coverage processes Verilated model-generated coverage reports.
 
 With `--annotate`, it reads the specified coverage data file and generates
-annotated source code with coverage metrics annotated.  With
+annotated source code with coverage metrics annotated. With
 `--annotate-points` the coverage points corresponding to each line are also
 shown.
 
@@ -21,25 +21,26 @@ those statistics of interest and save to a new .dat file.
 
 For Verilog conditions that should never occur, either add a $stop
 statement to the appropriate statement block, or see
-:option:`/*verilator&32;coverage_off*/`.  This will remove the coverage
+:option:`/*verilator&32;coverage_off*/`. This will remove the coverage
 points after the model is re-Verilated.
 
-For an overview of the use of verilator_coverage, see :ref:`Coverage Analysis`.
+For an overview of the use of verilator_coverage, see :ref:`Coverage
+Analysis`.
 
 
 verilator_coverage Example Usage
 --------------------------------
 
-..
+.. code-block:: bash
 
-    verilator_coverage --help
-    verilator_coverage --version
+   verilator_coverage --help
+   verilator_coverage --version
 
-    verilator_coverage --annotate obj_dir coverage.dat
+   verilator_coverage --annotate obj_dir coverage.dat
 
-    verilator_coverage --write merged.dat coverage.dat ...
+   verilator_coverage --write merged.dat coverage.dat ...
 
-    verilator_coverage --write-info merged.info coverage.dat ...
+   verilator_coverage --write-info merged.info coverage.dat ...
 
 
 verilator_coverage Arguments
@@ -49,8 +50,8 @@ verilator_coverage Arguments
 
 .. option:: <filename>
 
-   Specifies the input coverage data file.  Multiple filenames may be
-   provided to read multiple inputs.  If no data file is specified, by
+   Specifies the input coverage data file. Multiple filenames may be
+   provided to read multiple inputs. If no data file is specified, by
    default, "coverage.dat" will be read.
 
 .. option:: --annotate <output_directory>
@@ -59,8 +60,8 @@ verilator_coverage Arguments
    coverage data should be written.
 
    Points are children of each line coverage- branches, expressions or
-   toggle points.  When point counts are aggregated into a line, the
-   minimum and maximum counts are used to determine the status of the line
+   toggle points. When point counts are aggregated into a line, the minimum
+   and maximum counts are used to determine the status of the line
    (complete, partial, failing) The count is equal to the maximum of the
    points.
 
@@ -73,27 +74,28 @@ verilator_coverage Arguments
    * "%" indicates that all points on the line are below the coverage min.
    * "~" indicates that some points on the line are above the coverage min and some are below.
    * "+" coverage point was at or above the min. Only used with :option:`--annotate-points`.
-   * "-" coverage point was below the min.  Only used with :option:`--annotate-points`.
+   * "-" coverage point was below the min. Only used with
+     :option:`--annotate-points`.
 
    .. code-block::
 
-      100000  input logic a;      // Begins with whitespace, because
-                                  // number of hits (100000) is above the min.
-     +100000  point: comment=a    // Begins with +, because
-                                  // number of hits (100000) is above the min.
-     %000000  input logic b;      // Begins with %, because
-                                  // number of hits (0) is below the min.
-     -000000  point: comment=b    // Begins with -, because
-                                  // number of hits (0) is below the min.
-     ~000010  if (cyc!=0) begin   // Begins with ~, because
-                                  // branches are below and above the min.
-     +000010  point: comment=if   // The if branch is above the min.
-     -000000  point: comment=else // The else branch is below the min.
+      100000  input logic a;                  // Begins with whitespace, because
+                                              // number of hits (100000) is above the min.
+     +100000  point: type=line comment=a      // Begins with +, because
+                                              // number of hits (100000) is above the min.
+     %000000  input logic b;                  // Begins with %, because
+                                              // number of hits (0) is below the min.
+     -000000  point: type=line comment=b      // Begins with -, because
+                                              // number of hits (0) is below the min.
+     ~000010  if (cyc!=0) begin               // Begins with ~, because
+                                              // branches are below and above the min.
+     +000010  point: type=branch comment=if   // The if branch is above the min.
+     -000000  point: type=branch comment=else // The else branch is below the min.
 
 .. option:: --annotate-all
 
-   Specifies all files should be shown.  By default, only those source
-   files with low coverage are written to the output directory.
+   Specifies all files should be shown. By default, only those source files
+   with low coverage are written to the output directory.
 
    This option should be used together with :option:`--annotate`.
 
@@ -111,15 +113,15 @@ verilator_coverage Arguments
 
 .. option:: --annotate-points
 
-   Specifies all coverage points should be shown after each line of text.  By
-   default, only source lines are shown.
+   Specifies all coverage points should be shown after each line of text.
+   By default, only source lines are shown.
 
    .. code-block::
 
      100000  input logic a, b, c;
-    +100000 point: comment=a  // These lines are only shown
-    +200000 point: comment=b  // with option --annotate-points
-    +300000 point: comment=c  // enabled.
+    +100000 point: type=line comment=a  // These lines are only shown
+    +200000 point: type=line comment=b  // with option --annotate-points
+    +300000 point: type=line comment=c  // enabled.
 
 
    This option should be used together with :option:`--annotate`.
@@ -137,7 +139,7 @@ verilator_coverage Arguments
 .. option:: --rank
 
    Prints an experimental report listing the relative importance of each
-   test in covering all of the coverage points.  The report shows "Covered"
+   test in covering all of the coverage points. The report shows "Covered"
    which indicates the number of points the test covers; a test is
    considered to cover a point if it has a bucket count of at least 1. The
    "rank" column has a higher number t indicate the test is more critical,
@@ -159,7 +161,7 @@ verilator_coverage Arguments
 
    Specifies the aggregate coverage results, summed across all the files,
    should be written to the given filename in verilator_coverage data
-   format.  This is useful in scripts to combine many coverage data files
+   format. This is useful in scripts to combine many coverage data files
    (likely generated from random test runs) into one master coverage file.
 
 .. option:: --write-info <filename.info>

docs/guide/exe_verilator_gantt.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 verilator_gantt
@@ -31,50 +31,50 @@ In waveforms, there are the following signals. In GTKWave, use "decimal"
 data format to remove the leading zeros and make the traces easier to read.
 
 trace/section
-  Shows the name of the current top of the execution section stack.
-  Set GTKWave data format to "ASCII".
+   Shows the name of the current top of the execution section stack. Set
+   GTKWave data format to "ASCII".
 
 trace/depth
-  Shows the depth of the execution section stack.
-  Set GTKWave data format to "Analog".
+   Shows the depth of the execution section stack. Set GTKWave data format
+   to "Analog".
 
 measured_parallelism
-  The number of mtasks active at this time, for best performance, this will
-  match the thread count. In GTKWave, use a data format of "analog step" to
-  view this signal.
+   The number of mtasks active at this time, for best performance, this
+   will match the thread count. In GTKWave, use a data format of "analog
+   step" to view this signal.
 
 predicted_parallelism
-  The number of mtasks Verilator predicted would be active at this time,
-  for best performance this will match the thread count. In GTKWave, use a
-  data format of "analog step" to view this signal.
+   The number of mtasks Verilator predicted would be active at this time,
+   for best performance this will match the thread count. In GTKWave, use a
+   data format of "analog step" to view this signal.
 
 cpu#_thread
-  For the given CPU number, the thread number measured to be executing.
+   For the given CPU number, the thread number measured to be executing.
 
 cpu#_waiting
-  For the given CPU number, aggregated waiting time for mtask dependencies.
-  Visualized as `X` values.
+   For the given CPU number, aggregated waiting time for mtask
+   dependencies. Visualized as `X` values.
 
 mtask#_cpu
-  For the given mtask id, the CPU it was measured to execute on.
+   For the given mtask id, the CPU it was measured to execute on.
 
 thread#_mtask
-  For the given thread number, the mtask id it was executing.
+   For the given thread number, the mtask id it was executing.
 
 predicted_thread#_mtask
-  For the given thread number, the mtask id Verilator predicted would be
-  executing.
+   For the given thread number, the mtask id Verilator predicted would be
+   executing.
 
 
 verilator_gantt Example Usage
 -----------------------------
 
-..
+.. code-block:: bash
 
-    verilator_gantt --help
-    verilator_gantt --version
+   verilator_gantt --help
+   verilator_gantt --version
 
-    verilator_gantt profile_exec.dat
+   verilator_gantt profile_exec.dat
 
 
 verilator_gantt Arguments

docs/guide/exe_verilator_profcfunc.rst

@@ -1,29 +1,29 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 verilator_profcfunc
 ===================
 
-Verilator_profcfunc reads a profile report created by gprof.  The names of
+Verilator_profcfunc reads a profile report created by gprof. The names of
 the functions are then transformed, assuming the user used Verilator's
 --prof-cfuncs, and a report printed showing the percentage of the time,
 etc., in each Verilog block.
 
 Due to rounding errors in gprof reports, the input report's percentages may
-not total 100%.  In the verilator_profcfunc report this will get
-reported as a rounding error.
+not total 100%. In the verilator_profcfunc report this will get reported as
+a rounding error.
 
 For an overview of the use of verilator_profcfunc, see :ref:`Profiling`.
 
 verilator_profcfunc Example Usage
 ---------------------------------
 
-..
+.. code-block:: bash
 
-    verilator_profcfunc --help
-    verilator_profcfunc --version
+   verilator_profcfunc --help
+   verilator_profcfunc --version
 
-    verilator_profcfunc gprof.out
+   verilator_profcfunc gprof.out
 
 
 verilator_profcfunc Arguments

docs/guide/executables.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *********************************

docs/guide/extensions.rst

@@ -1,35 +1,35 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-=====================
- Language Extensions
-=====================
+===================
+Language Extensions
+===================
 
 The following additional constructs are the extensions Verilator supports
-on top of standard Verilog code.  Using these features outside of comments
+on top of standard Verilog code. Using these features outside of comments
 or "`ifdef`"'s may break other tools.
 
 .. option:: """ [string] """
 
    A triple-quoted block specifies a string that may include newlines and
-   single quotes.  This extension was standardized in IEEE 1800-2023.
+   single quotes. This extension was standardized in IEEE 1800-2023.
 
 .. option:: `__FILE__
 
    The :option:`\`__FILE__` define expands to the current filename as a
-   string, like C++'s __FILE__.  This Verilator feature, added in 2006, was
+   string, like C++'s __FILE__. This Verilator feature, added in 2006, was
    incorporated into IEEE 1800-2009.
 
 .. option:: `__LINE__
 
    The :option:`\`__LINE__` define expands to the current line number like
-   C++'s __LINE__.  This Verilator feature added in 2006 was incorporated
+   C++'s __LINE__. This Verilator feature added in 2006 was incorporated
    into IEEE 1800-2009.
 
 .. option:: `coverage_block_off
 
    Specifies the entire begin/end block should be ignored for coverage
-   analysis.  Must be inside a code block, e.g., within a begin/end pair.
+   analysis. Must be inside a code block, e.g., within a begin/end pair.
    Same as :option:`coverage_block_off` in :ref:`Verilator Control Files`.
 
 .. option:: `error [string]
@@ -50,14 +50,14 @@ or "`ifdef`"'s may break other tools.
    blocks, replaced with the C++ class name generated for the given
    containing SystemVerilog class or module. Currently this is replaced
    blindly, ignoring quoting or other escapes; this behavior may change in
-   the future.  This attribute is indented only to be used internally in
+   the future. This attribute is indented only to be used internally in
    `verilated_std.sv`.
 
 .. option:: `systemc_ctor
 
    Take the remaining text up to the next :option:`\`verilog` or
    :option:`\`systemc_... <\`systemc_header>` mode switch and place it
-   verbatim into the C++ class constructor.  Must be placed as a module or
+   verbatim into the C++ class constructor. Must be placed as a module or
    class item, e.g., directly inside a module/endmodule or class/endclass
    pair. Despite the name of this macro, this also works in pure C++ code.
 
@@ -65,7 +65,7 @@ or "`ifdef`"'s may break other tools.
 
    Take the remaining text up to the next :option:`\`verilog` or
    :option:`\`systemc_... <\`systemc_header>` mode switch and place it
-   verbatim into the C++ class destructor.  Must be placed as a module or
+   verbatim into the C++ class destructor. Must be placed as a module or
    class item, e.g., directly inside a module/endmodule or class/endclass
    pair. Despite the name of this macro, this also works in pure C++ code.
 
@@ -73,10 +73,9 @@ or "`ifdef`"'s may break other tools.
 
    Take the remaining text up to the next :option:`\`verilog` or
    :option:`\`systemc_... <\`systemc_header>` mode switch and place it
-   verbatim into the output .h file's header.  Must be placed as a module
-   or class item, e.g., directly inside a module/endmodule or
-   class/endclass pair. Despite the name of this macro, this also works in
-   pure C++ code.
+   verbatim into the output .h file's header. Must be placed as a module or
+   class item, e.g., directly inside a module/endmodule or class/endclass
+   pair. Despite the name of this macro, this also works in pure C++ code.
 
 .. option:: `systemc_header_post
 
@@ -100,21 +99,21 @@ or "`ifdef`"'s may break other tools.
 
    Take the remaining text up to the next :option:`\`verilog` or
    :option:`\`systemc_... <\`systemc_header>` mode switch and place it
-   verbatim into a single file of the C++ class implementation.  Must be
+   verbatim into a single file of the C++ class implementation. Must be
    placed as a module or class item, e.g., directly inside a
    module/endmodule or class/endclass pair. Despite the name of this macro,
    this also works in pure C++ code.
 
    If you will be reading or writing any Verilog variables in the C++
    functions, the Verilog signals must be declared with a
-   :option:`/*verilator&32;public*/` metacomment.  See also the public task
+   :option:`/*verilator&32;public*/` metacomment. See also the public task
    feature; writing an accessor may result in cleaner code.
 
 .. option:: `systemc_interface
 
    Take the remaining text up to the next :option:`\`verilog` or
    :option:`\`systemc_... <\`systemc_header>` mode switch and place it
-   verbatim into the C++ class interface.  Must be placed as a module or
+   verbatim into the C++ class interface. Must be placed as a module or
    class item, e.g., directly inside a module/endmodule or class/endclass
    pair. Despite the name of this macro, this also works in pure C++ code.
 
@@ -136,22 +135,22 @@ or "`ifdef`"'s may break other tools.
 .. option:: `verilator_config
 
    Take the remaining text up to the next :option:`\`verilog` mode switch
-   and treat it as Verilator Control File commands.  See :ref:`Verilator
+   and treat it as Verilator Control File commands. See :ref:`Verilator
    Control Files`.
 
 .. option:: `VERILATOR_TIMING
 
    The VERILATOR_TIMING define is set when :vlopt:`--timing` is used to
-   allow an "\`ifdef" of code dependent on this feature.  Note that this define
-   is not affected by the :option:`timing_off` control file option
+   allow an "\`ifdef" of code dependent on this feature. Note that this
+   define is not affected by the :option:`timing_off` control file option
    nor timing metacomments.
 
 .. option:: `verilog
 
-   Switch back to processing Verilog code after a
-   :option:`\`systemc_... <\`systemc_header>` mode switch.  The Verilog
-   code returns to the last language mode specified with
-   "\`begin_keywords", or SystemVerilog if none was specified.
+   Switch back to processing Verilog code after a :option:`\`systemc_...
+   <\`systemc_header>` mode switch. The Verilog code returns to the last
+   language mode specified with "\`begin_keywords", or SystemVerilog if
+   none was specified.
 
 
    .. t_dist_docs_style restart_sort
@@ -159,7 +158,7 @@ or "`ifdef`"'s may break other tools.
 .. option:: $c([string], ...);, $cpure([string], ...);
 
    The string will be embedded directly in the output C++ code at the point
-   where the surrounding Verilog code is compiled.  It may either be a
+   where the surrounding Verilog code is compiled. It may either be a
    standalone statement (with a trailing ; in the string), or a function
    that returns up to a 32-bit number (without a trailing ;). This can be
    used to call C++ functions from your Verilog code.
@@ -171,28 +170,27 @@ or "`ifdef`"'s may break other tools.
    via an explicit 'this->' pointer dereference.
 
    Expression arguments will have the code to evaluate the expression
-   inserted.  Thus to call a C++ function, :code:`$c("func(",a,")")` will
-   result in :code:`func(a)` in the output C++ code.  For input arguments,
-   rather than hard-coding variable names in the string
-   :code:`$c("func(a)")`, instead pass the variable as an expression
-   ::code:`$c("func(",a,")")`.  This will allow the call to work inside
-   Verilog functions where the variable is flattened out and enable other
-   optimizations.
+   inserted. Thus to call a C++ function, ``$c("func(",a,")")`` will result
+   in ``func(a)`` in the output C++ code. For input arguments, rather than
+   hard-coding variable names in the string ``$c("func(a)")``, instead pass
+   the variable as an expression :``$c("func(",a,")")``. This will allow
+   the call to work inside Verilog functions where the variable is
+   flattened out and enable other optimizations.
 
    Verilator does not use any text inside the quotes for
-   ordering/scheduling.  If you need the $c to be called at a specific
-   time, e.g., when a variable changes, then the $c must be under an
-   appropriate sensitivity statement, e.g.,
-   :code:`always @(posedge clk) $c("func()")` to call it on every edge, or,
-   e.g., :code:`always @* c("func(",a,")")` to call it when :code:`a`
-   changes (the latter working because :code:`a` is outside the quotes).
+   ordering/scheduling. If you need the $c to be called at a specific time,
+   e.g., when a variable changes, then the $c must be under an appropriate
+   sensitivity statement, e.g., ``always @(posedge clk) $c("func()")`` to
+   call it on every edge, or, e.g., ``always @* c("func(",a,")")`` to call
+   it when ``a`` changes (the latter working because ``a`` is outside the
+   quotes).
 
    If you will be reading or writing any Verilog variables inside the C++
    functions, the Verilog signals must be declared with
    :option:`/*verilator&32;public*/` metacomments.
 
-   You may also append a number to $c, which specifies the bit width of
-   the output, e.g., :code:`signal_32_bits = $c32("...");`.  This allows for
+   You may also append a number to $c, which specifies the bit width of the
+   output, e.g., ``signal_32_bits = $c32("...");``. This allows for
    compatibility with other simulators, which require a differently named
    PLI function name for each different output width.
 
@@ -203,31 +201,39 @@ or "`ifdef`"'s may break other tools.
 
 .. option:: $display, $write, $fdisplay, $fwrite, $sformat, $swrite
 
-   Format arguments may use C fprintf sizes after the % escape.  Per the
+   Format arguments may use C fprintf sizes after the % escape. Per the
    Verilog standard, %x prints a number with the natural width, and %0x
-   prints a number with minimum width.  Verilator extends this so %5x
-   prints 5 digits per the C standard. This extension was standardized into
+   prints a number with minimum width. Verilator extends this so %5x prints
+   5 digits per the C standard. This extension was standardized into
    1800-2009.
 
+.. option:: $get_initial_random_seed()
+
+   Returns an integer with the initial random seed used for the simulation.
+   This is the value provided via the :vlopt:`+verilator+seed+\<value\>`
+   runtime option. If no seed is specified, it returns the default
+   initialization seed (typically 0). This is not defined by IEEE
+   1800-2023, but most simulators support it.
+
 .. option:: $stacktrace
 
-   Called as a task, print a stack trace.  Called as a function, return a
-   string with a stack trace.  This relies on the C++ system trace, which
+   Called as a task, print a stack trace. Called as a function, return a
+   string with a stack trace. This relies on the C++ system trace, which
    may give less meaningful results if the model is not compiled with debug
-   symbols.  Also, the data represents the C++ stack; the SystemVerilog
+   symbols. Also, the data represents the C++ stack; the SystemVerilog
    functions/tasks involved may be renamed and/or inlined before becoming
-   the C++ functions that may be visible in the stack trace.  This
-   extension was standardized in IEEE 1800-2023.
+   the C++ functions that may be visible in the stack trace. This extension
+   was standardized in IEEE 1800-2023.
 
 .. option:: $timeprecision
 
-   Returns the timeprecision of the model as an integer.  This extension is
+   Returns the timeprecision of the model as an integer. This extension is
    experimental and may be removed without deprecation.
 
 .. option:: $timeunit
 
-   Returns the timeunit of the current module as an integer.  This
-   extension is experimental and may be removed without deprecation.
+   Returns the timeunit of the current module as an integer. This extension
+   is experimental and may be removed without deprecation.
 
 .. option:: /*verilator&32;clock_enable*/
 
@@ -242,10 +248,10 @@ or "`ifdef`"'s may break other tools.
 
    .. code-block:: sv
 
-         reg enable_r /*verilator clock_enable*/;
-         wire gated_clk = clk & enable_r;
-         always_ff @(posedge clk)
-           enable_r <= enable_early;
+      reg enable_r /*verilator clock_enable*/;
+      wire gated_clk = clk & enable_r;
+      always_ff @(posedge clk)
+        enable_r <= enable_early;
 
    The clock_enable attribute will cause the clock gate to be ignored in
    the scheduling algorithm, sometimes required for correct clock behavior,
@@ -287,6 +293,15 @@ or "`ifdef`"'s may break other tools.
    (if appropriate :vlopt:`--coverage` flags are passed) after being
    disabled earlier with :option:`/*verilator&32;coverage_off*/`.
 
+.. option:: /*verilator&32;fargs <arguments>*/
+
+   For Verilator developers only. When a source file containing these `fargs`
+   metacomments is passed to Verilator on the command line via the :vlopt:`-f`
+   or :vlopt:`-F` option, the provided arguments will be added as if specified
+   on the command line. The source file is not preprocessed before parsing for
+   arguments, and all `fargs` comments will take effect, even if placed
+   undef an inactive `\`ifdef`.
+
 .. option:: /*verilator&32;forceable*/
 
    Specifies that the signal (net or variable) should be made forceable from
@@ -306,10 +321,10 @@ or "`ifdef`"'s may break other tools.
 
 .. option:: /*verilator&32;hier_block*/
 
-   Specifies that the module is a unit of hierarchical Verilation.  This
-   metacomment must be between :code:`module module_name(...);` and
-   :code:`endmodule`.  The module will not be inlined nor uniquified for
-   each instance in hierarchical Verilation.  Note that the metacomment is
+   Specifies that the module is a unit of hierarchical Verilation. This
+   metacomment must be between ``module module_name(...);`` and
+   ``endmodule``. The module will not be inlined nor uniquified for each
+   instance in hierarchical Verilation. Note that the metacomment is
    ignored unless the :vlopt:`--hierarchical` option is specified.
 
    See :ref:`Hierarchical Verilation`.
@@ -317,17 +332,17 @@ or "`ifdef`"'s may break other tools.
 .. option:: /*verilator&32;inline_module*/
 
    Specifies the module the comment appears in may be inlined into any
-   modules that use this module.  This is useful to speed up simulation
-   runtime.  Note if using :vlopt:`--public` that signals under inlined
-   submodules will be named :code:`{submodule}__DOT__{subsignal}` as C++
-   does not allow "." in signal names.
+   modules that use this module. This is useful to speed up simulation
+   runtime. Note if using :vlopt:`--public` that signals under inlined
+   submodules will be named ``{submodule}__DOT__{subsignal}`` as C++ does
+   not allow "." in signal names.
 
    Same as :option:`inline` control file option.
 
 .. option:: /*verilator&32;isolate_assignments*/
 
    Used after a signal declaration to indicate the assignments to this
-   signal in any blocks should be isolated into new blocks.  When large
+   signal in any blocks should be isolated into new blocks. When large
    combinatorial block results in a :option:`UNOPTFLAT` warning, attaching
    this to the signal that was causing a false loop may work around the
    warning.
@@ -336,14 +351,14 @@ or "`ifdef`"'s may break other tools.
 
    .. code-block:: sv
 
-         reg splitme /* verilator isolate_assignments*/;
-         // Note the placement of the semicolon above
-         always_comb begin
-           if (....) begin
-             splitme = ....;
-             other assignments
-           end
-         end
+      reg splitme /* verilator isolate_assignments*/;
+      // Note the placement of the semicolon above
+      always_comb begin
+        if (....) begin
+          splitme = ....;
+          other assignments
+        end
+      end
 
    Verilator will internally split the block that assigns to "splitme" into
    two blocks:
@@ -370,36 +385,36 @@ or "`ifdef`"'s may break other tools.
 .. option:: /*verilator&32;lint_off <msgs>*/
 
    Disable the specified warning message(s) for any warnings following the
-   comment.  Multiple messages may be specified, separated with commas.
+   comment. Multiple messages may be specified, separated with commas.
 
    If a one-line slash-slash-format comment is used, then the metacomment
    ends at the newline or at an earlier next slash-slash. This allow
-   commenting the reason for the disable, e.g. :code:`// verilator lint_off
-   MSG // Because...`.
+   commenting the reason for the disable, e.g. ``// verilator lint_off
+   MSG // Because...``.
 
 .. option:: /*verilator&32;lint_on <msgs>*/
 
    Re-enable the specified warning message(s) for any warnings following
-   the comment.  Multiple messages may be specified, separated with commas.
+   the comment. Multiple messages may be specified, separated with commas.
 
 .. option:: /*verilator&32;lint_restore*/
 
-   After a :code:`/*verilator&32;lint_save*/`, pop the stack containing lint
-   message state.  Often this is useful at the bottom of include files.
+   After a ``/*verilator&32;lint_save*/``, pop the stack containing lint
+   message state. Often this is useful at the bottom of include files.
 
 .. option:: /*verilator&32;lint_save*/
 
-   Push the current state of what lint messages are turned on or off
-   to a stack.  Later meta-comments may then lint_on or lint_off specific
+   Push the current state of what lint messages are turned on or off to a
+   stack. Later meta-comments may then lint_on or lint_off specific
    messages, then return to the earlier message state by using
-   :code:`/*verilator&32;lint_restore*/`.  For example:
+   ``/*verilator&32;lint_restore*/``. For example:
 
    .. code-block:: sv
 
-         // verilator lint_save
-         // verilator lint_off WIDTH
-         ...  // code needing WIDTH turned off
-         // verilator lint_restore
+      // verilator lint_save
+      // verilator lint_off WIDTH
+      ...  // code needing WIDTH turned off
+      // verilator lint_restore
 
    If WIDTH was on before the lint_off, it would now be restored to on, and
    if it was off before the lint_off it would remain off.
@@ -414,11 +429,10 @@ or "`ifdef`"'s may break other tools.
 .. option:: /*verilator&32;no_inline_task*/
 
    Used in a function or task variable definition section to specify the
-   function or task should not be inlined into where it is used.  This may
+   function or task should not be inlined into where it is used. This may
    reduce the size of the final executable when a task is used a very large
-   number of times.  For this flag to work, the task and tasks below it
-   must be pure; they cannot reference any variables outside the task
-   itself.
+   number of times. For this flag to work, the task and tasks below it must
+   be pure; they cannot reference any variables outside the task itself.
 
    Same as :option:`no_inline` control file option.
 
@@ -430,21 +444,21 @@ or "`ifdef`"'s may break other tools.
 
    .. code-block:: sv
 
-         parameter [2:0] PARAM /*verilator public*/ = 2'b0;
+      parameter [2:0] PARAM /*verilator public*/ = 2'b0;
 
 .. option:: /*verilator&32;public*/ (on task/function)
 
    Used inside the declaration section of a function or task declaration to
    indicate the function or task should be made into a C++ function, public
-   to outside callers.  Public tasks will be declared as a void C++
+   to outside callers. Public tasks will be declared as a void C++
    function, public functions will get the appropriate non-void (bool,
-   uint32_t, etc.) return type.  Any input arguments will become C++
-   arguments to the function.  Any output arguments will become C++
-   reference arguments.  Any local registers/integers will become function
+   uint32_t, etc.) return type. Any input arguments will become C++
+   arguments to the function. Any output arguments will become C++
+   reference arguments. Any local registers/integers will become function
    automatic variables on the stack.
 
    Wide variables over 64 bits cannot be function returns, to avoid
-   exposing complexities.  However, wide variables can be input/outputs;
+   exposing complexities. However, wide variables can be input/outputs;
    they will be passed as references to an array of 32-bit numbers.
 
    Generally, only the values of stored state (flops) should be written, as
@@ -464,17 +478,17 @@ or "`ifdef`"'s may break other tools.
 
    .. code-block:: sv
 
-         typedef enum logic [2:0] { ZERO = 3'b0 } pub_t /*verilator public*/;
+      typedef enum logic [2:0] { ZERO = 3'b0 } pub_t /*verilator public*/;
 
 .. option:: /*verilator&32;public*/ (on variable)
 
    Used after an input, output, register, or wire declaration to indicate
    the signal should be declared so that C code may read or write the value
-   of the signal.  This will also declare this module public; otherwise, use
-   :code:`/*verilator&32;public_flat*/`.
+   of the signal. This will also declare this module public; otherwise, use
+   ``/*verilator&32;public_flat*/``.
 
    Instead of using public variables, consider making a DPI or public
-   function that accesses the variable.  This is nicer as it provides an
+   function that accesses the variable. This is nicer as it provides an
    obvious entry point compatible across simulators.
 
    Same as :option:`public` control file option.
@@ -484,30 +498,30 @@ or "`ifdef`"'s may break other tools.
    Used to wrap multiple signals and parameters with the respective public attribute.
    See attribute above for their respective behavior. Cannot be nested. e.g:
 
-      .. code-block:: sv
+   .. code-block:: sv
 
-         /*verilator public_flat_rw_on*/
-         logic clk;
-         logic rst;
-         parameter width = 8;
-         /* verilator public_off*/
-         logic data;
+      /*verilator public_flat_rw_on*/
+      logic clk;
+      logic rst;
+      parameter width = 8;
+      /* verilator public_off*/
+      logic data;
 
    Is equivalent to:
 
-      .. code-block:: sv
+   .. code-block:: sv
 
-         logic clk /*verilator public_flat_rw*/;
-         logic rst /*verilator public_flat_rw*/;
-         parameter width /*verilator public_flat_rw*/ = 8;
-         logic data;
+      logic clk /*verilator public_flat_rw*/;
+      logic rst /*verilator public_flat_rw*/;
+      parameter width /*verilator public_flat_rw*/ = 8;
+      logic data;
 
 .. option:: /*verilator&32;public_flat*/ (on variable)
 
    Used after an input, output, register, or wire declaration to indicate
    the signal should be declared so that C code may read or write the value
-   of the signal.  This will not declare this module public, which means
-   the name of the signal or path to it may change based upon the module
+   of the signal. This will not declare this module public, which means the
+   name of the signal or path to it may change based upon the module
    inlining which takes place.
 
    Same as :option:`public_flat` control file option.
@@ -536,9 +550,9 @@ or "`ifdef`"'s may break other tools.
 
    Used after a module statement to indicate the module should not be
    inlined (unless specifically requested) so that C code may access the
-   module.  Verilator automatically sets this attribute when the module
-   contains public signals or \`systemc_ directives.  Use of this is
-   implied when using the :vlopt:`--public` option.
+   module. Verilator automatically sets this attribute when the module
+   contains public signals or \`systemc_ directives. Use of this is implied
+   when using the :vlopt:`--public` option.
 
    Same as :option:`public` control file option.
 
@@ -546,31 +560,40 @@ or "`ifdef`"'s may break other tools.
 
    Terminates the previous `/*verilator public*_on*/` directive; see above.
 
+.. option:: /*verilator&32;sc_biguint*/
+
+   Used after a port declaration. It sets the port to be of
+   ``sc_biguint<{width}>`` type, for signals of any width. This may be
+   useful if the port width is parameterized and the instantiating C++ code
+   always wants to have a sc_biguint accept any width. In general, you
+   should avoid using this attribute when unnecessary, as the performance
+   decreases significantly with increasing usage of sc_biguint.
+
 .. option:: /*verilator&32;sc_bv*/
 
-   Used after a port declaration.  It sets the port to be of
-   :code:`sc_bv<{width}>` type, instead of bool, uint32_t, or uint64_t.
-   This may be useful if the port width is parameterized and the
-   instantiating C++ code always wants to have a sc_bv accept any width.
-   In general, you should avoid using this attribute when unnecessary, as
-   the performance decreases significantly with increasing usage of sc_bv.
+   Used after a port declaration. It sets the port to be of
+   ``sc_bv<{width}>`` type, instead of bool, uint32_t, or uint64_t. This
+   may be useful if the port width is parameterized and the instantiating
+   C++ code always wants to have a sc_bv accept any width. In general, you
+   should avoid using this attribute when unnecessary, as the performance
+   decreases significantly with increasing usage of sc_bv.
 
    Same as :option:`sc_bv` control file option.
 
 .. option:: /*verilator&32;sc_clock*/
 
-   Deprecated and ignored.  Previously used after an input declaration to
+   Deprecated and ignored. Previously used after an input declaration to
    indicate the signal should be declared in SystemC as a sc_clock instead
-   of a bool.  This was needed in SystemC 1.1 and 1.2 only; versions 2.0
-   and later do not require clock pins to be sc_clocks, and this is no
-   longer needed and is ignored.
+   of a bool. This was needed in SystemC 1.1 and 1.2 only; versions 2.0 and
+   later do not require clock pins to be sc_clocks, and this is no longer
+   needed and is ignored.
 
 .. option:: /*verilator&32;sformat*/
 
    Attached to the final argument of type "input string" of a function or
    task to indicate that the function or task should pass all remaining
-   arguments through $sformatf.  This allows creation of DPI functions with
-   $display-like behavior.  See the :file:`test_regress/t/t_dpi_display.v`
+   arguments through $sformatf. This allows creation of DPI functions with
+   $display-like behavior. See the :file:`test_regress/t/t_dpi_display.v`
    file for an example.
 
    Same as :option:`sformat` control file option.
@@ -587,14 +610,14 @@ or "`ifdef`"'s may break other tools.
 
    .. code-block:: sv
 
-         logic [7:0] x [0:1]  /*verilator split_var*/;
+      logic [7:0] x [0:1]  /*verilator split_var*/;
 
    To:
 
    .. code-block:: sv
 
-         logic [7:0] x__BRA__0__KET__ /*verilator split_var*/;
-         logic [7:0] x__BRA__1__KET__ /*verilator split_var*/;
+      logic [7:0] x__BRA__0__KET__ /*verilator split_var*/;
+      logic [7:0] x__BRA__1__KET__ /*verilator split_var*/;
 
    Note that the generated packed variables retain the split_var
    metacomment because they may be split into smaller pieces according to
@@ -602,7 +625,7 @@ or "`ifdef`"'s may break other tools.
 
    This only supports unpacked arrays, packed arrays, and packed structs of
    integer types (reg, logic, bit, byte, int...); otherwise, if a split was
-   requested but cannot occur, a SPLITVAR warning is issued.  Splitting
+   requested but cannot occur, a SPLITVAR warning is issued. Splitting
    large arrays may slow down the Verilation speed, so use this only on
    variables that require it.
 
@@ -613,12 +636,11 @@ or "`ifdef`"'s may break other tools.
 
    .. code-block:: sv
 
-         logic [1:0][31:0] tmp;
-
-         assign tmp[0] = foo    + a;
-         assign tmp[1] = tmp[1] + b;
-         assign bar    = tmp[1] + c;
+      logic [1:0][31:0] tmp;
 
+      assign tmp[0] = foo    + a;
+      assign tmp[1] = tmp[1] + b;
+      assign bar    = tmp[1] + c;
 
    Same as :option:`split_var` control file option.
 
@@ -632,8 +654,8 @@ or "`ifdef`"'s may break other tools.
 
    Ignore all timing constructs after this metacomment. All timing controls
    behave as if they were not there (the same way as with
-   :option:`--no-timing`), and :code:`fork`/:code:`join*` blocks are
-   converted into :code:`begin`/:code:`end` blocks.
+   :option:`--no-timing`), and ``fork``/``join*`` blocks are
+   converted into ``begin``/``end`` blocks.
 
    Same as :option:`timing_off` control file option.
 
@@ -658,7 +680,7 @@ or "`ifdef`"'s may break other tools.
 .. option:: /*verilator&32;tracing_off*/
 
    Disable waveform tracing for all future signals declared in this module,
-   or instances below this module.  Often this is placed just after a
+   or instances below this module. Often this is placed just after a
    primitive's module statement, so that the entire module and instances
    below it are not traced.
 
@@ -671,7 +693,7 @@ or "`ifdef`"'s may break other tools.
 
    Used in a statement position to indicate the immediately following loop
    at the same statement level should not be unrolled by Verilator,
-   ignoring :vlopt:`--unroll-count`.  This is similar to clang's ``#pragma
+   ignoring :vlopt:`--unroll-count`. This is similar to clang's ``#pragma
    clang loop unroll(disable)``.
 
    This option does not currently disable the C++ compiler's unrolling (or
@@ -681,5 +703,5 @@ or "`ifdef`"'s may break other tools.
 
    Rarely needed. Used in a statement position to indicate the immediately
    following loop at the same statement level should always be fully
-   unrolled by Verilator, ignoring :vlopt:`--unroll-count`.  This is
-   similar to clang's ``#pragma clang loop unroll(full)``.
+   unrolled by Verilator, ignoring :vlopt:`--unroll-count`. This is similar
+   to clang's ``#pragma clang loop unroll(full)``.

docs/guide/faq.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ******************************
@@ -13,9 +13,9 @@ Questions
 Can I contribute?
 """""""""""""""""
 
-Please contribute!  Just submit a pull request, or raise an issue to
-discuss if you are looking for something to help on.  For more information
-see our contributor agreement.
+Please contribute! Just submit a pull request, or raise an issue to discuss
+if you are looking for something to help on. For more information see our
+contributor agreement.
 
 
 How widely is Verilator used?
@@ -25,10 +25,10 @@ Verilator is used by many of the largest silicon design companies, large
 organizations such as CERN, and even by college student projects.
 
 Verilator is one of the "big 4" simulators, meaning one of the four leading
-SystemVerilog simulators available, namely the closed-source products Synopsys
-VCS (tm), Mentor Questa/ModelSim (tm), Cadence
-Xcelium/Incisive/NC-Verilog/NC-Sim (tm), and the open-source Verilator.
-The three closed-source offerings are often collectively called the "big 3"
+SystemVerilog simulators available, namely the closed-source products
+Synopsys VCS (tm), Mentor Questa/ModelSim (tm), Cadence
+Xcelium/Incisive/NC-Verilog/NC-Sim (tm), and the open-source Verilator. The
+three closed-source offerings are often collectively called the "big 3"
 simulators.
 
 
@@ -37,7 +37,7 @@ Does Verilator run under Windows?
 
 Yes, ideally, run Ubuntu under Windows Subsystem for Linux (WSL2).
 Alternatively, use Cygwin, though this tends to be slower and is not
-regularly tested.  Verilated output also compiles under Microsoft Visual
+regularly tested. Verilated output also compiles under Microsoft Visual
 C++, but this is also not regularly tested.
 
 
@@ -46,8 +46,8 @@ Can you provide binaries?
 
 You can install Verilator via the system package manager (apt, yum, etc.)
 on many Linux distributions, including Debian, Ubuntu, SuSE, Red Hat, and
-others.  These packages are provided by the Linux distributions and
-generally will lag the version of the mainline Verilator repository.  If no
+others. These packages are provided by the Linux distributions and
+generally will lag the version of the mainline Verilator repository. If no
 binary package is available for your distribution, how about you set one
 up?
 
@@ -59,24 +59,25 @@ Generally, the implied part of the question is "... with all of the
 manpower they can put into developing it."
 
 Most simulators must comply with the complete IEEE 1364 (Verilog) and IEEE
-1800 (SystemVerilog) standards, meaning they have to be event-driven.  This
+1800 (SystemVerilog) standards, meaning they have to be event-driven. This
 prevents them from being able to reorder blocks and make netlist-style
 optimizations, which are where most of the gains come from.
 
-You should not be scared by non-compliance.  Your synthesis tool isn't
+You should not be scared by non-compliance. Your synthesis tool isn't
 compliant with the whole standard to start with, so your simulator need not
-be either.  Verilator is closer to the synthesis interpretation, which is
-a good thing for getting working silicon.
+be either. Verilator is closer to the synthesis interpretation, which is a
+good thing for getting working silicon.
 
 
 Will Verilator output remain under my own license/copyright?
 """"""""""""""""""""""""""""""""""""""""""""""""""""""""""""
 
-Your SystemVerilog, VPI/DPI, or main() C++ code remains under your own license.
+Your SystemVerilog, VPI/DPI, or main() C++ code remains under your own
+license.
 
 It's just like how using GCC on your programs does not change the copyright
 of your program; this is why Verilator uses the "GNU **Lesser** Public
-License Version 3" instead of the more typical "GNU Public License".  See
+License Version 3" instead of the more typical "GNU Public License". See
 the licenses for details.
 
 Some examples:
@@ -98,15 +99,15 @@ Some examples:
 You also have the option of using the Perl Artistic License, which again
 does not require you to release your Verilog, C++, or generated code. This
 license also allows you to modify Verilator for internal use without
-distributing the modified version.  But please contribute back to the
+distributing the modified version. But please contribute back to the
 community!
 
-Under both licenses, you can offer a commercial product based on
-Verilator directly or embedded within.  However, under both licenses,
-any changes you make to Verilator for such a product must be open-sourced.
+Under both licenses, you can offer a commercial product based on Verilator
+directly or embedded within. However, under both licenses, any changes you
+make to Verilator for such a product must be open-sourced.
 
 As is standard with Open Source, contributions back to Verilator will be
-placed under the Verilator copyright and LGPL/Artistic license.  Small test
+placed under the Verilator copyright and LGPL/Artistic license. Small test
 cases will be released into the public domain so they can be used anywhere,
 and large tests under the LGPL/Artistic, unless requested otherwise.
 
@@ -114,13 +115,13 @@ and large tests under the LGPL/Artistic, unless requested otherwise.
 Why is running Verilator (to create a model) so slow?
 """""""""""""""""""""""""""""""""""""""""""""""""""""
 
-Verilator may require more memory than the resulting simulation,
-as Verilator internally creates all of the state of the resulting
-generated simulator to optimize it.  If it takes more than a few
-minutes or so (and you're not using :vlopt:`--debug` since debug mode is
-disk bound), see if your machine is paging; most likely, you need to run it
-on a machine with more memory. Very large designs are known to have topped
-64 GB resident set size.  Alternatively, see :ref:`Hierarchical Verilation`.
+Verilator may require more memory than the resulting simulation, as
+Verilator internally creates all of the state of the resulting generated
+simulator to optimize it. If it takes more than a few minutes or so (and
+you're not using :vlopt:`--debug` since debug mode is disk bound), see if
+your machine is paging; most likely, you need to run it on a machine with
+more memory. Very large designs are known to have topped 64 GB resident set
+size. Alternatively, see :ref:`Hierarchical Verilation`.
 
 
 How do I generate waveforms (traces) in C++?
@@ -128,16 +129,16 @@ How do I generate waveforms (traces) in C++?
 
 See also the next question for tracing in SystemC mode.
 
-A. Pass the :vlopt:`--trace-vcd` option to Verilator.  Then you may use ``$dumpfile`` and
-   ``$dumpvars`` to enable traces, the same as with any Verilog simulator,
-   although Verilator ignores the arguments to ``$dumpvars``. See
-   ``examples/make_tracing_c`` in the distribution.
+A. Pass the :vlopt:`--trace-vcd` option to Verilator. Then you may use
+   ``$dumpfile`` and ``$dumpvars`` to enable traces, the same as with any
+   Verilog simulator, although Verilator ignores the arguments to
+   ``$dumpvars``. See ``examples/make_tracing_c`` in the distribution.
 
    If writing the top-level C code, call ``Verilated::traceEverOn(true)``;
    this is done for you if using :vlopt:`--binary`.
 
 B. Or, for finer-grained control, or C++ files with multiple Verilated
-   modules, you may also create the trace purely from C++.  Create a
+   modules, you may also create the trace purely from C++. Create a
    VerilatedVcdC object, and in your main loop, right after ``eval()`` call
    ``trace_object->dump(contextp->time())`` every time step, and finally
    call ``trace_object->close()``.
@@ -166,27 +167,26 @@ B. Or, for finer-grained control, or C++ files with multiple Verilated
 
 You also need to compile :file:`verilated_vcd_c.cpp` and add it to your
 link, preferably by adding the dependencies in your Makefile's
-:code:`$(VK_GLOBAL_OBJS)` link rule.  This is done for you if you are using
-the Verilator :vlopt:`--binary` or :vlopt:`--exe` option.
+``$(VK_GLOBAL_OBJS)`` link rule. This is done for you if you are using the
+Verilator :vlopt:`--binary` or :vlopt:`--exe` option.
 
-you can call :code:`trace_object->trace()` on multiple Verilated objects
-with the same trace file if you want all data to land in the same output
-file.
+you can call ``trace_object->trace()`` on multiple Verilated objects with
+the same trace file if you want all data to land in the same output file.
 
 
 How do I generate waveforms (traces) in SystemC?
 """"""""""""""""""""""""""""""""""""""""""""""""
 
 A. Pass the :vlopt:`--trace-vcd` option to Verilator, and in your top-level
-   :code:`sc_main()`, call :code:`Verilated::traceEverOn(true)`.  Then you
-   may use :code:`$dumpfile` and code:`$dumpvars` to enable traces, as
-   with any Verilog simulator; see the non-SystemC example in
+   ``sc_main()``, call ``Verilated::traceEverOn(true)``. Then you may use
+   ``$dumpfile`` and code:`$dumpvars` to enable traces, as with any Verilog
+   simulator; see the non-SystemC example in
    :file:`examples/make_tracing_c`. This will trace only the module
-   containing the :code:`$dumpvar`.
+   containing the ``$dumpvar``.
 
 B. Or, you may create a trace purely from SystemC, which may trace all
    Verilated designs in the SystemC model. Create a VerilatedVcdSc object
-   as you would create a standard SystemC trace file.  For an example, see
+   as you would create a standard SystemC trace file. For an example, see
    the call to ``VerilatedVcdSc`` in the
    :file:`examples/make_tracing_sc/sc_main.cpp` file of the distribution,
    and below.
@@ -212,57 +212,53 @@ C. Alternatively, you may use the C++ trace mechanism described in the
           tfp->close();
       }
 
-
-
 You also need to compile :file:`verilated_vcd_sc.cpp` and
 :file:`verilated_vcd_c.cpp` and add them to your link, preferably by adding
-the dependencies in your Makefile's :code:`$(VK_GLOBAL_OBJS)` link rule.
-This is done for you if you are using the Verilator :vlopt:`--binary` or
+the dependencies in your Makefile's ``$(VK_GLOBAL_OBJS)`` link rule. This
+is done for you if you are using the Verilator :vlopt:`--binary` or
 :vlopt:`--exe` option.
 
-You can call :code:`->trace()` on multiple Verilated objects with the same
+You can call ``->trace()`` on multiple Verilated objects with the same
 trace file if you want all data to land in the same output file.
 
 
 How do I generate FST waveforms (traces) in C++ or SystemC?
 """""""""""""""""""""""""""""""""""""""""""""""""""""""""""
 
-FST is a trace file format developed by GTKWave.  Verilator provides basic
-FST support.  To dump traces in FST format, add the :vlopt:`--trace-fst`
+FST is a trace file format developed by GTKWave. Verilator provides basic
+FST support. To dump traces in FST format, add the :vlopt:`--trace-fst`
 option to Verilator and either:
 
-Use :code:`$dumpfile & $dumpvars` in Verilog as described in the VCD
-example above,
+Use ``$dumpfile & $dumpvars`` in Verilog as described in the VCD example
+above,
 
 Or, in C++ change the include described in the VCD example above:
 
-  .. code-block:: C++
-
-      #include "verilated_fst_c.h"
-      VerilatedFstC* tfp = new VerilatedFstC;
+.. code-block:: C++
 
+   #include "verilated_fst_c.h"
+   VerilatedFstC* tfp = new VerilatedFstC;
 
 Or, in SystemC, change the include described in the VCD example above:
 
-  .. code-block:: C++
-
-      #include "verilated_fst_sc.h"
-      VerilatedFstC* tfp = new VerilatedFstSc;
+.. code-block:: C++
 
+   #include "verilated_fst_sc.h"
+   VerilatedFstC* tfp = new VerilatedFstSc;
 
 Currently, supporting FST and VCD in a single simulation is not supported,
-but such usage should be unlikely.  You can however ifdef around the trace
+but such usage should be unlikely. You can however ifdef around the trace
 format in your C++ main loop, and select VCD or FST at compile time.
 
 
 How do I view waveforms (aka dumps or traces)?
 """"""""""""""""""""""""""""""""""""""""""""""
 
-Verilator creates standard VCD (Value Change Dump) and FST files.  VCD
-files are viewable with the open-source
-`GTKWave <https://gtkwave.sourceforge.net/>`_,
-`Surfer <https://surfer-project.org/>`_, Dinotrace (legacy), or any of the
-many closed-source viewer offerings; FST is supported only by GTKWave and
+Verilator creates standard VCD (Value Change Dump) and FST files. VCD files
+are viewable with the open-source `GTKWave
+<https://gtkwave.sourceforge.net/>`_, `Surfer
+<https://surfer-project.org/>`_, Dinotrace (legacy), or any of the many
+closed-source viewer offerings; FST is supported only by GTKWave and
 Surfer.
 
 
@@ -287,24 +283,24 @@ D. You can also consider using FST tracing instead of VCD. FST dumps are a
    is prohibitively large.
 
 E. Write your trace files to a machine-local solid-state drive instead of a
-   network drive.  Network drives are generally far slower.
+   network drive. Network drives are generally far slower.
 
 
-Where is the translate_off command?  (How do I ignore a construct?)
-"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
+Where is the translate_off command? (How do I ignore a construct?)
+""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
 
 Translate on/off pragmas are generally a bad idea, as it's easy to have
 mismatched pairs, and you can't see what another tool sees by just
-preprocessing the code.  Instead, use the preprocessor; Verilator defines
+preprocessing the code. Instead, use the preprocessor; Verilator defines
 the ``\`VERILATOR`` define for you, so just wrap the code in an ifndef
 region:
 
- .. code-block:: sv
-    :emphasize-lines: 1
+.. code-block:: sv
+   :emphasize-lines: 1
 
-    `ifndef VERILATOR
-       Something_Verilator_Dislikes;
-    `endif
+   `ifndef VERILATOR
+      Something_Verilator_Dislikes;
+   `endif
 
 Most synthesis tools similarly define SYNTHESIS for you.
 
@@ -312,10 +308,10 @@ Most synthesis tools similarly define SYNTHESIS for you.
 Why do I get "unexpected 'do'" or "unexpected 'bit'" errors?
 """"""""""""""""""""""""""""""""""""""""""""""""""""""""""""
 
-The words \ ``do``\ , \ ``bit``\ , \ ``ref``\ , \ ``return``\ , and others
-are reserved keywords in SystemVerilog.  Older Verilog code might use these
-as identifiers, and you should change your code to not use them to ensure it
-works with newer tools.  Alternatively, surround them by the Verilog
+The words ``do``, ``bit``, ``ref``, ``return``, and others are reserved
+keywords in SystemVerilog. Older Verilog code might use these as
+identifiers, and you should change your code to not use them to ensure it
+works with newer tools. Alternatively, surround them by the Verilog
 2005/SystemVerilog begin_keywords pragma to indicate Verilog 2001 code.
 
 .. code-block:: sv
@@ -325,7 +321,6 @@ works with newer tools.  Alternatively, surround them by the Verilog
       integer bit; initial bit = 1;
    `end_keywords
 
-
 If you want the whole design parsed as Verilog 2001, see the
 :vlopt:`--default-language` option.
 
@@ -333,8 +328,8 @@ If you want the whole design parsed as Verilog 2001, see the
 How do I prevent my assertions from firing during reset?
 """"""""""""""""""""""""""""""""""""""""""""""""""""""""
 
-Call :code:`Verilated::assertOn(false)` before you first call the model,
-then turn it back on after reset.  It defaults to true.  When false, all
+Call ``Verilated::assertOn(false)`` before you first call the model, then
+turn it back on after reset. It defaults to true. When false, all
 assertions are disabled.
 
 
@@ -342,36 +337,36 @@ Why do I get "undefined reference to sc_time_stamp()?
 """""""""""""""""""""""""""""""""""""""""""""""""""""
 
 In Verilator 4.200 and later, using the timeInc function is recommended
-instead.  See the :ref:`Connecting to C++` examples.  Some linkers (MSVC++)
-still require :code:`sc_time_stamp()` to be defined; either define this
-with :code:`double sc_time_stamp() { return 0; }` or compile the Verilated
-code with :code:`-CFLAGS -DVL_TIME_CONTEXT`.
+instead. See the :ref:`Connecting to C++` examples. Some linkers (MSVC++)
+still require ``sc_time_stamp()`` to be defined; either define this with
+``double sc_time_stamp() { return 0; }`` or compile the Verilated code with
+``-CFLAGS -DVL_TIME_CONTEXT``.
 
-Before Verilator 4.200, the :code:`sc_time_stamp()` function needs to be
+Before Verilator 4.200, the ``sc_time_stamp()`` function needs to be
 defined in C++ (non SystemC) to return the current simulation time.
 
 
 Why do I get "undefined reference to \`VL_RAND_RESET_I' or \`Verilated::...'"?
 """"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
 
-You need to link your compiled Verilated code against the
-:code:`verilated.cpp` file found in the include directory of the Verilator
-kit.  This is one target in the ``$(VK_GLOBAL_OBJS)`` make variable, which
-should be part of your Makefile's link rule.  If you use :vlopt:`--exe` or
-:vlopt:`--binary`, this is done for you.
+You need to link your compiled Verilated code against the ``verilated.cpp``
+file found in the include directory of the Verilator kit. This is one
+target in the ``$(VK_GLOBAL_OBJS)`` make variable, which should be part of
+your Makefile's link rule. If you use :vlopt:`--exe` or :vlopt:`--binary`,
+this is done for you.
 
 
 Is the PLI supported?
 """""""""""""""""""""
 
-Only somewhat.  More specifically, the common PLI-ish calls $display,
-$finish, $stop, $time, $write are converted to C++ equivalents.  You can
+Only somewhat. More specifically, the common PLI-ish calls $display,
+$finish, $stop, $time, $write are converted to C++ equivalents. You can
 also use the "import DPI" SystemVerilog feature to call C code (see the
-chapter above).  There is also limited VPI access to public signals.
+chapter above). There is also limited VPI access to public signals.
 
 If you want something more complex, since Verilator emits standard C++
-code, you can write C++ routines that can access and modify signal
-values without needing any PLI interface code, and call it with
+code, you can write C++ routines that can access and modify signal values
+without needing any PLI interface code, and call it with
 $c("{any_c++_statement}").
 
 See the :ref:`Connecting` section.
@@ -380,8 +375,8 @@ See the :ref:`Connecting` section.
 How do I make a Verilog module that contains a C++ object?
 """"""""""""""""""""""""""""""""""""""""""""""""""""""""""
 
-You need to add the object to the structure Verilator creates, then
-use $c to call a method inside your object.  The
+You need to add the object to the structure Verilator creates, then use $c
+to call a method inside your object. The
 :file:`test_regress/t/t_extend_class` files in the distribution show an
 example of how to do this.
 
@@ -399,17 +394,17 @@ How do I get faster build times?
   disabled on these routines. See the OPT_FAST and OPT_SLOW make variables
   and :ref:`Benchmarking & Optimization`.
 
-* Use a recent compiler.  Newer compilers tend to be faster.
+* Use a recent compiler. Newer compilers tend to be faster.
 
 * Compile in parallel on many machines and use caching; see the web for the
-  ccache, sccache, distcc, or icecream packages. ccache will skip GCC runs between
-  identical source builds, even across different users.  If ccache was
-  installed when Verilator was built, it is used, or see OBJCACHE
+  ccache, sccache, distcc, or icecream packages. ccache will skip GCC runs
+  between identical source builds, even across different users. If ccache
+  was installed when Verilator was built, it is used, or see OBJCACHE
   environment variable to override this. Also see the
   :vlopt:`--output-split` option and :ref: `Profiling ccache efficiency`.
 
-* To reduce the compile time of classes that use a Verilated module (e.g., a
-  top CPP file) you may wish to add a
+* To reduce the compile time of classes that use a Verilated module (e.g.,
+  a top CPP file) you may wish to add a
   :option:`/*verilator&32;no_inline_module*/` metacomment to your top-level
   module. This will decrease the amount of code in the model's Verilated
   class, improving compile times of any instantiating top-level C++ code,
@@ -421,27 +416,27 @@ How do I get faster build times?
 Why do so many files need to recompile when I add a signal?
 """""""""""""""""""""""""""""""""""""""""""""""""""""""""""
 
-Adding a new signal requires the symbol table to be recompiled.  Verilator
-uses one large symbol table, resulting in 2-3 fewer assembly
-instructions for each signal access.  This makes the execution time 10-15%
-faster, but can result in more compilations when something changes.
+Adding a new signal requires the symbol table to be recompiled. Verilator
+uses one large symbol table, resulting in 2-3 fewer assembly instructions
+for each signal access. This makes the execution time 10-15% faster, but
+can result in more compilations when something changes.
 
 
 How do I access Verilog functions/tasks in C?
 """""""""""""""""""""""""""""""""""""""""""""
 
-Use the SystemVerilog Direct Programming Interface.  You write a Verilog
+Use the SystemVerilog Direct Programming Interface. You write a Verilog
 function or task with input/outputs that match what you want to call in
-with C.  Then mark that function as a DPI export function.  See the DPI
+with C. Then mark that function as a DPI export function. See the DPI
 chapter in the IEEE Standard.
 
 
 How do I access C++ functions/tasks in Verilog?
 """""""""""""""""""""""""""""""""""""""""""""""
 
-Use the SystemVerilog Direct Programming Interface.  You write a Verilog
+Use the SystemVerilog Direct Programming Interface. You write a Verilog
 function or task with input/outputs that match what you want to call in
-with C.  Then mark that function as a DPI import function.  See the DPI
+with C. Then mark that function as a DPI import function. See the DPI
 chapter in the IEEE Standard.
 
 
@@ -450,44 +445,43 @@ How do I access signals in C?
 
 The best thing to do is to make a SystemVerilog "export DPI" task or
 function that accesses that signal, as described in the DPI chapter in the
-manual and DPI tutorials on the web.  This will allow Verilator to
-optimize the model better and should be portable across simulators.
+manual and DPI tutorials on the web. This will allow Verilator to optimize
+the model better and should be portable across simulators.
 
 If you really want raw access to the signals, declare the signals you will
 be accessing with a :option:`/*verilator&32;public*/` metacomment before
-the closing semicolon.  Then scope into the C++ class to read the value of
+the closing semicolon. Then scope into the C++ class to read the value of
 the signal, as you would any other member variable.
 
 Signals are the smallest of 8-bit unsigned chars (equivalent to uint8_t),
 16-bit unsigned shorts (uint16_t), 32-bit unsigned longs (uint32_t), or
 64-bit unsigned long longs (uint64_t) that fit the width of the signal.
-Generally, you can use just uint32_t's for 1 to 32 bits, or uint64_t for
-1 to 64 bits, and the compiler will properly up-convert smaller entities.
+Generally, you can use just uint32_t's for 1 to 32 bits, or uint64_t for 1
+to 64 bits, and the compiler will properly up-convert smaller entities.
 Note that even signed ports are declared as unsigned; you must sign extend
 yourself to the appropriate signal width.
 
 Signals wider than 64 bits are stored as an array of 32-bit uint32_t's.
 Thus, to read bits 31:0, access signal[0], and for bits 63:32, access
-signal[1].  Unused bits (for example, bit numbers 65-96 of a 65-bit vector)
-will always be zero.  If you change the value, you must pack
-zeros in the unused bits, or core-dumps may result because Verilator strips
-array bound checks where it believes them to be unnecessary to improve
-performance.
+signal[1]. Unused bits (for example, bit numbers 65-96 of a 65-bit vector)
+will always be zero. If you change the value, you must pack zeros in the
+unused bits, or core-dumps may result because Verilator strips array bound
+checks where it believes them to be unnecessary to improve performance.
 
 In the SYSTEMC example above, if you had in our.v:
 
- .. code-block:: sv
+.. code-block:: sv
 
-      input clk /*verilator public*/;
-      // Note the placement of the semicolon above
+   input clk /*verilator public*/;
+   // Note the placement of the semicolon above
 
 From the sc_main.cpp file, you'd then:
 
- .. code-block:: C++
+.. code-block:: C++
 
-      #include "Vour.h"
-      #include "Vour_our.h"
-      std::cout << "clock is " << top->our->clk << std::endl;
+   #include "Vour.h"
+   #include "Vour_our.h"
+   std::cout << "clock is " << top->our->clk << std::endl;
 
 
 In this example, clk is a bool you can read or set as any other variable.
@@ -498,11 +492,11 @@ clocks, or you'll get strange results.
 Should a module be in Verilog or SystemC?
 """""""""""""""""""""""""""""""""""""""""
 
-Sometimes there is a block that only interconnects instances, and you have a
-choice if you write it in Verilog or SystemC.  Everything else being
-equal, the best performance is when Verilator sees all of the design.  So, look
-at the hierarchy of your design, labeling instances as to if they are
-SystemC or Verilog.  Then:
+Sometimes there is a block that only interconnects instances, and you have
+a choice if you write it in Verilog or SystemC. Everything else being
+equal, the best performance is when Verilator sees all of the design. So,
+look at the hierarchy of your design, labeling instances as to if they are
+SystemC or Verilog. Then:
 
 * A module with only SystemC instances below must be SystemC.
 
@@ -510,7 +504,7 @@ SystemC or Verilog.  Then:
   SystemC. (As Verilator cannot connect to lower-level SystemC instances.)
 
 * A module with only Verilog instances below can be either, but for best
-  performance should be Verilog.  (The exception is if you have a design
-  that is instantiated many times; in this case, Verilating one of the lower
-  modules and instantiating that Verilated instances multiple times into a
-  SystemC module *may* be faster.)
+  performance should be Verilog. (The exception is if you have a design
+  that is instantiated many times; in this case, Verilating one of the
+  lower modules and instantiating that Verilated instances multiple times
+  into a SystemC module *may* be faster.)

docs/guide/files.rst

@@ -1,11 +1,11 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *****
 Files
 *****
 
-.. _Files in the Distribution:
+.. _files in the distribution:
 
 Files in the Git Tree
 =====================
@@ -28,7 +28,7 @@ Verilator:
    test_regress                => Internal tests
 
 
-.. _Files Read/Written:
+.. _files read/written:
 
 Files Read/Written
 ==================
@@ -42,33 +42,33 @@ For --cc/--sc, it creates:
 
 .. list-table::
 
-   * - *{prefix}*\ .json
+   * - *{prefix}*.json
      - JSON build definition compiling (from --make json)
-   * - *{prefix}*\ .mk
+   * - *{prefix}*.mk
      - Make include file for compiling (from --make gmake)
    * - *{prefix}*\ _classes.mk
      - Make include file with class names (from --make gmake)
-   * - *{prefix}*\ .h
+   * - *{prefix}*.h
      - Model header
-   * - *{prefix}*\ .cpp
+   * - *{prefix}*.cpp
      - Model C++ file
    * - *{prefix}*\ ___024root.h
      - Top-level internal header file (from SystemVerilog $root)
    * - *{prefix}*\ ___024root.cpp
      - Top-level internal C++ file (from SystemVerilog $root)
-   * - *{prefix}*\ ___024root\ *{__n}*\ .cpp
+   * - *{prefix}*\ ___024root\ *{__n}*.cpp
      - Additional top-level internal C++ files
-   * - *{prefix}*\ ___024root__Slow\ *{__n}*\ .cpp
+   * - *{prefix}*\ ___024root__Slow\ *{__n}*.cpp
      - Infrequent cold routines
-   * - *{prefix}*\ ___024root__Trace\ *{__n}*\ .cpp
+   * - *{prefix}*\ ___024root__Trace\ *{__n}*.cpp
      - Wave file generation code (from --trace-\*)
-   * - *{prefix}*\ ___024root__Trace__Slow\ *{__n}*\ .cpp
+   * - *{prefix}*\ ___024root__Trace__Slow\ *{__n}*.cpp
      - Wave file generation code (from --trace-\*)
    * - *{prefix}*\ __Dpi.h
      - DPI import and export declarations (from --dpi)
    * - *{prefix}*\ __Dpi.cpp
      - Global DPI export wrappers (from --dpi)
-   * - *{prefix}*\ __Dpi_Export\ *{__n}*\ .cpp
+   * - *{prefix}*\ __Dpi_Export\ *{__n}*.cpp
      - DPI export wrappers scoped to this particular model (from --dpi)
    * - *{prefix}*\ __Inlines.h
      - Inline support functions
@@ -76,11 +76,11 @@ For --cc/--sc, it creates:
      - Global symbol table header
    * - *{prefix}*\ __Syms.cpp
      - Global symbol table C++
-   * - *{prefix}{each_verilog_module}*\ .h
+   * - *{prefix}{each_verilog_module}*.h
      - Lower level internal header files
-   * - *{prefix}{each_verilog_module}*\ .cpp
+   * - *{prefix}{each_verilog_module}*.cpp
      - Lower level internal C++ files
-   * - *{prefix}{each_verilog_module}{__n}*\ .cpp
+   * - *{prefix}{each_verilog_module}{__n}*.cpp
      - Additional lower C++ files
 
 For --hierarchical mode, it creates:
@@ -106,14 +106,12 @@ In specific debug and other modes, it also creates:
 
 .. list-table::
 
-   * - *{prefix}*\ .sarif
+   * - *{prefix}*.sarif
      - SARIF diagnostics (from --diagnostics-sarif)
-   * - *{prefix}*\ .tree.json
+   * - *{prefix}*.tree.json
      - JSON tree information (from --json-only)
-   * - *{prefix}*\ .tree.meta.json
+   * - *{prefix}*.tree.meta.json
      - JSON tree metadata (from --json-only)
-   * - *{prefix}*\ .xml
-     - XML tree information (from --xml)
    * - *{prefix}*\ __cdc.txt
      - Clock Domain Crossing checks (from --cdc)
    * - *{prefix}*\ __stats.txt
@@ -124,30 +122,30 @@ In specific debug and other modes, it also creates:
      - Make dependencies (from -MMD)
    * - *{prefix}*\ __verFiles.dat
      - Timestamps (from --skip-identical)
-   * - *{prefix}{misc}*\ .dot
+   * - *{prefix}{misc}*.dot
      - Debugging graph files (from --debug)
-   * - *{prefix}{misc}*\ .tree
+   * - *{prefix}{misc}*.tree
      - Debugging files (from --debug)
-   * - *{prefix}*\ __inputs\ .vpp
+   * - *{prefix}*\ __inputs.vpp
      - Pre-processed verilog for all files (from --debug)
-   * - *{prefix}*\ _ *{each_verilog_base_filename}*\ .vpp
+   * - *{prefix}*\ _ *{each_verilog_base_filename}*.vpp
      - Pre-processed verilog for each file (from --debug)
 
 After running Make, the C++ compiler may produce the following:
 
 .. list-table::
 
-   * - verilated{misc}*\ .d
+   * - verilated{misc}*.d
      - Intermediate dependencies
-   * - verilated{misc}*\ .o
+   * - verilated{misc}*.o
      - Intermediate objects
-   * - {mod_prefix}{misc}*\ .d
+   * - {mod_prefix}{misc}*.d
      - Intermediate dependencies
-   * - {mod_prefix}{misc}*\ .o
+   * - {mod_prefix}{misc}*.o
      - Intermediate objects
    * - *{prefix}*\
      - Final executable (from --exe)
-   * - lib\ *{prefix}*\ .a
+   * - lib\ *{prefix}*.a
      - Final archive (default lib mode)
    * - libverilated.a
      - Runtime for verilated model (default lib mode)
@@ -155,9 +153,9 @@ After running Make, the C++ compiler may produce the following:
      - Library of all Verilated objects
    * - *{prefix}*\ __ALL.cpp
      - Include of all code for single compile
-   * - *{prefix}{misc}*\ .d
+   * - *{prefix}{misc}*.d
      - Intermediate dependencies
-   * - *{prefix}{misc}*\ .o
+   * - *{prefix}{misc}*.o
      - Intermediate objects
 
 The Verilated executable may produce the following: