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Support array and struct info metadata in FST traces (#7255) 

- Emit arrays under the new FST scope type FST_ST_SV_ARRAY
- Emit packed/unpacked 'array' attributes before FST_ST_SV_ARRAY,
  including left and right indices of the array
- Emit packed/unpacked 'pack' attributes before FST_ST_VCD_STRUCT and
  FST_ST_VCD_UNION, including the number of members in the types

All attributes apply to the immediately following scope definition (just
like enum dtype attributes).
This commit is contained in:
Geza Lore 2026-03-14 12:31:33 +00:00 committed by GitHub
parent bb5a9dc247
commit 9d38a63563
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
43 changed files with 8752 additions and 7210 deletions
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69
include/verilated_fst_c.cpp
View File

@ -82,6 +82,7 @@ void VerilatedFst::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) {
fstWriterSetPackType(m_fst, FST_WR_PT_LZ4);
fstWriterSetTimescaleFromString(m_fst, timeResStr().c_str()); // lintok-begin-on-ref
if (m_useFstWriterThread) fstWriterSetParallelMode(m_fst, 1);
fstWriterSetVersion(m_fst, "Generated by VerilatedFst");
constDump(true); // First dump must contain the const signals
fullDump(true); // First dump must be full for fst
@ -138,19 +139,8 @@ void VerilatedFst::declDTypeEnum(int dtypenum, const char* name, uint32_t elemen
assert(newEntry);
}
// TODO: should return std::optional<fstScopeType>, but I can't have C++17
static std::pair<bool, fstScopeType> toFstScopeType(VerilatedTracePrefixType type) {
switch (type) {
case VerilatedTracePrefixType::SCOPE_MODULE: return {true, FST_ST_VCD_MODULE};
case VerilatedTracePrefixType::SCOPE_INTERFACE: return {true, FST_ST_VCD_INTERFACE};
case VerilatedTracePrefixType::STRUCT_PACKED:
case VerilatedTracePrefixType::STRUCT_UNPACKED: return {true, FST_ST_VCD_STRUCT};
case VerilatedTracePrefixType::UNION_PACKED: return {true, FST_ST_VCD_UNION};
default: return {false, /* unused so whatever, just need a value */ FST_ST_VCD_SCOPE};
}
}
void VerilatedFst::pushPrefix(const char* namep, VerilatedTracePrefixType type) {
void VerilatedFst::pushPrefix(const char* namep, VerilatedTracePrefixType type, int left,
int right) {
assert(!m_prefixStack.empty()); // Constructor makes an empty entry
const std::string name{namep};
// An empty name means this is the root of a model created with
@ -167,23 +157,58 @@ void VerilatedFst::pushPrefix(const char* namep, VerilatedTracePrefixType type)
return;
}
bool isProperScope = true;
switch (type) {
case VerilatedTracePrefixType::ARRAY_PACKED:
case VerilatedTracePrefixType::ARRAY_UNPACKED: isProperScope = false; break;
default: break;
}
// This code assumes a signal at a given prefix level is declared before
// any pushPrefix are done at that same level.
const std::string newPrefix = prevPrefix + name;
const auto pair = toFstScopeType(type);
const bool properScope = pair.first;
const fstScopeType scopeType = pair.second;
m_prefixStack.emplace_back(newPrefix + (properScope ? " " : ""), type);
if (properScope) {
const std::string scopeName = lastWord(newPrefix);
fstWriterSetScope(m_fst, scopeType, scopeName.c_str(), nullptr);
m_prefixStack.emplace_back(newPrefix + (isProperScope ? " " : ""), type);
const uint32_t l = static_cast<uint32_t>(left);
const uint32_t r = static_cast<uint32_t>(right);
const uint64_t lr = static_cast<uint64_t>(l) << 32 | static_cast<uint64_t>(r);
switch (type) {
case VerilatedTracePrefixType::SCOPE_MODULE:
fstWriterSetScope(m_fst, FST_ST_VCD_MODULE, namep, nullptr);
break;
case VerilatedTracePrefixType::SCOPE_INTERFACE:
fstWriterSetScope(m_fst, FST_ST_VCD_INTERFACE, namep, nullptr);
break;
case VerilatedTracePrefixType::STRUCT_PACKED:
fstWriterSetAttrBegin(m_fst, FST_AT_PACK, FST_PT_PACKED, "members", l);
fstWriterSetScope(m_fst, FST_ST_VCD_STRUCT, namep, nullptr);
break;
case VerilatedTracePrefixType::STRUCT_UNPACKED:
fstWriterSetAttrBegin(m_fst, FST_AT_PACK, FST_PT_UNPACKED, "members", l);
fstWriterSetScope(m_fst, FST_ST_VCD_STRUCT, namep, nullptr);
break;
case VerilatedTracePrefixType::UNION_PACKED:
fstWriterSetAttrBegin(m_fst, FST_AT_PACK, FST_PT_PACKED, "members", l);
fstWriterSetScope(m_fst, FST_ST_VCD_UNION, namep, nullptr);
break;
case VerilatedTracePrefixType::ARRAY_PACKED:
fstWriterSetAttrBegin(m_fst, FST_AT_ARRAY, FST_AR_PACKED, "bounds", lr);
fstWriterSetScope(m_fst, FST_ST_SV_ARRAY, namep, nullptr);
break;
case VerilatedTracePrefixType::ARRAY_UNPACKED:
fstWriterSetAttrBegin(m_fst, FST_AT_ARRAY, FST_AR_UNPACKED, "bounds", lr);
fstWriterSetScope(m_fst, FST_ST_SV_ARRAY, namep, nullptr);
break;
default: break;
}
}
void VerilatedFst::popPrefix() {
assert(!m_prefixStack.empty());
const bool properScope = toFstScopeType(m_prefixStack.back().second).first;
if (properScope) fstWriterSetUpscope(m_fst);
if (m_prefixStack.back().second != VerilatedTracePrefixType::ROOTIO_WRAPPER) {
fstWriterSetUpscope(m_fst);
}
m_prefixStack.pop_back();
assert(!m_prefixStack.empty()); // Always one left, the constructor's initial one
}

5
include/verilated_fst_c.h
View File

@ -110,7 +110,7 @@ public:
//=========================================================================
// Internal interface to Verilator generated code
void pushPrefix(const char*, VerilatedTracePrefixType);
void pushPrefix(const char*, VerilatedTracePrefixType, int left = 0, int right = 0);
void popPrefix();
// versions to call when the sig is not array member
@ -149,7 +149,8 @@ public:
};
// We use macros to drop unused arguments at compile time. This saves code size.
#define VL_TRACE_PUSH_PREFIX(tracep, name, type, left, right) tracep->pushPrefix(name, type);
#define VL_TRACE_PUSH_PREFIX(tracep, name, type, left, right) \
tracep->pushPrefix(name, type, left, right);
#define VL_TRACE_POP_PREFIX(tracep) tracep->popPrefix();
#define VL_TRACE_DECL_EVENT(tracep, code, fidx, name, dtypenum, dir, kind, type) \

61
test_regress/driver.py
View File

@ -2546,6 +2546,52 @@ class VlTest:
out = VtOs.run_capture(cmd, check=False)
print(out)
# Post-process file and fix up to match upcoming fst2vcd output
# also reindent for readability
# Slurp whole file
with open(fn2, 'r', encoding='latin-1') as fd:
lines = fd.readlines()
# Process line by line
new_lines = []
fixup_array_scope = False
indent = ""
for line in lines:
line = line.strip()
# Change "$attrbegin class" to "$attrbegin pack"
if match := re.match(r'^(\$attrbegin\s+)class(.*)', line):
line = indent + match.group(1) + "pack" + match.group(2)
# Check for "$attrbegin array"
elif re.search(r'^\$attrbegin\s+array', line):
line = indent + line
fixup_array_scope = True
# Check for "$scope"
elif match := re.match(r'(\$scope\s)(\S+)(.*)', line.lstrip('\r\n')):
if not indent:
indent = " "
# Fix up array scope
if (match.group(2) == "module") and fixup_array_scope:
line = indent + match.group(1) + "sv_array" + match.group(3)
fixup_array_scope = False
else:
line = indent + line
indent += " "
# Check for "$upscope"
elif re.search(r'^\$upscope', line):
indent = indent[0:-1]
line = indent + line
if len(indent) == 1:
indent = ""
# Just reindent
else:
line = indent + line
new_lines.append(line + "\n")
# Write back to file
with open(fn2, 'w', encoding='latin-1') as fd:
fd.writelines(new_lines)
def fst_identical(self, fn1: str, fn2: str, ignore_attr: bool = False) -> None:
"""Test if two FST files have logically-identical contents"""
if fn1.endswith(".fst"):
@ -2585,8 +2631,9 @@ class VlTest:
with open(filename, 'r', encoding='latin-1') as fh:
hier_stack = ["TOP"]
var = []
attr = []
for line in fh:
match1 = re.search(r'\$scope (module|struct|interface)\s+(\S+)', line)
match1 = re.search(r'\$scope (\S*)\s+(\S+)', line)
match2 = re.search(r'(\$var \S+\s+\d+\s+)\S+\s+(.+)\s+\$end', line)
match3 = re.search(r'(\$attrbegin .* \$end)', line)
line = line.rstrip()
@ -2597,16 +2644,20 @@ class VlTest:
hier_stack += [name]
scope = '.'.join(hier_stack)
data[scope] = match1.group(1) + " " + name
if attr:
data[scope + "#"] = " ".join(attr)
attr = []
elif match2: # $var
# print("VR"+ ' '*len(hier_stack) +" var " + line)
scope = '.'.join(hier_stack)
var = match2.group(2)
data[scope + "." + var] = match2.group(1)
if attr:
data[scope + "." + var + "#"] = " ".join(attr)
attr = []
elif match3: # $attrbegin
# print("VR"+ ' '*len(hier_stack) +" attr " + line)
if var:
scope = '.'.join(hier_stack)
data[scope + "." + var + "#"] = match3.group(1)
attr.append(match3.group(1))
elif re.search(r'\$enddefinitions', line):
break
n = len(re.findall(r'\$upscope', line))
@ -2614,6 +2665,8 @@ class VlTest:
for i in range(0, n): # pylint: disable=unused-variable
# print("VR"+ ' '*len(hier_stack) +" upscope " + line)
hier_stack.pop()
if attr:
self.error(f"Unhandled attribute: {attr}")
return data
def inline_checks(self) -> None:

20
test_regress/t/t_trace_abort_cc_fst.out
View File

@ -1,20 +1,20 @@
$date
Wed Feb 23 00:00:18 2022
Sat Mar 14 09:17:24 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var logic 3 " cyc [2:0] $end
$upscope $end
$upscope $end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var logic 3 " cyc [2:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

18
test_regress/t/t_trace_abort_sc_fst.out
View File

@ -1,19 +1,19 @@
$date
Sat Apr 5 13:56:20 2025
Sat Mar 14 09:16:46 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$scope module t $end
$var wire 1 ! clk $end
$var logic 3 " cyc [2:0] $end
$upscope $end
$upscope $end
$scope module top $end
$scope module t $end
$var wire 1 ! clk $end
$var logic 3 " cyc [2:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

27
test_regress/t/t_trace_array_cc_fst.out
View File

@ -1,23 +1,24 @@
$date
Tue Oct 7 13:25:18 2025
Sat Mar 14 09:16:42 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$scope struct biggie $end
$var logic 131073 # d [131072:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$attrbegin pack packed members 1 $end
$scope struct biggie $end
$var logic 131073 # d [131072:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

25
test_regress/t/t_trace_array_sc_fst.out
View File

@ -1,22 +1,23 @@
$date
Tue Oct 7 13:26:27 2025
Sat Mar 14 09:16:51 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$scope struct biggie $end
$var logic 131073 # d [131072:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module top $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$attrbegin pack packed members 1 $end
$scope struct biggie $end
$var logic 131073 # d [131072:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

68
test_regress/t/t_trace_ascendingrange_cc_fst.out
View File

@ -1,44 +1,44 @@
$date
Wed Feb 23 00:02:30 2022
Sat Mar 14 09:17:14 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var parameter 8 " P [0:7] $end
$var wire 1 ! clk $end
$var int 32 # cyc [31:0] $end
$var parameter 8 $ Q [0:7] $end
$var logic 1 % v_a [0:0] $end
$var logic 2 & v_b [0:1] $end
$var logic 8 ' v_c [0:7] $end
$var logic 9 ( v_d [0:8] $end
$var logic 16 ) v_e [0:15] $end
$var logic 17 * v_f [0:16] $end
$var logic 32 + v_g [0:31] $end
$var logic 33 , v_h [0:32] $end
$var logic 64 - v_i [0:63] $end
$var logic 65 . v_j [0:64] $end
$var logic 128 / v_k [0:127] $end
$var logic 129 0 v_l [0:128] $end
$var logic 256 1 v_m [0:255] $end
$var logic 257 2 v_n [0:256] $end
$var logic 512 3 v_o [0:511] $end
$var logic 3 4 v_p [-1:1] $end
$var logic 15 5 v_q [-7:7] $end
$var logic 31 6 v_r [-15:15] $end
$var logic 63 7 v_s [-31:31] $end
$var logic 127 8 v_t [-63:63] $end
$var logic 255 9 v_u [-127:127] $end
$var logic 511 : v_v [-255:255] $end
$upscope $end
$upscope $end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var parameter 8 " P [0:7] $end
$var wire 1 ! clk $end
$var int 32 # cyc [31:0] $end
$var parameter 8 $ Q [0:7] $end
$var logic 1 % v_a [0:0] $end
$var logic 2 & v_b [0:1] $end
$var logic 8 ' v_c [0:7] $end
$var logic 9 ( v_d [0:8] $end
$var logic 16 ) v_e [0:15] $end
$var logic 17 * v_f [0:16] $end
$var logic 32 + v_g [0:31] $end
$var logic 33 , v_h [0:32] $end
$var logic 64 - v_i [0:63] $end
$var logic 65 . v_j [0:64] $end
$var logic 128 / v_k [0:127] $end
$var logic 129 0 v_l [0:128] $end
$var logic 256 1 v_m [0:255] $end
$var logic 257 2 v_n [0:256] $end
$var logic 512 3 v_o [0:511] $end
$var logic 3 4 v_p [-1:1] $end
$var logic 15 5 v_q [-7:7] $end
$var logic 31 6 v_r [-15:15] $end
$var logic 63 7 v_s [-31:31] $end
$var logic 127 8 v_t [-63:63] $end
$var logic 255 9 v_u [-127:127] $end
$var logic 511 : v_v [-255:255] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

66
test_regress/t/t_trace_ascendingrange_sc_fst.out
View File

@ -1,43 +1,43 @@
$date
Sat Apr 5 13:56:21 2025
Sat Mar 14 09:17:01 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$scope module t $end
$var parameter 8 ! P [0:7] $end
$var wire 1 " clk $end
$var int 32 # cyc [31:0] $end
$var parameter 8 $ Q [0:7] $end
$var logic 1 % v_a [0:0] $end
$var logic 2 & v_b [0:1] $end
$var logic 8 ' v_c [0:7] $end
$var logic 9 ( v_d [0:8] $end
$var logic 16 ) v_e [0:15] $end
$var logic 17 * v_f [0:16] $end
$var logic 32 + v_g [0:31] $end
$var logic 33 , v_h [0:32] $end
$var logic 64 - v_i [0:63] $end
$var logic 65 . v_j [0:64] $end
$var logic 128 / v_k [0:127] $end
$var logic 129 0 v_l [0:128] $end
$var logic 256 1 v_m [0:255] $end
$var logic 257 2 v_n [0:256] $end
$var logic 512 3 v_o [0:511] $end
$var logic 3 4 v_p [-1:1] $end
$var logic 15 5 v_q [-7:7] $end
$var logic 31 6 v_r [-15:15] $end
$var logic 63 7 v_s [-31:31] $end
$var logic 127 8 v_t [-63:63] $end
$var logic 255 9 v_u [-127:127] $end
$var logic 511 : v_v [-255:255] $end
$upscope $end
$upscope $end
$scope module top $end
$scope module t $end
$var parameter 8 ! P [0:7] $end
$var wire 1 " clk $end
$var int 32 # cyc [31:0] $end
$var parameter 8 $ Q [0:7] $end
$var logic 1 % v_a [0:0] $end
$var logic 2 & v_b [0:1] $end
$var logic 8 ' v_c [0:7] $end
$var logic 9 ( v_d [0:8] $end
$var logic 16 ) v_e [0:15] $end
$var logic 17 * v_f [0:16] $end
$var logic 32 + v_g [0:31] $end
$var logic 33 , v_h [0:32] $end
$var logic 64 - v_i [0:63] $end
$var logic 65 . v_j [0:64] $end
$var logic 128 / v_k [0:127] $end
$var logic 129 0 v_l [0:128] $end
$var logic 256 1 v_m [0:255] $end
$var logic 257 2 v_n [0:256] $end
$var logic 512 3 v_o [0:511] $end
$var logic 3 4 v_p [-1:1] $end
$var logic 15 5 v_q [-7:7] $end
$var logic 31 6 v_r [-15:15] $end
$var logic 63 7 v_s [-31:31] $end
$var logic 127 8 v_t [-63:63] $end
$var logic 255 9 v_u [-127:127] $end
$var logic 511 : v_v [-255:255] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

99
test_regress/t/t_trace_basic_cc_fst.out
View File

@ -1,58 +1,61 @@
$date
Thu Mar 12 09:10:51 2026
Sat Mar 14 09:17:07 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$var wire 1 ! clk $end
$var wire 5 " state [4:0] $end
$var wire 1 # fst_inout $end
$scope module t $end
$var wire 1 ! clk $end
$var wire 5 " state [4:0] $end
$var wire 1 # fst_inout $end
$var int 32 $ cyc [31:0] $end
$var logic 1 % rstn $end
$var real_parameter 64 & fst_gparam_real $end
$var real_parameter 64 ' fst_lparam_real $end
$var real 64 & fst_real $end
$var integer 32 ( fst_integer [31:0] $end
$var bit 1 ) fst_bit $end
$var logic 1 * fst_logic $end
$var int 32 + fst_int [31:0] $end
$var shortint 16 , fst_shortint [15:0] $end
$var longint 64 - fst_longint [63:0] $end
$var byte 8 . fst_byte [7:0] $end
$var time 64 / fst_time [63:0] $end
$var parameter 32 0 fst_parameter [31:0] $end
$var parameter 32 1 fst_lparam [31:0] $end
$var supply0 1 # fst_supply0 $end
$var supply1 1 2 fst_supply1 $end
$var tri0 1 # fst_tri0 $end
$var tri1 1 2 fst_tri1 $end
$var tri 1 3 fst_tri $end
$var triand 1 4 fst_triand $end
$var trior 1 5 fst_trior $end
$var triand 1 6 fst_wand $end
$var trior 1 7 fst_wor $end
$var wire 1 8 fst_wire $end
$var wire 1 9 fst_uwire $end
$scope module test $end
$var wire 1 ! clk $end
$var wire 1 % rstn $end
$var wire 5 " state [4:0] $end
$var logic 5 : state_w [4:0] $end
$var logic 5 ; state_array[0] [4:0] $end
$var logic 5 < state_array[1] [4:0] $end
$var logic 5 = state_array[2] [4:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module top $end
$var wire 1 ! clk $end
$var wire 5 " state [4:0] $end
$var wire 1 # fst_inout $end
$scope module t $end
$var wire 1 ! clk $end
$var wire 5 " state [4:0] $end
$var wire 1 # fst_inout $end
$var int 32 $ cyc [31:0] $end
$var logic 1 % rstn $end
$var real_parameter 64 & fst_gparam_real $end
$var real_parameter 64 ' fst_lparam_real $end
$var real 64 & fst_real $end
$var integer 32 ( fst_integer [31:0] $end
$var bit 1 ) fst_bit $end
$var logic 1 * fst_logic $end
$var int 32 + fst_int [31:0] $end
$var shortint 16 , fst_shortint [15:0] $end
$var longint 64 - fst_longint [63:0] $end
$var byte 8 . fst_byte [7:0] $end
$var time 64 / fst_time [63:0] $end
$var parameter 32 0 fst_parameter [31:0] $end
$var parameter 32 1 fst_lparam [31:0] $end
$var supply0 1 # fst_supply0 $end
$var supply1 1 2 fst_supply1 $end
$var tri0 1 # fst_tri0 $end
$var tri1 1 2 fst_tri1 $end
$var tri 1 3 fst_tri $end
$var triand 1 4 fst_triand $end
$var trior 1 5 fst_trior $end
$var triand 1 6 fst_wand $end
$var trior 1 7 fst_wor $end
$var wire 1 8 fst_wire $end
$var wire 1 9 fst_uwire $end
$scope module test $end
$var wire 1 ! clk $end
$var wire 1 % rstn $end
$var wire 5 " state [4:0] $end
$var logic 5 : state_w [4:0] $end
$attrbegin array unpacked bounds 2 $end
$scope sv_array state_array $end
$var logic 5 ; state_array[0] [4:0] $end
$var logic 5 < state_array[1] [4:0] $end
$var logic 5 = state_array[2] [4:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

93
test_regress/t/t_trace_basic_sc_fst.out
View File

@ -1,55 +1,58 @@
$date
Thu Mar 12 09:11:07 2026
Sat Mar 14 09:17:04 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$scope module t $end
$var wire 1 ! clk $end
$var wire 5 " state [4:0] $end
$var wire 1 # fst_inout $end
$var int 32 $ cyc [31:0] $end
$var logic 1 % rstn $end
$var real_parameter 64 & fst_gparam_real $end
$var real_parameter 64 ' fst_lparam_real $end
$var real 64 & fst_real $end
$var integer 32 ( fst_integer [31:0] $end
$var bit 1 ) fst_bit $end
$var logic 1 * fst_logic $end
$var int 32 + fst_int [31:0] $end
$var shortint 16 , fst_shortint [15:0] $end
$var longint 64 - fst_longint [63:0] $end
$var byte 8 . fst_byte [7:0] $end
$var time 64 / fst_time [63:0] $end
$var parameter 32 0 fst_parameter [31:0] $end
$var parameter 32 1 fst_lparam [31:0] $end
$var supply0 1 2 fst_supply0 $end
$var supply1 1 3 fst_supply1 $end
$var tri0 1 2 fst_tri0 $end
$var tri1 1 3 fst_tri1 $end
$var tri 1 4 fst_tri $end
$var triand 1 5 fst_triand $end
$var trior 1 6 fst_trior $end
$var triand 1 7 fst_wand $end
$var trior 1 8 fst_wor $end
$var wire 1 9 fst_wire $end
$var wire 1 : fst_uwire $end
$scope module test $end
$var wire 1 ! clk $end
$var wire 1 % rstn $end
$var wire 5 " state [4:0] $end
$var logic 5 ; state_w [4:0] $end
$var logic 5 < state_array[0] [4:0] $end
$var logic 5 = state_array[1] [4:0] $end
$var logic 5 > state_array[2] [4:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module top $end
$scope module t $end
$var wire 1 ! clk $end
$var wire 5 " state [4:0] $end
$var wire 1 # fst_inout $end
$var int 32 $ cyc [31:0] $end
$var logic 1 % rstn $end
$var real_parameter 64 & fst_gparam_real $end
$var real_parameter 64 ' fst_lparam_real $end
$var real 64 & fst_real $end
$var integer 32 ( fst_integer [31:0] $end
$var bit 1 ) fst_bit $end
$var logic 1 * fst_logic $end
$var int 32 + fst_int [31:0] $end
$var shortint 16 , fst_shortint [15:0] $end
$var longint 64 - fst_longint [63:0] $end
$var byte 8 . fst_byte [7:0] $end
$var time 64 / fst_time [63:0] $end
$var parameter 32 0 fst_parameter [31:0] $end
$var parameter 32 1 fst_lparam [31:0] $end
$var supply0 1 2 fst_supply0 $end
$var supply1 1 3 fst_supply1 $end
$var tri0 1 2 fst_tri0 $end
$var tri1 1 3 fst_tri1 $end
$var tri 1 4 fst_tri $end
$var triand 1 5 fst_triand $end
$var trior 1 6 fst_trior $end
$var triand 1 7 fst_wand $end
$var trior 1 8 fst_wor $end
$var wire 1 9 fst_wire $end
$var wire 1 : fst_uwire $end
$scope module test $end
$var wire 1 ! clk $end
$var wire 1 % rstn $end
$var wire 5 " state [4:0] $end
$var logic 5 ; state_w [4:0] $end
$attrbegin array unpacked bounds 2 $end
$scope sv_array state_array $end
$var logic 5 < state_array[0] [4:0] $end
$var logic 5 = state_array[1] [4:0] $end
$var logic 5 > state_array[2] [4:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

22
test_regress/t/t_trace_cat_renew_fst_part_0000.out
View File

@ -1,21 +1,21 @@
$date
Wed Feb 23 00:00:47 2022
Sat Mar 14 09:17:00 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var integer 32 # unchanged [31:0] $end
$upscope $end
$upscope $end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var integer 32 # unchanged [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

22
test_regress/t/t_trace_cat_renew_fst_part_0100.out
View File

@ -1,21 +1,21 @@
$date
Wed Feb 23 00:26:16 2022
Sat Mar 14 09:17:49 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var integer 32 # unchanged [31:0] $end
$upscope $end
$upscope $end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var integer 32 # unchanged [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#100
$dumpvars

22
test_regress/t/t_trace_cat_reopen_fst_part_0000.out
View File

@ -1,21 +1,21 @@
$date
Wed Feb 23 00:00:47 2022
Sat Mar 14 09:16:55 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var integer 32 # unchanged [31:0] $end
$upscope $end
$upscope $end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var integer 32 # unchanged [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

22
test_regress/t/t_trace_cat_reopen_fst_part_0100.out
View File

@ -1,21 +1,21 @@
$date
Wed Feb 23 00:26:16 2022
Sat Mar 14 09:17:45 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var integer 32 # unchanged [31:0] $end
$upscope $end
$upscope $end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var integer 32 # unchanged [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#100
$dumpvars

136
test_regress/t/t_trace_complex_default_cc_fst.out
View File

@ -1,66 +1,90 @@
$date
Tue Feb 17 01:32:41 2026
Sat Mar 14 09:16:56 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
$var wire 1 ! clk $end
$scope module $unit $end
$var bit 1 " global_bit $end
$upscope $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 # cyc [31:0] $end
$var bit 2 $ v_strp [1:0] $end
$var bit 4 % v_strp_strp [3:0] $end
$var bit 2 & v_unip_strp [1:0] $end
$var bit 2 ' v_arrp [2:1] $end
$var bit 4 ( v_arrp_arrp [3:0] $end
$var bit 4 ) v_arrp_strp [3:0] $end
$var bit 1 * v_arru[1] $end
$var bit 1 + v_arru[2] $end
$var bit 1 , v_arru_arru[3][1] $end
$var bit 1 - v_arru_arru[3][2] $end
$var bit 1 . v_arru_arru[4][1] $end
$var bit 1 / v_arru_arru[4][2] $end
$var bit 2 0 v_arru_arrp[3] [2:1] $end
$var bit 2 1 v_arru_arrp[4] [2:1] $end
$var bit 2 2 v_arru_strp[3] [1:0] $end
$var bit 2 3 v_arru_strp[4] [1:0] $end
$var real 64 4 v_real $end
$var real 64 5 v_arr_real[0] $end
$var real 64 6 v_arr_real[1] $end
$var longint 64 7 v_chandle [63:0] $end
$var logic 64 8 v_str32x2 [63:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 9 v_enumed [31:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 : v_enumed2 [31:0] $end
$attrbegin misc 07 "" 2 $end
$var logic 3 ; v_enumb [2:0] $end
$var logic 6 < v_enumb2_str [5:0] $end
$var logic 8 = unpacked_array[-2] [7:0] $end
$var logic 8 > unpacked_array[-1] [7:0] $end
$var logic 8 ? unpacked_array[0] [7:0] $end
$var bit 1 @ LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
$var parameter 32 A PARAM [31:0] $end
$upscope $end
$scope module p2 $end
$var parameter 32 B PARAM [31:0] $end
$upscope $end
$scope module p3 $end
$var parameter 32 C PARAM [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module top $end
$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
$var wire 1 ! clk $end
$scope module $unit $end
$var bit 1 " global_bit $end
$upscope $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 # cyc [31:0] $end
$var bit 2 $ v_strp [1:0] $end
$var bit 4 % v_strp_strp [3:0] $end
$var bit 2 & v_unip_strp [1:0] $end
$var bit 2 ' v_arrp [2:1] $end
$var bit 4 ( v_arrp_arrp [3:0] $end
$var bit 4 ) v_arrp_strp [3:0] $end
$attrbegin array unpacked bounds 8589934593 $end
$scope sv_array v_arru $end
$var bit 1 * v_arru[2] $end
$var bit 1 + v_arru[1] $end
$upscope $end
$attrbegin array unpacked bounds 17179869187 $end
$scope sv_array v_arru_arru $end
$attrbegin array unpacked bounds 8589934593 $end
$scope sv_array [4] $end
$var bit 1 , v_arru_arru[4][2] $end
$var bit 1 - v_arru_arru[4][1] $end
$upscope $end
$attrbegin array unpacked bounds 8589934593 $end
$scope sv_array [3] $end
$var bit 1 . v_arru_arru[3][2] $end
$var bit 1 / v_arru_arru[3][1] $end
$upscope $end
$upscope $end
$attrbegin array unpacked bounds 17179869187 $end
$scope sv_array v_arru_arrp $end
$var bit 2 0 v_arru_arrp[4] [2:1] $end
$var bit 2 1 v_arru_arrp[3] [2:1] $end
$upscope $end
$attrbegin array unpacked bounds 17179869187 $end
$scope sv_array v_arru_strp $end
$var bit 2 2 v_arru_strp[4] [1:0] $end
$var bit 2 3 v_arru_strp[3] [1:0] $end
$upscope $end
$var real 64 4 v_real $end
$attrbegin array unpacked bounds 1 $end
$scope sv_array v_arr_real $end
$var real 64 5 v_arr_real[0] $end
$var real 64 6 v_arr_real[1] $end
$upscope $end
$var longint 64 7 v_chandle [63:0] $end
$var logic 64 8 v_str32x2 [63:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 9 v_enumed [31:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 : v_enumed2 [31:0] $end
$attrbegin misc 07 "" 2 $end
$var logic 3 ; v_enumb [2:0] $end
$var logic 6 < v_enumb2_str [5:0] $end
$attrbegin array unpacked bounds -8589934592 $end
$scope sv_array unpacked_array $end
$var logic 8 = unpacked_array[-2] [7:0] $end
$var logic 8 > unpacked_array[-1] [7:0] $end
$var logic 8 ? unpacked_array[0] [7:0] $end
$upscope $end
$var bit 1 @ LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
$var parameter 32 A PARAM [31:0] $end
$upscope $end
$scope module p2 $end
$var parameter 32 B PARAM [31:0] $end
$upscope $end
$scope module p3 $end
$var parameter 32 C PARAM [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

134
test_regress/t/t_trace_complex_default_sc_fst.out
View File

@ -1,65 +1,89 @@
$date
Tue Feb 17 01:32:41 2026
Sat Mar 14 09:16:46 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
$scope module $unit $end
$var bit 1 ! global_bit $end
$upscope $end
$scope module t $end
$var wire 1 " clk $end
$var integer 32 # cyc [31:0] $end
$var bit 2 $ v_strp [1:0] $end
$var bit 4 % v_strp_strp [3:0] $end
$var bit 2 & v_unip_strp [1:0] $end
$var bit 2 ' v_arrp [2:1] $end
$var bit 4 ( v_arrp_arrp [3:0] $end
$var bit 4 ) v_arrp_strp [3:0] $end
$var bit 1 * v_arru[1] $end
$var bit 1 + v_arru[2] $end
$var bit 1 , v_arru_arru[3][1] $end
$var bit 1 - v_arru_arru[3][2] $end
$var bit 1 . v_arru_arru[4][1] $end
$var bit 1 / v_arru_arru[4][2] $end
$var bit 2 0 v_arru_arrp[3] [2:1] $end
$var bit 2 1 v_arru_arrp[4] [2:1] $end
$var bit 2 2 v_arru_strp[3] [1:0] $end
$var bit 2 3 v_arru_strp[4] [1:0] $end
$var real 64 4 v_real $end
$var real 64 5 v_arr_real[0] $end
$var real 64 6 v_arr_real[1] $end
$var longint 64 7 v_chandle [63:0] $end
$var logic 64 8 v_str32x2 [63:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 9 v_enumed [31:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 : v_enumed2 [31:0] $end
$attrbegin misc 07 "" 2 $end
$var logic 3 ; v_enumb [2:0] $end
$var logic 6 < v_enumb2_str [5:0] $end
$var logic 8 = unpacked_array[-2] [7:0] $end
$var logic 8 > unpacked_array[-1] [7:0] $end
$var logic 8 ? unpacked_array[0] [7:0] $end
$var bit 1 @ LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
$var parameter 32 A PARAM [31:0] $end
$upscope $end
$scope module p2 $end
$var parameter 32 B PARAM [31:0] $end
$upscope $end
$scope module p3 $end
$var parameter 32 C PARAM [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module top $end
$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
$scope module $unit $end
$var bit 1 ! global_bit $end
$upscope $end
$scope module t $end
$var wire 1 " clk $end
$var integer 32 # cyc [31:0] $end
$var bit 2 $ v_strp [1:0] $end
$var bit 4 % v_strp_strp [3:0] $end
$var bit 2 & v_unip_strp [1:0] $end
$var bit 2 ' v_arrp [2:1] $end
$var bit 4 ( v_arrp_arrp [3:0] $end
$var bit 4 ) v_arrp_strp [3:0] $end
$attrbegin array unpacked bounds 8589934593 $end
$scope sv_array v_arru $end
$var bit 1 * v_arru[2] $end
$var bit 1 + v_arru[1] $end
$upscope $end
$attrbegin array unpacked bounds 17179869187 $end
$scope sv_array v_arru_arru $end
$attrbegin array unpacked bounds 8589934593 $end
$scope sv_array [4] $end
$var bit 1 , v_arru_arru[4][2] $end
$var bit 1 - v_arru_arru[4][1] $end
$upscope $end
$attrbegin array unpacked bounds 8589934593 $end
$scope sv_array [3] $end
$var bit 1 . v_arru_arru[3][2] $end
$var bit 1 / v_arru_arru[3][1] $end
$upscope $end
$upscope $end
$attrbegin array unpacked bounds 17179869187 $end
$scope sv_array v_arru_arrp $end
$var bit 2 0 v_arru_arrp[4] [2:1] $end
$var bit 2 1 v_arru_arrp[3] [2:1] $end
$upscope $end
$attrbegin array unpacked bounds 17179869187 $end
$scope sv_array v_arru_strp $end
$var bit 2 2 v_arru_strp[4] [1:0] $end
$var bit 2 3 v_arru_strp[3] [1:0] $end
$upscope $end
$var real 64 4 v_real $end
$attrbegin array unpacked bounds 1 $end
$scope sv_array v_arr_real $end
$var real 64 5 v_arr_real[0] $end
$var real 64 6 v_arr_real[1] $end
$upscope $end
$var longint 64 7 v_chandle [63:0] $end
$var logic 64 8 v_str32x2 [63:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 9 v_enumed [31:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 : v_enumed2 [31:0] $end
$attrbegin misc 07 "" 2 $end
$var logic 3 ; v_enumb [2:0] $end
$var logic 6 < v_enumb2_str [5:0] $end
$attrbegin array unpacked bounds -8589934592 $end
$scope sv_array unpacked_array $end
$var logic 8 = unpacked_array[-2] [7:0] $end
$var logic 8 > unpacked_array[-1] [7:0] $end
$var logic 8 ? unpacked_array[0] [7:0] $end
$upscope $end
$var bit 1 @ LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
$var parameter 32 A PARAM [31:0] $end
$upscope $end
$scope module p2 $end
$var parameter 32 B PARAM [31:0] $end
$upscope $end
$scope module p3 $end
$var parameter 32 C PARAM [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

234
test_regress/t/t_trace_complex_fst_thread.out
View File

@ -1,234 +0,0 @@
$date
Wed May 1 19:09:18 2019
$end
$version
fstWriter
$end
$timescale
1ns
$end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc $end
$var logic 2 # v_strp $end
$var logic 4 $ v_strp_strp $end
$var logic 2 % v_unip_strp $end
$var logic 2 & v_arrp $end
$var logic 4 ' v_arrp_arrp $end
$var logic 4 ( v_arrp_strp $end
$var logic 1 ) v_arru(1) $end
$var logic 1 * v_arru(2) $end
$var logic 1 + v_arru_arru(3)(1) $end
$var logic 1 , v_arru_arru(3)(2) $end
$var logic 1 - v_arru_arru(4)(1) $end
$var logic 1 . v_arru_arru(4)(2) $end
$var logic 2 / v_arru_arrp(3) $end
$var logic 2 0 v_arru_arrp(4) $end
$var logic 2 1 v_arru_strp(3) $end
$var logic 2 2 v_arru_strp(4) $end
$var real 64 3 v_real $end
$var real 64 4 v_arr_real(0) $end
$var real 64 5 v_arr_real(1) $end
$var logic 64 6 v_str32x2 $end
$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
$attrbegin misc 07 "" 1 $end
$var logic 32 7 v_enumed $end
$attrbegin misc 07 "" 1 $end
$var logic 32 8 v_enumed2 $end
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
$attrbegin misc 07 "" 2 $end
$var logic 3 9 v_enumb $end
$scope module unnamedblk1 $end
$var integer 32 : b $end
$scope module unnamedblk2 $end
$var integer 32 ; a $end
$upscope $end
$upscope $end
$scope module p2 $end
$var parameter 32 < PARAM $end
$upscope $end
$scope module p3 $end
$var parameter 32 = PARAM $end
$upscope $end
$upscope $end
$scope module $unit $end
$var bit 1 > global_bit $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
0!
b00000000000000000000000000000000 "
b00 #
b0000 $
b00 %
b00 &
b0000 '
b0000 (
0)
0*
0+
0,
0-
0.
b00 /
b00 0
b00 1
b00 2
r0 3
r0 4
r0 5
b0000000000000000000000000000000000000000000000000000000011111111 6
b00000000000000000000000000000000 7
b00000000000000000000000000000000 8
b000 9
b00000000000000000000000000000000 :
b00000000000000000000000000000000 ;
b00000000000000000000000000000010 <
b00000000000000000000000000000011 =
1>
#10
b00000000000000000000000000000101 ;
b00000000000000000000000000000101 :
b111 9
b00000000000000000000000000000010 8
b00000000000000000000000000000001 7
b0000000000000000000000000000000100000000000000000000000011111110 6
r0.3 5
r0.2 4
r0.1 3
b11 2
b11 1
b11 0
b11 /
b1111 (
b1111 '
b11 &
b11 %
b1111 $
b11 #
b00000000000000000000000000000001 "
1!
#15
0!
#20
1!
b00000000000000000000000000000010 "
b00 #
b0000 $
b00 %
b00 &
b0000 '
b0000 (
b00 /
b00 0
b00 1
b00 2
r0.2 3
r0.4 4
r0.6 5
b0000000000000000000000000000001000000000000000000000000011111101 6
b00000000000000000000000000000010 7
b00000000000000000000000000000100 8
b110 9
b00000000000000000000000000000101 :
b00000000000000000000000000000101 ;
#25
0!
#30
1!
b00000000000000000000000000000101 ;
b00000000000000000000000000000101 :
b101 9
b00000000000000000000000000000110 8
b00000000000000000000000000000011 7
b0000000000000000000000000000001100000000000000000000000011111100 6
r0.8999999999999999 5
r0.6000000000000001 4
r0.3 3
b11 2
b11 1
b11 0
b11 /
b1111 (
b1111 '
b11 &
b11 %
b1111 $
b11 #
b00000000000000000000000000000011 "
#35
0!
#40
1!
b00000000000000000000000000000100 "
b00 #
b0000 $
b00 %
b00 &
b0000 '
b0000 (
b00 /
b00 0
b00 1
b00 2
r0.4 3
r0.8 4
r1.2 5
b0000000000000000000000000000010000000000000000000000000011111011 6
b00000000000000000000000000000100 7
b00000000000000000000000000001000 8
b100 9
b00000000000000000000000000000101 :
b00000000000000000000000000000101 ;
#45
0!
#50
1!
b00000000000000000000000000000101 ;
b00000000000000000000000000000101 :
b011 9
b00000000000000000000000000001010 8
b00000000000000000000000000000101 7
b0000000000000000000000000000010100000000000000000000000011111010 6
r1.5 5
r1 4
r0.5 3
b11 2
b11 1
b11 0
b11 /
b1111 (
b1111 '
b11 &
b11 %
b1111 $
b11 #
b00000000000000000000000000000101 "
#55
0!
#60
1!
b00000000000000000000000000000110 "
b00 #
b0000 $
b00 %
b00 &
b0000 '
b0000 (
b00 /
b00 0
b00 1
b00 2
r0.6 3
r1.2 4
r1.8 5
b0000000000000000000000000000011000000000000000000000000011111001 6
b00000000000000000000000000000110 7
b00000000000000000000000000001100 8
b010 9
b00000000000000000000000000000101 :
b00000000000000000000000000000101 ;

136
test_regress/t/t_trace_complex_params_cc_fst.out
View File

@ -1,66 +1,90 @@
$date
Tue Feb 17 01:32:41 2026
Sat Mar 14 09:16:42 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
$var wire 1 ! clk $end
$scope module $unit $end
$var bit 1 " global_bit $end
$upscope $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 # cyc [31:0] $end
$var bit 2 $ v_strp [1:0] $end
$var bit 4 % v_strp_strp [3:0] $end
$var bit 2 & v_unip_strp [1:0] $end
$var bit 2 ' v_arrp [2:1] $end
$var bit 4 ( v_arrp_arrp [3:0] $end
$var bit 4 ) v_arrp_strp [3:0] $end
$var bit 1 * v_arru[1] $end
$var bit 1 + v_arru[2] $end
$var bit 1 , v_arru_arru[3][1] $end
$var bit 1 - v_arru_arru[3][2] $end
$var bit 1 . v_arru_arru[4][1] $end
$var bit 1 / v_arru_arru[4][2] $end
$var bit 2 0 v_arru_arrp[3] [2:1] $end
$var bit 2 1 v_arru_arrp[4] [2:1] $end
$var bit 2 2 v_arru_strp[3] [1:0] $end
$var bit 2 3 v_arru_strp[4] [1:0] $end
$var real 64 4 v_real $end
$var real 64 5 v_arr_real[0] $end
$var real 64 6 v_arr_real[1] $end
$var longint 64 7 v_chandle [63:0] $end
$var logic 64 8 v_str32x2 [63:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 9 v_enumed [31:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 : v_enumed2 [31:0] $end
$attrbegin misc 07 "" 2 $end
$var logic 3 ; v_enumb [2:0] $end
$var logic 6 < v_enumb2_str [5:0] $end
$var logic 8 = unpacked_array[-2] [7:0] $end
$var logic 8 > unpacked_array[-1] [7:0] $end
$var logic 8 ? unpacked_array[0] [7:0] $end
$var bit 1 @ LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
$var parameter 32 A PARAM [31:0] $end
$upscope $end
$scope module p2 $end
$var parameter 32 B PARAM [31:0] $end
$upscope $end
$scope module p3 $end
$var parameter 32 C PARAM [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module top $end
$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
$var wire 1 ! clk $end
$scope module $unit $end
$var bit 1 " global_bit $end
$upscope $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 # cyc [31:0] $end
$var bit 2 $ v_strp [1:0] $end
$var bit 4 % v_strp_strp [3:0] $end
$var bit 2 & v_unip_strp [1:0] $end
$var bit 2 ' v_arrp [2:1] $end
$var bit 4 ( v_arrp_arrp [3:0] $end
$var bit 4 ) v_arrp_strp [3:0] $end
$attrbegin array unpacked bounds 8589934593 $end
$scope sv_array v_arru $end
$var bit 1 * v_arru[2] $end
$var bit 1 + v_arru[1] $end
$upscope $end
$attrbegin array unpacked bounds 17179869187 $end
$scope sv_array v_arru_arru $end
$attrbegin array unpacked bounds 8589934593 $end
$scope sv_array [4] $end
$var bit 1 , v_arru_arru[4][2] $end
$var bit 1 - v_arru_arru[4][1] $end
$upscope $end
$attrbegin array unpacked bounds 8589934593 $end
$scope sv_array [3] $end
$var bit 1 . v_arru_arru[3][2] $end
$var bit 1 / v_arru_arru[3][1] $end
$upscope $end
$upscope $end
$attrbegin array unpacked bounds 17179869187 $end
$scope sv_array v_arru_arrp $end
$var bit 2 0 v_arru_arrp[4] [2:1] $end
$var bit 2 1 v_arru_arrp[3] [2:1] $end
$upscope $end
$attrbegin array unpacked bounds 17179869187 $end
$scope sv_array v_arru_strp $end
$var bit 2 2 v_arru_strp[4] [1:0] $end
$var bit 2 3 v_arru_strp[3] [1:0] $end
$upscope $end
$var real 64 4 v_real $end
$attrbegin array unpacked bounds 1 $end
$scope sv_array v_arr_real $end
$var real 64 5 v_arr_real[0] $end
$var real 64 6 v_arr_real[1] $end
$upscope $end
$var longint 64 7 v_chandle [63:0] $end
$var logic 64 8 v_str32x2 [63:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 9 v_enumed [31:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 : v_enumed2 [31:0] $end
$attrbegin misc 07 "" 2 $end
$var logic 3 ; v_enumb [2:0] $end
$var logic 6 < v_enumb2_str [5:0] $end
$attrbegin array unpacked bounds -8589934592 $end
$scope sv_array unpacked_array $end
$var logic 8 = unpacked_array[-2] [7:0] $end
$var logic 8 > unpacked_array[-1] [7:0] $end
$var logic 8 ? unpacked_array[0] [7:0] $end
$upscope $end
$var bit 1 @ LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
$var parameter 32 A PARAM [31:0] $end
$upscope $end
$scope module p2 $end
$var parameter 32 B PARAM [31:0] $end
$upscope $end
$scope module p3 $end
$var parameter 32 C PARAM [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

134
test_regress/t/t_trace_complex_params_sc_fst.out
View File

@ -1,65 +1,89 @@
$date
Tue Feb 17 01:32:41 2026
Sat Mar 14 09:17:23 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
$scope module $unit $end
$var bit 1 ! global_bit $end
$upscope $end
$scope module t $end
$var wire 1 " clk $end
$var integer 32 # cyc [31:0] $end
$var bit 2 $ v_strp [1:0] $end
$var bit 4 % v_strp_strp [3:0] $end
$var bit 2 & v_unip_strp [1:0] $end
$var bit 2 ' v_arrp [2:1] $end
$var bit 4 ( v_arrp_arrp [3:0] $end
$var bit 4 ) v_arrp_strp [3:0] $end
$var bit 1 * v_arru[1] $end
$var bit 1 + v_arru[2] $end
$var bit 1 , v_arru_arru[3][1] $end
$var bit 1 - v_arru_arru[3][2] $end
$var bit 1 . v_arru_arru[4][1] $end
$var bit 1 / v_arru_arru[4][2] $end
$var bit 2 0 v_arru_arrp[3] [2:1] $end
$var bit 2 1 v_arru_arrp[4] [2:1] $end
$var bit 2 2 v_arru_strp[3] [1:0] $end
$var bit 2 3 v_arru_strp[4] [1:0] $end
$var real 64 4 v_real $end
$var real 64 5 v_arr_real[0] $end
$var real 64 6 v_arr_real[1] $end
$var longint 64 7 v_chandle [63:0] $end
$var logic 64 8 v_str32x2 [63:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 9 v_enumed [31:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 : v_enumed2 [31:0] $end
$attrbegin misc 07 "" 2 $end
$var logic 3 ; v_enumb [2:0] $end
$var logic 6 < v_enumb2_str [5:0] $end
$var logic 8 = unpacked_array[-2] [7:0] $end
$var logic 8 > unpacked_array[-1] [7:0] $end
$var logic 8 ? unpacked_array[0] [7:0] $end
$var bit 1 @ LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
$var parameter 32 A PARAM [31:0] $end
$upscope $end
$scope module p2 $end
$var parameter 32 B PARAM [31:0] $end
$upscope $end
$scope module p3 $end
$var parameter 32 C PARAM [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module top $end
$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
$scope module $unit $end
$var bit 1 ! global_bit $end
$upscope $end
$scope module t $end
$var wire 1 " clk $end
$var integer 32 # cyc [31:0] $end
$var bit 2 $ v_strp [1:0] $end
$var bit 4 % v_strp_strp [3:0] $end
$var bit 2 & v_unip_strp [1:0] $end
$var bit 2 ' v_arrp [2:1] $end
$var bit 4 ( v_arrp_arrp [3:0] $end
$var bit 4 ) v_arrp_strp [3:0] $end
$attrbegin array unpacked bounds 8589934593 $end
$scope sv_array v_arru $end
$var bit 1 * v_arru[2] $end
$var bit 1 + v_arru[1] $end
$upscope $end
$attrbegin array unpacked bounds 17179869187 $end
$scope sv_array v_arru_arru $end
$attrbegin array unpacked bounds 8589934593 $end
$scope sv_array [4] $end
$var bit 1 , v_arru_arru[4][2] $end
$var bit 1 - v_arru_arru[4][1] $end
$upscope $end
$attrbegin array unpacked bounds 8589934593 $end
$scope sv_array [3] $end
$var bit 1 . v_arru_arru[3][2] $end
$var bit 1 / v_arru_arru[3][1] $end
$upscope $end
$upscope $end
$attrbegin array unpacked bounds 17179869187 $end
$scope sv_array v_arru_arrp $end
$var bit 2 0 v_arru_arrp[4] [2:1] $end
$var bit 2 1 v_arru_arrp[3] [2:1] $end
$upscope $end
$attrbegin array unpacked bounds 17179869187 $end
$scope sv_array v_arru_strp $end
$var bit 2 2 v_arru_strp[4] [1:0] $end
$var bit 2 3 v_arru_strp[3] [1:0] $end
$upscope $end
$var real 64 4 v_real $end
$attrbegin array unpacked bounds 1 $end
$scope sv_array v_arr_real $end
$var real 64 5 v_arr_real[0] $end
$var real 64 6 v_arr_real[1] $end
$upscope $end
$var longint 64 7 v_chandle [63:0] $end
$var logic 64 8 v_str32x2 [63:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 9 v_enumed [31:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 : v_enumed2 [31:0] $end
$attrbegin misc 07 "" 2 $end
$var logic 3 ; v_enumb [2:0] $end
$var logic 6 < v_enumb2_str [5:0] $end
$attrbegin array unpacked bounds -8589934592 $end
$scope sv_array unpacked_array $end
$var logic 8 = unpacked_array[-2] [7:0] $end
$var logic 8 > unpacked_array[-1] [7:0] $end
$var logic 8 ? unpacked_array[0] [7:0] $end
$upscope $end
$var bit 1 @ LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
$var parameter 32 A PARAM [31:0] $end
$upscope $end
$scope module p2 $end
$var parameter 32 B PARAM [31:0] $end
$upscope $end
$scope module p3 $end
$var parameter 32 C PARAM [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

259
test_regress/t/t_trace_complex_structs_cc_fst.out
View File

@ -1,102 +1,149 @@
$date
Tue Feb 17 01:32:41 2026
Sat Mar 14 09:17:04 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
$var wire 1 ! clk $end
$scope module $unit $end
$var bit 1 " global_bit $end
$upscope $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 # cyc [31:0] $end
$scope struct v_strp $end
$var bit 1 $ b1 $end
$var bit 1 % b0 $end
$upscope $end
$scope struct v_strp_strp $end
$scope struct x1 $end
$var bit 1 & b1 $end
$var bit 1 ' b0 $end
$upscope $end
$scope struct x0 $end
$var bit 1 ( b1 $end
$var bit 1 ) b0 $end
$upscope $end
$upscope $end
$scope union v_unip_strp $end
$scope struct x1 $end
$var bit 1 * b1 $end
$var bit 1 + b0 $end
$upscope $end
$scope struct x0 $end
$var bit 1 * b1 $end
$var bit 1 + b0 $end
$upscope $end
$upscope $end
$var bit 2 , v_arrp [2:1] $end
$var bit 2 - v_arrp_arrp[3] [2:1] $end
$var bit 2 . v_arrp_arrp[4] [2:1] $end
$scope struct v_arrp_strp[3] $end
$var bit 1 / b1 $end
$var bit 1 0 b0 $end
$upscope $end
$scope struct v_arrp_strp[4] $end
$var bit 1 1 b1 $end
$var bit 1 2 b0 $end
$upscope $end
$var bit 1 3 v_arru[1] $end
$var bit 1 4 v_arru[2] $end
$var bit 1 5 v_arru_arru[3][1] $end
$var bit 1 6 v_arru_arru[3][2] $end
$var bit 1 7 v_arru_arru[4][1] $end
$var bit 1 8 v_arru_arru[4][2] $end
$var bit 2 9 v_arru_arrp[3] [2:1] $end
$var bit 2 : v_arru_arrp[4] [2:1] $end
$scope struct v_arru_strp[3] $end
$var bit 1 ; b1 $end
$var bit 1 < b0 $end
$upscope $end
$scope struct v_arru_strp[4] $end
$var bit 1 = b1 $end
$var bit 1 > b0 $end
$upscope $end
$var real 64 ? v_real $end
$var real 64 @ v_arr_real[0] $end
$var real 64 A v_arr_real[1] $end
$var longint 64 B v_chandle [63:0] $end
$scope struct v_str32x2[0] $end
$var logic 32 C data [31:0] $end
$upscope $end
$scope struct v_str32x2[1] $end
$var logic 32 D data [31:0] $end
$upscope $end
$attrbegin misc 07 "" 1 $end
$var int 32 E v_enumed [31:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 F v_enumed2 [31:0] $end
$attrbegin misc 07 "" 2 $end
$var logic 3 G v_enumb [2:0] $end
$scope struct v_enumb2_str $end
$attrbegin misc 07 "" 2 $end
$var logic 3 H a [2:0] $end
$attrbegin misc 07 "" 2 $end
$var logic 3 I b [2:0] $end
$upscope $end
$var logic 8 J unpacked_array[-2] [7:0] $end
$var logic 8 K unpacked_array[-1] [7:0] $end
$var logic 8 L unpacked_array[0] [7:0] $end
$var bit 1 M LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
$upscope $end
$upscope $end
$scope module top $end
$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
$var wire 1 ! clk $end
$scope module $unit $end
$var bit 1 " global_bit $end
$upscope $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 # cyc [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct v_strp $end
$var bit 1 $ b1 $end
$var bit 1 % b0 $end
$upscope $end
$attrbegin pack packed members 2 $end
$scope struct v_strp_strp $end
$attrbegin pack packed members 2 $end
$scope struct x1 $end
$var bit 1 & b1 $end
$var bit 1 ' b0 $end
$upscope $end
$attrbegin pack packed members 2 $end
$scope struct x0 $end
$var bit 1 ( b1 $end
$var bit 1 ) b0 $end
$upscope $end
$upscope $end
$attrbegin pack packed members 2 $end
$scope union v_unip_strp $end
$attrbegin pack packed members 2 $end
$scope struct x1 $end
$var bit 1 * b1 $end
$var bit 1 + b0 $end
$upscope $end
$attrbegin pack packed members 2 $end
$scope struct x0 $end
$var bit 1 * b1 $end
$var bit 1 + b0 $end
$upscope $end
$upscope $end
$var bit 2 , v_arrp [2:1] $end
$attrbegin array packed bounds 17179869187 $end
$scope sv_array v_arrp_arrp $end
$var bit 2 - v_arrp_arrp[4] [2:1] $end
$var bit 2 . v_arrp_arrp[3] [2:1] $end
$upscope $end
$attrbegin array packed bounds 17179869187 $end
$scope sv_array v_arrp_strp $end
$attrbegin pack packed members 2 $end
$scope struct [4] $end
$var bit 1 / b1 $end
$var bit 1 0 b0 $end
$upscope $end
$attrbegin pack packed members 2 $end
$scope struct [3] $end
$var bit 1 1 b1 $end
$var bit 1 2 b0 $end
$upscope $end
$upscope $end
$attrbegin array unpacked bounds 8589934593 $end
$scope sv_array v_arru $end
$var bit 1 3 v_arru[2] $end
$var bit 1 4 v_arru[1] $end
$upscope $end
$attrbegin array unpacked bounds 17179869187 $end
$scope sv_array v_arru_arru $end
$attrbegin array unpacked bounds 8589934593 $end
$scope sv_array [4] $end
$var bit 1 5 v_arru_arru[4][2] $end
$var bit 1 6 v_arru_arru[4][1] $end
$upscope $end
$attrbegin array unpacked bounds 8589934593 $end
$scope sv_array [3] $end
$var bit 1 7 v_arru_arru[3][2] $end
$var bit 1 8 v_arru_arru[3][1] $end
$upscope $end
$upscope $end
$attrbegin array unpacked bounds 17179869187 $end
$scope sv_array v_arru_arrp $end
$var bit 2 9 v_arru_arrp[4] [2:1] $end
$var bit 2 : v_arru_arrp[3] [2:1] $end
$upscope $end
$attrbegin array unpacked bounds 17179869187 $end
$scope sv_array v_arru_strp $end
$attrbegin pack packed members 2 $end
$scope struct [4] $end
$var bit 1 ; b1 $end
$var bit 1 < b0 $end
$upscope $end
$attrbegin pack packed members 2 $end
$scope struct [3] $end
$var bit 1 = b1 $end
$var bit 1 > b0 $end
$upscope $end
$upscope $end
$var real 64 ? v_real $end
$attrbegin array unpacked bounds 1 $end
$scope sv_array v_arr_real $end
$var real 64 @ v_arr_real[0] $end
$var real 64 A v_arr_real[1] $end
$upscope $end
$var longint 64 B v_chandle [63:0] $end
$attrbegin array packed bounds 4294967296 $end
$scope sv_array v_str32x2 $end
$attrbegin pack packed members 1 $end
$scope struct [1] $end
$var logic 32 C data [31:0] $end
$upscope $end
$attrbegin pack packed members 1 $end
$scope struct [0] $end
$var logic 32 D data [31:0] $end
$upscope $end
$upscope $end
$attrbegin misc 07 "" 1 $end
$var int 32 E v_enumed [31:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 F v_enumed2 [31:0] $end
$attrbegin misc 07 "" 2 $end
$var logic 3 G v_enumb [2:0] $end
$attrbegin pack packed members 2 $end
$scope struct v_enumb2_str $end
$attrbegin misc 07 "" 2 $end
$var logic 3 H a [2:0] $end
$attrbegin misc 07 "" 2 $end
$var logic 3 I b [2:0] $end
$upscope $end
$attrbegin array unpacked bounds -8589934592 $end
$scope sv_array unpacked_array $end
$var logic 8 J unpacked_array[-2] [7:0] $end
$var logic 8 K unpacked_array[-1] [7:0] $end
$var logic 8 L unpacked_array[0] [7:0] $end
$upscope $end
$var bit 1 M LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
@ -109,8 +156,8 @@ b000 H
b000 G
b00000000000000000000000000000000 F
b00000000000000000000000000000000 E
b00000000000000000000000000000000 D
b00000000000000000000000011111111 C
b00000000000000000000000011111111 D
b00000000000000000000000000000000 C
b0000000000000000000000000000000000000000000000000000000000000000 B
r0 A
r0 @
@ -173,8 +220,8 @@ b11 :
r0.1 ?
r0.2 @
r0.3 A
b00000000000000000000000011111110 C
b00000000000000000000000000000001 D
b00000000000000000000000000000001 C
b00000000000000000000000011111110 D
b00000000000000000000000000000001 E
b00000000000000000000000000000010 F
b111 G
@ -185,8 +232,8 @@ b111 G
b110 G
b00000000000000000000000000000100 F
b00000000000000000000000000000010 E
b00000000000000000000000000000010 D
b00000000000000000000000011111101 C
b00000000000000000000000011111101 D
b00000000000000000000000000000010 C
r0.6 A
r0.4 @
r0.2 ?
@ -245,8 +292,8 @@ b11 :
r0.3 ?
r0.6000000000000001 @
r0.8999999999999999 A
b00000000000000000000000011111100 C
b00000000000000000000000000000011 D
b00000000000000000000000000000011 C
b00000000000000000000000011111100 D
b00000000000000000000000000000011 E
b00000000000000000000000000000110 F
b101 G
@ -257,8 +304,8 @@ b101 G
b100 G
b00000000000000000000000000001000 F
b00000000000000000000000000000100 E
b00000000000000000000000000000100 D
b00000000000000000000000011111011 C
b00000000000000000000000011111011 D
b00000000000000000000000000000100 C
r1.2 A
r0.8 @
r0.4 ?
@ -317,8 +364,8 @@ b11 :
r0.5 ?
r1 @
r1.5 A
b00000000000000000000000011111010 C
b00000000000000000000000000000101 D
b00000000000000000000000000000101 C
b00000000000000000000000011111010 D
b00000000000000000000000000000101 E
b00000000000000000000000000001010 F
b011 G
@ -329,8 +376,8 @@ b011 G
b010 G
b00000000000000000000000000001100 F
b00000000000000000000000000000110 E
b00000000000000000000000000000110 D
b00000000000000000000000011111001 C
b00000000000000000000000011111001 D
b00000000000000000000000000000110 C
r1.8 A
r1.2 @
r0.6 ?

257
test_regress/t/t_trace_complex_structs_sc_fst.out
View File

@ -1,101 +1,148 @@
$date
Tue Feb 17 01:32:42 2026
Sat Mar 14 09:16:58 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
$scope module $unit $end
$var bit 1 ! global_bit $end
$upscope $end
$scope module t $end
$var wire 1 " clk $end
$var integer 32 # cyc [31:0] $end
$scope struct v_strp $end
$var bit 1 $ b1 $end
$var bit 1 % b0 $end
$upscope $end
$scope struct v_strp_strp $end
$scope struct x1 $end
$var bit 1 & b1 $end
$var bit 1 ' b0 $end
$upscope $end
$scope struct x0 $end
$var bit 1 ( b1 $end
$var bit 1 ) b0 $end
$upscope $end
$upscope $end
$scope union v_unip_strp $end
$scope struct x1 $end
$var bit 1 * b1 $end
$var bit 1 + b0 $end
$upscope $end
$scope struct x0 $end
$var bit 1 * b1 $end
$var bit 1 + b0 $end
$upscope $end
$upscope $end
$var bit 2 , v_arrp [2:1] $end
$var bit 2 - v_arrp_arrp[3] [2:1] $end
$var bit 2 . v_arrp_arrp[4] [2:1] $end
$scope struct v_arrp_strp[3] $end
$var bit 1 / b1 $end
$var bit 1 0 b0 $end
$upscope $end
$scope struct v_arrp_strp[4] $end
$var bit 1 1 b1 $end
$var bit 1 2 b0 $end
$upscope $end
$var bit 1 3 v_arru[1] $end
$var bit 1 4 v_arru[2] $end
$var bit 1 5 v_arru_arru[3][1] $end
$var bit 1 6 v_arru_arru[3][2] $end
$var bit 1 7 v_arru_arru[4][1] $end
$var bit 1 8 v_arru_arru[4][2] $end
$var bit 2 9 v_arru_arrp[3] [2:1] $end
$var bit 2 : v_arru_arrp[4] [2:1] $end
$scope struct v_arru_strp[3] $end
$var bit 1 ; b1 $end
$var bit 1 < b0 $end
$upscope $end
$scope struct v_arru_strp[4] $end
$var bit 1 = b1 $end
$var bit 1 > b0 $end
$upscope $end
$var real 64 ? v_real $end
$var real 64 @ v_arr_real[0] $end
$var real 64 A v_arr_real[1] $end
$var longint 64 B v_chandle [63:0] $end
$scope struct v_str32x2[0] $end
$var logic 32 C data [31:0] $end
$upscope $end
$scope struct v_str32x2[1] $end
$var logic 32 D data [31:0] $end
$upscope $end
$attrbegin misc 07 "" 1 $end
$var int 32 E v_enumed [31:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 F v_enumed2 [31:0] $end
$attrbegin misc 07 "" 2 $end
$var logic 3 G v_enumb [2:0] $end
$scope struct v_enumb2_str $end
$attrbegin misc 07 "" 2 $end
$var logic 3 H a [2:0] $end
$attrbegin misc 07 "" 2 $end
$var logic 3 I b [2:0] $end
$upscope $end
$var logic 8 J unpacked_array[-2] [7:0] $end
$var logic 8 K unpacked_array[-1] [7:0] $end
$var logic 8 L unpacked_array[0] [7:0] $end
$var bit 1 M LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
$upscope $end
$upscope $end
$scope module top $end
$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
$scope module $unit $end
$var bit 1 ! global_bit $end
$upscope $end
$scope module t $end
$var wire 1 " clk $end
$var integer 32 # cyc [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct v_strp $end
$var bit 1 $ b1 $end
$var bit 1 % b0 $end
$upscope $end
$attrbegin pack packed members 2 $end
$scope struct v_strp_strp $end
$attrbegin pack packed members 2 $end
$scope struct x1 $end
$var bit 1 & b1 $end
$var bit 1 ' b0 $end
$upscope $end
$attrbegin pack packed members 2 $end
$scope struct x0 $end
$var bit 1 ( b1 $end
$var bit 1 ) b0 $end
$upscope $end
$upscope $end
$attrbegin pack packed members 2 $end
$scope union v_unip_strp $end
$attrbegin pack packed members 2 $end
$scope struct x1 $end
$var bit 1 * b1 $end
$var bit 1 + b0 $end
$upscope $end
$attrbegin pack packed members 2 $end
$scope struct x0 $end
$var bit 1 * b1 $end
$var bit 1 + b0 $end
$upscope $end
$upscope $end
$var bit 2 , v_arrp [2:1] $end
$attrbegin array packed bounds 17179869187 $end
$scope sv_array v_arrp_arrp $end
$var bit 2 - v_arrp_arrp[4] [2:1] $end
$var bit 2 . v_arrp_arrp[3] [2:1] $end
$upscope $end
$attrbegin array packed bounds 17179869187 $end
$scope sv_array v_arrp_strp $end
$attrbegin pack packed members 2 $end
$scope struct [4] $end
$var bit 1 / b1 $end
$var bit 1 0 b0 $end
$upscope $end
$attrbegin pack packed members 2 $end
$scope struct [3] $end
$var bit 1 1 b1 $end
$var bit 1 2 b0 $end
$upscope $end
$upscope $end
$attrbegin array unpacked bounds 8589934593 $end
$scope sv_array v_arru $end
$var bit 1 3 v_arru[2] $end
$var bit 1 4 v_arru[1] $end
$upscope $end
$attrbegin array unpacked bounds 17179869187 $end
$scope sv_array v_arru_arru $end
$attrbegin array unpacked bounds 8589934593 $end
$scope sv_array [4] $end
$var bit 1 5 v_arru_arru[4][2] $end
$var bit 1 6 v_arru_arru[4][1] $end
$upscope $end
$attrbegin array unpacked bounds 8589934593 $end
$scope sv_array [3] $end
$var bit 1 7 v_arru_arru[3][2] $end
$var bit 1 8 v_arru_arru[3][1] $end
$upscope $end
$upscope $end
$attrbegin array unpacked bounds 17179869187 $end
$scope sv_array v_arru_arrp $end
$var bit 2 9 v_arru_arrp[4] [2:1] $end
$var bit 2 : v_arru_arrp[3] [2:1] $end
$upscope $end
$attrbegin array unpacked bounds 17179869187 $end
$scope sv_array v_arru_strp $end
$attrbegin pack packed members 2 $end
$scope struct [4] $end
$var bit 1 ; b1 $end
$var bit 1 < b0 $end
$upscope $end
$attrbegin pack packed members 2 $end
$scope struct [3] $end
$var bit 1 = b1 $end
$var bit 1 > b0 $end
$upscope $end
$upscope $end
$var real 64 ? v_real $end
$attrbegin array unpacked bounds 1 $end
$scope sv_array v_arr_real $end
$var real 64 @ v_arr_real[0] $end
$var real 64 A v_arr_real[1] $end
$upscope $end
$var longint 64 B v_chandle [63:0] $end
$attrbegin array packed bounds 4294967296 $end
$scope sv_array v_str32x2 $end
$attrbegin pack packed members 1 $end
$scope struct [1] $end
$var logic 32 C data [31:0] $end
$upscope $end
$attrbegin pack packed members 1 $end
$scope struct [0] $end
$var logic 32 D data [31:0] $end
$upscope $end
$upscope $end
$attrbegin misc 07 "" 1 $end
$var int 32 E v_enumed [31:0] $end
$attrbegin misc 07 "" 1 $end
$var int 32 F v_enumed2 [31:0] $end
$attrbegin misc 07 "" 2 $end
$var logic 3 G v_enumb [2:0] $end
$attrbegin pack packed members 2 $end
$scope struct v_enumb2_str $end
$attrbegin misc 07 "" 2 $end
$var logic 3 H a [2:0] $end
$attrbegin misc 07 "" 2 $end
$var logic 3 I b [2:0] $end
$upscope $end
$attrbegin array unpacked bounds -8589934592 $end
$scope sv_array unpacked_array $end
$var logic 8 J unpacked_array[-2] [7:0] $end
$var logic 8 K unpacked_array[-1] [7:0] $end
$var logic 8 L unpacked_array[0] [7:0] $end
$upscope $end
$var bit 1 M LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
@ -108,8 +155,8 @@ b000 H
b000 G
b00000000000000000000000000000000 F
b00000000000000000000000000000000 E
b00000000000000000000000000000000 D
b00000000000000000000000011111111 C
b00000000000000000000000011111111 D
b00000000000000000000000000000000 C
b0000000000000000000000000000000000000000000000000000000000000000 B
r0 A
r0 @
@ -172,8 +219,8 @@ b11 :
r0.1 ?
r0.2 @
r0.3 A
b00000000000000000000000011111110 C
b00000000000000000000000000000001 D
b00000000000000000000000000000001 C
b00000000000000000000000011111110 D
b00000000000000000000000000000001 E
b00000000000000000000000000000010 F
b111 G
@ -184,8 +231,8 @@ b111 G
b110 G
b00000000000000000000000000000100 F
b00000000000000000000000000000010 E
b00000000000000000000000000000010 D
b00000000000000000000000011111101 C
b00000000000000000000000011111101 D
b00000000000000000000000000000010 C
r0.6 A
r0.4 @
r0.2 ?
@ -244,8 +291,8 @@ b11 :
r0.3 ?
r0.6000000000000001 @
r0.8999999999999999 A
b00000000000000000000000011111100 C
b00000000000000000000000000000011 D
b00000000000000000000000000000011 C
b00000000000000000000000011111100 D
b00000000000000000000000000000011 E
b00000000000000000000000000000110 F
b101 G
@ -256,8 +303,8 @@ b101 G
b100 G
b00000000000000000000000000001000 F
b00000000000000000000000000000100 E
b00000000000000000000000000000100 D
b00000000000000000000000011111011 C
b00000000000000000000000011111011 D
b00000000000000000000000000000100 C
r1.2 A
r0.8 @
r0.4 ?
@ -316,8 +363,8 @@ b11 :
r0.5 ?
r1 @
r1.5 A
b00000000000000000000000011111010 C
b00000000000000000000000000000101 D
b00000000000000000000000000000101 C
b00000000000000000000000011111010 D
b00000000000000000000000000000101 E
b00000000000000000000000000001010 F
b011 G
@ -328,8 +375,8 @@ b011 G
b010 G
b00000000000000000000000000001100 F
b00000000000000000000000000000110 E
b00000000000000000000000000000110 D
b00000000000000000000000011111001 C
b00000000000000000000000011111001 D
b00000000000000000000000000000110 C
r1.8 A
r1.2 @
r0.6 ?

100
test_regress/t/t_trace_dumpvars_dyn_0_cc_fst.out
View File

@ -1,60 +1,60 @@
$date
Sat Jul 19 22:57:16 2025
Sat Mar 14 09:17:08 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var int 32 " cyc [31:0] $end
$scope module sub1a $end
$var parameter 32 # ADD [31:0] $end
$var wire 32 " cyc [31:0] $end
$var int 32 $ value [31:0] $end
$scope module sub2a $end
$var parameter 32 % ADD [31:0] $end
$var wire 32 " cyc [31:0] $end
$var int 32 & value [31:0] $end
$upscope $end
$scope module sub2b $end
$var parameter 32 ' ADD [31:0] $end
$var wire 32 " cyc [31:0] $end
$var int 32 ( value [31:0] $end
$upscope $end
$scope module sub2c $end
$var parameter 32 ) ADD [31:0] $end
$var wire 32 " cyc [31:0] $end
$var int 32 * value [31:0] $end
$upscope $end
$upscope $end
$scope module sub1b $end
$var parameter 32 + ADD [31:0] $end
$var wire 32 " cyc [31:0] $end
$var int 32 , value [31:0] $end
$scope module sub2a $end
$var parameter 32 - ADD [31:0] $end
$var wire 32 " cyc [31:0] $end
$var int 32 . value [31:0] $end
$upscope $end
$scope module sub2b $end
$var parameter 32 / ADD [31:0] $end
$var wire 32 " cyc [31:0] $end
$var int 32 0 value [31:0] $end
$upscope $end
$scope module sub2c $end
$var parameter 32 1 ADD [31:0] $end
$var wire 32 " cyc [31:0] $end
$var int 32 2 value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var int 32 " cyc [31:0] $end
$scope module sub1a $end
$var parameter 32 # ADD [31:0] $end
$var wire 32 " cyc [31:0] $end
$var int 32 $ value [31:0] $end
$scope module sub2a $end
$var parameter 32 % ADD [31:0] $end
$var wire 32 " cyc [31:0] $end
$var int 32 & value [31:0] $end
$upscope $end
$scope module sub2b $end
$var parameter 32 ' ADD [31:0] $end
$var wire 32 " cyc [31:0] $end
$var int 32 ( value [31:0] $end
$upscope $end
$scope module sub2c $end
$var parameter 32 ) ADD [31:0] $end
$var wire 32 " cyc [31:0] $end
$var int 32 * value [31:0] $end
$upscope $end
$upscope $end
$scope module sub1b $end
$var parameter 32 + ADD [31:0] $end
$var wire 32 " cyc [31:0] $end
$var int 32 , value [31:0] $end
$scope module sub2a $end
$var parameter 32 - ADD [31:0] $end
$var wire 32 " cyc [31:0] $end
$var int 32 . value [31:0] $end
$upscope $end
$scope module sub2b $end
$var parameter 32 / ADD [31:0] $end
$var wire 32 " cyc [31:0] $end
$var int 32 0 value [31:0] $end
$upscope $end
$scope module sub2c $end
$var parameter 32 1 ADD [31:0] $end
$var wire 32 " cyc [31:0] $end
$var int 32 2 value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

78
test_regress/t/t_trace_dumpvars_dyn_1_cc_fst.out
View File

@ -1,49 +1,49 @@
$date
Sat Jul 19 22:57:23 2025
Sat Mar 14 09:17:06 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$scope module t $end
$var int 32 ! cyc [31:0] $end
$scope module sub1a $end
$var parameter 32 " ADD [31:0] $end
$var wire 32 ! cyc [31:0] $end
$var int 32 # value [31:0] $end
$scope module sub2a $end
$upscope $end
$scope module sub2b $end
$upscope $end
$scope module sub2c $end
$upscope $end
$upscope $end
$scope module sub1b $end
$var parameter 32 $ ADD [31:0] $end
$var wire 32 ! cyc [31:0] $end
$var int 32 % value [31:0] $end
$scope module sub2a $end
$var parameter 32 & ADD [31:0] $end
$var wire 32 ! cyc [31:0] $end
$var int 32 ' value [31:0] $end
$upscope $end
$scope module sub2b $end
$var parameter 32 ( ADD [31:0] $end
$var wire 32 ! cyc [31:0] $end
$var int 32 ) value [31:0] $end
$upscope $end
$scope module sub2c $end
$var parameter 32 * ADD [31:0] $end
$var wire 32 ! cyc [31:0] $end
$var int 32 + value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module top $end
$scope module t $end
$var int 32 ! cyc [31:0] $end
$scope module sub1a $end
$var parameter 32 " ADD [31:0] $end
$var wire 32 ! cyc [31:0] $end
$var int 32 # value [31:0] $end
$scope module sub2a $end
$upscope $end
$scope module sub2b $end
$upscope $end
$scope module sub2c $end
$upscope $end
$upscope $end
$scope module sub1b $end
$var parameter 32 $ ADD [31:0] $end
$var wire 32 ! cyc [31:0] $end
$var int 32 % value [31:0] $end
$scope module sub2a $end
$var parameter 32 & ADD [31:0] $end
$var wire 32 ! cyc [31:0] $end
$var int 32 ' value [31:0] $end
$upscope $end
$scope module sub2b $end
$var parameter 32 ( ADD [31:0] $end
$var wire 32 ! cyc [31:0] $end
$var int 32 ) value [31:0] $end
$upscope $end
$scope module sub2c $end
$var parameter 32 * ADD [31:0] $end
$var wire 32 ! cyc [31:0] $end
$var int 32 + value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

42
test_regress/t/t_trace_enum_fst.out
View File

@ -1,31 +1,31 @@
$date
Tue Feb 10 13:05:32 2026
Sat Mar 14 09:16:43 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$attrbegin misc 07 $unit::state_t 4 VAL_A VAL_B VAL_C VAL_D 00 01 10 11 1 $end
$attrbegin misc 07 t.other_state_t 3 VAL_X VAL_Y VAL_Z 00 01 10 2 $end
$var wire 1 ! clk $end
$scope module $unit $end
$upscope $end
$scope module t $end
$var wire 1 ! clk $end
$attrbegin misc 07 "" 1 $end
$var logic 2 " v_enumed [1:0] $end
$attrbegin misc 07 "" 2 $end
$var logic 2 # v_other_enumed [1:0] $end
$scope interface sink $end
$attrbegin misc 07 "" 1 $end
$var logic 2 $ state [1:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module top $end
$attrbegin misc 07 $unit::state_t 4 VAL_A VAL_B VAL_C VAL_D 00 01 10 11 1 $end
$attrbegin misc 07 t.other_state_t 3 VAL_X VAL_Y VAL_Z 00 01 10 2 $end
$var wire 1 ! clk $end
$scope module $unit $end
$upscope $end
$scope module t $end
$var wire 1 ! clk $end
$attrbegin misc 07 "" 1 $end
$var logic 2 " v_enumed [1:0] $end
$attrbegin misc 07 "" 2 $end
$var logic 2 # v_other_enumed [1:0] $end
$scope interface sink $end
$attrbegin misc 07 "" 1 $end
$var logic 2 $ state [1:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

18
test_regress/t/t_trace_event_fst.out
View File

@ -1,19 +1,19 @@
$date
Tue Jun 10 19:02:19 2025
Sat Mar 14 09:16:50 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module t $end
$var event 1 ! ev_test $end
$var int 32 " i [31:0] $end
$var bit 1 # toggle $end
$var bit 1 $ clk $end
$upscope $end
$scope module t $end
$var event 1 ! ev_test $end
$var int 32 " i [31:0] $end
$var bit 1 # toggle $end
$var bit 1 $ clk $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

7910
test_regress/t/t_trace_hier_block_default_cc_fst.out
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File diff suppressed because it is too large Load Diff

2042
test_regress/t/t_trace_hier_block_default_sc_fst.out
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2042
test_regress/t/t_trace_hier_block_notop_cc_fst.out
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test_regress/t/t_trace_hier_fst.out
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$version Generated by VerilatedVcd $end
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Sat Mar 14 09:16:58 2026
$end
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Generated by VerilatedFst
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#0
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0#
0$
0%
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0&
0'
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01
02
03
04
05
08
09
0:
0;
0<
0=
0>
0?
0@
0A
0B
0C
0D
0E
$dumpvars
0F
0G
0E
0D
0C
0B
0A
0@
0?
0>
0=
0<
0;
0:
09
08
07
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0#
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616
test_regress/t/t_trace_interface_ref_cc_fst.out
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@ -1,308 +1,328 @@
$date
Tue Oct 24 11:00:16 2023
Sat Mar 14 09:16:41 2026
$end
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fstWriter
Generated by VerilatedFst
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1ps
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$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 # value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 $ val100 [31:0] $end
$var integer 32 % val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 & value [31:0] $end
$upscope $end
$upscope $end
$scope interface intf_2 $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 ' value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 ( val100 [31:0] $end
$var integer 32 ) val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 * value [31:0] $end
$upscope $end
$upscope $end
$scope module s1 $end
$scope interface intf_for_struct $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 # value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 $ val100 [31:0] $end
$var integer 32 % val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 & value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module s2 $end
$scope interface intf_for_struct $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 ' value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 ( val100 [31:0] $end
$var integer 32 ) val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 * value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

614
test_regress/t/t_trace_interface_ref_sc_fst.out
View File

@ -1,307 +1,327 @@
$date
Sat Apr 5 13:55:38 2025
Sat Mar 14 09:17:10 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$scope interface intf_1 $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 # value [31:0] $end
$scope struct the_struct $end
$var integer 32 $ val100 [31:0] $end
$var integer 32 % val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 & value [31:0] $end
$upscope $end
$upscope $end
$scope interface intf_2 $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 ' value [31:0] $end
$scope struct the_struct $end
$var integer 32 ( val100 [31:0] $end
$var integer 32 ) val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 * value [31:0] $end
$upscope $end
$upscope $end
$scope module a $end
$scope interface intf_one $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 # value [31:0] $end
$scope struct the_struct $end
$var integer 32 $ val100 [31:0] $end
$var integer 32 % val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 & value [31:0] $end
$upscope $end
$upscope $end
$scope interface intf_two $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 ' value [31:0] $end
$scope struct the_struct $end
$var integer 32 ( val100 [31:0] $end
$var integer 32 ) val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 * value [31:0] $end
$upscope $end
$upscope $end
$scope interface intf_in_sub_all $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 + value [31:0] $end
$scope struct the_struct $end
$var integer 32 , val100 [31:0] $end
$var integer 32 - val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 . value [31:0] $end
$upscope $end
$upscope $end
$scope module ac1 $end
$scope interface intf_for_check $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 # value [31:0] $end
$scope struct the_struct $end
$var integer 32 $ val100 [31:0] $end
$var integer 32 % val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 & value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module ac2 $end
$scope interface intf_for_check $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 ' value [31:0] $end
$scope struct the_struct $end
$var integer 32 ( val100 [31:0] $end
$var integer 32 ) val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 * value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module ac3 $end
$scope interface intf_for_check $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 + value [31:0] $end
$scope struct the_struct $end
$var integer 32 , val100 [31:0] $end
$var integer 32 - val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 . value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module as3 $end
$scope interface intf_for_struct $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 + value [31:0] $end
$scope struct the_struct $end
$var integer 32 , val100 [31:0] $end
$var integer 32 - val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 . value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module abcdefghijklmnopqrstuvwxyz $end
$scope interface intf_one $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 ' value [31:0] $end
$scope struct the_struct $end
$var integer 32 ( val100 [31:0] $end
$var integer 32 ) val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 * value [31:0] $end
$upscope $end
$upscope $end
$scope interface intf_two $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 # value [31:0] $end
$scope struct the_struct $end
$var integer 32 $ val100 [31:0] $end
$var integer 32 % val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 & value [31:0] $end
$upscope $end
$upscope $end
$scope interface intf_in_sub_all $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 / value [31:0] $end
$scope struct the_struct $end
$var integer 32 0 val100 [31:0] $end
$var integer 32 1 val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 2 value [31:0] $end
$upscope $end
$upscope $end
$scope module ac1 $end
$scope interface intf_for_check $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 ' value [31:0] $end
$scope struct the_struct $end
$var integer 32 ( val100 [31:0] $end
$var integer 32 ) val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 * value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module ac2 $end
$scope interface intf_for_check $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 # value [31:0] $end
$scope struct the_struct $end
$var integer 32 $ val100 [31:0] $end
$var integer 32 % val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 & value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module ac3 $end
$scope interface intf_for_check $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 / value [31:0] $end
$scope struct the_struct $end
$var integer 32 0 val100 [31:0] $end
$var integer 32 1 val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 2 value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module as3 $end
$scope interface intf_for_struct $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 / value [31:0] $end
$scope struct the_struct $end
$var integer 32 0 val100 [31:0] $end
$var integer 32 1 val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 2 value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module c1 $end
$scope interface intf_for_check $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 # value [31:0] $end
$scope struct the_struct $end
$var integer 32 $ val100 [31:0] $end
$var integer 32 % val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 & value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module c2 $end
$scope interface intf_for_check $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 ' value [31:0] $end
$scope struct the_struct $end
$var integer 32 ( val100 [31:0] $end
$var integer 32 ) val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 * value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module s1 $end
$scope interface intf_for_struct $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 # value [31:0] $end
$scope struct the_struct $end
$var integer 32 $ val100 [31:0] $end
$var integer 32 % val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 & value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module s2 $end
$scope interface intf_for_struct $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 ' value [31:0] $end
$scope struct the_struct $end
$var integer 32 ( val100 [31:0] $end
$var integer 32 ) val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 * value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module top $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$scope module a $end
$scope module ac1 $end
$scope interface intf_for_check $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 # value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 $ val100 [31:0] $end
$var integer 32 % val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 & value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module ac2 $end
$scope interface intf_for_check $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 ' value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 ( val100 [31:0] $end
$var integer 32 ) val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 * value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module ac3 $end
$scope interface intf_for_check $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 + value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 , val100 [31:0] $end
$var integer 32 - val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 . value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module as3 $end
$scope interface intf_for_struct $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 + value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 , val100 [31:0] $end
$var integer 32 - val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 . value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope interface intf_in_sub_all $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 + value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 , val100 [31:0] $end
$var integer 32 - val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 . value [31:0] $end
$upscope $end
$upscope $end
$scope interface intf_one $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 # value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 $ val100 [31:0] $end
$var integer 32 % val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 & value [31:0] $end
$upscope $end
$upscope $end
$scope interface intf_two $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 ' value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 ( val100 [31:0] $end
$var integer 32 ) val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 * value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module abcdefghijklmnopqrstuvwxyz $end
$scope module ac1 $end
$scope interface intf_for_check $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 ' value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 ( val100 [31:0] $end
$var integer 32 ) val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 * value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module ac2 $end
$scope interface intf_for_check $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 # value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 $ val100 [31:0] $end
$var integer 32 % val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 & value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module ac3 $end
$scope interface intf_for_check $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 / value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 0 val100 [31:0] $end
$var integer 32 1 val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 2 value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module as3 $end
$scope interface intf_for_struct $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 / value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 0 val100 [31:0] $end
$var integer 32 1 val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 2 value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope interface intf_in_sub_all $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 / value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 0 val100 [31:0] $end
$var integer 32 1 val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 2 value [31:0] $end
$upscope $end
$upscope $end
$scope interface intf_one $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 ' value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 ( val100 [31:0] $end
$var integer 32 ) val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 * value [31:0] $end
$upscope $end
$upscope $end
$scope interface intf_two $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 # value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 $ val100 [31:0] $end
$var integer 32 % val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 & value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module c1 $end
$scope interface intf_for_check $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 # value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 $ val100 [31:0] $end
$var integer 32 % val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 & value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module c2 $end
$scope interface intf_for_check $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 ' value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 ( val100 [31:0] $end
$var integer 32 ) val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 * value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope interface intf_1 $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 # value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 $ val100 [31:0] $end
$var integer 32 % val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 & value [31:0] $end
$upscope $end
$upscope $end
$scope interface intf_2 $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 ' value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 ( val100 [31:0] $end
$var integer 32 ) val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 * value [31:0] $end
$upscope $end
$upscope $end
$scope module s1 $end
$scope interface intf_for_struct $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 # value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 $ val100 [31:0] $end
$var integer 32 % val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 & value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module s2 $end
$scope interface intf_for_struct $end
$var wire 1 ! clk $end
$var wire 32 " cyc [31:0] $end
$var integer 32 ' value [31:0] $end
$attrbegin pack packed members 2 $end
$scope struct the_struct $end
$var integer 32 ( val100 [31:0] $end
$var integer 32 ) val200 [31:0] $end
$upscope $end
$scope interface inner $end
$var wire 32 " cyc [31:0] $end
$var integer 32 * value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

32
test_regress/t/t_trace_no_top_name2_fst.out
View File

@ -1,26 +1,26 @@
$date
Tue Jun 10 18:57:59 2025
Sat Mar 14 09:17:09 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module $rootio $end
$var wire 1 ! clk $end
$upscope $end
$scope module foo_pkg $end
$var int 32 " foo_func__Vstatic__b_current [31:0] $end
$upscope $end
$scope module t $end
$var wire 1 ! clk $end
$var int 32 # cyc [31:0] $end
$scope module sub $end
$var int 32 $ a [31:0] $end
$upscope $end
$upscope $end
$scope module $rootio $end
$var wire 1 ! clk $end
$upscope $end
$scope module foo_pkg $end
$var int 32 " foo_func__Vstatic__b_current [31:0] $end
$upscope $end
$scope module t $end
$var wire 1 ! clk $end
$var int 32 # cyc [31:0] $end
$scope module sub $end
$var int 32 $ a [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

18
test_regress/t/t_trace_no_top_name_fst.out
View File

@ -1,19 +1,19 @@
$date
Thu Mar 12 09:19:45 2026
Sat Mar 14 09:17:18 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module another_top $end
$var wire 1 ! b $end
$upscope $end
$scope module t $end
$var wire 1 ! a $end
$upscope $end
$scope module another_top $end
$var wire 1 ! b $end
$upscope $end
$scope module t $end
$var wire 1 ! a $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

33
test_regress/t/t_trace_packed_struct_cc_fst.out
View File

@ -1,29 +1,32 @@
$date
Wed Feb 23 00:02:43 2022
Sat Mar 14 09:17:23 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var int 32 " cnt [31:0] $end
$var parameter 96 # v[0] [95:0] $end
$var parameter 96 $ v[1] [95:0] $end
$var parameter 96 % v[2] [95:0] $end
$upscope $end
$upscope $end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var int 32 " cnt [31:0] $end
$attrbegin array unpacked bounds 8589934592 $end
$scope sv_array v $end
$var parameter 96 # v[2] [95:0] $end
$var parameter 96 $ v[1] [95:0] $end
$var parameter 96 % v[0] [95:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b000100000000000000000000000000100001000000000000000000000000000100010000000000000000000000000000 %
b001100000000000000000000000000100011000000000000000000000000000100110000000000000000000000000000 %
b001000000000000000000000000000100010000000000000000000000000000100100000000000000000000000000000 $
b001100000000000000000000000000100011000000000000000000000000000100110000000000000000000000000000 #
b000100000000000000000000000000100001000000000000000000000000000100010000000000000000000000000000 #
b00000000000000000000000000000000 "
0!
$end

31
test_regress/t/t_trace_packed_struct_sc_fst.out
View File

@ -1,28 +1,31 @@
$date
Sat Apr 5 13:56:26 2025
Sat Mar 14 09:17:13 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$scope module t $end
$var wire 1 ! clk $end
$var int 32 " cnt [31:0] $end
$var parameter 96 # v[0] [95:0] $end
$var parameter 96 $ v[1] [95:0] $end
$var parameter 96 % v[2] [95:0] $end
$upscope $end
$upscope $end
$scope module top $end
$scope module t $end
$var wire 1 ! clk $end
$var int 32 " cnt [31:0] $end
$attrbegin array unpacked bounds 8589934592 $end
$scope sv_array v $end
$var parameter 96 # v[2] [95:0] $end
$var parameter 96 $ v[1] [95:0] $end
$var parameter 96 % v[0] [95:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b000100000000000000000000000000100001000000000000000000000000000100010000000000000000000000000000 %
b001100000000000000000000000000100011000000000000000000000000000100110000000000000000000000000000 %
b001000000000000000000000000000100010000000000000000000000000000100100000000000000000000000000000 $
b001100000000000000000000000000100011000000000000000000000000000100110000000000000000000000000000 #
b000100000000000000000000000000100001000000000000000000000000000100010000000000000000000000000000 #
b00000000000000000000000000000000 "
0!
$end

34
test_regress/t/t_trace_param_fst.out
View File

@ -1,27 +1,27 @@
$date
Thu Mar 12 07:53:08 2026
Sat Mar 14 09:16:46 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$var wire 1 ! i_clk $end
$var wire 3 " i_d [2:0] $end
$var wire 3 # o_q [2:0] $end
$scope module my_module_types $end
$var parameter 32 $ MY_PARAM [31:0] $end
$var parameter 32 % MY_PARAM2 [31:0] $end
$upscope $end
$scope module t $end
$var wire 1 ! i_clk $end
$var wire 3 " i_d [2:0] $end
$var wire 3 # o_q [2:0] $end
$upscope $end
$upscope $end
$scope module top $end
$var wire 1 ! i_clk $end
$var wire 3 " i_d [2:0] $end
$var wire 3 # o_q [2:0] $end
$scope module my_module_types $end
$var parameter 32 $ MY_PARAM [31:0] $end
$var parameter 32 % MY_PARAM2 [31:0] $end
$upscope $end
$scope module t $end
$var wire 1 ! i_clk $end
$var wire 3 " i_d [2:0] $end
$var wire 3 # o_q [2:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

36
test_regress/t/t_trace_primitive_cc_fst.out
View File

@ -1,28 +1,28 @@
$date
Wed Mar 11 13:01:26 2026
Sat Mar 14 09:17:00 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var logic 1 # a $end
$var logic 1 $ b $end
$var logic 1 % z $end
$scope module sub_t_i $end
$var wire 1 # x $end
$var wire 1 $ y $end
$var wire 1 % z $end
$upscope $end
$upscope $end
$upscope $end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var logic 1 # a $end
$var logic 1 $ b $end
$var logic 1 % z $end
$scope module sub_t_i $end
$var wire 1 # x $end
$var wire 1 $ y $end
$var wire 1 % z $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

34
test_regress/t/t_trace_primitive_sc_fst.out
View File

@ -1,27 +1,27 @@
$date
Wed Mar 11 13:01:29 2026
Sat Mar 14 09:17:00 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module top $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var logic 1 # a $end
$var logic 1 $ b $end
$var logic 1 % z $end
$scope module sub_t_i $end
$var wire 1 # x $end
$var wire 1 $ y $end
$var wire 1 % z $end
$upscope $end
$upscope $end
$upscope $end
$scope module top $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var logic 1 # a $end
$var logic 1 $ b $end
$var logic 1 % z $end
$scope module sub_t_i $end
$var wire 1 # x $end
$var wire 1 $ y $end
$var wire 1 % z $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

28
test_regress/t/t_trace_timing_fst.out
View File

@ -1,24 +1,24 @@
$date
Tue Jun 10 19:01:39 2025
Sat Mar 14 09:17:24 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module t $end
$var parameter 32 ! CLK_PERIOD [31:0] $end
$var parameter 32 " CLK_HALF_PERIOD [31:0] $end
$var logic 1 # rst $end
$var logic 1 $ clk $end
$var logic 1 % a $end
$var logic 1 & b $end
$var logic 1 ' c $end
$var logic 1 ( d $end
$var event 1 ) ev $end
$upscope $end
$scope module t $end
$var parameter 32 ! CLK_PERIOD [31:0] $end
$var parameter 32 " CLK_HALF_PERIOD [31:0] $end
$var logic 1 # rst $end
$var logic 1 $ clk $end
$var logic 1 % a $end
$var logic 1 & b $end
$var logic 1 ' c $end
$var logic 1 ( d $end
$var event 1 ) ev $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

52
test_regress/t/t_trace_two_dump_cc_fst.out
View File

@ -1,36 +1,36 @@
$date
Sat Mar 30 14:01:55 2024
Sat Mar 14 09:16:59 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module topa $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var integer 32 # c_trace_on [31:0] $end
$scope module sub $end
$var integer 32 $ inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module topb $end
$var wire 1 % clk $end
$scope module t $end
$var wire 1 % clk $end
$var integer 32 & cyc [31:0] $end
$var integer 32 ' c_trace_on [31:0] $end
$var real 64 ( r $end
$scope module sub $end
$var integer 32 ) inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module topa $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var integer 32 # c_trace_on [31:0] $end
$scope module sub $end
$var integer 32 $ inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module topb $end
$var wire 1 % clk $end
$scope module t $end
$var wire 1 % clk $end
$var integer 32 & cyc [31:0] $end
$var integer 32 ' c_trace_on [31:0] $end
$var real 64 ( r $end
$scope module sub $end
$var integer 32 ) inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#10
$dumpvars

52
test_regress/t/t_trace_two_hdr_cc_fst.out
View File

@ -1,36 +1,36 @@
$date
Wed Feb 23 00:03:39 2022
Sat Mar 14 09:17:27 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module topa $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var integer 32 # c_trace_on [31:0] $end
$scope module sub $end
$var integer 32 $ inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module topb $end
$var wire 1 % clk $end
$scope module t $end
$var wire 1 % clk $end
$var integer 32 & cyc [31:0] $end
$var integer 32 ' c_trace_on [31:0] $end
$var real 64 ( r $end
$scope module sub $end
$var integer 32 ) inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module topa $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var integer 32 # c_trace_on [31:0] $end
$scope module sub $end
$var integer 32 $ inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module topb $end
$var wire 1 % clk $end
$scope module t $end
$var wire 1 % clk $end
$var integer 32 & cyc [31:0] $end
$var integer 32 ' c_trace_on [31:0] $end
$var real 64 ( r $end
$scope module sub $end
$var integer 32 ) inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars

52
test_regress/t/t_trace_two_port_cc_fst.out
View File

@ -1,36 +1,36 @@
$date
Sat Mar 30 14:08:31 2024
Sat Mar 14 09:16:43 2026
$end
$version
fstWriter
Generated by VerilatedFst
$end
$timescale
1ps
1ps
$end
$scope module topa $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var integer 32 # c_trace_on [31:0] $end
$scope module sub $end
$var integer 32 $ inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module topb $end
$var wire 1 % clk $end
$scope module t $end
$var wire 1 % clk $end
$var integer 32 & cyc [31:0] $end
$var integer 32 ' c_trace_on [31:0] $end
$var real 64 ( r $end
$scope module sub $end
$var integer 32 ) inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module topa $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var integer 32 # c_trace_on [31:0] $end
$scope module sub $end
$var integer 32 $ inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module topb $end
$var wire 1 % clk $end
$scope module t $end
$var wire 1 % clk $end
$var integer 32 & cyc [31:0] $end
$var integer 32 ' c_trace_on [31:0] $end
$var real 64 ( r $end
$scope module sub $end
$var integer 32 ) inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#10
$dumpvars