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Tests: Renames. No test change.

This commit is contained in:
Wilson Snyder 2026-02-20 18:54:36 -05:00
parent f25a85ea57
commit c970743b07
11 changed files with 169 additions and 167 deletions
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37
test_regress/t/t_sys_rand.v
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@ -1,37 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2008 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t;
reg [31:0] lastrand;
reg [31:0] thisrand;
integer same = 0;
integer i;
`define TRIES 20
initial begin
// There's a 1^32 chance of the numbers being the same twice,
// so we'll allow one failure
lastrand = $random;
for (i=0; i<`TRIES; i=i+1) begin
thisrand = $random;
`ifdef TEST_VERBOSE
$write("Random = %x\n", thisrand);
`endif
if (thisrand == lastrand) same=same+1;
lastrand = thisrand;
end
if (same > 1) begin
$write("%%Error: Too many similar numbers: %d\n", same);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

60
test_regress/t/t_sys_rand_concat.v
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@ -1,60 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2008 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
module t;
`define TRIES 100
bit [6:0] b5a; // We use larger than [4:0] so make sure we truncate
bit [6:0] b5b; // We use larger than [4:0] so make sure we truncate
bit [6:0] b7c;
bit [6:0] b7d;
bit [59:0] b60c;
bit [89:0] b90c;
bit [6:0] max_b5a;
bit [6:0] max_b5b;
bit [6:0] max_b7c;
bit [6:0] max_b7d;
bit [59:0] max_b60c;
bit [89:0] max_b90c;
initial begin
for (int i = 0; i < `TRIES; ++i) begin
// verilator lint_off WIDTH
// Optimize away extracts
b5a = {$random}[4:0];
b5b = {$random}[14:10];
// Optimize away concats
b7c = {$random, $random, $random, $random, $random, $random, $random};
b7d = {{{$random}[0]}, {{$random}[0]}, {{$random}[0]}, {{$random}[0]}, {{$random}[0]}};
b60c = {$random, $random, $random, $random, $random, $random, $random};
b90c = {$random, $random, $random, $random, $random, $random, $random};
// verilator lint_on WIDTH
max_b5a = max_b5a | b5a;
max_b5b = max_b5b | b5b;
max_b7c = max_b7c | b7c;
max_b7d = max_b7d | b7d;
max_b60c = max_b60c | b60c;
max_b90c = max_b90c | b90c;
end
`checkh(max_b5a, 7'h1f);
`checkh(max_b5b, 7'h1f);
`checkh(max_b7c, 7'h7f);
`checkh(max_b7d, 7'h1f);
`checkh(max_b60c, ~ 60'h0);
`checkh(max_b90c, ~ 90'h0);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

70
test_regress/t/t_sys_rand_seed.v
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@ -1,70 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2020 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t;
integer seeda;
integer seedb;
integer seedc;
int valuea;
int valueb;
int valuec;
int igna;
int ignb;
int ignc;
initial begin
// $random unlike $urandom updates the value if given
seeda = 10;
valuea = $random(seeda);
seedb = 10;
valueb = $random(seedb);
if (valuea !== valueb) $stop;
seeda = 10;
valuea = $random(seeda);
seedb = seeda;
valueb = $random(seedb);
seedc = seedb;
valuec = $random(seedc);
if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64
if (seeda == seedb && seedb == seedc) $stop; // May false fail 1 in 1^64
valuea = $urandom(10);
valueb = $urandom(10);
valuec = $urandom(10);
if (valuea !== valueb && valueb != valuec) $stop;
valuea = $urandom(10);
valueb = $urandom(11);
valuec = $urandom(12);
if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64
$urandom(10);
valuea = $urandom;
$urandom(10);
valueb = $urandom;
$urandom(10);
valuec = $urandom;
if (valuea != valueb && valueb != valuec) $stop; // May false fail 1 in 1^64
igna = $urandom(10);
valuea = $urandom;
ignb = $urandom(10);
valueb = $urandom;
ignc = $urandom(10);
valuec = $urandom;
if (valuea != valueb && valueb != valuec) $stop; // May false fail 1 in 1^64
valuea = $urandom(10);
valueb = $urandom();
valuec = $urandom();
if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

0
test_regress/t/t_sys_rand.py → test_regress/t/t_sys_random.py
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37
test_regress/t/t_sys_random.v Normal file
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@ -0,0 +1,37 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2008 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t;
reg [31:0] lastrand;
reg [31:0] thisrand;
integer same = 0;
integer i;
`define TRIES 20
initial begin
// There's a 1^32 chance of the numbers being the same twice,
// so we'll allow one failure
lastrand = $random;
for (i = 0; i < `TRIES; i = i + 1) begin
thisrand = $random;
`ifdef TEST_VERBOSE
$write("Random = %x\n", thisrand);
`endif
if (thisrand == lastrand) same = same + 1;
lastrand = thisrand;
end
if (same > 1) begin
$write("%%Error: Too many similar numbers: %d\n", same);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

0
test_regress/t/t_sys_rand_concat.py → test_regress/t/t_sys_random_concat.py
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62
test_regress/t/t_sys_random_concat.v Normal file
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2008 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
// verilog_format: on
module t;
`define TRIES 100
bit [6:0] b5a; // We use larger than [4:0] so make sure we truncate
bit [6:0] b5b; // We use larger than [4:0] so make sure we truncate
bit [6:0] b7c;
bit [6:0] b7d;
bit [59:0] b60c;
bit [89:0] b90c;
bit [6:0] max_b5a;
bit [6:0] max_b5b;
bit [6:0] max_b7c;
bit [6:0] max_b7d;
bit [59:0] max_b60c;
bit [89:0] max_b90c;
initial begin
for (int i = 0; i < `TRIES; ++i) begin
// verilator lint_off WIDTH
// Optimize away extracts
b5a = {$random}[4:0];
b5b = {$random}[14:10];
// Optimize away concats
b7c = {$random, $random, $random, $random, $random, $random, $random};
b7d = {{{$random}[0]}, {{$random}[0]}, {{$random}[0]}, {{$random}[0]}, {{$random}[0]}};
b60c = {$random, $random, $random, $random, $random, $random, $random};
b90c = {$random, $random, $random, $random, $random, $random, $random};
// verilator lint_on WIDTH
max_b5a = max_b5a | b5a;
max_b5b = max_b5b | b5b;
max_b7c = max_b7c | b7c;
max_b7d = max_b7d | b7d;
max_b60c = max_b60c | b60c;
max_b90c = max_b90c | b90c;
end
`checkh(max_b5a, 7'h1f);
`checkh(max_b5b, 7'h1f);
`checkh(max_b7c, 7'h7f);
`checkh(max_b7d, 7'h1f);
`checkh(max_b60c, ~60'h0);
`checkh(max_b90c, ~90'h0);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

0
test_regress/t/t_sys_rand_seed.py → test_regress/t/t_sys_random_seed.py
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70
test_regress/t/t_sys_random_seed.v Normal file
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@ -0,0 +1,70 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2020 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t;
integer seeda;
integer seedb;
integer seedc;
int valuea;
int valueb;
int valuec;
int igna;
int ignb;
int ignc;
initial begin
// $random unlike $urandom updates the value if given
seeda = 10;
valuea = $random(seeda);
seedb = 10;
valueb = $random(seedb);
if (valuea !== valueb) $stop;
seeda = 10;
valuea = $random(seeda);
seedb = seeda;
valueb = $random(seedb);
seedc = seedb;
valuec = $random(seedc);
if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64
if (seeda == seedb && seedb == seedc) $stop; // May false fail 1 in 1^64
valuea = $urandom(10);
valueb = $urandom(10);
valuec = $urandom(10);
if (valuea !== valueb && valueb != valuec) $stop;
valuea = $urandom(10);
valueb = $urandom(11);
valuec = $urandom(12);
if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64
$urandom(10);
valuea = $urandom;
$urandom(10);
valueb = $urandom;
$urandom(10);
valuec = $urandom;
if (valuea != valueb && valueb != valuec) $stop; // May false fail 1 in 1^64
igna = $urandom(10);
valuea = $urandom;
ignb = $urandom(10);
valueb = $urandom;
ignc = $urandom(10);
valuec = $urandom;
if (valuea != valueb && valueb != valuec) $stop; // May false fail 1 in 1^64
valuea = $urandom(10);
valueb = $urandom();
valuec = $urandom();
if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

0
test_regress/t/t_scoped_rand_is_random.py → test_regress/t/t_x_rand_scoped_is_random.py
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0
test_regress/t/t_scoped_rand_is_random.v → test_regress/t/t_x_rand_scoped_is_random.v
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