Fix randcase under fork (#6843).
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@ -111,6 +111,7 @@ Verilator 5.043 devel
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* Fix nested struct within parameter port list (#6818) (#6824). [Luca Colagrande]
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* Fix duplicate name error with interface initial blocks (#6804) (#6805). [Thomas Dybdahl Ahle]
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* Fix firing array selects of events (#6829). [Amal Araweelo Almis]
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* Fix randcase under fork (#6843). [Amal Araweelo Almis]
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Verilator 5.042 2025-11-02
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@ -2634,6 +2634,7 @@ class RandomizeVisitor final : public VNVisitor {
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const std::string name = "__Vrandcase" + cvtToStr(m_randCaseNum++);
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AstVar* const randVarp = new AstVar{fl, VVarType::BLOCKTEMP, name, sumDTypep};
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randVarp->noSubst(true);
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randVarp->lifetime(VLifetime::AUTOMATIC_EXPLICIT);
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if (m_ftaskp) randVarp->funcLocal(true);
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AstNodeExpr* sump = new AstConst{fl, AstConst::WidthedValue{}, 64, 0};
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AstNodeIf* const firstIfsp
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator_st')
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test.compile(verilator_flags2=['--binary'])
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test.execute()
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test.passes()
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@ -0,0 +1,24 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module randcase_tb;
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int count;
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initial begin
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for (int i = 0; i < 100; i++) begin
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fork
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randcase
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1: count++;
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5: count--;
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3: ;
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endcase
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join_none
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end
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#1;
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if (count > 30) $stop; // Realistically won't happen (10^25) though not impossible
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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