Support signed multiplication in constraints (#7008)
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@ -4172,6 +4172,7 @@ public:
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}
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string emitVerilog() override { return "%k(%l %f* %r)"; }
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string emitC() override { return "VL_MULS_%nq%lq%rq(%lw, %P, %li, %ri)"; }
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string emitSMT() const override { return "(bvmul %l %r)"; }
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string emitSimpleOperator() override { return ""; }
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bool emitCheckMaxWords() override { return true; }
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bool cleanOut() const override { return false; }
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@ -6,6 +6,8 @@
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class Packet;
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rand int x;
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rand int y;
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rand int z;
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rand bit [31:0] b;
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rand bit [31:0] c;
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rand bit [31:0] d;
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@ -22,6 +24,14 @@ class Packet;
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constraint arith { x + x - x == x; }
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constraint divmod { int'((x % 5) / 2) != (b % 99) / 7; }
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constraint mul { x * 9 != b * 3; }
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constraint mul_signed {
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y * y == 4;
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y > 0;
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y < 4;
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z * z == 4;
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z < 0;
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z > -4;
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}
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constraint impl { tiny == 1 -> x != 10; }
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constraint concat { {c, b} != 'h1111; }
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constraint unary { !(-~c == 'h22); }
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@ -79,6 +89,8 @@ module t;
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if (v != 1) $stop;
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if ((p.x % 5) / 2 == (p.b % 99) / 7) $stop;
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if (p.x * 9 == p.b * 3) $stop;
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if (p.y != 2) $stop;
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if (p.z != -2) $stop;
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if (p.tiny && p.x == 10) $stop;
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if ({p.c, p.b} == 'h1111) $stop;
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if (-~p.c == 'h22) $stop;
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