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Tests: Verilog format

This commit is contained in:
Veripool API Bot 2026-03-09 21:38:29 -04:00 committed by Wilson Snyder
parent b33537d7a7
commit 1f67080a1f
1199 changed files with 39894 additions and 39281 deletions
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8
docs/gen/ex_PINMISSING_faulty.rst
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@ -4,8 +4,8 @@
:emphasize-lines: 2
module t;
sub sub(); // <--- Warning
endmodule
module sub
(output port);
sub sub (); // <--- Warning
endmodule
module sub (
output port
);

2
docs/gen/ex_PINMISSING_msg.rst
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@ -1,4 +1,4 @@
.. comment: generated by t_lint_pinmissing_bad
.. code-block::
%Warning-PINMISSING: example.v:1:8 Instance has missing pin: 'port'
%Warning-PINMISSING: example.v:1:7 Instance has missing pin: 'port'

2
test_regress/t/t_class_new_scoped.v
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@ -4,8 +4,10 @@
// SPDX-FileCopyrightText: 2024 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
class Base;
int m_ia = 10;

8
test_regress/t/t_class_param_bad_paren.out
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@ -1,6 +1,6 @@
%Error: t/t_class_param_bad_paren.v:28:11: Reference to parameterized class without #() (IEEE 1800-2023 8.25.1)
: ... Suggest use 'Cls#()'
28 | if (Cls::OTHER != 12) $stop;
| ^~~
%Error: t/t_class_param_bad_paren.v:30:9: Reference to parameterized class without #() (IEEE 1800-2023 8.25.1)
: ... Suggest use 'Cls#()'
30 | if (Cls::OTHER != 12) $stop;
| ^~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

24
test_regress/t/t_class_param_bad_paren.v
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@ -4,11 +4,13 @@
// SPDX-FileCopyrightText: 2023 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0
class Cls #(int PARAM = 1);
parameter OTHER = 12;
class Cls #(
int PARAM = 1
);
parameter OTHER = 12;
endclass
class Other extends Cls#(); // Ok
class Other extends Cls #(); // Ok
endclass
class OtherMaybe extends Cls; // Questionable but others do not warn
@ -16,16 +18,16 @@ endclass
module t;
typedef Cls#(2) Cls2_t; // Ok
typedef Cls ClsNone_t; // Ok
typedef Cls#(2) Cls2_t; // Ok
typedef Cls ClsNone_t; // Ok
Cls c; // Ok
Cls c; // Ok
initial begin
if (Cls#()::OTHER != 12) $stop; // Ok
if (Cls2_t::OTHER != 12) $stop; // ok
initial begin
if (Cls#()::OTHER != 12) $stop; // Ok
if (Cls2_t::OTHER != 12) $stop; // ok
if (Cls::OTHER != 12) $stop; // Bad #() required
end
if (Cls::OTHER != 12) $stop; // Bad #() required
end
endmodule

100
test_regress/t/t_clocking_out_on_change.v
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@ -5,57 +5,59 @@
// SPDX-License-Identifier: CC0-1.0
module t;
logic clk = 0;
initial forever #5 clk = ~clk;
int cyc = 0;
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 4) begin
$write("*-* All Finished *-*\n");
$finish();
end
end
logic clk = 0;
initial forever #5 clk = ~clk;
int cyc = 0;
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 4) begin
$write("*-* All Finished *-*\n");
$finish();
end
end
// Skew 0
logic ok1 = 1;
always @(posedge clk)
if (cyc == 0) begin
if (!ok1) $stop;
#1 cb.ok1 <= 0;
#1 if (!ok1) $stop;
end else if (cyc == 1) begin
if (!ok1) $stop;
#1 if (ok1) $stop;
end
else if (cyc == 2) ok1 <= 1;
else if (!ok1) $stop;
// Skew 0
logic ok1 = 1;
always @(posedge clk)
if (cyc == 0) begin
if (!ok1) $stop;
#1 cb.ok1 <= 0;
#1 if (!ok1) $stop;
end
else if (cyc == 1) begin
if (!ok1) $stop;
#1 if (ok1) $stop;
end
else if (cyc == 2) ok1 <= 1;
else if (!ok1) $stop;
// Skew > 0
logic ok2 = 1;
always @(posedge clk)
if (cyc == 0) begin
if (!ok2) $stop;
#1 cb.ok2 <= 0;
#2 if (!ok2) $stop;
#3 if (!ok2) $stop;
end else if (cyc == 1) begin
if (!ok2) $stop;
#1 if (!ok2) $stop;
#2 if (ok2) $stop;
end
else if (cyc == 2) ok2 <= 1;
else if (!ok2) $stop;
// Skew > 0
logic ok2 = 1;
always @(posedge clk)
if (cyc == 0) begin
if (!ok2) $stop;
#1 cb.ok2 <= 0;
#2 if (!ok2) $stop;
#3 if (!ok2) $stop;
end
else if (cyc == 1) begin
if (!ok2) $stop;
#1 if (!ok2) $stop;
#2 if (ok2) $stop;
end
else if (cyc == 2) ok2 <= 1;
else if (!ok2) $stop;
// No timing
logic ok3 = 0;
always @(posedge clk)
if (cyc == 0) ok3 <= 1;
else if (cyc == 1) if (!ok3) $stop;
// No timing
logic ok3 = 0;
always @(posedge clk)
if (cyc == 0) ok3 <= 1;
else if (cyc == 1) if (!ok3) $stop;
// Clocking (used in all tests)
clocking cb @(posedge clk);
output ok1;
output #1 ok2;
output ok3;
endclocking
// Clocking (used in all tests)
clocking cb @(posedge clk);
output ok1;
output #1 ok2;
output ok3;
endclocking
endmodule

94
test_regress/t/t_constraint_state.v
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@ -7,71 +7,71 @@
`define check_rand(cl, field, cond) \
begin \
automatic longint prev_result; \
automatic int ok; \
if (!bit'(cl.randomize())) $stop; \
prev_result = longint'(field); \
if (!(cond)) $stop; \
repeat(9) begin \
longint result; \
if (!bit'(cl.randomize())) $stop; \
result = longint'(field); \
if (!(cond)) $stop; \
if (result != prev_result) ok = 1; \
prev_result = result; \
end \
if (ok != 1) $stop; \
automatic longint prev_result; \
automatic int ok; \
if (!bit'(cl.randomize())) $stop; \
prev_result = longint'(field); \
if (!(cond)) $stop; \
repeat(9) begin \
longint result; \
if (!bit'(cl.randomize())) $stop; \
result = longint'(field); \
if (!(cond)) $stop; \
if (result != prev_result) ok = 1; \
prev_result = result; \
end \
if (ok != 1) $stop; \
end
class Foo;
int x;
int x;
endclass
class Bar;
rand int y;
rand int y;
endclass
class Packet;
rand int rf;
int state;
rand int a;
rand Foo foo;
Bar bar;
rand int rf;
int state;
rand int a;
rand Foo foo;
Bar bar;
constraint c1 { rf == state; }
constraint c2 { a > foo.x; a < bar.y; }
constraint c1 { rf == state; }
constraint c2 { a > foo.x; a < bar.y; }
function new(int s, int x, int y);
state = s;
foo = new;
foo.x = x;
bar = new;
bar.y = y;
endfunction
function new(int s, int x, int y);
state = s;
foo = new;
foo.x = x;
bar = new;
bar.y = y;
endfunction
endclass
module t;
Packet p;
Packet p;
int v;
int v;
initial begin
p = new(123, 10, 20);
v = p.randomize();
if (v != 1) $stop;
if (p.rf != 123) $stop;
initial begin
p = new(123, 10, 20);
v = p.randomize();
if (v != 1) $stop;
if (p.rf != 123) $stop;
`check_rand(p, p.a, p.a > 10 && p.a < 20)
if (p.foo.x != 10) $stop;
if (p.bar.y != 20) $stop;
`check_rand(p, p.a, p.a > 10 && p.a < 20)
if (p.foo.x != 10) $stop;
if (p.bar.y != 20) $stop;
p.state = 234;
v = p.randomize();
if (v != 1) $stop;
if (p.rf != 234) $stop;
p.state = 234;
v = p.randomize();
if (v != 1) $stop;
if (p.rf != 234) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

5
test_regress/t/t_flag_parameter.v
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@ -20,9 +20,10 @@
// | -gC6="32'h600D600D" | 32'h600D600D| 32'h600D600D| UNSUPPORTED | 32'h600D600D|
// | -gC7='AB CD' | AB CD | UNSUPPORTED | UNSUPPORTED | UNSUPPORTED |
// verilog_format: off
`define stop $stop
`define check(gotv,
expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: Wrong parameter value", `__FILE__,`__LINE__); `stop; end while(0);
`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: Wrong parameter value", `__FILE__,`__LINE__); `stop; end while(0);
// verilog_format: on
typedef enum logic [1:0] {
enum_val_0 = 2'd0,

5
test_regress/t/t_flag_parameter_hier.v
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@ -4,9 +4,10 @@
// SPDX-FileCopyrightText: 2016 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define check(gotv,
expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: %m: Wrong parameter value\n", `__FILE__,`__LINE__); `stop; end while(0);
`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: %m: Wrong parameter value\n", `__FILE__,`__LINE__); `stop; end while(0);
// verilog_format: on
module t (
input clk

36
test_regress/t/t_flag_topmodule.v
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@ -5,34 +5,34 @@
// SPDX-License-Identifier: CC0-1.0
module a;
c c ();
initial begin
$write("Bad top modules\n");
$stop;
end
c c ();
initial begin
$write("Bad top modules\n");
$stop;
end
endmodule
module a2;
initial begin
$write("Bad top modules\n");
$stop;
end
initial begin
$write("Bad top modules\n");
$stop;
end
endmodule
module b;
d d ();
d d ();
endmodule
module c;
initial begin
$write("Bad mid modules\n");
$stop;
end
initial begin
$write("Bad mid modules\n");
$stop;
end
endmodule
module d;
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

34
test_regress/t/t_flag_topmodule_inline.v
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@ -5,26 +5,30 @@
// SPDX-License-Identifier: CC0-1.0
module a;
a2 a2 (.tmp(1'b0));
initial begin
$write("Bad top modules\n");
$stop;
end
a2 a2 (.tmp(1'b0));
initial begin
$write("Bad top modules\n");
$stop;
end
endmodule
module a2 (input tmp);
l3 l3 (.tmp(tmp));
module a2 (
input tmp
);
l3 l3 (.tmp(tmp));
endmodule
module b;
l3 l3 (.tmp(1'b1));
l3 l3 (.tmp(1'b1));
endmodule
module l3 (input tmp);
initial begin
if (tmp) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
module l3 (
input tmp
);
initial begin
if (tmp) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule

5
test_regress/t/t_func_arg_complex.v
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@ -4,9 +4,10 @@
// SPDX-FileCopyrightText: 2023 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkd(gotv,
expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
class Cls;
enum {

6
test_regress/t/t_func_const3_bad.out
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@ -1,7 +1,7 @@
%Warning-WIDTHCONCAT: t/t_func_const3_bad.v:12:28: Replication of more that --replication-limit 8192 is suspect: 9000
%Warning-WIDTHCONCAT: t/t_func_const3_bad.v:13:27: Replication of more that --replication-limit 8192 is suspect: 9000
: ... note: In instance 't.b9k.c9'
12 | localparam SOMEP = {BITS{1'b0}};
| ^
13 | localparam SOMEP = {BITS{1'b0}};
| ^
... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest
... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.
%Error: Exiting due to

40
test_regress/t/t_func_const3_bad.v
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@ -4,34 +4,36 @@
// SPDX-FileCopyrightText: 2017 Todd Strader
// SPDX-License-Identifier: CC0-1.0
module c9
#(parameter A = 1,
parameter B = 1);
module c9 #(
parameter A = 1,
parameter B = 1
);
localparam BITS = A*B;
localparam SOMEP = {BITS{1'b0}};
localparam BITS = A * B;
localparam SOMEP = {BITS{1'b0}};
endmodule
module b9
#(parameter A = 1);
module b9 #(
parameter A = 1
);
c9
#(.A (A),
.B (9))
c9();
c9 #(
.A(A),
.B(9)
) c9 ();
endmodule
module t;
b9 b9();
b9 #(.A (100)) b900();
b9 #(.A (1000)) b9k();
b9 b9 ();
b9 #(.A(100)) b900 ();
b9 #(.A(1000)) b9k ();
initial begin
// Should never get here
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
// Should never get here
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

524
test_regress/t/t_hier_block.v
View File

@ -26,9 +26,9 @@ logic global_flag = 1'b0;
`endif
interface byte_ifs(input clk);
logic [7:0] data;
modport sender(input clk, output data);
modport receiver(input clk, input data);
logic [7:0] data;
modport sender(input clk, output data);
modport receiver(input clk, input data);
endinterface;
typedef enum logic [1:0] {
@ -47,74 +47,74 @@ typedef enum logic [1:0] {
`ifdef AS_PROT_LIB
module secret (
clk
);
clk
);
`else
module t #(
parameter int PARAM_A = 33,
parameter int PARAM_B = 44
) (/*AUTOARG*/
// Inputs
clk
);
// Inputs
clk
);
`endif
input clk;
input clk;
`ifdef PROTLIB_TOP
secret i_secred(.clk(clk));
secret i_secred(.clk(clk));
`else
wire [7:0] out0;
wire [7:0] out1;
wire [7:0] out2;
wire [7:0] out3;
wire [7:0] out3_2;
wire [7:0] out5;
wire [7:0] out6;
int count = 0;
wire [7:0] out0;
wire [7:0] out1;
wire [7:0] out2;
wire [7:0] out3;
wire [7:0] out3_2;
wire [7:0] out5;
wire [7:0] out6;
int count = 0;
non_hier_sub0 i_sub0(.clk(clk), .in(out3), .out(out0));
sub1 i_sub1(.clk(clk), .in(out0), .out(out1));
sub2 i_sub2(.clk(clk), .in(out1), .out(out2));
sub3 #(.P0(1)) i_sub3(.clk(clk), .in(out2), .out(out3));
// Must not use the same wrapper
sub3 #(.STR("abc"), .P0(1)) i_sub3_2(.clk(clk), .in(out2), .out(out3_2));
delay #(.N(2), 8) i_delay0(clk, out3, out5);
delay #(.N(3), 8) i_delay1(clk, out5, out6);
non_hier_sub0 i_sub0(.clk(clk), .in(out3), .out(out0));
sub1 i_sub1(.clk(clk), .in(out0), .out(out1));
sub2 i_sub2(.clk(clk), .in(out1), .out(out2));
sub3 #(.P0(1)) i_sub3(.clk(clk), .in(out2), .out(out3));
// Must not use the same wrapper
sub3 #(.STR("abc"), .P0(1)) i_sub3_2(.clk(clk), .in(out2), .out(out3_2));
delay #(.N(2), 8) i_delay0(clk, out3, out5);
delay #(.N(3), 8) i_delay1(clk, out5, out6);
always_ff @(posedge clk) begin
if (out3 != out3_2) $stop;
always_ff @(posedge clk) begin
if (out3 != out3_2) $stop;
`ifndef AS_PROT_LIB
`ifdef PARAM_OVERRIDE
if (PARAM_A != 100) $stop;
if (PARAM_B != 200) $stop;
if (PARAM_A != 100) $stop;
if (PARAM_B != 200) $stop;
`else
if (PARAM_A != 33) $stop;
if (PARAM_B != 44) $stop;
if (PARAM_A != 33) $stop;
if (PARAM_B != 44) $stop;
`endif
`endif
$display("%d %m out0:%d %d %d %d %d", count, out0, out1, out2, out3, out5, out6);
$display("%d %m child input ports: %d %d %d", count, i_sub1.in, i_sub2.in, i_sub3.in);
$display("%d %m child output ports: %d %d %d", count, i_sub1.out, i_sub2.out, i_sub3.out);
if (count == 16) begin
if (out6 == 19) begin
$write("*-* All Finished *-*\n");
$finish;
end else begin
$write("Missmatch\n");
$stop;
end
$display("%d %m out0:%d %d %d %d %d", count, out0, out1, out2, out3, out5, out6);
$display("%d %m child input ports: %d %d %d", count, i_sub1.in, i_sub2.in, i_sub3.in);
$display("%d %m child output ports: %d %d %d", count, i_sub1.out, i_sub2.out, i_sub3.out);
if (count == 16) begin
if (out6 == 19) begin
$write("*-* All Finished *-*\n");
$finish;
end else begin
$write("Missmatch\n");
$stop;
end
count <= count + 1;
end
count <= count + 1;
`ifdef STATEFUL_PKG
global_flag <= ~global_flag;
global_flag <= ~global_flag;
`endif
end
end
`ifdef CPP_MACRO
initial begin
$display("Macro for C++ compiler is defined for Verilator");
$stop;
end
initial begin
$display("Macro for C++ compiler is defined for Verilator");
$stop;
end
`endif
`systemc_implementation
@ -123,9 +123,9 @@ module t #(
#define STRINGIFY(str) STRINGIFY_IMPL(str)
namespace {
struct statically_initialized {
statically_initialized() {
std::cout << "MACRO:" << STRINGIFY(CPP_MACRO) << " is defined" << std::endl;
}
statically_initialized() {
std::cout << "MACRO:" << STRINGIFY(CPP_MACRO) << " is defined" << std::endl;
}
} g_statically_initialized;
}
`verilog
@ -135,285 +135,285 @@ struct statically_initialized {
endmodule
module non_hier_sub0(
input wire clk,
input wire[7:0] in,
output wire [7:0] out);
input wire clk,
input wire[7:0] in,
output wire [7:0] out);
sub0 i_sub0(.*);
sub0 i_sub0(.*);
endmodule
module sub0(
input wire clk,
input wire [7:0] in,
output wire [7:0] out); `HIER_BLOCK
input wire clk,
input wire [7:0] in,
output wire [7:0] out); `HIER_BLOCK
`ifdef NO_INLINE
/* verilator no_inline_module */
/* verilator no_inline_module */
`endif
logic [7:0] ff;
logic [7:0] ff;
always_ff @(posedge clk) ff <= in;
assign out = ff;
always_ff @(posedge clk) ff <= in;
assign out = ff;
`ifdef STATEFUL_PKG
always_ff @(posedge clk) if (ff[0]) global_flag <= ff[1];
always_ff @(posedge clk) if (ff[0]) global_flag <= ff[1];
`endif
endmodule
module sub1(
input wire clk,
input wire [11:4] in, // Uses higher LSB to cover bug3539
output wire [7:0] out); `HIER_BLOCK
input wire clk,
input wire [11:4] in, // Uses higher LSB to cover bug3539
output wire [7:0] out); `HIER_BLOCK
`ifdef NO_INLINE
/* verilator no_inline_module */
/* verilator no_inline_module */
`endif
logic [7:0] ff;
enum_t enum_v;
logic [7:0] ff;
enum_t enum_v;
always_ff @(posedge clk) ff <= in + 8'(stateless_pkg::ONE);
always_ff @(posedge clk) enum_v <= enum_v.next();
assign out = ff;
always_ff @(posedge clk) ff <= in + 8'(stateless_pkg::ONE);
always_ff @(posedge clk) enum_v <= enum_v.next();
assign out = ff;
endmodule
module sub2(
input wire clk,
input wire [7:0] in,
output wire [7:0] out); `HIER_BLOCK
input wire clk,
input wire [7:0] in,
output wire [7:0] out); `HIER_BLOCK
logic [7:0] ff;
alt_enum_t alt_enum_v;
logic [7:0] ff;
alt_enum_t alt_enum_v;
// dpi_import_func returns (dpi_eport_func(v) -1)
import "DPI-C" context function int dpi_import_func(int v);
export "DPI-C" function dpi_export_func;
// dpi_import_func returns (dpi_eport_func(v) -1)
import "DPI-C" context function int dpi_import_func(int v);
export "DPI-C" function dpi_export_func;
function int dpi_export_func(int v);
return v + 1;
endfunction
function int dpi_export_func(int v);
return v + 1;
endfunction
always_ff @(posedge clk) ff <= 8'(dpi_import_func({24'b0, in})) + 8'd2;
always_ff @(posedge clk) alt_enum_v <= alt_enum_v.next();
always_ff @(posedge clk) ff <= 8'(dpi_import_func({24'b0, in})) + 8'd2;
always_ff @(posedge clk) alt_enum_v <= alt_enum_v.next();
byte_ifs in_ifs(.clk(clk));
byte_ifs out_ifs(.clk(clk));
assign in_ifs.data = ff;
assign out = out_ifs.data;
non_hier_sub3 i_sub3(.in(in_ifs), .out(out_ifs));
byte_ifs in_ifs(.clk(clk));
byte_ifs out_ifs(.clk(clk));
assign in_ifs.data = ff;
assign out = out_ifs.data;
non_hier_sub3 i_sub3(.in(in_ifs), .out(out_ifs));
always @(posedge clk)
// dotted access within a hierarchical block should be OK
if (i_sub3.in_wire != ff) begin
$display("Error mismatch in %m");
$stop;
end
always @(posedge clk)
// dotted access within a hierarchical block should be OK
if (i_sub3.in_wire != ff) begin
$display("Error mismatch in %m");
$stop;
end
endmodule
module non_hier_sub3(
byte_ifs.receiver in,
byte_ifs.sender out);
byte_ifs.receiver in,
byte_ifs.sender out);
wire [7:0] in_wire, out_1, out_2;
assign in_wire = in.data;
localparam string sparam = "single quote escape comma:'\\,";
// Parameter appears in the different order from module declaration
sub3 #(.STR(sparam), .UNUSED(-16'sd3), .P0(8'd3), .ENUM(enum_val_3)) i_sub3(.clk(in.clk), .in(in.data), .out(out_1));
// Instantiate again, should use the same wrapper
sub3 #(.STR(sparam), .UNUSED(-16'sd3), .P0(8'd3), .ENUM(enum_val_3)) i_sub3_2(.clk(in.clk), .in(in.data), .out(out_2));
always @(posedge in.clk)
if (out_1 != out_2) $stop;
wire [7:0] in_wire, out_1, out_2;
assign in_wire = in.data;
localparam string sparam = "single quote escape comma:'\\,";
// Parameter appears in the different order from module declaration
sub3 #(.STR(sparam), .UNUSED(-16'sd3), .P0(8'd3), .ENUM(enum_val_3)) i_sub3(.clk(in.clk), .in(in.data), .out(out_1));
// Instantiate again, should use the same wrapper
sub3 #(.STR(sparam), .UNUSED(-16'sd3), .P0(8'd3), .ENUM(enum_val_3)) i_sub3_2(.clk(in.clk), .in(in.data), .out(out_2));
always @(posedge in.clk)
if (out_1 != out_2) $stop;
assign out.data = out_1;
assign out.data = out_1;
endmodule
module sub3 #(
parameter logic [7:0] P0 = 2 + 1,
type TYPE = logic,
parameter int UNPACKED_ARRAY[2] = '{0, 1},
parameter logic signed [15:0] UNUSED = -3,
parameter string STR = "str",
parameter enum_t ENUM = enum_val_0) (
input wire clk,
input wire [7:0] in,
output wire [7:0] out); `HIER_BLOCK
parameter logic [7:0] P0 = 2 + 1,
type TYPE = logic,
parameter int UNPACKED_ARRAY[2] = '{0, 1},
parameter logic signed [15:0] UNUSED = -3,
parameter string STR = "str",
parameter enum_t ENUM = enum_val_0) (
input wire clk,
input wire [7:0] in,
output wire [7:0] out); `HIER_BLOCK
`ifdef NO_INLINE
/* verilator no_inline_module */
/* verilator no_inline_module */
`endif
initial $display("P0:%d UNUSED:%d %s %d", P0, UNUSED, STR, ENUM);
initial $display("P0:%d UNUSED:%d %s %d", P0, UNUSED, STR, ENUM);
TYPE [7:0] ff;
always_ff @(posedge clk) ff <= in + P0;
always_ff @(posedge clk) if (out4 != out4_2) $stop;
TYPE [7:0] ff;
always_ff @(posedge clk) ff <= in + P0;
always_ff @(posedge clk) if (out4 != out4_2) $stop;
wire [7:0] out4;
wire [7:0] out4_2;
assign out = out4;
/* verilator lint_off REALCVT */
sub4 #(.P0(1.6), .P1(3.1), .P3(4.1)) i_sub4_0(.clk(clk), .in(ff), .out(out4)); // incr 2
sub4 #(.P0(2.4), .P1(3.1), .P3(5)) i_sub4_1(.clk(clk), .in(), .out(out4_2));
/* verilator lint_on REALCVT */
/* verilator lint_off ASSIGNIN */
assign i_sub4_1.in = ff; // Hierarchical reference to port of hier_block is OK
/* verilator lint_off ASSIGNIN */
wire [7:0] out4;
wire [7:0] out4_2;
assign out = out4;
/* verilator lint_off REALCVT */
sub4 #(.P0(1.6), .P1(3.1), .P3(4.1)) i_sub4_0(.clk(clk), .in(ff), .out(out4)); // incr 2
sub4 #(.P0(2.4), .P1(3.1), .P3(5)) i_sub4_1(.clk(clk), .in(), .out(out4_2));
/* verilator lint_on REALCVT */
/* verilator lint_off ASSIGNIN */
assign i_sub4_1.in = ff; // Hierarchical reference to port of hier_block is OK
/* verilator lint_off ASSIGNIN */
always @(posedge clk) begin
$display("%d %m child input ports: %d %d", $time, i_sub4_0.in, i_sub4_1.in);
$display("%d %m child output ports: %d %d", $time, i_sub4_0.out, i_sub4_1.out);
end
always @(posedge clk) begin
$display("%d %m child input ports: %d %d", $time, i_sub4_0.in, i_sub4_1.in);
$display("%d %m child output ports: %d %d", $time, i_sub4_0.out, i_sub4_1.out);
end
endmodule
module sub4 #(
parameter int P0 = 1.1,
parameter P1 = 2,
parameter real P3 = 3) (
input wire clk,
input wire [7:0] in,
output wire[7:0] out); `HIER_BLOCK
parameter int P0 = 1.1,
parameter P1 = 2,
parameter real P3 = 3) (
input wire clk,
input wire [7:0] in,
output wire[7:0] out); `HIER_BLOCK
`ifdef NO_INLINE
/* verilator no_inline_module */
/* verilator no_inline_module */
`endif
initial begin
if (P1 == 2) begin
$display("P1(%f) is not properly set", P1);
$stop;
initial begin
if (P1 == 2) begin
$display("P1(%f) is not properly set", P1);
$stop;
end
end
reg [7:0] ff;
always_ff @(posedge clk) ff <= in + 8'(P0);
assign out = ff;
logic [127:0] sub5_in[2][3];
wire [7:0] sub5_out[2][3];
sub5 i_sub5(.clk(clk), .in(sub5_in), .out(sub5_out));
int count = 0;
always @(posedge clk) begin
if (!count[0]) begin
sub5_in[0][0] <= 128'd0;
sub5_in[0][1] <= 128'd1;
sub5_in[0][2] <= 128'd2;
sub5_in[1][0] <= 128'd3;
sub5_in[1][1] <= 128'd4;
sub5_in[1][2] <= 128'd5;
end else begin
sub5_in[0][0] <= 128'd0;
sub5_in[0][1] <= 128'd0;
sub5_in[0][2] <= 128'd0;
sub5_in[1][0] <= 128'd0;
sub5_in[1][1] <= 128'd0;
sub5_in[1][2] <= 128'd0;
end
end
int driven_from_bind = 0;
always @(posedge clk) begin
count <= count + 1;
if (count > 0) begin
for (int i = 0; i < 2; ++i) begin
for (int j = 0; j < 3; ++j) begin
automatic byte exp = !count[0] ? 8'(3 * (1 - i) + (2- j) + 1) : 8'b0;
if (sub5_out[i][j] != exp) begin
$display("in[%d][%d] act:%d exp:%d", i, j, sub5_out[i][j], exp);
$stop;
end
if (i_sub5.out[i][j] != exp) begin
$display("in[%d][%d] act:%d exp:%d", i, j, i_sub5.out[i][j], exp);
$stop;
end
end
end
end
reg [7:0] ff;
always_ff @(posedge clk) ff <= in + 8'(P0);
assign out = ff;
logic [127:0] sub5_in[2][3];
wire [7:0] sub5_out[2][3];
sub5 i_sub5(.clk(clk), .in(sub5_in), .out(sub5_out));
int count = 0;
always @(posedge clk) begin
if (!count[0]) begin
sub5_in[0][0] <= 128'd0;
sub5_in[0][1] <= 128'd1;
sub5_in[0][2] <= 128'd2;
sub5_in[1][0] <= 128'd3;
sub5_in[1][1] <= 128'd4;
sub5_in[1][2] <= 128'd5;
end else begin
sub5_in[0][0] <= 128'd0;
sub5_in[0][1] <= 128'd0;
sub5_in[0][2] <= 128'd0;
sub5_in[1][0] <= 128'd0;
sub5_in[1][1] <= 128'd0;
sub5_in[1][2] <= 128'd0;
if (driven_from_bind != int'(2*P1)) begin
$display("%m driven_from_bind: %0d != %0d", driven_from_bind, int'(2*P1));
$stop;
end
end
int driven_from_bind = 0;
always @(posedge clk) begin
count <= count + 1;
if (count > 0) begin
for (int i = 0; i < 2; ++i) begin
for (int j = 0; j < 3; ++j) begin
automatic byte exp = !count[0] ? 8'(3 * (1 - i) + (2- j) + 1) : 8'b0;
if (sub5_out[i][j] != exp) begin
$display("in[%d][%d] act:%d exp:%d", i, j, sub5_out[i][j], exp);
$stop;
end
if (i_sub5.out[i][j] != exp) begin
$display("in[%d][%d] act:%d exp:%d", i, j, i_sub5.out[i][j], exp);
$stop;
end
end
end
if (driven_from_bind != int'(2*P1)) begin
$display("%m driven_from_bind: %0d != %0d", driven_from_bind, int'(2*P1));
$stop;
end
end
end
end
end
endmodule
module sub5 (input wire clk, input wire [127:0] in[2][3], output logic [7:0] out[2][3]); `HIER_BLOCK
`ifdef NO_INLINE
/* verilator no_inline_module */
/* verilator no_inline_module */
`endif
int count = 0;
always @(posedge clk) begin
count <= count + 1;
if (count > 0) begin
for (int i = 0; i < 2; ++i) begin
for (int j = 0; j < 3; ++j) begin
automatic bit [127:0] exp = count[0] ? 128'(3 * i + 128'(j)) : 128'd0;
if (in[i][j] != exp) begin
$display("in[%d][%d] act:%d exp:%d", i, j, in[i][j], exp);
$stop;
end
end
end
int count = 0;
always @(posedge clk) begin
count <= count + 1;
if (count > 0) begin
for (int i = 0; i < 2; ++i) begin
for (int j = 0; j < 3; ++j) begin
automatic bit [127:0] exp = count[0] ? 128'(3 * i + 128'(j)) : 128'd0;
if (in[i][j] != exp) begin
$display("in[%d][%d] act:%d exp:%d", i, j, in[i][j], exp);
$stop;
end
end
end
end
end
end
always @(posedge clk) begin
if (count[0]) begin
out[0][0] <= 8'd6;
out[0][1] <= 8'd5;
out[0][2] <= 8'd4;
out[1][0] <= 8'd3;
out[1][1] <= 8'd2;
out[1][2] <= 8'd1;
end else begin
out[0][0] <= 8'd0;
out[0][1] <= 8'd0;
out[0][2] <= 8'd0;
out[1][0] <= 8'd0;
out[1][1] <= 8'd0;
out[1][2] <= 8'd0;
end
end
always @(posedge clk) begin
if (count[0]) begin
out[0][0] <= 8'd6;
out[0][1] <= 8'd5;
out[0][2] <= 8'd4;
out[1][0] <= 8'd3;
out[1][1] <= 8'd2;
out[1][2] <= 8'd1;
end else begin
out[0][0] <= 8'd0;
out[0][1] <= 8'd0;
out[0][2] <= 8'd0;
out[1][0] <= 8'd0;
out[1][1] <= 8'd0;
out[1][2] <= 8'd0;
end
end
wire [7:0] val0[2];
wire [7:0] val1[2];
wire [7:0] val2[2];
wire [7:0] val3[2];
sub6 i_sub0(.out(val0));
sub6 #(.P0(1)) i_sub1(.out(val1)); // Setting the default value
sub6 #(.P0(1), .P1(2)) i_sub2(.out(val2)); // Setting the default value
sub6 #(.P0(1), .P1(3)) i_sub3(.out(val3));
wire [7:0] val0[2];
wire [7:0] val1[2];
wire [7:0] val2[2];
wire [7:0] val3[2];
sub6 i_sub0(.out(val0));
sub6 #(.P0(1)) i_sub1(.out(val1)); // Setting the default value
sub6 #(.P0(1), .P1(2)) i_sub2(.out(val2)); // Setting the default value
sub6 #(.P0(1), .P1(3)) i_sub3(.out(val3));
always @(posedge clk) begin
if (val0[0] != 1 || val0[1] != 2) $stop;
if (val1[0] != 1 || val1[1] != 2) $stop;
if (val2[0] != 1 || val2[1] != 2) $stop;
if (val3[0] != 1 || val3[1] != 3) $stop;
end
always @(posedge clk) begin
if (val0[0] != 1 || val0[1] != 2) $stop;
if (val1[0] != 1 || val1[1] != 2) $stop;
if (val2[0] != 1 || val2[1] != 2) $stop;
if (val3[0] != 1 || val3[1] != 3) $stop;
end
endmodule
module sub6 #(parameter P0 = 1, parameter P1 = 2) (output wire [7:0] out[2]); `HIER_BLOCK
`ifdef NO_INLINE
/* verilator no_inline_module */
/* verilator no_inline_module */
`endif
assign out[0] = 8'(P0);
assign out[1] = 8'(P1);
assign out[0] = 8'(P0);
assign out[1] = 8'(P1);
endmodule
module delay #(
parameter N = 1,
parameter WIDTH = 8) (
input wire clk,
input wire[WIDTH-1:0] in,
output wire [WIDTH-1:0]out); `HIER_BLOCK
parameter N = 1,
parameter WIDTH = 8) (
input wire clk,
input wire[WIDTH-1:0] in,
output wire [WIDTH-1:0]out); `HIER_BLOCK
reg [WIDTH-1:0] tmp;
always_ff @(posedge clk) tmp <= in;
if (N > 1) begin
delay #(.N(N - 1), WIDTH) i_delay(clk, tmp, out);
end else begin
assign out = tmp;
end
reg [WIDTH-1:0] tmp;
always_ff @(posedge clk) tmp <= in;
if (N > 1) begin
delay #(.N(N - 1), WIDTH) i_delay(clk, tmp, out);
end else begin
assign out = tmp;
end
endmodule
// Module bound into parametrized hier_block that undergoes name mangling

40
test_regress/t/t_inside3.v
View File

@ -14,24 +14,24 @@ class Foo;
endclass
module t;
Foo foo;
Foo array[100];
Foo res[$];
initial begin
foo = new;
for (int i = 0; i < 100; ++i) begin
array[i] = new;
end
if (!(foo.get() inside {3,4,5,6,7,8,9})) $stop;
if (foo.callCount != 1) $stop;
if (!(foo.get() inside {[3:9]})) $stop;
if (foo.callCount != 2) $stop;
res = array.find(x) with (x.get() inside {5,7,8,9});
if (res.size() != 0) $stop;
for (int i = 0; i < 100; ++i) begin
if (array[i].callCount != 1) $stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
Foo foo;
Foo array[100];
Foo res[$];
initial begin
foo = new;
for (int i = 0; i < 100; ++i) begin
array[i] = new;
end
if (!(foo.get() inside {3, 4, 5, 6, 7, 8, 9})) $stop;
if (foo.callCount != 1) $stop;
if (!(foo.get() inside {[3 : 9]})) $stop;
if (foo.callCount != 2) $stop;
res = array.find(x) with (x.get() inside {5, 7, 8, 9});
if (res.size() != 0) $stop;
for (int i = 0; i < 100; ++i) begin
if (array[i].callCount != 1) $stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

59
test_regress/t/t_langext_1.v
View File

@ -12,40 +12,41 @@
// SPDX-FileCopyrightText: 2012 Jeremy Bennett
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
// Inputs
clk
);
input clk;
wire [1:0] res;
wire [1:0] res;
// Instantiate the test
test test_i (// Outputs
.res (res[1:0]),
// Inputs
.clk (clk),
.in (1'b1));
// Instantiate the test
test test_i ( // Outputs
.res(res[1:0]),
// Inputs
.clk(clk),
.in(1'b1)
);
endmodule
module test (// Outputs
res,
// Inputs
clk,
in
);
output reg [1:0] res;
input clk;
input in;
module test ( // Outputs
res,
// Inputs
clk,
in
);
output reg [1:0] res;
input clk;
input in;
// This is a Verilog 2001 test
generate
genvar i;
for (i=0; i<2; i=i+1) begin
always @(posedge clk) begin
res[i:i] <= in;
end
// This is a Verilog 2001 test
generate
genvar i;
for (i = 0; i < 2; i = i + 1) begin
always @(posedge clk) begin
res[i:i] <= in;
end
endgenerate
end
endgenerate
endmodule

10
test_regress/t/t_langext_1_bad.out
View File

@ -1,9 +1,9 @@
%Error: t/t_langext_1.v:44:7: syntax error, unexpected IDENTIFIER-for-type
44 | genvar i;
| ^~~~~~
%Error: t/t_langext_1.v:45:5: syntax error, unexpected IDENTIFIER-for-type
45 | genvar i;
| ^~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_langext_1.v:51:1: syntax error, unexpected endmodule, expecting '('
51 | endmodule
%Error: t/t_langext_1.v:52:1: syntax error, unexpected endmodule, expecting '('
52 | endmodule
| ^~~~~~~~~
%Error: Cannot continue
... This fatal error may be caused by the earlier error(s); resolve those first.

10
test_regress/t/t_langext_1d_bad.out
View File

@ -1,9 +1,9 @@
%Error: t/t_langext_1.v:44:7: syntax error, unexpected IDENTIFIER-for-type
44 | genvar i;
| ^~~~~~
%Error: t/t_langext_1.v:45:5: syntax error, unexpected IDENTIFIER-for-type
45 | genvar i;
| ^~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_langext_1.v:51:1: syntax error, unexpected endmodule, expecting '('
51 | endmodule
%Error: t/t_langext_1.v:52:1: syntax error, unexpected endmodule, expecting '('
52 | endmodule
| ^~~~~~~~~
%Error: Cannot continue
... This fatal error may be caused by the earlier error(s); resolve those first.

67
test_regress/t/t_langext_2.v
View File

@ -12,45 +12,46 @@
// SPDX-FileCopyrightText: 2012 Jeremy Bennett
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t ( /*AUTOARG*/
// Inputs
clk
);
input clk;
reg [1:0] res;
reg [1:0] res;
// Instantiate the test
test test_i (/*AUTOINST*/
// Outputs
.res (res),
// Inputs
.clk (clk),
.in (1'b1));
// Instantiate the test
test test_i ( /*AUTOINST*/
// Outputs
.res(res),
// Inputs
.clk(clk),
.in(1'b1)
);
endmodule
module test (// Outputs
res,
// Inputs
clk,
in
);
output [1:0] res;
input clk;
input in;
module test ( // Outputs
res,
// Inputs
clk,
in
);
output [1:0] res;
input clk;
input in;
// This is a SystemVerilog 2009 only test
generate
genvar i;
for (i=0; i<2; i=i+1) begin
always @(posedge clk) begin
unique0 case (i)
0: res[0:0] <= in;
1: res[1:1] <= in;
endcase
end
// This is a SystemVerilog 2009 only test
generate
genvar i;
for (i = 0; i < 2; i = i + 1) begin
always @(posedge clk) begin
unique0 case (i)
0: res[0:0] <= in;
1: res[1:1] <= in;
endcase
end
endgenerate
end
endgenerate
endmodule

12
test_regress/t/t_langext_2_bad.out
View File

@ -1,9 +1,9 @@
%Error: t/t_langext_2.v:46:7: syntax error, unexpected IDENTIFIER-for-type
46 | genvar i;
| ^~~~~~
%Error: t/t_langext_2.v:47:5: syntax error, unexpected IDENTIFIER-for-type
47 | genvar i;
| ^~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_langext_2.v:49:21: syntax error, unexpected case
49 | unique0 case (i)
| ^~~~
%Error: t/t_langext_2.v:50:17: syntax error, unexpected case
50 | unique0 case (i)
| ^~~~
%Error: Cannot continue
... This fatal error may be caused by the earlier error(s); resolve those first.

12
test_regress/t/t_langext_3.v
View File

@ -11,12 +11,12 @@
// SPDX-FileCopyrightText: 2012 Jeremy Bennett
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t ( /*AUTOARG*/
// Inputs
clk
);
input clk;
uwire w; // Only in Verilog 2005
uwire w; // Only in Verilog 2005
endmodule

6
test_regress/t/t_langext_3_bad.out
View File

@ -1,5 +1,5 @@
%Error: t/t_langext_3.v:20:4: Can't find typedef/interface: 'uwire'
20 | uwire w;
| ^~~~~
%Error: t/t_langext_3.v:20:3: Can't find typedef/interface: 'uwire'
20 | uwire w;
| ^~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

6
test_regress/t/t_langext_4_bad.out
View File

@ -1,6 +1,6 @@
%Error: t/t_langext_2.v:49:21: syntax error, unexpected case
49 | unique0 case (i)
| ^~~~
%Error: t/t_langext_2.v:50:17: syntax error, unexpected case
50 | unique0 case (i)
| ^~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Cannot continue
... This fatal error may be caused by the earlier error(s); resolve those first.

2
test_regress/t/t_langext_order.v
View File

@ -9,5 +9,5 @@
// verilator lint_off SYMRSVDWORD
module t(input do);
t_langext_order_sub sub (.do(do));
t_langext_order_sub sub (.do(do));
endmodule

26
test_regress/t/t_leak.v
View File

@ -4,22 +4,24 @@
// SPDX-FileCopyrightText: 2006 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (clk);
module t (
clk
);
sub sub ();
sub sub ();
input clk;
integer cyc=1;
input clk;
integer cyc = 1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==2) begin
// Not $finish; as we don't want a message to scroll by
$c("Verilated::threadContextp()->gotFinish(true);");
end
end
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 2) begin
// Not $finish; as we don't want a message to scroll by
$c("Verilated::threadContextp()->gotFinish(true);");
end
end
endmodule
module sub;
/* verilator public_module */
/* verilator public_module */
endmodule

50
test_regress/t/t_let.v
View File

@ -5,35 +5,35 @@
// SPDX-License-Identifier: CC0-1.0
package Pkg;
let P = 11;
let PP(a) = 30 + a;
let P = 11;
let PP(a) = 30 + a;
endpackage
module t;
let A = 10;
let B() = 20;
let C(a) = 30 + a;
let D(a, b) = 30 + a + b;
let E(a=1, b=7) = 30 + a + b;
let F(untyped a) = 30 + a;
let A = 10;
let B() = 20;
let C(a) = 30 + a;
let D(a, b) = 30 + a + b;
let E(a=1, b=7) = 30 + a + b;
let F(untyped a) = 30 + a;
initial begin
if (A != 10) $stop;
if (A() != 10) $stop;
if (B != 20) $stop;
if (B() != 20) $stop;
if (C(1) != (30 + 1)) $stop;
if (C(.a(1)) != (30 + 1)) $stop;
if (D(1, 2) != (30 + 1 + 2)) $stop;
if (D(.a(1), .b(2)) != (30 + 1 + 2)) $stop;
if (E(2) != (30 + 2 + 7)) $stop;
if (E(.b(1)) != (30 + 1 + 1)) $stop;
if (F(1) != (30 + 1)) $stop;
if (Pkg::P != 11) $stop;
if (Pkg::PP(6) != (30 + 6)) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
if (A != 10) $stop;
if (A() != 10) $stop;
if (B != 20) $stop;
if (B() != 20) $stop;
if (C(1) != (30 + 1)) $stop;
if (C(.a(1)) != (30 + 1)) $stop;
if (D(1, 2) != (30 + 1 + 2)) $stop;
if (D(.a(1), .b(2)) != (30 + 1 + 2)) $stop;
if (E(2) != (30 + 2 + 7)) $stop;
if (E(.b(1)) != (30 + 1 + 1)) $stop;
if (F(1) != (30 + 1)) $stop;
if (Pkg::P != 11) $stop;
if (Pkg::PP(6) != (30 + 6)) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

54
test_regress/t/t_let_arg_bad.out
View File

@ -1,29 +1,29 @@
%Error: t/t_let_arg_bad.v:13:18: Too many arguments in call to let 'NO_ARG'
13 | if (NO_ARG(10) != 10) $stop;
| ^~~~~~
: ... Location of let 'NO_ARG' declaration:
9 | let NO_ARG = 10;
| ^~~~~~
%Error: t/t_let_arg_bad.v:13:16: Too many arguments in call to let 'NO_ARG'
13 | if (NO_ARG(10) != 10) $stop;
| ^~~~~~
: ... Location of let 'NO_ARG' declaration:
9 | let NO_ARG = 10;
| ^~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_let_arg_bad.v:14:11: Missing argument on non-defaulted argument 'a' in function call to LET 'ONE_ARG'
14 | if (ONE_ARG != 10) $stop;
| ^~~~~~~
%Error: t/t_let_arg_bad.v:15:11: Missing argument on non-defaulted argument 'a' in function call to LET 'ONE_ARG'
15 | if (ONE_ARG() != 10) $stop;
| ^~~~~~~
%Error: t/t_let_arg_bad.v:16:23: Too many arguments in call to let 'ONE_ARG'
16 | if (ONE_ARG(10, 20) != 10) $stop;
| ^~~~~~~
: ... Location of let 'ONE_ARG' declaration:
10 | let ONE_ARG(a) = 10;
| ^~~~~~~
%Error: t/t_let_arg_bad.v:17:20: No such argument 'b' in call to let 'ONE_ARG'
17 | if (ONE_ARG(.b(1)) != 10) $stop;
| ^~~~~~~
: ... Location of let 'ONE_ARG' declaration
10 | let ONE_ARG(a) = 10;
| ^~~~~~~
%Error: t/t_let_arg_bad.v:17:11: Missing argument on non-defaulted argument 'a' in function call to LET 'ONE_ARG'
17 | if (ONE_ARG(.b(1)) != 10) $stop;
| ^~~~~~~
%Error: t/t_let_arg_bad.v:14:9: Missing argument on non-defaulted argument 'a' in function call to LET 'ONE_ARG'
14 | if (ONE_ARG != 10) $stop;
| ^~~~~~~
%Error: t/t_let_arg_bad.v:15:9: Missing argument on non-defaulted argument 'a' in function call to LET 'ONE_ARG'
15 | if (ONE_ARG() != 10) $stop;
| ^~~~~~~
%Error: t/t_let_arg_bad.v:16:21: Too many arguments in call to let 'ONE_ARG'
16 | if (ONE_ARG(10, 20) != 10) $stop;
| ^~~~~~~
: ... Location of let 'ONE_ARG' declaration:
10 | let ONE_ARG(a) = 10;
| ^~~~~~~
%Error: t/t_let_arg_bad.v:17:18: No such argument 'b' in call to let 'ONE_ARG'
17 | if (ONE_ARG(.b(1)) != 10) $stop;
| ^~~~~~~
: ... Location of let 'ONE_ARG' declaration
10 | let ONE_ARG(a) = 10;
| ^~~~~~~
%Error: t/t_let_arg_bad.v:17:9: Missing argument on non-defaulted argument 'a' in function call to LET 'ONE_ARG'
17 | if (ONE_ARG(.b(1)) != 10) $stop;
| ^~~~~~~
%Error: Exiting due to

22
test_regress/t/t_let_arg_bad.v
View File

@ -6,17 +6,17 @@
module t;
let NO_ARG = 10;
let ONE_ARG(a) = 10;
let NO_ARG = 10;
let ONE_ARG(a) = 10;
initial begin
if (NO_ARG(10) != 10) $stop; // BAD extra arg
if (ONE_ARG != 10) $stop; // BAD need arg
if (ONE_ARG() != 10) $stop; // BAD need arg
if (ONE_ARG(10, 20) != 10) $stop; // BAD extra arg
if (ONE_ARG(.b(1)) != 10) $stop; // BAD wrong arg name
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
if (NO_ARG(10) != 10) $stop; // BAD extra arg
if (ONE_ARG != 10) $stop; // BAD need arg
if (ONE_ARG() != 10) $stop; // BAD need arg
if (ONE_ARG(10, 20) != 10) $stop; // BAD extra arg
if (ONE_ARG(.b(1)) != 10) $stop; // BAD wrong arg name
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

6
test_regress/t/t_let_recurse_bad.out
View File

@ -1,5 +1,5 @@
%Error: t/t_let_recurse_bad.v:9:36: Recursive let substitution 'RECURSE'
9 | let RECURSE(a) = (a == 1) ? 1 : RECURSE(a - 1);
| ^~~~~~~
%Error: t/t_let_recurse_bad.v:9:35: Recursive let substitution 'RECURSE'
9 | let RECURSE(a) = (a == 1) ? 1 : RECURSE(a - 1);
| ^~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

12
test_regress/t/t_let_recurse_bad.v
View File

@ -6,12 +6,12 @@
module t;
let RECURSE(a) = (a == 1) ? 1 : RECURSE(a - 1); // BAD no recursion per IEEE 1800-2023 11.12
let RECURSE(a) = (a == 1) ? 1 : RECURSE(a - 1); // BAD no recursion per IEEE 1800-2023 11.12
initial begin
if (RECURSE(1) != 1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
if (RECURSE(1) != 1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

6
test_regress/t/t_let_stmt_bad.out
View File

@ -1,5 +1,5 @@
%Error: t/t_let_stmt_bad.v:15:14: Expected statement, not let substitution 'letf'
15 | 0: letf(0);
| ^~~~
%Error: t/t_let_stmt_bad.v:15:10: Expected statement, not let substitution 'letf'
15 | 0: letf(0);
| ^~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

14
test_regress/t/t_let_stmt_bad.v
View File

@ -6,14 +6,14 @@
module t;
wire clk;
wire clk;
let letf(x) = (x << 1);
let letf(x) = (x << 1);
always @(posedge clk) begin
case (0)
0: letf(0); // Bad, need a statement
endcase
end
always @(posedge clk) begin
case (0)
0: letf(0); // Bad, need a statement
endcase
end
endmodule

12
test_regress/t/t_let_unsup.out
View File

@ -1,8 +1,8 @@
%Error-UNSUPPORTED: t/t_let_unsup.v:10:10: Unsupported: let typed ports
10 | let G(int a) = 30 + a;
| ^~~
%Error-UNSUPPORTED: t/t_let_unsup.v:10:9: Unsupported: let typed ports
10 | let G(int a) = 30 + a;
| ^~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_let_unsup.v:11:10: Unsupported: let typed ports
11 | let H(signed a) = 30 + a;
| ^~~~~~
%Error-UNSUPPORTED: t/t_let_unsup.v:11:9: Unsupported: let typed ports
11 | let H(signed a) = 30 + a;
| ^~~~~~
%Error: Exiting due to

20
test_regress/t/t_let_unsup.v
View File

@ -6,16 +6,16 @@
module t;
let F(untyped a) = 30 + a;
let G(int a) = 30 + a;
let H(signed a) = 30 + a;
let F(untyped a) = 30 + a;
let G(int a) = 30 + a;
let H(signed a) = 30 + a;
initial begin
if (F(1) != (30 + 1)) $stop;
if (G(1) != (30 + 1)) $stop;
if (H(1) != (30 + 1)) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
if (F(1) != (30 + 1)) $stop;
if (G(1) != (30 + 1)) $stop;
if (H(1) != (30 + 1)) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

334
test_regress/t/t_lib_prot.v
View File

@ -10,187 +10,187 @@ sig``_in <= {8{crc}}; \
/* verilator lint_on WIDTH */
`define CHECK(sig) \
if (cyc > 0 && sig``_in != sig``_out) begin \
$display(`"%%Error (%m) sig``_in (0x%0x) != sig``_out (0x%0x)`", \
sig``_in, sig``_out); \
$stop; \
end
$display(`"%%Error (%m) sig``_in (0x%0x) != sig``_out (0x%0x)`", \
sig``_in, sig``_out); \
$stop; \
end
module t #(parameter GATED_CLK = 0) (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Inputs
clk
);
input clk;
localparam last_cyc =
localparam last_cyc =
`ifdef TEST_BENCHMARK
`TEST_BENCHMARK;
`TEST_BENCHMARK;
`else
10;
10;
`endif
genvar x;
generate
for (x = 0; x < 2; x = x + 1) begin: gen_loop
integer cyc = 0;
reg [63:0] crc = 64'h5aef0c8d_d70a4497;
logic [31:0] accum_in;
logic [31:0] accum_out;
logic accum_bypass;
logic [31:0] accum_bypass_out;
logic [31:0] accum_out_expect;
logic [31:0] accum_bypass_out_expect;
logic s1_in;
logic s1_out;
logic s1up_in[2];
logic s1up_out[2];
logic [1:0] s2_in;
logic [1:0] s2_out;
logic [7:0] s8_in;
logic [7:0] s8_out;
logic [32:0] s33_in;
logic [32:0] s33_out;
logic [63:0] s64_in;
logic [63:0] s64_out;
logic [64:0] s65_in;
logic [64:0] s65_out;
logic [128:0] s129_in;
logic [128:0] s129_out;
logic [3:0] [31:0] s4x32_in;
logic [3:0] [31:0] s4x32_out;
/*verilator lint_off ASCRANGE*/
logic [0:15] s6x16up_in[0:1][2:0];
logic [0:15] s6x16up_out[0:1][2:0];
/*verilator lint_on ASCRANGE*/
logic [15:0] s8x16up_in[1:0][0:3];
logic [15:0] s8x16up_out[1:0][0:3];
logic [15:0] s8x16up_3d_in[1:0][0:1][0:1];
logic [15:0] s8x16up_3d_out[1:0][0:1][0:1];
genvar x;
generate
for (x = 0; x < 2; x = x + 1) begin: gen_loop
integer cyc = 0;
reg [63:0] crc = 64'h5aef0c8d_d70a4497;
logic [31:0] accum_in;
logic [31:0] accum_out;
logic accum_bypass;
logic [31:0] accum_bypass_out;
logic [31:0] accum_out_expect;
logic [31:0] accum_bypass_out_expect;
logic s1_in;
logic s1_out;
logic s1up_in[2];
logic s1up_out[2];
logic [1:0] s2_in;
logic [1:0] s2_out;
logic [7:0] s8_in;
logic [7:0] s8_out;
logic [32:0] s33_in;
logic [32:0] s33_out;
logic [63:0] s64_in;
logic [63:0] s64_out;
logic [64:0] s65_in;
logic [64:0] s65_out;
logic [128:0] s129_in;
logic [128:0] s129_out;
logic [3:0] [31:0] s4x32_in;
logic [3:0] [31:0] s4x32_out;
/*verilator lint_off ASCRANGE*/
logic [0:15] s6x16up_in[0:1][2:0];
logic [0:15] s6x16up_out[0:1][2:0];
/*verilator lint_on ASCRANGE*/
logic [15:0] s8x16up_in[1:0][0:3];
logic [15:0] s8x16up_out[1:0][0:3];
logic [15:0] s8x16up_3d_in[1:0][0:1][0:1];
logic [15:0] s8x16up_3d_out[1:0][0:1][0:1];
wire clk_en = crc[0];
wire clk_en = crc[0];
secret
secret (
.accum_in,
.accum_out,
.accum_bypass,
.accum_bypass_out,
.s1_in,
.s1_out,
.s1up_in,
.s1up_out,
.s2_in,
.s2_out,
.s8_in,
.s8_out,
.s33_in,
.s33_out,
.s64_in,
.s64_out,
.s65_in,
.s65_out,
.s129_in,
.s129_out,
.s4x32_in,
.s4x32_out,
.s6x16up_in,
.s6x16up_out,
.s8x16up_in,
.s8x16up_out,
.s8x16up_3d_in,
.s8x16up_3d_out,
.clk_en,
.clk);
secret
secret (
.accum_in,
.accum_out,
.accum_bypass,
.accum_bypass_out,
.s1_in,
.s1_out,
.s1up_in,
.s1up_out,
.s2_in,
.s2_out,
.s8_in,
.s8_out,
.s33_in,
.s33_out,
.s64_in,
.s64_out,
.s65_in,
.s65_out,
.s129_in,
.s129_out,
.s4x32_in,
.s4x32_out,
.s6x16up_in,
.s6x16up_out,
.s8x16up_in,
.s8x16up_out,
.s8x16up_3d_in,
.s8x16up_3d_out,
.clk_en,
.clk);
always @(posedge clk) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$display("[%0t] x=%0d, cyc=%0d accum_in=%0d accum_out=%0d accum_bypass_out=%0d",
$time, x, cyc, accum_in, accum_out, accum_bypass_out);
$display("[%0t] x=%0d, cyc=%0d accum_in=%0d accum_out=%0d accum_bypass_out=%0d",
$time, x, cyc, accum_in, accum_out, accum_bypass_out);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
accum_in <= accum_in + 5;
`DRIVE(s1)
`DRIVE(s2)
`DRIVE(s8)
`DRIVE(s33)
`DRIVE(s64)
`DRIVE(s65)
`DRIVE(s129)
`DRIVE(s4x32)
{s1up_in[1], s1up_in[0]} <= {^crc, ~(^crc)};
{s6x16up_in[0][0], s6x16up_in[0][1], s6x16up_in[0][2]} <= crc[47:0];
{s6x16up_in[1][0], s6x16up_in[1][1], s6x16up_in[1][2]} <= ~crc[63:16];
{s8x16up_in[0][0], s8x16up_in[0][1], s8x16up_in[0][2], s8x16up_in[0][3]} <= crc;
{s8x16up_in[1][0], s8x16up_in[1][1], s8x16up_in[1][2], s8x16up_in[1][3]} <= ~crc;
{s8x16up_3d_in[0][0][0], s8x16up_3d_in[0][0][1]} <= ~crc[31:0];
{s8x16up_3d_in[0][1][0], s8x16up_3d_in[0][1][1]} <= ~crc[63:32];
{s8x16up_3d_in[1][0][0], s8x16up_3d_in[1][0][1]} <= crc[31:0];
{s8x16up_3d_in[1][1][0], s8x16up_3d_in[1][1][1]} <= crc[63:32];
if (cyc == 0) begin
accum_in <= x*100;
accum_bypass <= '0;
end else if (cyc > 0) begin
if (accum_out_expect != accum_out) begin
$display("%%Error: (%m) accum_out expected %0d got %0d",
accum_out_expect, accum_out);
$stop;
end
if (accum_bypass_out_expect != accum_bypass_out) begin
$display("%%Error: (%m) accum_bypass_out expected %0d got %0d",
accum_bypass_out_expect, accum_bypass_out);
$stop;
end
end
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
accum_in <= accum_in + 5;
`DRIVE(s1)
`DRIVE(s2)
`DRIVE(s8)
`DRIVE(s33)
`DRIVE(s64)
`DRIVE(s65)
`DRIVE(s129)
`DRIVE(s4x32)
{s1up_in[1], s1up_in[0]} <= {^crc, ~(^crc)};
{s6x16up_in[0][0], s6x16up_in[0][1], s6x16up_in[0][2]} <= crc[47:0];
{s6x16up_in[1][0], s6x16up_in[1][1], s6x16up_in[1][2]} <= ~crc[63:16];
{s8x16up_in[0][0], s8x16up_in[0][1], s8x16up_in[0][2], s8x16up_in[0][3]} <= crc;
{s8x16up_in[1][0], s8x16up_in[1][1], s8x16up_in[1][2], s8x16up_in[1][3]} <= ~crc;
{s8x16up_3d_in[0][0][0], s8x16up_3d_in[0][0][1]} <= ~crc[31:0];
{s8x16up_3d_in[0][1][0], s8x16up_3d_in[0][1][1]} <= ~crc[63:32];
{s8x16up_3d_in[1][0][0], s8x16up_3d_in[1][0][1]} <= crc[31:0];
{s8x16up_3d_in[1][1][0], s8x16up_3d_in[1][1][1]} <= crc[63:32];
if (cyc == 0) begin
accum_in <= x*100;
accum_bypass <= '0;
end else if (cyc > 0) begin
if (accum_out_expect != accum_out) begin
$display("%%Error: (%m) accum_out expected %0d got %0d",
accum_out_expect, accum_out);
$stop;
end
if (accum_bypass_out_expect != accum_bypass_out) begin
$display("%%Error: (%m) accum_bypass_out expected %0d got %0d",
accum_bypass_out_expect, accum_bypass_out);
$stop;
end
end
if (cyc == 5) accum_bypass <= '1;
if (cyc == 5) accum_bypass <= '1;
if (x == 0 && cyc == last_cyc) begin
$display("final cycle = %0d", cyc);
$write("*-* All Finished *-*\n");
$finish;
end
end
logic possibly_gated_clk;
if (GATED_CLK != 0) begin: yes_gated_clock
logic clk_en_latch;
// verilator lint_off COMBDLY,LATCH
always_comb if (clk == '0) clk_en_latch <= clk_en;
// verilator lint_on COMBDLY,LATCH
assign possibly_gated_clk = clk & clk_en_latch;
end else begin: no_gated_clock
assign possibly_gated_clk = clk;
end
always @(posedge possibly_gated_clk) begin
// 7 is the secret_value inside the secret module
accum_out_expect <= accum_in + accum_out_expect + 7;
end
always @(*) begin
// XSim (and maybe all event simulators?) sees the moment where
// s1_in has not yet propagated to s1_out, however, they do always
// both change at the same time
/* verilator lint_off STMTDLY */
#1;
/* verilator lint_on STMTDLY */
`CHECK(s1)
`CHECK(s1up)
`CHECK(s2)
`CHECK(s8)
`CHECK(s33)
`CHECK(s64)
`CHECK(s65)
`CHECK(s129)
`CHECK(s4x32)
`CHECK(s6x16up)
`CHECK(s8x16up)
`CHECK(s8x16up_3d)
end
assign accum_bypass_out_expect = accum_bypass ? accum_in :
accum_out_expect;
if (x == 0 && cyc == last_cyc) begin
$display("final cycle = %0d", cyc);
$write("*-* All Finished *-*\n");
$finish;
end
end
endgenerate
logic possibly_gated_clk;
if (GATED_CLK != 0) begin: yes_gated_clock
logic clk_en_latch;
// verilator lint_off COMBDLY,LATCH
always_comb if (clk == '0) clk_en_latch <= clk_en;
// verilator lint_on COMBDLY,LATCH
assign possibly_gated_clk = clk & clk_en_latch;
end else begin: no_gated_clock
assign possibly_gated_clk = clk;
end
always @(posedge possibly_gated_clk) begin
// 7 is the secret_value inside the secret module
accum_out_expect <= accum_in + accum_out_expect + 7;
end
always @(*) begin
// XSim (and maybe all event simulators?) sees the moment where
// s1_in has not yet propagated to s1_out, however, they do always
// both change at the same time
/* verilator lint_off STMTDLY */
#1;
/* verilator lint_on STMTDLY */
`CHECK(s1)
`CHECK(s1up)
`CHECK(s2)
`CHECK(s8)
`CHECK(s33)
`CHECK(s64)
`CHECK(s65)
`CHECK(s129)
`CHECK(s4x32)
`CHECK(s6x16up)
`CHECK(s8x16up)
`CHECK(s8x16up_3d)
end
assign accum_bypass_out_expect = accum_bypass ? accum_in :
accum_out_expect;
end
endgenerate
endmodule

92
test_regress/t/t_lib_prot_comb.v
View File

@ -4,53 +4,71 @@
// SPDX-License-Identifier: CC0-1.0
`ifdef PROCESS_TOP
// verilog_format: off
`define CHECK if (out0 != (in0 ^ in1) || out1 != (in0 | in1) || out2__under != (in0 & in1)) begin \
$display("Mismatch in0:%b in1:%b out0:%b out1:%b out2:%b", in0, in1, out0, out1, out2__under); \
$stop; \
end
// verilog_format: on
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t ( /*AUTOARG*/
// Inputs
clk
);
input clk;
logic in0, in1;
logic out0, out1, out2__under;
logic [31:0] count = 0;
// actually XOR and OR and AND
secret i_secret(.in0(in0), .in1(in1), .out0(out0), .out1(out1), .out2__under(out2__under));
logic in0, in1;
logic out0, out1, out2__under;
logic [31:0] count = 0;
// actually XOR and OR and AND
secret i_secret (
.in0(in0),
.in1(in1),
.out0(out0),
.out1(out1),
.out2__under(out2__under)
);
always @(posedge clk) begin
count <= count + 32'd1;
if (count == 32'd1) begin
in0 <= 1'b0;
in1 <= 1'b0;
end else if (count == 32'd2) begin
`CHECK
in0 <= 1'b1;
in1 <= 1'b0;
end else if (count == 32'd3) begin
`CHECK
in0 <= 1'b0;
in1 <= 1'b1;
end else if (count == 32'd4) begin
`CHECK
in0 <= 1'b1;
in1 <= 1'b1;
end else if (count == 32'd5) begin
`CHECK
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge clk) begin
count <= count + 32'd1;
if (count == 32'd1) begin
in0 <= 1'b0;
in1 <= 1'b0;
end
else if (count == 32'd2) begin
`CHECK
in0 <= 1'b1;
in1 <= 1'b0;
end
else if (count == 32'd3) begin
`CHECK
in0 <= 1'b0;
in1 <= 1'b1;
end
else if (count == 32'd4) begin
`CHECK
in0 <= 1'b1;
in1 <= 1'b1;
end
else if (count == 32'd5) begin
`CHECK
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`else
module secret(input in0, input in1, output out0, output out1, output out2__under);
assign out0 = in0 ^ in1;
assign out1 = in0 | in1;
assign out2__under = in0 & in1;
module secret (
input in0,
input in1,
output out0,
output out1,
output out2__under
);
assign out0 = in0 ^ in1;
assign out1 = in0 | in1;
assign out2__under = in0 & in1;
endmodule
`endif

8
test_regress/t/t_lib_prot_delay_bad.v
View File

@ -4,8 +4,8 @@
// SPDX-License-Identifier: CC0-1.0
module secret_impl;
initial begin
#10;
$stop;
end
initial begin
#10;
$stop;
end
endmodule

6
test_regress/t/t_lib_prot_inout_bad.out
View File

@ -1,5 +1,5 @@
%Error-UNSUPPORTED: t/t_lib_prot_inout_bad.v:9:28: Unsupported: --lib-create port direction: INOUT
9 | inout z,
| ^
%Error-UNSUPPORTED: t/t_lib_prot_inout_bad.v:9:11: Unsupported: --lib-create port direction: INOUT
9 | inout z,
| ^
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

13
test_regress/t/t_lib_prot_inout_bad.v
View File

@ -4,12 +4,13 @@
// SPDX-License-Identifier: CC0-1.0
module secret_impl (
input a,
input oe,
inout z,
output y);
input a,
input oe,
inout z,
output y
);
assign z = oe ? a : 1'bz;
assign y = z;
assign z = oe ? a : 1'bz;
assign y = z;
endmodule

175
test_regress/t/t_lib_prot_secret.v
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@ -3,108 +3,115 @@
// SPDX-FileCopyrightText: 2019 Todd Strader
// SPDX-License-Identifier: CC0-1.0
module secret #(parameter GATED_CLK = 0)
(
input [31:0] accum_in,
output wire [31:0] accum_out,
input accum_bypass,
output [31:0] accum_bypass_out,
input s1_in,
output logic s1_out,
input s1up_in[2],
output logic s1up_out[2],
input [1:0] s2_in,
output logic [1:0] s2_out,
input [7:0] s8_in,
output logic [7:0] s8_out,
input [32:0] s33_in,
output logic [32:0] s33_out,
input [63:0] s64_in,
output logic [63:0] s64_out,
input [64:0] s65_in,
output logic [64:0] s65_out,
input [128:0] s129_in,
output logic [128:0] s129_out,
input [3:0] [31:0] s4x32_in,
output logic [3:0] [31:0] s4x32_out,
module secret #(
parameter GATED_CLK = 0
) (
input [31:0] accum_in,
output wire [31:0] accum_out,
input accum_bypass,
output [31:0] accum_bypass_out,
input s1_in,
output logic s1_out,
input s1up_in[2],
output logic s1up_out[2],
input [1:0] s2_in,
output logic [1:0] s2_out,
input [7:0] s8_in,
output logic [7:0] s8_out,
input [32:0] s33_in,
output logic [32:0] s33_out,
input [63:0] s64_in,
output logic [63:0] s64_out,
input [64:0] s65_in,
output logic [64:0] s65_out,
input [128:0] s129_in,
output logic [128:0] s129_out,
input [3:0][31:0] s4x32_in,
output logic [3:0][31:0] s4x32_out,
/*verilator lint_off ASCRANGE*/
input [0:15] s6x16up_in[0:1][2:0],
output logic [0:15] s6x16up_out[0:1][2:0],
input [0:15] s6x16up_in[0:1][2:0],
output logic [0:15] s6x16up_out[0:1][2:0],
/*verilator lint_on ASCRANGE*/
input [15:0] s8x16up_in[1:0][0:3],
output logic [15:0] s8x16up_out[1:0][0:3],
input [15:0] s8x16up_3d_in[1:0][0:1][0:1],
output logic [15:0] s8x16up_3d_out[1:0][0:1][0:1],
input clk_en,
input clk);
input [15:0] s8x16up_in[1:0][0:3],
output logic [15:0] s8x16up_out[1:0][0:3],
input [15:0] s8x16up_3d_in[1:0][0:1][0:1],
output logic [15:0] s8x16up_3d_out[1:0][0:1][0:1],
input clk_en,
input clk
);
logic [31:0] secret_accum_q = 0;
logic [31:0] secret_value = 7;
logic [31:0] secret_accum_q = 0;
logic [31:0] secret_value = 7;
initial $display("created %m");
initial $display("created %m");
logic the_clk;
generate
if (GATED_CLK != 0) begin: yes_gated_clock
logic clk_en_latch;
/* verilator lint_off COMBDLY */
/* verilator lint_off LATCH */
always_comb if (clk == '0) clk_en_latch <= clk_en;
/* verilator lint_on LATCH */
/* verilator lint_on COMBDLY */
assign the_clk = clk & clk_en_latch;
end else begin: no_gated_clock
assign the_clk = clk;
end
endgenerate
logic the_clk;
generate
if (GATED_CLK != 0) begin : yes_gated_clock
logic clk_en_latch;
/* verilator lint_off COMBDLY */
/* verilator lint_off LATCH */
always_comb if (clk == '0) clk_en_latch <= clk_en;
/* verilator lint_on LATCH */
/* verilator lint_on COMBDLY */
assign the_clk = clk & clk_en_latch;
end
else begin : no_gated_clock
assign the_clk = clk;
end
endgenerate
always @(posedge the_clk) begin
secret_accum_q <= secret_accum_q + accum_in + secret_value;
end
always @(posedge the_clk) begin
secret_accum_q <= secret_accum_q + accum_in + secret_value;
end
// Test combinatorial paths of different sizes
always @(*) begin
s1_out = s1_in;
s1up_out = s1up_in;
s2_out = s2_in;
s8_out = s8_in;
s64_out = s64_in;
s65_out = s65_in;
s129_out = s129_in;
s4x32_out = s4x32_in;
end
// Test combinatorial paths of different sizes
always @(*) begin
s1_out = s1_in;
s1up_out = s1up_in;
s2_out = s2_in;
s8_out = s8_in;
s64_out = s64_in;
s65_out = s65_in;
s129_out = s129_in;
s4x32_out = s4x32_in;
end
for (genvar i = 0; i < 3; ++i) begin
assign s6x16up_out[0][i] = s6x16up_in[0][i];
assign s6x16up_out[1][i] = s6x16up_in[1][i];
end
for (genvar i = 0; i < 4; ++i) begin
assign s8x16up_out[0][i] = s8x16up_in[0][i];
assign s8x16up_out[1][i] = s8x16up_in[1][i];
end
for (genvar i = 0; i < 8; ++i) begin
assign s8x16up_3d_out[i[2]][i[1]][i[0]] = s8x16up_3d_in[i[2]][i[1]][i[0]];
end
for (genvar i = 0; i < 3; ++i) begin
assign s6x16up_out[0][i] = s6x16up_in[0][i];
assign s6x16up_out[1][i] = s6x16up_in[1][i];
end
for (genvar i = 0; i < 4; ++i) begin
assign s8x16up_out[0][i] = s8x16up_in[0][i];
assign s8x16up_out[1][i] = s8x16up_in[1][i];
end
for (genvar i = 0; i < 8; ++i) begin
assign s8x16up_3d_out[i[2]][i[1]][i[0]] = s8x16up_3d_in[i[2]][i[1]][i[0]];
end
sub sub (.sub_in(s33_in), .sub_out(s33_out));
sub sub (
.sub_in(s33_in),
.sub_out(s33_out)
);
// Test sequential path
assign accum_out = secret_accum_q;
// Test sequential path
assign accum_out = secret_accum_q;
// Test mixed combinatorial/sequential path
assign accum_bypass_out = accum_bypass ? accum_in : secret_accum_q;
// Test mixed combinatorial/sequential path
assign accum_bypass_out = accum_bypass ? accum_in : secret_accum_q;
final $display("destroying %m");
final $display("destroying %m");
endmodule
module sub (
input [32:0] sub_in,
output [32:0] sub_out);
input [32:0] sub_in,
output [32:0] sub_out
);
/*verilator no_inline_module*/
/*verilator no_inline_module*/
assign sub_out = sub_in;
assign sub_out = sub_in;
endmodule

24
test_regress/t/t_lint_always_comb_bad.out
View File

@ -1,20 +1,20 @@
%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:29:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'temp1'
%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:29:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'temp1'
: ... note: In instance 't'
29 | temp1 = 'h0;
| ^~~~~
29 | temp1 = 'h0;
| ^~~~~
... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest
%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:31:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'temp1'
%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:31:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'temp1'
: ... note: In instance 't'
31 | temp1 = (temp1_d1r - 'h1);
| ^~~~~
%Warning-ALWCOMBORDER: t/t_lint_always_comb_bad.v:32:7: Always_comb variable driven after use: 'mid'
31 | temp1 = (temp1_d1r - 'h1);
| ^~~~~
%Warning-ALWCOMBORDER: t/t_lint_always_comb_bad.v:32:5: Always_comb variable driven after use: 'mid'
: ... note: In instance 't'
32 | mid = (temp1_d1r == 'h0);
| ^~~
32 | mid = (temp1_d1r == 'h0);
| ^~~
... For warning description see https://verilator.org/warn/ALWCOMBORDER?v=latest
... Use "/* verilator lint_off ALWCOMBORDER */" and lint_on around source to disable this message.
%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:46:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'temp1_d1r'
%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:46:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'temp1_d1r'
: ... note: In instance 't'
46 | temp1_d1r <= temp1;
| ^~~~~~~~~
46 | temp1_d1r <= temp1;
| ^~~~~~~~~
%Error: Exiting due to

70
test_regress/t/t_lint_always_comb_bad.v
View File

@ -5,45 +5,45 @@
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
mid, o3,
// Inputs
clk, i3
);
input clk;
output logic mid;
input i3;
output logic o3;
// Outputs
mid, o3,
// Inputs
clk, i3
);
input clk;
output logic mid;
input i3;
output logic o3;
wire [15:0] temp1;
wire [15:0] temp1_d1r;
wire [15:0] temp1;
wire [15:0] temp1_d1r;
logic setbefore;
always_comb begin
setbefore = 1'b1;
if (setbefore) setbefore = 1'b0; // fine
end
logic setbefore;
always_comb begin
setbefore = 1'b1;
if (setbefore) setbefore = 1'b0; // fine
end
always_comb begin
if (mid)
temp1 = 'h0;
else
temp1 = (temp1_d1r - 'h1);
mid = (temp1_d1r == 'h0); // BAD
end
always_comb begin
if (mid)
temp1 = 'h0;
else
temp1 = (temp1_d1r - 'h1);
mid = (temp1_d1r == 'h0); // BAD
end
always_comb begin
o3 = 'h0;
case (i3)
1'b1: begin
o3 = i3;
end
default: ;
endcase
end
always_comb begin
o3 = 'h0;
case (i3)
1'b1: begin
o3 = i3;
end
default: ;
endcase
end
always_ff @ (posedge clk) begin
temp1_d1r <= temp1;
end
always_ff @ (posedge clk) begin
temp1_d1r <= temp1;
end
endmodule

109
test_regress/t/t_lint_always_comb_iface.v
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@ -6,89 +6,80 @@
interface my_if;
logic valid;
logic [7:0] data ;
logic valid;
logic [7:0] data;
modport slave_mp (
input valid,
input data
);
modport slave_mp(input valid, input data);
modport master_mp (
output valid,
output data
);
modport master_mp(output valid, output data);
endinterface
module t
(
input wire in_valid,
input wire [7:0] in_data
);
module t (
input wire in_valid,
input wire [7:0] in_data
);
my_if in_i ();
my_if out1_i ();
my_if out2_i ();
my_if out3_i ();
my_if in_i ();
my_if out1_i ();
my_if out2_i ();
my_if out3_i ();
assign in_i.valid = in_valid;
assign in_i.data = in_data ;
assign in_i.valid = in_valid;
assign in_i.data = in_data;
my_module1 my_module1_i (
.in_i (in_i ),
.out_i (out1_i)
);
my_module1 my_module1_i (
.in_i(in_i),
.out_i(out1_i)
);
my_module2 my_module2_i (
.in_i (in_i ),
.out_i (out2_i)
);
my_module2 my_module2_i (
.in_i(in_i),
.out_i(out2_i)
);
my_module3 my_module3_i (
.in_i (in_i ),
.out_i (out3_i)
);
my_module3 my_module3_i (
.in_i(in_i),
.out_i(out3_i)
);
endmodule
module my_module1 (
my_if.slave_mp in_i,
my_if.master_mp out_i
);
my_if.slave_mp in_i,
my_if.master_mp out_i
);
// Gives ALWCOMBORDER warning
always_comb
begin
out_i.valid = in_i.valid;
out_i.data = in_i.data ;
end
// Gives ALWCOMBORDER warning
always_comb begin
out_i.valid = in_i.valid;
out_i.data = in_i.data;
end
endmodule
module my_module2 (
my_if.slave_mp in_i,
my_if.master_mp out_i
);
my_if.slave_mp in_i,
my_if.master_mp out_i
);
// Works if you initialise to non-interface signal first
always_comb
begin
out_i.valid = '0;
out_i.data = 'X;
out_i.valid = in_i.valid;
out_i.data = in_i.data ;
end
// Works if you initialise to non-interface signal first
always_comb begin
out_i.valid = '0;
out_i.data = 'X;
out_i.valid = in_i.valid;
out_i.data = in_i.data;
end
endmodule
module my_module3 (
my_if.slave_mp in_i,
my_if.master_mp out_i
);
my_if.slave_mp in_i,
my_if.master_mp out_i
);
// Works if you use assign signal
assign out_i.valid = in_i.valid;
assign out_i.data = in_i.data ;
// Works if you use assign signal
assign out_i.valid = in_i.valid;
assign out_i.data = in_i.data;
endmodule

140
test_regress/t/t_lint_always_comb_multidriven_bad.out
View File

@ -1,83 +1,83 @@
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:26:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out1'
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:26:15: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out1'
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:26:16:
26 | always_comb out1 = d;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:25:11: ... Location of other write
25 | assign out1 = 1'b0;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:26:15:
26 | always_comb out1 = d;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:25:10: ... Location of other write
25 | assign out1 = 1'b0;
| ^~~~
... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest
... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message.
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:29:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out2'
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:29:15: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out2'
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:29:16:
29 | always_comb out2 = 1'b0;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:28:11: ... Location of other write
28 | assign out2 = d;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:32:11: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'out3'
t/t_lint_always_comb_multidriven_bad.v:29:15:
29 | always_comb out2 = 1'b0;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:28:10: ... Location of other write
28 | assign out2 = d;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:32:10: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'out3'
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:32:11:
32 | assign out3 = 1'b0;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:31:16: ... Location of always_comb write
31 | always_comb out3 = d;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:35:11: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'out4'
t/t_lint_always_comb_multidriven_bad.v:32:10:
32 | assign out3 = 1'b0;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:31:15: ... Location of always_comb write
31 | always_comb out3 = d;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:35:10: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'out4'
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:35:11:
35 | assign out4 = d;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:34:16: ... Location of always_comb write
34 | always_comb out4 = 1'b0;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:38:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out5'
t/t_lint_always_comb_multidriven_bad.v:35:10:
35 | assign out4 = d;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:34:15: ... Location of always_comb write
34 | always_comb out4 = 1'b0;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:38:15: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out5'
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:38:16:
38 | always_comb out5 = d;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:37:16: ... Location of other write
37 | always_comb out5 = 1'b0;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:41:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out6'
t/t_lint_always_comb_multidriven_bad.v:38:15:
38 | always_comb out5 = d;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:37:15: ... Location of other write
37 | always_comb out5 = 1'b0;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:41:15: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out6'
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:41:16:
41 | always_comb out6 = 1'b0;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:40:16: ... Location of other write
40 | always_comb out6 = d;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:17:15: Bit [0] of signal 'out2' have multiple combinational drivers. This can cause performance degradation.
t/t_lint_always_comb_multidriven_bad.v:41:15:
41 | always_comb out6 = 1'b0;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:40:15: ... Location of other write
40 | always_comb out6 = d;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:17:14: Bit [0] of signal 'out2' have multiple combinational drivers. This can cause performance degradation.
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:28:16: ... Location of offending driver
28 | assign out2 = d;
| ^
t/t_lint_always_comb_multidriven_bad.v:29:21: ... Location of offending driver
29 | always_comb out2 = 1'b0;
| ^
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:19:15: Bit [0] of signal 'out4' have multiple combinational drivers. This can cause performance degradation.
t/t_lint_always_comb_multidriven_bad.v:28:15: ... Location of offending driver
28 | assign out2 = d;
| ^
t/t_lint_always_comb_multidriven_bad.v:29:20: ... Location of offending driver
29 | always_comb out2 = 1'b0;
| ^
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:19:14: Bit [0] of signal 'out4' have multiple combinational drivers. This can cause performance degradation.
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:34:21: ... Location of offending driver
34 | always_comb out4 = 1'b0;
| ^
t/t_lint_always_comb_multidriven_bad.v:35:16: ... Location of offending driver
35 | assign out4 = d;
| ^
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:20:15: Bit [0] of signal 'out5' have multiple combinational drivers. This can cause performance degradation.
t/t_lint_always_comb_multidriven_bad.v:34:20: ... Location of offending driver
34 | always_comb out4 = 1'b0;
| ^
t/t_lint_always_comb_multidriven_bad.v:35:15: ... Location of offending driver
35 | assign out4 = d;
| ^
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:20:14: Bit [0] of signal 'out5' have multiple combinational drivers. This can cause performance degradation.
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:37:21: ... Location of offending driver
37 | always_comb out5 = 1'b0;
| ^
t/t_lint_always_comb_multidriven_bad.v:38:21: ... Location of offending driver
38 | always_comb out5 = d;
| ^
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:21:15: Bit [0] of signal 'out6' have multiple combinational drivers. This can cause performance degradation.
t/t_lint_always_comb_multidriven_bad.v:37:20: ... Location of offending driver
37 | always_comb out5 = 1'b0;
| ^
t/t_lint_always_comb_multidriven_bad.v:38:20: ... Location of offending driver
38 | always_comb out5 = d;
| ^
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:21:14: Bit [0] of signal 'out6' have multiple combinational drivers. This can cause performance degradation.
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:40:21: ... Location of offending driver
40 | always_comb out6 = d;
| ^
t/t_lint_always_comb_multidriven_bad.v:41:21: ... Location of offending driver
41 | always_comb out6 = 1'b0;
| ^
t/t_lint_always_comb_multidriven_bad.v:40:20: ... Location of offending driver
40 | always_comb out6 = d;
| ^
t/t_lint_always_comb_multidriven_bad.v:41:20: ... Location of offending driver
41 | always_comb out6 = 1'b0;
| ^
%Error: Exiting due to

108
test_regress/t/t_lint_always_comb_multidriven_bad.v
View File

@ -5,72 +5,72 @@
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
out1, out2, out3, out4, out5, out6, out7, out8,
// Inputs
clk, d
);
// Outputs
out1, out2, out3, out4, out5, out6, out7, out8,
// Inputs
clk, d
);
input clk;
input d;
output reg out1;
output reg out2;
output reg out3;
output reg out4;
output reg out5;
output reg out6;
output reg out7;
output reg out8;
input clk;
input d;
output reg out1;
output reg out2;
output reg out3;
output reg out4;
output reg out5;
output reg out6;
output reg out7;
output reg out8;
assign out1 = 1'b0;
always_comb out1 = d; // <--- Warning
assign out1 = 1'b0;
always_comb out1 = d; // <--- Warning
assign out2 = d;
always_comb out2 = 1'b0; // <--- Warning
assign out2 = d;
always_comb out2 = 1'b0; // <--- Warning
always_comb out3 = d;
assign out3 = 1'b0; // <--- Warning
always_comb out3 = d;
assign out3 = 1'b0; // <--- Warning
always_comb out4 = 1'b0;
assign out4 = d; // <--- Warning
always_comb out4 = 1'b0;
assign out4 = d; // <--- Warning
always_comb out5 = 1'b0;
always_comb out5 = d; // <--- Warning
always_comb out5 = 1'b0;
always_comb out5 = d; // <--- Warning
always_comb out6 = d;
always_comb out6 = 1'b0; // <--- Warning
always_comb out6 = d;
always_comb out6 = 1'b0; // <--- Warning
always_comb begin
out7 = 1'b0;
out7 = d;
end
always_comb begin
out7 = 1'b0;
out7 = d;
end
always_comb begin
out8 = d;
out8 = 1'b0;
end
always_comb begin
out8 = d;
out8 = 1'b0;
end
reg [1:0] arr_packed;
reg arr_unpacked [0:1];
reg [1:0] gen_arr_packed;
reg gen_arr_unpacked [0:1];
genvar g;
reg [1:0] arr_packed;
reg arr_unpacked [0:1];
reg [1:0] gen_arr_packed;
reg gen_arr_unpacked [0:1];
genvar g;
always_comb begin
arr_packed[0] = d;
arr_packed[1] = d;
end
always_comb begin
arr_packed[0] = d;
arr_packed[1] = d;
end
always_comb begin
arr_unpacked[0] = d;
arr_unpacked[1] = d;
end
always_comb begin
arr_unpacked[0] = d;
arr_unpacked[1] = d;
end
generate
for (g=0; g<2; ++g) begin
always_comb gen_arr_packed[g] = d;
always_comb gen_arr_unpacked[g] = d;
end
endgenerate
generate
for (g=0; g<2; ++g) begin
always_comb gen_arr_packed[g] = d;
always_comb gen_arr_unpacked[g] = d;
end
endgenerate
endmodule

140
test_regress/t/t_lint_always_comb_multidriven_public_bad.out
View File

@ -1,83 +1,83 @@
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:26:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out1'
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:26:15: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out1'
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:26:16:
26 | always_comb out1 = d;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:25:11: ... Location of other write
25 | assign out1 = 1'b0;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:26:15:
26 | always_comb out1 = d;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:25:10: ... Location of other write
25 | assign out1 = 1'b0;
| ^~~~
... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest
... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message.
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:29:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out2'
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:29:15: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out2'
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:29:16:
29 | always_comb out2 = 1'b0;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:28:11: ... Location of other write
28 | assign out2 = d;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:32:11: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'out3'
t/t_lint_always_comb_multidriven_bad.v:29:15:
29 | always_comb out2 = 1'b0;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:28:10: ... Location of other write
28 | assign out2 = d;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:32:10: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'out3'
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:32:11:
32 | assign out3 = 1'b0;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:31:16: ... Location of always_comb write
31 | always_comb out3 = d;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:35:11: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'out4'
t/t_lint_always_comb_multidriven_bad.v:32:10:
32 | assign out3 = 1'b0;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:31:15: ... Location of always_comb write
31 | always_comb out3 = d;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:35:10: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'out4'
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:35:11:
35 | assign out4 = d;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:34:16: ... Location of always_comb write
34 | always_comb out4 = 1'b0;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:38:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out5'
t/t_lint_always_comb_multidriven_bad.v:35:10:
35 | assign out4 = d;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:34:15: ... Location of always_comb write
34 | always_comb out4 = 1'b0;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:38:15: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out5'
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:38:16:
38 | always_comb out5 = d;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:37:16: ... Location of other write
37 | always_comb out5 = 1'b0;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:41:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out6'
t/t_lint_always_comb_multidriven_bad.v:38:15:
38 | always_comb out5 = d;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:37:15: ... Location of other write
37 | always_comb out5 = 1'b0;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:41:15: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out6'
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:41:16:
41 | always_comb out6 = 1'b0;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:40:16: ... Location of other write
40 | always_comb out6 = d;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:17:15: Bit [0] of signal 'out2' have multiple combinational drivers. This can cause performance degradation.
t/t_lint_always_comb_multidriven_bad.v:41:15:
41 | always_comb out6 = 1'b0;
| ^~~~
t/t_lint_always_comb_multidriven_bad.v:40:15: ... Location of other write
40 | always_comb out6 = d;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:17:14: Bit [0] of signal 'out2' have multiple combinational drivers. This can cause performance degradation.
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:28:16: ... Location of offending driver
28 | assign out2 = d;
| ^
t/t_lint_always_comb_multidriven_bad.v:29:21: ... Location of offending driver
29 | always_comb out2 = 1'b0;
| ^
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:19:15: Bit [0] of signal 'out4' have multiple combinational drivers. This can cause performance degradation.
t/t_lint_always_comb_multidriven_bad.v:28:15: ... Location of offending driver
28 | assign out2 = d;
| ^
t/t_lint_always_comb_multidriven_bad.v:29:20: ... Location of offending driver
29 | always_comb out2 = 1'b0;
| ^
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:19:14: Bit [0] of signal 'out4' have multiple combinational drivers. This can cause performance degradation.
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:34:21: ... Location of offending driver
34 | always_comb out4 = 1'b0;
| ^
t/t_lint_always_comb_multidriven_bad.v:35:16: ... Location of offending driver
35 | assign out4 = d;
| ^
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:20:15: Bit [0] of signal 'out5' have multiple combinational drivers. This can cause performance degradation.
t/t_lint_always_comb_multidriven_bad.v:34:20: ... Location of offending driver
34 | always_comb out4 = 1'b0;
| ^
t/t_lint_always_comb_multidriven_bad.v:35:15: ... Location of offending driver
35 | assign out4 = d;
| ^
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:20:14: Bit [0] of signal 'out5' have multiple combinational drivers. This can cause performance degradation.
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:37:21: ... Location of offending driver
37 | always_comb out5 = 1'b0;
| ^
t/t_lint_always_comb_multidriven_bad.v:38:21: ... Location of offending driver
38 | always_comb out5 = d;
| ^
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:21:15: Bit [0] of signal 'out6' have multiple combinational drivers. This can cause performance degradation.
t/t_lint_always_comb_multidriven_bad.v:37:20: ... Location of offending driver
37 | always_comb out5 = 1'b0;
| ^
t/t_lint_always_comb_multidriven_bad.v:38:20: ... Location of offending driver
38 | always_comb out5 = d;
| ^
%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:21:14: Bit [0] of signal 'out6' have multiple combinational drivers. This can cause performance degradation.
: ... note: In instance 't'
t/t_lint_always_comb_multidriven_bad.v:40:21: ... Location of offending driver
40 | always_comb out6 = d;
| ^
t/t_lint_always_comb_multidriven_bad.v:41:21: ... Location of offending driver
41 | always_comb out6 = 1'b0;
| ^
t/t_lint_always_comb_multidriven_bad.v:40:20: ... Location of offending driver
40 | always_comb out6 = d;
| ^
t/t_lint_always_comb_multidriven_bad.v:41:20: ... Location of offending driver
41 | always_comb out6 = 1'b0;
| ^
%Error: Exiting due to

176
test_regress/t/t_lint_blkseq_loop.v
View File

@ -4,106 +4,106 @@
// SPDX-FileCopyrightText: 2010 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
data_out,
// Inputs
wr, wa, rst_l, rd, ra, data_in, clk
);
input clk;
module t ( /*AUTOARG*/
// Outputs
data_out,
// Inputs
wr, wa, rst_l, rd, ra, data_in, clk
);
input clk;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [31:0] data_in; // To sub of reg_1r1w.v
input [7:0] ra; // To sub of reg_1r1w.v
input rd; // To sub of reg_1r1w.v
input rst_l; // To sub of reg_1r1w.v
input [7:0] wa; // To sub of reg_1r1w.v
input wr; // To sub of reg_1r1w.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [31:0] data_out; // From sub of reg_1r1w.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [31:0] data_in; // To sub of reg_1r1w.v
input [7:0] ra; // To sub of reg_1r1w.v
input rd; // To sub of reg_1r1w.v
input rst_l; // To sub of reg_1r1w.v
input [7:0] wa; // To sub of reg_1r1w.v
input wr; // To sub of reg_1r1w.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [31:0] data_out; // From sub of reg_1r1w.v
// End of automatics
reg_1r1w #(.WIDTH(32), .DEPTH(256), .ADRWID(8))
sub
(/*AUTOINST*/
// Outputs
.data_out (data_out[31:0]),
// Inputs
.data_in (data_in[31:0]),
.ra (ra[7:0]),
.wa (wa[7:0]),
.wr (wr),
.rd (rd),
.clk (clk),
.rst_l (rst_l));
reg_1r1w #(
.WIDTH(32),
.DEPTH(256),
.ADRWID(8)
) sub ( /*AUTOINST*/
// Outputs
.data_out (data_out[31:0]),
// Inputs
.data_in (data_in[31:0]),
.ra (ra[7:0]),
.wa (wa[7:0]),
.wr (wr),
.rd (rd),
.clk (clk),
.rst_l (rst_l));
endmodule
module reg_1r1w
#(
parameter WIDTH=32,
parameter ADRWID=10,
parameter DEPTH=1024,
parameter RST=0
)
(/*AUTOARG*/
// Outputs
data_out,
// Inputs
data_in, ra, wa, wr, rd, clk, rst_l
);
module reg_1r1w #(
parameter WIDTH = 32,
parameter ADRWID = 10,
parameter DEPTH = 1024,
parameter RST = 0
) ( /*AUTOARG*/
// Outputs
data_out,
// Inputs
data_in, ra, wa, wr, rd, clk, rst_l
);
input [WIDTH-1:0] data_in;
input [ADRWID-1:0] ra;
input [ADRWID-1:0] wa;
input wr;
input rd;
input clk;
input rst_l;
input [WIDTH-1:0] data_in;
input [ADRWID-1:0] ra;
input [ADRWID-1:0] wa;
input wr;
input rd;
input clk;
input rst_l;
output [WIDTH-1:0] data_out;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] array [DEPTH-1:0];
reg [ADRWID-1:0] ra_r, wa_r;
reg [WIDTH-1:0] data_in_r;
reg wr_r;
reg rd_r;
reg [WIDTH-1:0] array[DEPTH-1:0];
reg [ADRWID-1:0] ra_r, wa_r;
reg [WIDTH-1:0] data_in_r;
reg wr_r;
reg rd_r;
integer x;
integer x;
// Message 679
always @(posedge clk) begin
// verilator lint_off IMPLICITSTATIC
int tmp = x + 1;
// verilator lint_on IMPLICITSTATIC
if (tmp !== x + 1) $stop;
// Message 679
always @(posedge clk) begin
// verilator lint_off IMPLICITSTATIC
int tmp = x + 1;
// verilator lint_on IMPLICITSTATIC
if (tmp !== x + 1) $stop;
end
always @(posedge clk or negedge rst_l) begin
if (!rst_l) begin
for (x = 0; x < DEPTH; x = x + 1) begin // <== VERILATOR FLAGS THIS LINE
if (RST == 1) begin
array[x] <= 0;
end
end
ra_r <= 0;
wa_r <= 0;
wr_r <= 0;
rd_r <= 0;
data_in_r <= 0;
end
always @(posedge clk or negedge rst_l) begin
if (!rst_l) begin
for (x=0; x<DEPTH; x=x+1) begin // <== VERILATOR FLAGS THIS LINE
if (RST == 1) begin
array[x] <= 0;
end
end
ra_r <= 0;
wa_r <= 0;
wr_r <= 0;
rd_r <= 0;
data_in_r <= 0;
end
else begin
ra_r <= ra;
wa_r <= wa;
wr_r <= wr;
rd_r <= rd;
data_in_r <= data_in;
if (wr_r) array[wa_r] <= data_in_r;
end
else begin
ra_r <= ra;
wa_r <= wa;
wr_r <= wr;
rd_r <= rd;
data_in_r <= data_in;
if (wr_r) array[wa_r] <= data_in_r;
end
end
endmodule
// Local Variables:

12
test_regress/t/t_lint_block_redecl_bad.out
View File

@ -1,8 +1,8 @@
%Error: t/t_lint_block_redecl_bad.v:17:27: Duplicate declaration of block: 'COMB'
17 | for(i=0; i<9; i++ ) begin: COMB
| ^~~~~
t/t_lint_block_redecl_bad.v:14:28: ... Location of original declaration
14 | for(i=0; i<10; i++ ) begin: COMB
| ^~~~~
%Error: t/t_lint_block_redecl_bad.v:17:25: Duplicate declaration of block: 'COMB'
17 | for(i=0; i<9; i++ ) begin: COMB
| ^~~~~
t/t_lint_block_redecl_bad.v:14:26: ... Location of original declaration
14 | for(i=0; i<10; i++ ) begin: COMB
| ^~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

14
test_regress/t/t_lint_block_redecl_bad.v
View File

@ -8,13 +8,13 @@
module t;
always_comb begin
integer i;
always_comb begin
integer i;
for(i=0; i<10; i++ ) begin: COMB
end
for(i=0; i<10; i++ ) begin: COMB
end
for(i=0; i<9; i++ ) begin: COMB
end
end
for(i=0; i<9; i++ ) begin: COMB
end
end
endmodule

6
test_regress/t/t_lint_caseincomplete_bad.out
View File

@ -1,6 +1,6 @@
%Warning-CASEINCOMPLETE: t/t_lint_caseincomplete_bad.v:15:7: Case values incompletely covered (example pattern 0x1)
15 | case (i)
| ^~~~
%Warning-CASEINCOMPLETE: t/t_lint_caseincomplete_bad.v:15:5: Case values incompletely covered (example pattern 0x1)
15 | case (i)
| ^~~~
... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=latest
... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message.
%Error: Exiting due to

22
test_regress/t/t_lint_caseincomplete_bad.v
View File

@ -5,17 +5,17 @@
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
i
);
// Inputs
i
);
input [1:0] i;
input [1:0] i;
always_comb begin
case (i)
2'b00: ;
2'b10: ;
2'b11: ;
endcase
end
always_comb begin
case (i)
2'b00: ;
2'b10: ;
2'b11: ;
endcase
end
endmodule

6
test_regress/t/t_lint_cmpconst_bad.out
View File

@ -1,7 +1,7 @@
%Warning-CMPCONST: t/t_lint_cmpconst_bad.v:13:15: Comparison is constant due to limited range
%Warning-CMPCONST: t/t_lint_cmpconst_bad.v:13:13: Comparison is constant due to limited range
: ... note: In instance 't'
13 | if (uns > 3'b111) $stop;
| ^
13 | if (uns > 3'b111) $stop;
| ^
... For warning description see https://verilator.org/warn/CMPCONST?v=latest
... Use "/* verilator lint_off CMPCONST */" and lint_on around source to disable this message.
%Error: Exiting due to

10
test_regress/t/t_lint_cmpconst_bad.v
View File

@ -6,10 +6,10 @@
module t;
bit [2:0] uns;
bit [2:0] uns;
initial begin
uns = 1;
if (uns > 3'b111) $stop;
end
initial begin
uns = 1;
if (uns > 3'b111) $stop;
end
endmodule

6
test_regress/t/t_lint_colonplus_bad.out
View File

@ -1,6 +1,6 @@
%Warning-COLONPLUS: t/t_lint_colonplus_bad.v:13:25: Perhaps instead of ':+' the intent was '+:'?
13 | output [2:1] z = r[2 :+ 1];
| ^~
%Warning-COLONPLUS: t/t_lint_colonplus_bad.v:13:24: Perhaps instead of ':+' the intent was '+:'?
13 | output [2:1] z = r[2 :+ 1];
| ^~
... For warning description see https://verilator.org/warn/COLONPLUS?v=latest
... Use "/* verilator lint_off COLONPLUS */" and lint_on around source to disable this message.
%Error: Exiting due to

10
test_regress/t/t_lint_colonplus_bad.v
View File

@ -5,11 +5,11 @@
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
z
);
// Outputs
z
);
reg [3:0] r = 4'b1010;
output [2:1] z = r[2 :+ 1];
reg [3:0] r = 4'b1010;
output [2:1] z = r[2 :+ 1];
endmodule

6
test_regress/t/t_lint_comb_bad.out
View File

@ -1,6 +1,6 @@
%Error: t/t_lint_comb_bad.v:14:4: Event control statements not legal under always_comb (IEEE 1800-2023 9.2.2.2.2)
%Error: t/t_lint_comb_bad.v:14:3: Event control statements not legal under always_comb (IEEE 1800-2023 9.2.2.2.2)
: ... Suggest use a normal 'always'
14 | always_comb @(*) begin
| ^~~~~~~~~~~
14 | always_comb @(*) begin
| ^~~~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

14
test_regress/t/t_lint_comb_bad.v
View File

@ -5,14 +5,14 @@
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
// Inputs
clk
);
input clk;
input clk;
always_comb @(*) begin
$stop;
end
always_comb @(*) begin
$stop;
end
endmodule

42
test_regress/t/t_lint_comb_use.v
View File

@ -4,28 +4,28 @@
// SPDX-FileCopyrightText: 2010 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
hval,
// Inputs
sel
);
module t ( /*AUTOARG*/
// Outputs
hval,
// Inputs
sel
);
input logic [2:0] sel;
output logic [3:0] hval;
input logic [2:0] sel;
output logic [3:0] hval;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
always_comb begin
unique case (sel)
3'h0: hval = 4'hd;
3'h1: hval = 4'hc;
3'h7: hval = 4'hf;
default: begin
$ignore ("ERROR : %s [%m]", $sformatf ("Illegal sel = %x", sel));
hval = 4'bx;
end
endcase
end
always_comb begin
unique case (sel)
3'h0: hval = 4'hd;
3'h1: hval = 4'hc;
3'h7: hval = 4'hf;
default: begin
$ignore("ERROR : %s [%m]", $sformatf("Illegal sel = %x", sel));
hval = 4'bx;
end
endcase
end
endmodule

16
test_regress/t/t_lint_const_func_dpi_bad.out
View File

@ -1,12 +1,12 @@
%Error: t/t_lint_const_func_dpi_bad.v:8:32: Constant function may not be DPI import (IEEE 1800-2023 13.4.3)
%Error: t/t_lint_const_func_dpi_bad.v:8:31: Constant function may not be DPI import (IEEE 1800-2023 13.4.3)
: ... note: In instance 't'
8 | import "DPI-C" function int dpiFunc();
| ^~~~~~~
8 | import "DPI-C" function int dpiFunc();
| ^~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_lint_const_func_dpi_bad.v:9:23: Expecting expression to be constant, but can't determine constant for FUNCREF 'dpiFunc'
%Error: t/t_lint_const_func_dpi_bad.v:9:22: Expecting expression to be constant, but can't determine constant for FUNCREF 'dpiFunc'
: ... note: In instance 't'
t/t_lint_const_func_dpi_bad.v:8:32: ... Location of non-constant FUNC 'dpiFunc': DPI import functions aren't simulatable
t/t_lint_const_func_dpi_bad.v:9:23: ... Called from 'dpiFunc()' with parameters:
9 | localparam PARAM = dpiFunc();
| ^~~~~~~
t/t_lint_const_func_dpi_bad.v:8:31: ... Location of non-constant FUNC 'dpiFunc': DPI import functions aren't simulatable
t/t_lint_const_func_dpi_bad.v:9:22: ... Called from 'dpiFunc()' with parameters:
9 | localparam PARAM = dpiFunc();
| ^~~~~~~
%Error: Exiting due to

4
test_regress/t/t_lint_const_func_dpi_bad.v
View File

@ -5,6 +5,6 @@
// SPDX-License-Identifier: CC0-1.0
module t;
import "DPI-C" function int dpiFunc();
localparam PARAM = dpiFunc();
import "DPI-C" function int dpiFunc();
localparam PARAM = dpiFunc();
endmodule

16
test_regress/t/t_lint_const_func_gen_bad.out
View File

@ -1,12 +1,12 @@
%Error: t/t_lint_const_func_gen_bad.v:11:30: Constant function may not be declared under generate (IEEE 1800-2023 13.4.3)
%Error: t/t_lint_const_func_gen_bad.v:11:28: Constant function may not be declared under generate (IEEE 1800-2023 13.4.3)
: ... note: In instance 't'
11 | function automatic bit constFunc();
| ^~~~~~~~~
11 | function automatic bit constFunc();
| ^~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_lint_const_func_gen_bad.v:15:26: Expecting expression to be constant, but can't determine constant for FUNCREF 'constFunc'
%Error: t/t_lint_const_func_gen_bad.v:15:24: Expecting expression to be constant, but can't determine constant for FUNCREF 'constFunc'
: ... note: In instance 't'
t/t_lint_const_func_gen_bad.v:11:30: ... Location of non-constant FUNC 'constFunc': Constant function called under generate
t/t_lint_const_func_gen_bad.v:15:26: ... Called from 'constFunc()' with parameters:
15 | localparam PARAM = constFunc();
| ^~~~~~~~~
t/t_lint_const_func_gen_bad.v:11:28: ... Location of non-constant FUNC 'constFunc': Constant function called under generate
t/t_lint_const_func_gen_bad.v:15:24: ... Called from 'constFunc()' with parameters:
15 | localparam PARAM = constFunc();
| ^~~~~~~~~
%Error: Exiting due to

16
test_regress/t/t_lint_const_func_gen_bad.v
View File

@ -5,13 +5,13 @@
// SPDX-License-Identifier: CC0-1.0
module t;
if (1) begin: GenConstFunc
// IEEE 1800-2023 13.4.3, constant functions shall not be declared inside a
//generate block
function automatic bit constFunc();
constFunc = 1'b1;
endfunction
if (1) begin: GenConstFunc
// IEEE 1800-2023 13.4.3, constant functions shall not be declared inside a
//generate block
function automatic bit constFunc();
constFunc = 1'b1;
endfunction
localparam PARAM = constFunc();
end
localparam PARAM = constFunc();
end
endmodule

6
test_regress/t/t_lint_contassreg_bad.out
View File

@ -1,6 +1,6 @@
%Error-CONTASSREG: t/t_lint_contassreg_bad.v:14:11: Continuous assignment to reg, perhaps intended wire (IEEE 1364-2005 6.1; Verilog only, legal in SV): 'r'
%Error-CONTASSREG: t/t_lint_contassreg_bad.v:14:10: Continuous assignment to reg, perhaps intended wire (IEEE 1364-2005 6.1; Verilog only, legal in SV): 'r'
: ... note: In instance 't'
14 | assign r = 1'b0;
| ^
14 | assign r = 1'b0;
| ^
... For error description see https://verilator.org/warn/CONTASSREG?v=latest
%Error: Exiting due to

6
test_regress/t/t_lint_contassreg_bad.v
View File

@ -7,10 +7,10 @@
module t(r);
output r;
output r;
reg r;
reg r;
assign r = 1'b0; // Bad
assign r = 1'b0; // Bad
endmodule

2
test_regress/t/t_lint_declfilename.v
View File

@ -5,7 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
module t;
t_lint_declfilename sub ();
t_lint_declfilename sub ();
endmodule
module t_lint_declfilename;

10
test_regress/t/t_lint_declfilename_bbox.v
View File

@ -5,9 +5,9 @@
// SPDX-License-Identifier: CC0-1.0
module t_lint_declfilename_bbox ();
parameter IN = 0;
if (IN) begin : gen_hasbbox
// Should not warn, see bug2430
BLACKBOXED bboxed ();
end
parameter IN = 0;
if (IN) begin : gen_hasbbox
// Should not warn, see bug2430
BLACKBOXED bboxed ();
end
endmodule

8
test_regress/t/t_lint_defparam.v
View File

@ -6,12 +6,12 @@
module t;
sub sub ();
defparam sub.P = 2;
sub sub ();
defparam sub.P = 2;
endmodule
module sub;
parameter P = 6;
if (P != 0) ; // Prevent unused
parameter P = 6;
if (P != 0); // Prevent unused
endmodule

6
test_regress/t/t_lint_defparam_bad.out
View File

@ -1,7 +1,7 @@
%Warning-DEFPARAM: t/t_lint_defparam.v:10:19: defparam is deprecated (IEEE 1800-2023 C.4.1)
%Warning-DEFPARAM: t/t_lint_defparam.v:10:18: defparam is deprecated (IEEE 1800-2023 C.4.1)
: ... Suggest use instantiation with #(.P(...etc...))
10 | defparam sub.P = 2;
| ^
10 | defparam sub.P = 2;
| ^
... For warning description see https://verilator.org/warn/DEFPARAM?v=latest
... Use "/* verilator lint_off DEFPARAM */" and lint_on around source to disable this message.
%Error: Exiting due to

12
test_regress/t/t_lint_edge_real_bad.out
View File

@ -1,10 +1,10 @@
%Error: t/t_lint_edge_real_bad.v:19:22: Edge event control not legal on real type (IEEE 1800-2023 6.12.1)
%Error: t/t_lint_edge_real_bad.v:19:21: Edge event control not legal on real type (IEEE 1800-2023 6.12.1)
: ... note: In instance 't'
19 | always @ (posedge rbad) $stop;
| ^~~~
19 | always @ (posedge rbad) $stop;
| ^~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_lint_edge_real_bad.v:20:22: Edge event control not legal on non-integral type (IEEE 1800-2023 9.4.2)
%Error: t/t_lint_edge_real_bad.v:20:21: Edge event control not legal on non-integral type (IEEE 1800-2023 9.4.2)
: ... note: In instance 't'
20 | always @ (posedge ebad) $stop;
| ^~~~
20 | always @ (posedge ebad) $stop;
| ^~~~
%Error: Exiting due to

22
test_regress/t/t_lint_edge_real_bad.v
View File

@ -5,18 +5,18 @@
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
rbad, rok
);
input real rbad;
input real rok;
event ebad;
struct packed { int a; } sok;
// Inputs
rbad, rok
);
input real rbad;
input real rok;
event ebad;
struct packed { int a; } sok;
always @ (rok) $stop;
always @ (sok) $stop;
always @ (rok) $stop;
always @ (sok) $stop;
always @ (posedge rbad) $stop;
always @ (posedge ebad) $stop;
always @ (posedge rbad) $stop;
always @ (posedge ebad) $stop;
endmodule

36
test_regress/t/t_lint_genunnamed_bad.out
View File

@ -1,27 +1,27 @@
%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:14:6: Unnamed generate block 'genblk2' (IEEE 1800-2023 27.6)
%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:14:5: Unnamed generate block 'genblk2' (IEEE 1800-2023 27.6)
: ... Suggest assign a label with 'begin : gen_<label_name>'
14 | begin
| ^~~~~
14 | begin
| ^~~~~
... For warning description see https://verilator.org/warn/GENUNNAMED?v=latest
... Use "/* verilator lint_off GENUNNAMED */" and lint_on around source to disable this message.
%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:18:6: Unnamed generate block 'genblk2' (IEEE 1800-2023 27.6)
%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:18:5: Unnamed generate block 'genblk2' (IEEE 1800-2023 27.6)
: ... Suggest assign a label with 'begin : gen_<label_name>'
18 | begin
| ^~~~~
%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:22:4: Unnamed generate block 'genblk3' (IEEE 1800-2023 27.6)
18 | begin
| ^~~~~
%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:22:3: Unnamed generate block 'genblk3' (IEEE 1800-2023 27.6)
: ... Suggest assign a label with 'begin : gen_<label_name>'
22 | for (genvar v = 0; v < P; ++v) ;
| ^~~
%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:24:4: Unnamed generate block 'genblk4' (IEEE 1800-2023 27.6)
22 | for (genvar v = 0; v < P; ++v) ;
| ^~~
%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:24:3: Unnamed generate block 'genblk4' (IEEE 1800-2023 27.6)
: ... Suggest assign a label with 'begin : gen_<label_name>'
24 | for (genvar v = 0; v < P; ++v)
| ^~~
%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:30:9: Unnamed generate block 'genblk5' (IEEE 1800-2023 27.6)
24 | for (genvar v = 0; v < P; ++v)
| ^~~
%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:30:8: Unnamed generate block 'genblk5' (IEEE 1800-2023 27.6)
: ... Suggest assign a label with 'begin : gen_<label_name>'
30 | 1: initial begin end
| ^~~~~~~
%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:31:9: Unnamed generate block 'genblk5' (IEEE 1800-2023 27.6)
30 | 1: initial begin end
| ^~~~~~~
%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:31:8: Unnamed generate block 'genblk5' (IEEE 1800-2023 27.6)
: ... Suggest assign a label with 'begin : gen_<label_name>'
31 | 2: begin
| ^~~~~
31 | 2: begin
| ^~~~~
%Error: Exiting due to

42
test_regress/t/t_lint_genunnamed_bad.v
View File

@ -6,31 +6,31 @@
module t;
parameter P = 1;
parameter P = 1;
if (P) ;
if (P) ;
if (P)
begin
initial $display;
end
else
begin
initial $display;
end
if (P)
begin
initial $display;
end
else
begin
initial $display;
end
for (genvar v = 0; v < P; ++v) ;
for (genvar v = 0; v < P; ++v) ;
for (genvar v = 0; v < P; ++v)
begin
initial $display;
end
for (genvar v = 0; v < P; ++v)
begin
initial $display;
end
case (P)
1: initial begin end
2: begin
initial begin end
end
endcase
case (P)
1: initial begin end
2: begin
initial begin end
end
endcase
endmodule

238
test_regress/t/t_lint_historical.v
View File

@ -5,124 +5,124 @@
// SPDX-License-Identifier: CC0-1.0
module t;
// Test all warnings, including those that are historically removed still parse
// verilator lint_off ALWCOMBORDER
// verilator lint_off ALWNEVER
// verilator lint_off ASCRANGE
// verilator lint_off ASSIGNDLY
// verilator lint_off ASSIGNEQEXPR
// verilator lint_off ASSIGNIN
// verilator lint_off BADSTDPRAGMA
// verilator lint_off BADVLTPRAGMA
// verilator lint_off BLKANDNBLK
// verilator lint_off BLKLOOPINIT
// verilator lint_off BLKSEQ
// verilator lint_off BSSPACE
// verilator lint_off CASEINCOMPLETE
// verilator lint_off CASEOVERLAP
// verilator lint_off CASEWITHX
// verilator lint_off CASEX
// verilator lint_off CASTCONST
// verilator lint_off CDCRSTLOGIC
// verilator lint_off CLKDATA
// verilator lint_off CMPCONST
// verilator lint_off COLONPLUS
// verilator lint_off COMBDLY
// verilator lint_off CONSTRAINTIGN
// verilator lint_off CONTASSREG
// verilator lint_off COVERIGN
// verilator lint_off DECLFILENAME
// verilator lint_off DEFOVERRIDE
// verilator lint_off DEFPARAM
// verilator lint_off DEPRECATED
// verilator lint_off ENCAPSULATED
// verilator lint_off ENDLABEL
// verilator lint_off ENUMITEMWIDTH
// verilator lint_off ENUMVALUE
// verilator lint_off EOFNEWLINE
// verilator lint_off FUNCTIMECTL
// verilator lint_off GENCLK
// verilator lint_off GENUNNAMED
// verilator lint_off HIERBLOCK
// verilator lint_off HIERPARAM
// verilator lint_off IFDEPTH
// verilator lint_off IGNOREDRETURN
// verilator lint_off IMPERFECTSCH
// verilator lint_off IMPLICIT
// verilator lint_off IMPLICITSTATIC
// verilator lint_off IMPORTSTAR
// verilator lint_off IMPURE
// verilator lint_off INCABSPATH
// verilator lint_off INFINITELOOP
// verilator lint_off INITIALDLY
// verilator lint_off INSECURE
// verilator lint_off INSIDETRUE
// verilator lint_off LATCH
// verilator lint_off LITENDIAN
// verilator lint_off MINTYPMAXDLY
// verilator lint_off MISINDENT
// verilator lint_off MODDUP
// verilator lint_off MODMISSING
// verilator lint_off MULTIDRIVEN
// verilator lint_off MULTITOP
// verilator lint_off NEWERSTD
// verilator lint_off NOEFFECT
// verilator lint_off NOLATCH
// verilator lint_off NONSTD
// verilator lint_off NORETURN
// verilator lint_off NULLPORT
// verilator lint_off PARAMNODEFAULT
// verilator lint_off PINCONNECTEMPTY
// verilator lint_off PINMISSING
// verilator lint_off PINNOCONNECT
// verilator lint_off PINNOTFOUND
// verilator lint_off PKGNODECL
// verilator lint_off PREPROCZERO
// verilator lint_off PROCASSINIT
// verilator lint_off PROCASSWIRE
// verilator lint_off PROFOUTOFDATE
// verilator lint_off PROTECTED
// verilator lint_off PROTOTYPEMIS
// verilator lint_off RANDC
// verilator lint_off REALCVT
// verilator lint_off REDEFMACRO
// verilator lint_off RISEFALLDLY
// verilator lint_off SELRANGE
// verilator lint_off SHORTREAL
// verilator lint_off SIDEEFFECT
// verilator lint_off SPECIFYIGN
// verilator lint_off SPLITVAR
// verilator lint_off STATICVAR
// verilator lint_off STMTDLY
// verilator lint_off SUPERNFIRST
// verilator lint_off SYMRSVDWORD
// verilator lint_off SYNCASYNCNET
// verilator lint_off TICKCOUNT
// verilator lint_off TIMESCALEMOD
// verilator lint_off UNDRIVEN
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
// verilator lint_off UNOPTTHREADS
// verilator lint_off UNPACKED
// verilator lint_off UNSATCONSTR
// verilator lint_off UNSIGNED
// verilator lint_off UNUSED
// verilator lint_off UNUSEDGENVAR
// verilator lint_off UNUSEDLOOP
// verilator lint_off UNUSEDPARAM
// verilator lint_off UNUSEDSIGNAL
// verilator lint_off USERERROR
// verilator lint_off USERFATAL
// verilator lint_off USERINFO
// verilator lint_off USERWARN
// verilator lint_off VARHIDDEN
// verilator lint_off WAITCONST
// verilator lint_off WIDTH
// verilator lint_off WIDTHCONCAT
// verilator lint_off WIDTHEXPAND
// verilator lint_off WIDTHTRUNC
// verilator lint_off WIDTHXZEXPAND
// verilator lint_off ZERODLY
// verilator lint_off ZEROREPL
// Test all warnings, including those that are historically removed still parse
// verilator lint_off ALWCOMBORDER
// verilator lint_off ALWNEVER
// verilator lint_off ASCRANGE
// verilator lint_off ASSIGNDLY
// verilator lint_off ASSIGNEQEXPR
// verilator lint_off ASSIGNIN
// verilator lint_off BADSTDPRAGMA
// verilator lint_off BADVLTPRAGMA
// verilator lint_off BLKANDNBLK
// verilator lint_off BLKLOOPINIT
// verilator lint_off BLKSEQ
// verilator lint_off BSSPACE
// verilator lint_off CASEINCOMPLETE
// verilator lint_off CASEOVERLAP
// verilator lint_off CASEWITHX
// verilator lint_off CASEX
// verilator lint_off CASTCONST
// verilator lint_off CDCRSTLOGIC
// verilator lint_off CLKDATA
// verilator lint_off CMPCONST
// verilator lint_off COLONPLUS
// verilator lint_off COMBDLY
// verilator lint_off CONSTRAINTIGN
// verilator lint_off CONTASSREG
// verilator lint_off COVERIGN
// verilator lint_off DECLFILENAME
// verilator lint_off DEFOVERRIDE
// verilator lint_off DEFPARAM
// verilator lint_off DEPRECATED
// verilator lint_off ENCAPSULATED
// verilator lint_off ENDLABEL
// verilator lint_off ENUMITEMWIDTH
// verilator lint_off ENUMVALUE
// verilator lint_off EOFNEWLINE
// verilator lint_off FUNCTIMECTL
// verilator lint_off GENCLK
// verilator lint_off GENUNNAMED
// verilator lint_off HIERBLOCK
// verilator lint_off HIERPARAM
// verilator lint_off IFDEPTH
// verilator lint_off IGNOREDRETURN
// verilator lint_off IMPERFECTSCH
// verilator lint_off IMPLICIT
// verilator lint_off IMPLICITSTATIC
// verilator lint_off IMPORTSTAR
// verilator lint_off IMPURE
// verilator lint_off INCABSPATH
// verilator lint_off INFINITELOOP
// verilator lint_off INITIALDLY
// verilator lint_off INSECURE
// verilator lint_off INSIDETRUE
// verilator lint_off LATCH
// verilator lint_off LITENDIAN
// verilator lint_off MINTYPMAXDLY
// verilator lint_off MISINDENT
// verilator lint_off MODDUP
// verilator lint_off MODMISSING
// verilator lint_off MULTIDRIVEN
// verilator lint_off MULTITOP
// verilator lint_off NEWERSTD
// verilator lint_off NOEFFECT
// verilator lint_off NOLATCH
// verilator lint_off NONSTD
// verilator lint_off NORETURN
// verilator lint_off NULLPORT
// verilator lint_off PARAMNODEFAULT
// verilator lint_off PINCONNECTEMPTY
// verilator lint_off PINMISSING
// verilator lint_off PINNOCONNECT
// verilator lint_off PINNOTFOUND
// verilator lint_off PKGNODECL
// verilator lint_off PREPROCZERO
// verilator lint_off PROCASSINIT
// verilator lint_off PROCASSWIRE
// verilator lint_off PROFOUTOFDATE
// verilator lint_off PROTECTED
// verilator lint_off PROTOTYPEMIS
// verilator lint_off RANDC
// verilator lint_off REALCVT
// verilator lint_off REDEFMACRO
// verilator lint_off RISEFALLDLY
// verilator lint_off SELRANGE
// verilator lint_off SHORTREAL
// verilator lint_off SIDEEFFECT
// verilator lint_off SPECIFYIGN
// verilator lint_off SPLITVAR
// verilator lint_off STATICVAR
// verilator lint_off STMTDLY
// verilator lint_off SUPERNFIRST
// verilator lint_off SYMRSVDWORD
// verilator lint_off SYNCASYNCNET
// verilator lint_off TICKCOUNT
// verilator lint_off TIMESCALEMOD
// verilator lint_off UNDRIVEN
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
// verilator lint_off UNOPTTHREADS
// verilator lint_off UNPACKED
// verilator lint_off UNSATCONSTR
// verilator lint_off UNSIGNED
// verilator lint_off UNUSED
// verilator lint_off UNUSEDGENVAR
// verilator lint_off UNUSEDLOOP
// verilator lint_off UNUSEDPARAM
// verilator lint_off UNUSEDSIGNAL
// verilator lint_off USERERROR
// verilator lint_off USERFATAL
// verilator lint_off USERINFO
// verilator lint_off USERWARN
// verilator lint_off VARHIDDEN
// verilator lint_off WAITCONST
// verilator lint_off WIDTH
// verilator lint_off WIDTHCONCAT
// verilator lint_off WIDTHEXPAND
// verilator lint_off WIDTHTRUNC
// verilator lint_off WIDTHXZEXPAND
// verilator lint_off ZERODLY
// verilator lint_off ZEROREPL
endmodule

48
test_regress/t/t_lint_iface_array_topmodule1.v
View File

@ -6,43 +6,35 @@
interface my_if;
logic valid;
logic [7:0] data ;
logic valid;
logic [7:0] data;
modport slave_mp (
input valid,
input data
);
modport slave_mp(input valid, input data);
modport master_mp (
output valid,
output data
);
modport master_mp(output valid, output data);
endinterface
module t
(
input wire clk,
my_if.slave_mp in_if [2],
my_if.master_mp out_if [2]
);
module t (
input wire clk,
my_if.slave_mp in_if[2],
my_if.master_mp out_if[2]
);
my_if my_i [2] ();
my_if my_i[2] ();
always @(posedge clk)
begin
my_i[0].valid <= in_if[0].valid;
my_i[0].data <= in_if[0].data;
always @(posedge clk) begin
my_i[0].valid <= in_if[0].valid;
my_i[0].data <= in_if[0].data;
my_i[1].valid <= in_if[1].valid;
my_i[1].data <= in_if[1].data;
end
my_i[1].valid <= in_if[1].valid;
my_i[1].data <= in_if[1].data;
end
assign out_if[0].valid = my_i[0].valid;
assign out_if[0].data = my_i[0].data;
assign out_if[0].valid = my_i[0].valid;
assign out_if[0].data = my_i[0].data;
assign out_if[1].valid = my_i[1].valid;
assign out_if[1].data = my_i[1].data;
assign out_if[1].valid = my_i[1].valid;
assign out_if[1].data = my_i[1].data;
endmodule

37
test_regress/t/t_lint_iface_array_topmodule2.v
View File

@ -5,35 +5,28 @@
// SPDX-License-Identifier: CC0-1.0
interface my_if #(
parameter DW = 8
) ();
parameter DW = 8
) ();
logic valid;
logic [DW-1:0] data ;
logic valid;
logic [DW-1:0] data;
modport slave_mp (
input valid,
input data
);
modport slave_mp(input valid, input data);
modport master_mp (
output valid,
output data
);
modport master_mp(output valid, output data);
endinterface
module t
(
input wire clk,
my_if.slave_mp in_if [2],
my_if.master_mp out_if [2]
);
module t (
input wire clk,
my_if.slave_mp in_if[2],
my_if.master_mp out_if[2]
);
assign out_if[0].valid = in_if[0].valid;
assign out_if[0].data = in_if[0].data;
assign out_if[0].valid = in_if[0].valid;
assign out_if[0].data = in_if[0].data;
assign out_if[1].valid = in_if[1].valid;
assign out_if[1].data = in_if[1].data;
assign out_if[1].valid = in_if[1].valid;
assign out_if[1].data = in_if[1].data;
endmodule

104
test_regress/t/t_lint_iface_array_topmodule3.v
View File

@ -4,74 +4,68 @@
// SPDX-FileCopyrightText: 2017 Josh Redford
// SPDX-License-Identifier: CC0-1.0
interface my_if #( parameter integer DW = 8 ) (input clk);
interface my_if #(
parameter integer DW = 8
) (
input clk
);
localparam DW_LOCAL = DW;
localparam DW_LOCAL = DW;
logic valid;
logic [DW-1:0] data;
logic valid;
logic [DW-1:0] data;
modport slave_mp (
input valid,
input data
);
modport slave_mp(input valid, input data);
modport master_mp (
output valid,
output data
);
modport master_mp(output valid, output data);
function automatic integer width();
return $bits(data);
endfunction
function automatic integer width();
return $bits(data);
endfunction
generate
if (DW < 4)
begin: dw_lt_4_G
function automatic integer min_width();
return 4;
endfunction
end
else
begin: dw_ge_4_G
function automatic integer min_width();
return 8;
endfunction
end
endgenerate
generate
if (DW < 4) begin : dw_lt_4_G
function automatic integer min_width();
return 4;
endfunction
end
else begin : dw_ge_4_G
function automatic integer min_width();
return 8;
endfunction
end
endgenerate
endinterface
module t
(
input wire clk,
my_if in_if [2],
my_if out_if [2]
);
module t (
input wire clk,
my_if in_if[2],
my_if out_if[2]
);
assign out_if[0].valid = in_if[0].valid;
assign out_if[0].data = in_if[0].data;
assign out_if[0].valid = in_if[0].valid;
assign out_if[0].data = in_if[0].data;
assign out_if[1].valid = in_if[1].valid;
assign out_if[1].data = in_if[1].data;
assign out_if[1].valid = in_if[1].valid;
assign out_if[1].data = in_if[1].data;
my_if my_i (.clk(clk));
my_if my_i (.clk(clk));
initial
begin
$display(in_if[0].DW_LOCAL);
$display(in_if[0].width());
$display(in_if[0].dw_ge_4_G.min_width());
$display(out_if[0].DW_LOCAL);
$display(out_if[0].width());
$display(out_if[0].dw_ge_4_G.min_width());
initial begin
$display(in_if[0].DW_LOCAL);
$display(in_if[0].width());
$display(in_if[0].dw_ge_4_G.min_width());
$display(out_if[0].DW_LOCAL);
$display(out_if[0].width());
$display(out_if[0].dw_ge_4_G.min_width());
$display(in_if[1].DW_LOCAL);
$display(in_if[1].width());
$display(in_if[1].dw_ge_4_G.min_width());
$display(out_if[1].DW_LOCAL);
$display(out_if[1].width());
$display(out_if[1].dw_ge_4_G.min_width());
end
$display(in_if[1].DW_LOCAL);
$display(in_if[1].width());
$display(in_if[1].dw_ge_4_G.min_width());
$display(out_if[1].DW_LOCAL);
$display(out_if[1].width());
$display(out_if[1].dw_ge_4_G.min_width());
end
endmodule

6
test_regress/t/t_lint_iface_array_topmodule_bad.out
View File

@ -1,6 +1,6 @@
%Error: t/t_lint_iface_array_topmodule_bad.v:8:24: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'DW'
%Error: t/t_lint_iface_array_topmodule_bad.v:8:23: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'DW'
: ... note: In instance 't'
8 | parameter integer DW
| ^~
8 | parameter integer DW
| ^~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

56
test_regress/t/t_lint_iface_array_topmodule_bad.v
View File

@ -5,46 +5,46 @@
// SPDX-License-Identifier: CC0-1.0
interface my_if #(
parameter integer DW
) ();
parameter integer DW
) ();
logic valid;
logic [7:0] data ;
logic valid;
logic [7:0] data ;
modport slave_mp (
input valid,
input data
);
modport slave_mp (
input valid,
input data
);
modport master_mp (
output valid,
output data
);
modport master_mp (
output valid,
output data
);
endinterface
module t
(
input wire clk,
my_if.slave_mp in_if [2],
my_if.master_mp out_if [2]
);
input wire clk,
my_if.slave_mp in_if [2],
my_if.master_mp out_if [2]
);
my_if my_i [2] ();
my_if my_i [2] ();
always @(posedge clk)
begin
my_i[0].valid <= in_if[0].valid;
my_i[0].data <= in_if[0].data;
always @(posedge clk)
begin
my_i[0].valid <= in_if[0].valid;
my_i[0].data <= in_if[0].data;
my_i[1].valid <= in_if[1].valid;
my_i[1].data <= in_if[1].data;
end
my_i[1].valid <= in_if[1].valid;
my_i[1].data <= in_if[1].data;
end
assign out_if[0].valid = my_i[0].valid;
assign out_if[0].data = my_i[0].data;
assign out_if[0].valid = my_i[0].valid;
assign out_if[0].data = my_i[0].data;
assign out_if[1].valid = my_i[1].valid;
assign out_if[1].data = my_i[1].data;
assign out_if[1].valid = my_i[1].valid;
assign out_if[1].data = my_i[1].data;
endmodule

40
test_regress/t/t_lint_iface_topmodule1.v
View File

@ -6,37 +6,29 @@
interface my_if;
logic valid;
logic [7:0] data ;
logic valid;
logic [7:0] data;
modport slave_mp (
input valid,
input data
);
modport slave_mp(input valid, input data);
modport master_mp (
output valid,
output data
);
modport master_mp(output valid, output data);
endinterface
module t
(
input wire clk,
my_if.slave_mp in_if,
my_if.master_mp out_if
);
module t (
input wire clk,
my_if.slave_mp in_if,
my_if.master_mp out_if
);
my_if my_i ();
my_if my_i ();
always @(posedge clk)
begin
my_i.valid <= in_if.valid;
my_i.data <= in_if.data;
end
always @(posedge clk) begin
my_i.valid <= in_if.valid;
my_i.data <= in_if.data;
end
assign out_if.valid = my_i.valid;
assign out_if.data = my_i.data;
assign out_if.valid = my_i.valid;
assign out_if.data = my_i.data;
endmodule

31
test_regress/t/t_lint_iface_topmodule2.v
View File

@ -6,30 +6,23 @@
interface my_if #(
parameter integer DW = 8
) ();
logic valid;
logic [DW-1:0] data;
) ();
logic valid;
logic [DW-1:0] data;
modport slave_mp (
input valid,
input data
);
modport slave_mp(input valid, input data);
modport master_mp (
output valid,
output data
);
modport master_mp(output valid, output data);
endinterface
module t
(
input wire clk,
my_if.slave_mp in_if,
my_if.master_mp out_if
);
module t (
input wire clk,
my_if.slave_mp in_if,
my_if.master_mp out_if
);
assign out_if.valid = in_if.valid;
assign out_if.data = in_if.data;
assign out_if.valid = in_if.valid;
assign out_if.data = in_if.data;
endmodule

88
test_regress/t/t_lint_iface_topmodule3.v
View File

@ -4,64 +4,58 @@
// SPDX-FileCopyrightText: 2017 Josh Redford
// SPDX-License-Identifier: CC0-1.0
interface my_if #( parameter integer DW = 8 ) (input clk);
interface my_if #(
parameter integer DW = 8
) (
input clk
);
localparam DW_LOCAL = DW;
localparam DW_LOCAL = DW;
logic valid;
logic [DW-1:0] data;
logic valid;
logic [DW-1:0] data;
modport slave_mp (
input valid,
input data
);
modport slave_mp(input valid, input data);
modport master_mp (
output valid,
output data
);
modport master_mp(output valid, output data);
function automatic integer width();
return $bits(data);
endfunction
function automatic integer width();
return $bits(data);
endfunction
generate
if (DW < 4)
begin: dw_lt_4_G
function automatic integer min_width();
return 4;
endfunction
end
else
begin: dw_ge_4_G
function automatic integer min_width();
return 8;
endfunction
end
endgenerate
generate
if (DW < 4) begin : dw_lt_4_G
function automatic integer min_width();
return 4;
endfunction
end
else begin : dw_ge_4_G
function automatic integer min_width();
return 8;
endfunction
end
endgenerate
endinterface
module t
(
input wire clk,
my_if in_if,
my_if out_if
);
module t (
input wire clk,
my_if in_if,
my_if out_if
);
assign out_if.valid = in_if.valid;
assign out_if.data = in_if.data;
assign out_if.valid = in_if.valid;
assign out_if.data = in_if.data;
my_if my_i (.clk(clk));
my_if my_i (.clk(clk));
initial
begin
$display(in_if.DW_LOCAL);
$display(in_if.width());
$display(in_if.dw_ge_4_G.min_width());
$display(out_if.DW_LOCAL);
$display(out_if.width());
$display(out_if.dw_ge_4_G.min_width());
end
initial begin
$display(in_if.DW_LOCAL);
$display(in_if.width());
$display(in_if.dw_ge_4_G.min_width());
$display(out_if.DW_LOCAL);
$display(out_if.width());
$display(out_if.dw_ge_4_G.min_width());
end
endmodule

6
test_regress/t/t_lint_iface_topmodule_bad.out
View File

@ -1,6 +1,6 @@
%Error: t/t_lint_iface_topmodule_bad.v:8:23: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'DW'
%Error: t/t_lint_iface_topmodule_bad.v:8:22: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'DW'
: ... note: In instance 't'
8 | parameter integer DW
| ^~
8 | parameter integer DW
| ^~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

48
test_regress/t/t_lint_iface_topmodule_bad.v
View File

@ -5,40 +5,40 @@
// SPDX-License-Identifier: CC0-1.0
interface my_if #(
parameter integer DW
) ();
parameter integer DW
) ();
logic valid;
logic [DW-1:0] data ;
logic valid;
logic [DW-1:0] data ;
modport slave_mp (
input valid,
input data
);
modport slave_mp (
input valid,
input data
);
modport master_mp (
output valid,
output data
);
modport master_mp (
output valid,
output data
);
endinterface
module t
(
input wire clk,
my_if.slave_mp in_if,
my_if.master_mp out_if
);
input wire clk,
my_if.slave_mp in_if,
my_if.master_mp out_if
);
my_if my_i ();
my_if my_i ();
always @(posedge clk)
begin
my_i.valid <= in_if.valid;
my_i.data <= in_if.data;
end
always @(posedge clk)
begin
my_i.valid <= in_if.valid;
my_i.data <= in_if.data;
end
assign out_if.valid = my_i.valid;
assign out_if.data = my_i.data;
assign out_if.valid = my_i.valid;
assign out_if.data = my_i.data;
endmodule

6
test_regress/t/t_lint_ifdepth_bad.out
View File

@ -1,7 +1,7 @@
%Warning-IFDEPTH: t/t_lint_ifdepth_bad.v:22:12: Deep 'if' statement; suggest unique/priority to avoid slow logic
%Warning-IFDEPTH: t/t_lint_ifdepth_bad.v:22:10: Deep 'if' statement; suggest unique/priority to avoid slow logic
: ... note: In instance 't'
22 | else if (value==11) begin end
| ^~
22 | else if (value==11) begin end
| ^~
... For warning description see https://verilator.org/warn/IFDEPTH?v=latest
... Use "/* verilator lint_off IFDEPTH */" and lint_on around source to disable this message.
%Error: Exiting due to

58
test_regress/t/t_lint_ifdepth_bad.v
View File

@ -6,36 +6,36 @@
module t;
integer value = 19;
integer value = 19;
initial begin
if (value==1) begin end
else if (value==2) begin end
else if (value==3) begin end
else if (value==4) begin end
else if (value==5) begin end
else if (value==6) begin end
else if (value==7) begin end
else if (value==8) begin end
else if (value==9) begin end
else if (value==10) begin end
else if (value==11) begin end // Warn about this one
else if (value==12) begin end
end
initial begin
if (value==1) begin end
else if (value==2) begin end
else if (value==3) begin end
else if (value==4) begin end
else if (value==5) begin end
else if (value==6) begin end
else if (value==7) begin end
else if (value==8) begin end
else if (value==9) begin end
else if (value==10) begin end
else if (value==11) begin end // Warn about this one
else if (value==12) begin end
end
initial begin
unique0 if (value==1) begin end
else if (value==2) begin end
else if (value==3) begin end
else if (value==4) begin end
else if (value==5) begin end
else if (value==6) begin end
else if (value==7) begin end
else if (value==8) begin end
else if (value==9) begin end
else if (value==10) begin end
else if (value==11) begin end // Warn about this one
else if (value==12) begin end
end
initial begin
unique0 if (value==1) begin end
else if (value==2) begin end
else if (value==3) begin end
else if (value==4) begin end
else if (value==5) begin end
else if (value==6) begin end
else if (value==7) begin end
else if (value==8) begin end
else if (value==9) begin end
else if (value==10) begin end
else if (value==11) begin end // Warn about this one
else if (value==12) begin end
end
endmodule

19
test_regress/t/t_lint_implicit.v
View File

@ -4,16 +4,19 @@
// SPDX-FileCopyrightText: 2008 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (a,z);
input a;
output z;
module t (
a,
z
);
input a;
output z;
assign b = 1'b1;
assign b = 1'b1;
or OR0 (nt0, a, b);
or OR0 (nt0, a, b);
logic [1:0] dummy_ip;
assign {dummy1, dummy2} = dummy_ip;
logic [1:0] dummy_ip;
assign {dummy1, dummy2} = dummy_ip;
assign z = nt0;
assign z = nt0;
endmodule

24
test_regress/t/t_lint_implicit_bad.out
View File

@ -1,17 +1,17 @@
%Warning-IMPLICIT: t/t_lint_implicit.v:11:11: Signal definition not found, creating implicitly: 'b'
11 | assign b = 1'b1;
| ^
%Warning-IMPLICIT: t/t_lint_implicit.v:14:10: Signal definition not found, creating implicitly: 'b'
14 | assign b = 1'b1;
| ^
... For warning description see https://verilator.org/warn/IMPLICIT?v=latest
... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.
%Warning-IMPLICIT: t/t_lint_implicit.v:13:14: Signal definition not found, creating implicitly: 'nt0'
13 | or OR0 (nt0, a, b);
| ^~~
%Warning-IMPLICIT: t/t_lint_implicit.v:16:12: Signal definition not found, creating implicitly: 'dummy1'
%Warning-IMPLICIT: t/t_lint_implicit.v:16:11: Signal definition not found, creating implicitly: 'nt0'
16 | or OR0 (nt0, a, b);
| ^~~
%Warning-IMPLICIT: t/t_lint_implicit.v:19:11: Signal definition not found, creating implicitly: 'dummy1'
: ... Suggested alternative: 'dummy_ip'
16 | assign {dummy1, dummy2} = dummy_ip;
| ^~~~~~
%Warning-IMPLICIT: t/t_lint_implicit.v:16:20: Signal definition not found, creating implicitly: 'dummy2'
19 | assign {dummy1, dummy2} = dummy_ip;
| ^~~~~~
%Warning-IMPLICIT: t/t_lint_implicit.v:19:19: Signal definition not found, creating implicitly: 'dummy2'
: ... Suggested alternative: 'dummy1'
16 | assign {dummy1, dummy2} = dummy_ip;
| ^~~~~~
19 | assign {dummy1, dummy2} = dummy_ip;
| ^~~~~~
%Error: Exiting due to

12
test_regress/t/t_lint_implicit_def_bad.out
View File

@ -1,10 +1,10 @@
%Warning-IMPLICIT: t/t_lint_implicit_def_bad.v:13:11: Signal definition not found, creating implicitly: 'imp_warn'
13 | assign imp_warn = 1'b1;
| ^~~~~~~~
%Warning-IMPLICIT: t/t_lint_implicit_def_bad.v:13:10: Signal definition not found, creating implicitly: 'imp_warn'
13 | assign imp_warn = 1'b1;
| ^~~~~~~~
... For warning description see https://verilator.org/warn/IMPLICIT?v=latest
... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.
%Error: t/t_lint_implicit_def_bad.v:18:11: Signal definition not found, and implicit disabled with `default_nettype: 'imp_err'
18 | assign imp_err = 1'b1;
| ^~~~~~~
%Error: t/t_lint_implicit_def_bad.v:18:10: Signal definition not found, and implicit disabled with `default_nettype: 'imp_err'
18 | assign imp_err = 1'b1;
| ^~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

18
test_regress/t/t_lint_implicit_def_bad.v
View File

@ -5,24 +5,24 @@
// SPDX-License-Identifier: CC0-1.0
module t (a,z);
input a;
output z;
input a;
output z;
sub sub ();
sub sub ();
assign imp_warn = 1'b1;
// verilator lint_off IMPLICIT
assign imp_ok = 1'b1;
assign imp_warn = 1'b1;
// verilator lint_off IMPLICIT
assign imp_ok = 1'b1;
`default_nettype none
assign imp_err = 1'b1;
assign imp_err = 1'b1;
`default_nettype wire
assign imp_ok2 = 1'b1;
assign imp_ok2 = 1'b1;
endmodule
`default_nettype none
`resetall
module sub;
assign imp_ok3 = 1'b1;
assign imp_ok3 = 1'b1;
endmodule

6
test_regress/t/t_lint_implicit_func_bad.out
View File

@ -1,6 +1,6 @@
%Error: t/t_lint_implicit_func_bad.v:12:11: Cannot call a task/void-function as a function: 'imp_func_conflict'
%Error: t/t_lint_implicit_func_bad.v:12:10: Cannot call a task/void-function as a function: 'imp_func_conflict'
: ... note: In instance 't'
12 | assign imp_func_conflict = 1'b1;
| ^~~~~~~~~~~~~~~~~
12 | assign imp_func_conflict = 1'b1;
| ^~~~~~~~~~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

6
test_regress/t/t_lint_implicit_func_bad.v
View File

@ -5,9 +5,9 @@
// SPDX-License-Identifier: CC0-1.0
module t;
function void imp_func_conflict();
endfunction
function void imp_func_conflict();
endfunction
`default_nettype wire
assign imp_func_conflict = 1'b1;
assign imp_func_conflict = 1'b1;
endmodule

39
test_regress/t/t_lint_implicit_port.v
View File

@ -4,30 +4,37 @@
// SPDX-FileCopyrightText: 2008 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
logic oe;
logic oe;
read r (.clk(clk), .data( ( ( oe == 1'd001 ) && implicit_write ) ) );
sets s (.clk(clk), .enable(implicit_write));
read u (.clk(clk), .data(~implicit_also));
read r (
.clk(clk),
.data(((oe == 1'd001) && implicit_write))
);
sets s (
.clk(clk),
.enable(implicit_write)
);
read u (
.clk(clk),
.data(~implicit_also)
);
endmodule
module sets (
input clk,
output enable
);
assign enable = 1'b0;
input clk,
output enable
);
assign enable = 1'b0;
endmodule
module read (
input clk,
input data
);
input clk,
input data
);
endmodule

18
test_regress/t/t_lint_implicit_type_bad.out
View File

@ -1,11 +1,11 @@
%Error: t/t_lint_implicit_type_bad.v:15:11: Data type used where a non-data type is expected: 'imp_typedef_conflict'
15 | assign imp_typedef_conflict = 1'b1;
| ^~~~~~~~~~~~~~~~~~~~
%Error: t/t_lint_implicit_type_bad.v:15:10: Data type used where a non-data type is expected: 'imp_typedef_conflict'
15 | assign imp_typedef_conflict = 1'b1;
| ^~~~~~~~~~~~~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_lint_implicit_type_bad.v:16:11: Data type used where a non-data type is expected: 'imp_Cls_conflict'
16 | assign imp_Cls_conflict = 1'b1;
| ^~~~~~~~~~~~~~~~
%Error: t/t_lint_implicit_type_bad.v:17:11: Data type used where a non-data type is expected: 'imp_PARAM_conflict'
17 | assign imp_PARAM_conflict = 1'b1;
| ^~~~~~~~~~~~~~~~~~
%Error: t/t_lint_implicit_type_bad.v:16:10: Data type used where a non-data type is expected: 'imp_Cls_conflict'
16 | assign imp_Cls_conflict = 1'b1;
| ^~~~~~~~~~~~~~~~
%Error: t/t_lint_implicit_type_bad.v:17:10: Data type used where a non-data type is expected: 'imp_PARAM_conflict'
17 | assign imp_PARAM_conflict = 1'b1;
| ^~~~~~~~~~~~~~~~~~
%Error: Exiting due to

10
test_regress/t/t_lint_implicit_type_bad.v
View File

@ -8,11 +8,11 @@ class imp_Cls_conflict;
endclass
module t;
typedef int imp_typedef_conflict;
localparam type imp_PARAM_conflict;
typedef int imp_typedef_conflict;
localparam type imp_PARAM_conflict;
`default_nettype wire
assign imp_typedef_conflict = 1'b1;
assign imp_Cls_conflict = 1'b1;
assign imp_PARAM_conflict = 1'b1;
assign imp_typedef_conflict = 1'b1;
assign imp_Cls_conflict = 1'b1;
assign imp_PARAM_conflict = 1'b1;
endmodule

2
test_regress/t/t_lint_import_name_bad.v
View File

@ -5,7 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
package defs;
int sig;
int sig;
endpackage
import defs::sigs;

6
test_regress/t/t_lint_importstar_bad.out
View File

@ -3,10 +3,10 @@
| ^~~~
... For warning description see https://verilator.org/warn/IMPORTSTAR?v=latest
... Use "/* verilator lint_off IMPORTSTAR */" and lint_on around source to disable this message.
%Warning-UNUSEDPARAM: t/t_lint_importstar_bad.v:8:15: Parameter is not used: 'PAR'
%Warning-UNUSEDPARAM: t/t_lint_importstar_bad.v:8:14: Parameter is not used: 'PAR'
: ... note: In instance 't'
8 | localparam PAR = 1;
| ^~~
8 | localparam PAR = 1;
| ^~~
... For warning description see https://verilator.org/warn/UNUSEDPARAM?v=latest
... Use "/* verilator lint_off UNUSEDPARAM */" and lint_on around source to disable this message.
%Error: Exiting due to

2
test_regress/t/t_lint_importstar_bad.v
View File

@ -5,7 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
package defs;
localparam PAR = 1;
localparam PAR = 1;
endpackage
import defs::*;

44
test_regress/t/t_lint_infinite.v
View File

@ -6,31 +6,31 @@
module t;
mailbox #(int) mbox;
mailbox #(int) mbox;
task main();
// See issue #4323; not an INFINITELOOP due to delay inside get()
forever begin
int i;
mbox.get(i);
$display("[%0t] Got %0d", $time, i);
end
endtask
task main();
// See issue #4323; not an INFINITELOOP due to delay inside get()
forever begin
int i;
mbox.get(i);
$display("[%0t] Got %0d", $time, i);
end
endtask
initial begin
mbox = new (1);
initial begin
mbox = new(1);
#10;
fork
main();
join_none
#10;
fork
main();
join_none
#10;
mbox.put(10);
mbox.put(11);
#10;
mbox.put(10);
mbox.put(11);
#10;
$write("*-* All Finished *-*\n");
$finish;
end
#10;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

12
test_regress/t/t_lint_infinite_bad.out
View File

@ -1,11 +1,11 @@
%Warning-INFINITELOOP: t/t_lint_infinite_bad.v:10:7: Infinite loop (condition always true)
%Warning-INFINITELOOP: t/t_lint_infinite_bad.v:10:5: Infinite loop (condition always true)
: ... note: In instance 't'
10 | forever begin end
| ^~~~~~~
10 | forever begin end
| ^~~~~~~
... For warning description see https://verilator.org/warn/INFINITELOOP?v=latest
... Use "/* verilator lint_off INFINITELOOP */" and lint_on around source to disable this message.
%Warning-INFINITELOOP: t/t_lint_infinite_bad.v:12:7: Infinite loop (condition always true)
%Warning-INFINITELOOP: t/t_lint_infinite_bad.v:12:5: Infinite loop (condition always true)
: ... note: In instance 't'
12 | for (reg [31:0] i=0; i>=0; i=i+1) begin end
| ^~~
12 | for (reg [31:0] i=0; i>=0; i=i+1) begin end
| ^~~
%Error: Exiting due to

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