Fix class initial-automatic insertion order (#7086 repair)
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@ -291,18 +291,23 @@ private:
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iterateChildren(nodep);
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}
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UASSERT_OBJ(m_ctorp, nodep, "class constructor missing"); // LinkDot always makes it
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AstNode* insertp = nullptr;
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for (AstInitialAutomatic* initialp : m_initialps) {
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if (AstNode* const newp = initialp->stmtsp()) {
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newp->unlinkFrBackWithNext();
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if (!m_ctorp->stmtsp()) {
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m_ctorp->addStmtsp(newp);
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} else {
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m_ctorp->stmtsp()->addHereThisAsNext(newp);
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}
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if (AstNode* const movep = initialp->stmtsp()) {
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movep->unlinkFrBackWithNext();
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// Next InitialAutomatic must go in order after what we inserted
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insertp = AstNode::addNextNull(insertp, movep);
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}
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VL_DO_DANGLING(pushDeletep(initialp->unlinkFrBack()), initialp);
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}
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m_initialps.clear();
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if (insertp) {
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if (!m_ctorp->stmtsp()) {
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m_ctorp->addStmtsp(insertp);
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} else {
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m_ctorp->stmtsp()->addHereThisAsNext(insertp);
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}
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}
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}
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void visit(AstInitialAutomatic* nodep) override {
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m_initialps.push_back(nodep);
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.execute()
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test.passes()
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@ -0,0 +1,68 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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class uvm_coreservice;
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static uvm_coreservice inst;
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function new(string name);
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endfunction
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static function uvm_coreservice get();
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if (inst == null) begin
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inst = new("cs-base");
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end
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return inst;
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endfunction
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virtual function string get_factory();
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return "factory";
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endfunction
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endclass
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class uvm_test;
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string m_name;
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string s0 = {m_name, "0"}; // Before new(); this must get "0" not "name0"
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function new(string name);
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m_name = name;
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endfunction
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endclass
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class test extends uvm_test;
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string s1 = {s0, "1"};
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string s2 = {s1, "2"};
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uvm_coreservice cs = uvm_coreservice::get();
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// Below assumes that the above 'cs' executes first.
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// Most simulators require this ordering, but some allow arbitrary order
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// This would require dataflow analysis, so for now Verilator requires user ordering
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string factory = cs.get_factory();
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function new(string name);
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super.new(name);
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endfunction
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endclass
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initial begin
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test t;
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string s;
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t = new("test");
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`checks(t.s0, "0");
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`checks(t.s1, "01");
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`checks(t.s2, "012");
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s = t.factory;
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`checks(s, "factory");
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$finish;
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end
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endmodule
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