Tests: Add t_inst_array_slice (#3433 test)

test_regress/t/t_inst_array_slice.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2026 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_inst_array_slice.v

@@ -0,0 +1,26 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2026 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// verilog_format: off
+`define stop $stop
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
+
+module t;
+  localparam int unsigned LARGE_ARRAY[5] = '{1, 2, 3, 4, 5};
+  localparam int unsigned SMALL_ARRAY[2] = LARGE_ARRAY[1+:2];
+  sub #(.VAL(SMALL_ARRAY)) u_sub ();
+endmodule
+
+module sub #(
+    parameter int unsigned VAL[2] = '{1, 2}
+) ();
+  initial begin
+    `checkd(VAL[0], 2);
+    `checkd(VAL[1], 3);
+    $finish;
+  end
+endmodule