luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Remove `--xml-only`.

This commit is contained in:
Wilson Snyder 2026-01-01 09:23:05 -05:00
parent 66bd173c86
commit a7b80966ec
59 changed files with 22 additions and 4091 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Changes
View File

@ -11,6 +11,9 @@ contributors that suggested or implemented a given issue are shown in []. Thanks
Verilator 5.045 devel
==========================
**Other:**
* Remove `--xml-only`.
Verilator 5.044 2026-01-01

2
bin/verilator
View File

@ -552,8 +552,6 @@ detailed descriptions of these arguments.
--x-assign <mode> Assign non-initial Xs to this value
--x-initial <mode> Assign initial Xs to this value
--x-initial-edge Enable initial X->0 and X->1 edge triggers
--xml-only Create XML parser output
--xml-output XML output filename
-y <dir> Directory to search for modules
This is a short summary of the simulation runtime arguments, i.e. for the

5
docs/guide/deprecations.rst
View File

@ -17,11 +17,6 @@ C++14 compiler support
the Ubuntu LTS versions of GCC and clang use C++20 by default, estimated
May 2028.)
XML output
Verilator currently supports XML parser output (enabled with
`--xml-only`). Support for `--xml-*` options will be deprecated no
sooner than January 2026.
`--make cmake`
The `--make cmake` options is deprecated and will be removed no sooner
than January 2026. Use `--make json` instead. Note that the CMake

17
docs/guide/exe_verilator.rst
View File

@ -2198,23 +2198,16 @@ Summary:
.. option:: --xml-only
Create XML output only, do not create any other output.
Removed in 5.046.
The XML format is intended to be used to leverage Verilator's parser and
elaboration to feed to other downstream tools.
.. note::
This feature is deprecated in favor of :vlopt:`--json-only`.
Created XML output only, did not create any other output.
.. option:: --xml-output <filename>
Specifies the filename for the XML output file. Using this option
automatically sets :vlopt:`--xml-only`.
Removed in 5.046.
.. note::
This feature is deprecated in favor of :vlopt:`--json-only`.
Specified the filename for the XML output file. Using this option
automatically set :vlopt:`--xml-only`.
.. option:: -y <dir>

2
docs/guide/files.rst
View File

@ -112,8 +112,6 @@ In specific debug and other modes, it also creates:
- JSON tree information (from --json-only)
* - *{prefix}*.tree.meta.json
- JSON tree metadata (from --json-only)
* - *{prefix}*.xml
- XML tree information (from --xml)
* - *{prefix}*\ __cdc.txt
- Clock Domain Crossing checks (from --cdc)
* - *{prefix}*\ __stats.txt

2
src/CMakeLists.txt
View File

@ -94,7 +94,6 @@ set(HEADERS
V3EmitMk.h
V3EmitMkJson.h
V3EmitV.h
V3EmitXml.h
V3Error.h
V3ExecGraph.h
V3Expand.h
@ -268,7 +267,6 @@ set(COMMON_SOURCES
V3EmitMk.cpp
V3EmitMkJson.cpp
V3EmitV.cpp
V3EmitXml.cpp
V3Error.cpp
V3ExecGraph.cpp
V3Expand.cpp

1
src/Makefile_obj.in
View File

@ -276,7 +276,6 @@ RAW_OBJS_PCH_ASTNOMT = \
V3EmitCSyms.o \
V3EmitMk.o \
V3EmitMkJson.o \
V3EmitXml.o \
V3ExecGraph.o \
V3Expand.o \
V3Force.o \

4
src/V3AstAttr.h
View File

@ -1019,10 +1019,6 @@ public:
static const char* const names[] = {"", "input", "output", "inout", "ref", "const ref"};
return names[m_e];
}
string xmlKwd() const { // For historical reasons no "put" suffix
static const char* const names[] = {"", "in", "out", "inout", "ref", "const ref"};
return names[m_e];
}
string prettyName() const { return verilogKwd(); }
bool isAny() const { return m_e != NONE; }
bool isInout() const { return m_e == INOUT; }

460
src/V3EmitXml.cpp
View File

@ -1,460 +0,0 @@
// -*- mode: C++; c-file-style: "cc-mode" -*-
//*************************************************************************
// DESCRIPTION: Verilator: Emit Verilog from tree
//
// Code available from: https://verilator.org
//
//*************************************************************************
//
// Copyright 2004-2026 by Wilson Snyder. This program is free software; you
// can redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
//
//*************************************************************************
#include "V3PchAstNoMT.h" // VL_MT_DISABLED_CODE_UNIT
#include "V3EmitXml.h"
#include "V3EmitCBase.h"
#include <map>
#include <vector>
VL_DEFINE_DEBUG_FUNCTIONS;
// ######################################################################
// Emit statements and expressions
class EmitXmlFileVisitor final : public VNVisitorConst {
// NODE STATE
// Entire netlist:
// AstNode::user1 -> uint64_t, number to connect crossrefs
const VNUser1InUse m_user1InUse;
// MEMBERS
V3OutFile* const m_ofp;
uint64_t m_id = 0;
// METHODS
// Outfile methods
V3OutFile* ofp() const { return m_ofp; }
virtual void puts(const string& str) { ofp()->puts(str); }
virtual void putsNoTracking(const string& str) { ofp()->putsNoTracking(str); }
virtual void putsQuoted(const string& str) {
// Quote \ and " for use inside C programs
// Don't use to quote a filename for #include - #include doesn't \ escape.
// Duplicate in V3File - here so we can print to string
putsNoTracking("\"");
putsNoTracking(V3OutFormatter::quoteNameControls(str, V3OutFormatter::LA_XML));
putsNoTracking("\"");
}
// XML methods
void outputId(AstNode* nodep) {
if (!nodep->user1()) nodep->user1(++m_id);
puts("\"" + cvtToStr(nodep->user1()) + "\"");
}
void outputTag(AstNode* nodep, const string& tagin) {
string tag = tagin;
if (tag == "") tag = VString::downcase(nodep->typeName());
puts("<" + tag);
puts(" " + nodep->fileline()->xmlDetailedLocation());
if (VN_IS(nodep, NodeDType)) {
puts(" id=");
outputId(nodep);
}
if (nodep->name() != "") {
puts(" name=");
putsQuoted(nodep->prettyName());
}
if (nodep->tag() != "") {
puts(" tag=");
putsQuoted(nodep->tag());
}
if (const AstNodeDType* const dtp = VN_CAST(nodep, NodeDType)) {
if (dtp->subDTypep()) {
puts(" sub_dtype_id=");
outputId(dtp->subDTypep()->skipRefp());
}
} else {
if (nodep->dtypep()) {
puts(" dtype_id=");
outputId(nodep->dtypep()->skipRefp());
}
}
}
void outputChildrenEnd(AstNode* nodep, const string& tagin) {
string tag = tagin;
if (tag == "") tag = VString::downcase(nodep->typeName());
if (nodep->op1p() || nodep->op2p() || nodep->op3p() || nodep->op4p()) {
puts(">\n");
iterateChildrenConst(nodep);
puts("</" + tag + ">\n");
} else {
puts("/>\n");
}
}
// VISITORS
void visit(AstAssignW* nodep) override {
outputTag(nodep, "contassign"); // IEEE: vpiContAssign
outputChildrenEnd(nodep, "contassign");
}
void visit(AstCell* nodep) override {
outputTag(nodep, "instance"); // IEEE: vpiInstance
puts(" defName=");
putsQuoted(nodep->modName()); // IEEE vpiDefName
puts(" origName=");
putsQuoted(nodep->origName());
outputChildrenEnd(nodep, "instance");
}
void visit(AstNodeIf* nodep) override {
outputTag(nodep, "if");
puts(">\n");
iterateAndNextConstNull(nodep->condp());
puts("<begin>\n");
iterateAndNextConstNull(nodep->thensp());
puts("</begin>\n");
if (nodep->elsesp()) {
puts("<begin>\n");
iterateAndNextConstNull(nodep->elsesp());
puts("</begin>\n");
}
puts("</if>\n");
}
void visit(AstLoop* nodep) override {
outputTag(nodep, "loop");
puts(">\n");
if (nodep->stmtsp()) {
puts("<begin>\n");
iterateAndNextConstNull(nodep->stmtsp());
puts("</begin>\n");
}
if (nodep->contsp()) {
puts("<begin>\n");
iterateAndNextConstNull(nodep->contsp());
puts("</begin>\n");
}
puts("</loop>\n");
}
void visit(AstLoopTest* nodep) override {
outputTag(nodep, "looptest");
puts(">\n");
iterateAndNextConstNull(nodep->condp());
puts("</looptest>\n");
}
void visit(AstNetlist* nodep) override {
puts("<netlist>\n");
iterateChildrenConst(nodep);
puts("</netlist>\n");
}
void visit(AstConstPool* nodep) override {
if (!v3Global.opt.xmlOnly()) {
puts("<constpool>\n");
iterateChildrenConst(nodep);
puts("</constpool>\n");
}
}
void visit(AstInitArray* nodep) override {
puts("<initarray>\n");
const auto& mapr = nodep->map();
for (const auto& itr : mapr) {
puts("<inititem index=\"");
puts(cvtToStr(itr.first));
puts("\">\n");
iterateChildrenConst(itr.second);
puts("</inititem>\n");
}
puts("</initarray>\n");
}
void visit(AstNodeModule* nodep) override {
outputTag(nodep, "");
puts(" origName=");
putsQuoted(nodep->origName());
if (nodep->isTop()) puts(" topModule=\"1\""); // IEEE vpiTopModule
if (nodep->modPublic()) puts(" public=\"true\"");
outputChildrenEnd(nodep, "");
}
void visit(AstVar* nodep) override {
const VVarType typ = nodep->varType();
const string kw = nodep->verilogKwd();
const string vt = nodep->dtypep() ? nodep->dtypep()->name() : "";
outputTag(nodep, "");
if (nodep->isIO()) {
puts(" dir=");
putsQuoted(kw);
if (nodep->pinNum() != 0) puts(" pinIndex=\"" + cvtToStr(nodep->pinNum()) + "\"");
puts(" vartype=");
putsQuoted(!vt.empty() ? vt : typ == VVarType::PORT ? "port" : "unknown");
} else {
puts(" vartype=");
putsQuoted(!vt.empty() ? vt : kw);
}
puts(" origName=");
putsQuoted(nodep->origName());
// Attributes
if (nodep->attrIsolateAssign()) puts(" isolate_assignments=\"true\"");
if (nodep->isLatched()) puts(" latched=\"true\"");
if (nodep->isSigPublic()) puts(" public=\"true\"");
if (nodep->isSigUserRdPublic()) puts(" public_flat_rd=\"true\"");
if (nodep->isSigUserRWPublic()) puts(" public_flat_rw=\"true\"");
if (nodep->isGParam()) {
puts(" param=\"true\"");
} else if (nodep->isParam()) {
puts(" localparam=\"true\"");
}
if (nodep->attrScBv()) puts(" sc_bv=\"true\"");
if (nodep->attrSFormat()) puts(" sformat=\"true\"");
outputChildrenEnd(nodep, "");
}
void visit(AstPin* nodep) override {
// What we call a pin in verilator is a port in the IEEE spec.
outputTag(nodep, "port"); // IEEE: vpiPort
if (nodep->modVarp() && nodep->modVarp()->isIO()) {
puts(" direction=\"" + nodep->modVarp()->direction().xmlKwd() + "\"");
}
puts(" portIndex=\"" + cvtToStr(nodep->pinNum()) + "\""); // IEEE: vpiPortIndex
// Children includes vpiHighConn and vpiLowConn; we don't support port bits (yet?)
outputChildrenEnd(nodep, "port");
}
void visit(AstSenItem* nodep) override {
outputTag(nodep, "");
puts(" edgeType=\"" + cvtToStr(nodep->edgeType().ascii()) + "\""); // IEEE vpiTopModule
outputChildrenEnd(nodep, "");
}
void visit(AstModportVarRef* nodep) override {
// Dump direction for Modport references
const string kw = nodep->direction().xmlKwd();
outputTag(nodep, "");
puts(" direction=");
putsQuoted(kw);
outputChildrenEnd(nodep, "");
}
void visit(AstVarXRef* nodep) override {
outputTag(nodep, "");
puts(" dotted=");
putsQuoted(nodep->dotted());
outputChildrenEnd(nodep, "");
}
void visit(AstNodeCCall* nodep) override {
outputTag(nodep, "");
puts(" func=");
putsQuoted(nodep->funcp() ? nodep->funcp()->name() : nodep->name());
outputChildrenEnd(nodep, "");
}
void visit(AstSel* nodep) override {
outputTag(nodep, "");
puts(" widthConst=\"" + cvtToStr(nodep->widthConst()) + "\"");
outputChildrenEnd(nodep, "");
}
// Data types
void visit(AstBasicDType* nodep) override {
outputTag(nodep, "basicdtype");
if (nodep->isRanged()) {
puts(" left=\"" + cvtToStr(nodep->left()) + "\"");
puts(" right=\"" + cvtToStr(nodep->right()) + "\"");
}
if (nodep->isSigned()) puts(" signed=\"true\"");
puts("/>\n");
}
void visit(AstIfaceRefDType* nodep) override {
string mpn;
outputTag(nodep, "");
if (nodep->isModport()) mpn = nodep->modportName();
puts(" modportname=");
putsQuoted(mpn);
outputChildrenEnd(nodep, "");
}
void visit(AstDisplay* nodep) override {
outputTag(nodep, "");
puts(" displaytype=");
putsQuoted(nodep->verilogKwd());
outputChildrenEnd(nodep, "");
}
void visit(AstElabDisplay* nodep) override {
outputTag(nodep, "");
puts(" displaytype=");
putsQuoted(nodep->verilogKwd());
outputChildrenEnd(nodep, "");
}
void visit(AstExtend* nodep) override {
outputTag(nodep, "");
puts(" width=");
putsQuoted(cvtToStr(nodep->width()));
puts(" widthminv=");
putsQuoted(cvtToStr(nodep->lhsp()->widthMinV()));
outputChildrenEnd(nodep, "");
}
void visit(AstExtendS* nodep) override {
outputTag(nodep, "");
puts(" width=");
putsQuoted(cvtToStr(nodep->width()));
puts(" widthminv=");
putsQuoted(cvtToStr(nodep->lhsp()->widthMinV()));
outputChildrenEnd(nodep, "");
}
// Default
void visit(AstNode* nodep) override {
outputTag(nodep, "");
outputChildrenEnd(nodep, "");
}
public:
EmitXmlFileVisitor(AstNode* nodep, V3OutFile* ofp)
: m_ofp{ofp} {
iterateConst(nodep);
}
~EmitXmlFileVisitor() override = default;
};
//######################################################################
// List of module files xml visitor
class ModuleFilesXmlVisitor final : public VNVisitorConst {
// MEMBERS
std::ostream& m_os;
std::set<std::string> m_modulesCovered;
std::deque<FileLine*> m_nodeModules;
// METHODS
// VISITORS
void visit(AstNetlist* nodep) override {
// Children are iterated backwards to ensure correct compilation order
iterateChildrenBackwardsConst(nodep);
}
void visit(AstNodeModule* nodep) override {
// Only list modules and interfaces
// Assumes modules and interfaces list is already sorted level wise
if (!nodep->dead() && (VN_IS(nodep, Module) || VN_IS(nodep, Iface))
&& m_modulesCovered.insert(nodep->fileline()->filename()).second) {
m_nodeModules.push_front(nodep->fileline());
}
}
//-----
void visit(AstNode*) override {
// All modules are present at root so no need to iterate on children
}
public:
// CONSTRUCTORS
ModuleFilesXmlVisitor(AstNetlist* nodep, std::ostream& os)
: m_os(os) { // Need () or GCC 4.8 false warning
// Operate on whole netlist
iterateConst(nodep);
// Xml output
m_os << "<module_files>\n";
for (const FileLine* ifp : m_nodeModules) {
m_os << "<file id=\"" << ifp->filenameLetters() << "\" filename=\""
<< ifp->filenameEsc() << "\" language=\"" << ifp->language().ascii() << "\"/>\n";
}
m_os << "</module_files>\n";
}
~ModuleFilesXmlVisitor() override = default;
};
//######################################################################
// Hierarchy of Cells visitor
class HierCellsXmlVisitor final : public VNVisitorConst {
// MEMBERS
std::ostream& m_os;
std::string m_hier;
bool m_hasChildren = false;
// METHODS
// VISITORS
void visit(AstConstPool*) override {}
void visit(AstNodeModule* nodep) override {
if (nodep->level() >= 0 && nodep->isTop()) {
m_os << "<cells>\n";
m_os << "<cell " << nodep->fileline()->xmlDetailedLocation() //
<< " name=\"" << nodep->prettyName() << "\"" << " submodname=\""
<< nodep->prettyName() << "\"" << " hier=\"" << nodep->prettyName() << "\"";
m_hier = nodep->prettyName() + ".";
m_hasChildren = false;
iterateChildrenConst(nodep);
if (m_hasChildren) {
m_os << "</cell>\n";
} else {
m_os << "/>\n";
}
m_os << "</cells>\n";
}
}
void visit(AstCell* nodep) override {
if (nodep->modp() && nodep->modp()->dead()) return;
if (!m_hasChildren) m_os << ">\n";
m_os << "<cell " << nodep->fileline()->xmlDetailedLocation() << " name=\"" << nodep->name()
<< "\"" << " submodname=\"" << nodep->modName() << "\"" << " hier=\""
<< m_hier + nodep->name() << "\"";
const std::string hier = m_hier;
m_hier += nodep->name() + ".";
m_hasChildren = false;
iterateChildrenConst(nodep->modp());
if (m_hasChildren) {
m_os << "</cell>\n";
} else {
m_os << "/>\n";
}
m_hier = hier;
m_hasChildren = true;
}
void visit(AstGenBlock* nodep) override {
VL_RESTORER(m_hier);
if (nodep->name() != "") m_hier += nodep->name() + ".";
iterateChildrenConst(nodep);
}
void visit(AstBegin* nodep) override {
VL_RESTORER(m_hier);
if (nodep->name() != "") m_hier += nodep->name() + ".";
iterateChildrenConst(nodep);
}
//-----
void visit(AstNode* nodep) override { iterateChildrenConst(nodep); }
public:
// CONSTRUCTORS
HierCellsXmlVisitor(AstNetlist* nodep, std::ostream& os)
: m_os(os) { // Need () or GCC 4.8 false warning
iterateConst(nodep);
}
~HierCellsXmlVisitor() override = default;
};
//######################################################################
// EmitXml class functions
void V3EmitXml::emitxml() {
UINFO(2, __FUNCTION__ << ":");
// All-in-one file
const string filename = (v3Global.opt.xmlOutput().empty()
? v3Global.opt.makeDir() + "/" + v3Global.opt.prefix() + ".xml"
: v3Global.opt.xmlOutput());
V3OutXmlFile of{filename};
of.putsHeader();
of.puts("<!-- DESCR"
"IPTION: Verilator output: XML representation of netlist -->\n");
of.puts("<verilator_xml>\n");
{
std::stringstream sstr;
FileLine::fileNameNumMapDumpXml(sstr);
of.puts(sstr.str());
}
{
std::stringstream sstr;
const ModuleFilesXmlVisitor moduleFilesVisitor{v3Global.rootp(), sstr};
const HierCellsXmlVisitor cellsVisitor{v3Global.rootp(), sstr};
of.puts(sstr.str());
}
const EmitXmlFileVisitor visitor{v3Global.rootp(), &of};
of.puts("</verilator_xml>\n");
}

30
src/V3EmitXml.h
View File

@ -1,30 +0,0 @@
// -*- mode: C++; c-file-style: "cc-mode" -*-
//*************************************************************************
// DESCRIPTION: Verilator: Emit XML code
//
// Code available from: https://verilator.org
//
//*************************************************************************
//
// Copyright 2003-2026 by Wilson Snyder. This program is free software; you
// can redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
//
//*************************************************************************
#ifndef VERILATOR_V3EMITXML_H_
#define VERILATOR_V3EMITXML_H_
#include "config_build.h"
#include "verilatedos.h"
//============================================================================
class V3EmitXml final {
public:
static void emitxml() VL_MT_DISABLED;
};
#endif // Guard

18
src/V3FileLine.cpp
View File

@ -77,18 +77,6 @@ FileLineSingleton::fileNameIdx_t FileLineSingleton::nameToNumber(const string& f
return idx;
}
//! Support XML output
//! Experimental. Updated to also put out the language.
void FileLineSingleton::fileNameNumMapDumpXml(std::ostream& os) {
os << "<files>\n";
for (const auto& itr : m_namemap) {
os << "<file id=\"" << filenameLetters(itr.second) << "\" filename=\""
<< V3OutFormatter::quoteNameControls(itr.first, V3OutFormatter::LA_XML)
<< "\" language=\"" << numberToLang(itr.second).ascii() << "\"/>\n";
}
os << "</files>\n";
}
void FileLineSingleton::fileNameNumMapDumpJson(std::ostream& os) {
std::string sep = "\n ";
os << "\"files\": {";
@ -241,12 +229,6 @@ void FileLine::newContent() {
m_contentLineno = 1;
}
string FileLine::xmlDetailedLocation() const {
return "loc=\"" + cvtToStr(filenameLetters()) + "," + cvtToStr(firstLineno()) + ","
+ cvtToStr(firstColumn()) + "," + cvtToStr(lastLineno()) + "," + cvtToStr(lastColumn())
+ "\"";
}
string FileLine::lineDirectiveStrg(int enterExit) const {
return "`line "s + cvtToStr(lastLineno()) + " \""
+ V3OutFormatter::quoteNameControls(filename()) + "\" " + cvtToStr(enterExit) + '\n';

3
src/V3FileLine.h
View File

@ -135,7 +135,6 @@ class FileLineSingleton final {
m_names.clear();
m_languages.clear();
}
void fileNameNumMapDumpXml(std::ostream& os);
void fileNameNumMapDumpJson(std::ostream& os);
static string filenameLetters(fileNameIdx_t fileno) VL_PURE;
@ -368,7 +367,6 @@ public:
string filebasenameNoExt() const;
string firstColumnLetters() const VL_MT_SAFE;
string profileFuncname() const;
string xmlDetailedLocation() const;
string lineDirectiveStrg(int enterExit) const;
// Turn on/off warning messages on this line.
@ -410,7 +408,6 @@ public:
static string globalWarnOffParse(const string& msgs, bool turnOff) {
return defaultFileLine().warnOffParse(msgs, turnOff);
}
static void fileNameNumMapDumpXml(std::ostream& os) { singleton().fileNameNumMapDumpXml(os); }
static void fileNameNumMapDumpJson(std::ostream& os) {
singleton().fileNameNumMapDumpJson(os);
}

19
src/V3Options.cpp
View File

@ -948,14 +948,14 @@ void V3Options::notify() VL_MT_DISABLED {
if (!outFormatOk() && v3Global.opt.main()) ccSet(); // --main implies --cc if not provided
if (!outFormatOk() && !dpiHdrOnly() && !lintOnly() && !preprocOnly() && !serializeOnly()) {
v3fatal("verilator: Need --binary, --cc, --sc, --dpi-hdr-only, --lint-only, "
"--xml-only, --json-only or --E option");
"--json-only or --E option");
}
if (m_build && (m_gmake || m_cmake || m_makeJson)) {
cmdfl->v3error("--make cannot be used together with --build. Suggest see manual");
}
// m_build, m_preprocOnly, m_dpiHdrOnly, m_lintOnly, m_jsonOnly and m_xmlOnly are mutually
// m_build, m_preprocOnly, m_dpiHdrOnly, m_lintOnly, and m_jsonOnly are mutually
// exclusive
std::vector<std::string> backendFlags;
if (m_build) {
@ -967,7 +967,6 @@ void V3Options::notify() VL_MT_DISABLED {
if (m_preprocOnly) backendFlags.push_back("-E");
if (m_dpiHdrOnly) backendFlags.push_back("--dpi-hdr-only");
if (m_lintOnly) backendFlags.push_back("--lint-only");
if (m_xmlOnly) backendFlags.push_back("--xml-only");
if (m_jsonOnly) backendFlags.push_back("--json-only");
if (backendFlags.size() > 1) {
std::string backendFlagsString = backendFlags.front();
@ -1039,8 +1038,7 @@ void V3Options::notify() VL_MT_DISABLED {
&& !v3Global.opt.serializeOnly());
}
if (m_timing.isDefault()
&& (v3Global.opt.jsonOnly() || v3Global.opt.lintOnly() || v3Global.opt.xmlOnly()))
if (m_timing.isDefault() && (v3Global.opt.jsonOnly() || v3Global.opt.lintOnly()))
v3Global.opt.m_timing.setTrueOrFalse(true);
if (trace()) {
@ -1944,17 +1942,6 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc,
}
});
DECL_OPTION("-x-initial-edge", OnOff, &m_xInitialEdge);
DECL_OPTION("-xml-only", CbOnOff, [this, fl](bool flag) {
if (!m_xmlOnly && flag)
fl->v3warn(DEPRECATED, "Option --xml-only is deprecated, move to --json-only");
m_xmlOnly = flag;
});
DECL_OPTION("-xml-output", CbVal, [this, fl](const char* valp) {
if (!m_xmlOnly)
fl->v3warn(DEPRECATED, "Option --xml-only is deprecated, move to --json-only");
m_xmlOutput = valp;
m_xmlOnly = true;
});
DECL_OPTION("-y", CbVal, [this, &optdir](const char* valp) {
addIncDirUser(parseFileArg(optdir, string{valp}));

6
src/V3Options.h
View File

@ -310,7 +310,6 @@ private:
bool m_vpi = false; // main switch: --vpi
bool m_waiverMultiline = false; // main switch: --waiver-multiline
bool m_xInitialEdge = false; // main switch: --x-initial-edge
bool m_xmlOnly = false; // main switch: --xml-only
int m_buildJobs = -1; // main switch: --build-jobs, -j
int m_coverageExprMax = 32; // main switch: --coverage-expr-max
@ -380,7 +379,6 @@ private:
string m_work = "work"; // main switch: --work {libname}
string m_xAssign; // main switch: --x-assign
string m_xInitial; // main switch: --x-initial
string m_xmlOutput; // main switch: --xml-output
// Language is now held in FileLine, on a per-node basis. However we still
// have a concept of the default language at a global level.
@ -589,8 +587,7 @@ public:
bool vpi() const { return m_vpi; }
bool waiverMultiline() const { return m_waiverMultiline; }
bool xInitialEdge() const { return m_xInitialEdge; }
bool xmlOnly() const { return m_xmlOnly; }
bool serializeOnly() const { return m_xmlOnly || m_jsonOnly; }
bool serializeOnly() const { return m_jsonOnly; }
bool topIfacesSupported() const { return lintOnly() && !hierarchical(); }
int buildJobs() const VL_MT_SAFE { return m_buildJobs; }
@ -681,7 +678,6 @@ public:
bool isWaiverOutput() const { return !m_waiverOutput.empty(); }
string xAssign() const { return m_xAssign; }
string xInitial() const { return m_xInitial; }
string xmlOutput() const { return m_xmlOutput; }
const VStringSet& cppFiles() const { return m_cppFiles; }
const VStringList& cFlags() const { return m_cFlags; }

5
src/Verilator.cpp
View File

@ -51,7 +51,6 @@
#include "V3EmitMk.h"
#include "V3EmitMkJson.h"
#include "V3EmitV.h"
#include "V3EmitXml.h"
#include "V3ExecGraph.h"
#include "V3Expand.h"
#include "V3File.h"
@ -139,7 +138,6 @@ static void emitJson() VL_MT_DISABLED {
}
static void emitSerialized() VL_MT_DISABLED {
if (v3Global.opt.xmlOnly()) V3EmitXml::emitxml();
if (v3Global.opt.jsonOnly()) emitJson();
}
@ -637,8 +635,7 @@ static void process() {
emitSerialized();
} else if (v3Global.opt.debugCheck() && !v3Global.opt.lintOnly()
&& !v3Global.opt.dpiHdrOnly()) {
// Check XML/JSON when debugging to make sure no missing node types
V3EmitXml::emitxml();
// Check JSON when debugging to make sure no missing node types
emitJson();
}

71
test_regress/t/t_constraint_xml.out
View File

@ -1,71 +0,0 @@
<?xml version="1.0" ?>
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml>
<files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_constraint_xml.v" language="1800-2023"/>
</files>
<module_files>
<file id="d" filename="t/t_constraint_xml.v" language="1800-2023"/>
</module_files>
<cells>
<cell loc="d,67,8,67,9" name="t" submodname="t" hier="t"/>
</cells>
<netlist>
<module loc="d,67,8,67,9" name="t" origName="t" topModule="1">
<var loc="d,69,11,69,12" name="p" dtype_id="1" vartype="Packet" origName="p"/>
<initial loc="d,71,4,71,11">
<begin loc="d,71,12,71,17">
<display loc="d,73,7,73,13" displaytype="$write">
<sformatf loc="d,73,7,73,13" name="*-* All Finished *-*&#10;" dtype_id="2"/>
</display>
<finish loc="d,74,7,74,14"/>
</begin>
</initial>
</module>
<package loc="a,0,0,0,0" name="$unit" origName="__024unit">
<class loc="d,7,1,7,6" name="Packet" origName="Packet">
<var loc="d,8,13,8,19" name="header" dtype_id="3" vartype="int" origName="header"/>
<var loc="d,9,13,9,19" name="length" dtype_id="3" vartype="int" origName="length"/>
<var loc="d,10,13,10,22" name="sublength" dtype_id="3" vartype="int" origName="sublength"/>
<var loc="d,11,13,11,17" name="if_4" dtype_id="4" vartype="bit" origName="if_4"/>
<var loc="d,12,13,12,20" name="iff_5_6" dtype_id="4" vartype="bit" origName="iff_5_6"/>
<var loc="d,13,13,13,24" name="if_state_ok" dtype_id="4" vartype="bit" origName="if_state_ok"/>
<var loc="d,15,13,15,18" name="array" dtype_id="5" vartype="" origName="array"/>
<var loc="d,17,11,17,16" name="state" dtype_id="2" vartype="string" origName="state"/>
<func loc="d,61,17,61,30" name="strings_equal" dtype_id="4">
<var loc="d,61,17,61,30" name="strings_equal" dtype_id="4" dir="output" vartype="bit" origName="strings_equal"/>
<var loc="d,61,38,61,39" name="a" dtype_id="2" dir="input" vartype="string" origName="a"/>
<var loc="d,61,48,61,49" name="b" dtype_id="2" dir="input" vartype="string" origName="b"/>
<assign loc="d,62,7,62,13" dtype_id="4">
<eqn loc="d,62,16,62,18" dtype_id="6">
<varref loc="d,62,14,62,15" name="a" dtype_id="2"/>
<varref loc="d,62,19,62,20" name="b" dtype_id="2"/>
</eqn>
<varref loc="d,62,7,62,13" name="strings_equal" dtype_id="4"/>
</assign>
</func>
<func loc="d,7,1,7,6" name="new" dtype_id="7"/>
<var loc="d,7,1,7,6" name="constraint" dtype_id="8" vartype="VlRandomizer" origName="constraint"/>
</class>
</package>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,22,14,22,15" id="6" name="logic"/>
<basicdtype loc="d,25,21,25,22" id="9" name="logic" left="31" right="0"/>
<basicdtype loc="d,73,7,73,13" id="2" name="string"/>
<basicdtype loc="d,8,9,8,12" id="3" name="int" left="31" right="0" signed="true"/>
<basicdtype loc="d,11,9,11,12" id="4" name="bit"/>
<unpackarraydtype loc="d,15,18,15,19" id="5" sub_dtype_id="3">
<range loc="d,15,18,15,19">
<const loc="d,15,19,15,20" name="32&apos;h0" dtype_id="9"/>
<const loc="d,15,19,15,20" name="32&apos;h1" dtype_id="9"/>
</range>
</unpackarraydtype>
<voiddtype loc="d,7,1,7,6" id="7"/>
<classrefdtype loc="d,69,4,69,10" id="1" name="Packet"/>
<basicdtype loc="d,7,1,7,6" id="8" name="VlRandomizer"/>
</typetable>
</netlist>
</verilator_xml>

23
test_regress/t/t_constraint_xml.py
View File

@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
out_filename = test.obj_dir + "/V" + test.name + ".xml"
test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '-Wno-CONSTRAINTIGN'],
verilator_make_gmake=False,
make_top_shell=False,
make_main=False)
test.files_identical(out_filename, test.golden_filename)
test.passes()

76
test_regress/t/t_constraint_xml.v
View File

@ -1,76 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
class Packet;
rand int header; // 0..7
rand int length; // 0..15
rand int sublength; // 0..15
rand bit if_4;
rand bit iff_5_6;
rand bit if_state_ok;
rand int array[2]; // 2,4,6
string state;
constraint empty {}
constraint size {
header > 0 && header <= 7;
length <= 15;
length >= header;
length dist { [0:1], [2:5] :/ 2, 6 := 6, 7 := 10, 1};
}
constraint ifs {
if (header > 4) {
if_4 == '1;
}
if (header == 5 || header == 6) {
iff_5_6 == '1;
iff_5_6 == '1;
iff_5_6 == '1;
} else {
iff_5_6 == '0;
}
}
constraint arr_uniq {
foreach (array[i]) {
array[i] inside {2, 4, 6};
}
unique { array[0], array[1] };
}
constraint order { solve length before header; }
constraint dis {
soft sublength;
disable soft sublength;
sublength <= length;
}
constraint meth {
if (strings_equal(state, "ok"))
if_state_ok == '1;
}
function bit strings_equal(string a, string b);
return a == b;
endfunction
endclass
module t;
Packet p;
initial begin
// Not testing use of constraints
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

2
test_regress/t/t_dist_docs_options.py
View File

@ -20,6 +20,8 @@ Doc_Waivers = [
'-order-clock-delay', # Deprecated
'-pp-comments', # Deprecated
'-prof-threads', # Deprecated
'-xml-only', # Removed
'-xml-output', # Removed
]
Test_Waivers = [

2
test_regress/t/t_flag_noop_bad.out
View File

@ -1,2 +1,2 @@
%Error: verilator: Need --binary, --cc, --sc, --dpi-hdr-only, --lint-only, --xml-only, --json-only or --E option
%Error: verilator: Need --binary, --cc, --sc, --dpi-hdr-only, --lint-only, --json-only or --E option
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.

2
test_regress/t/t_flag_only_bad.out
View File

@ -1,3 +1,3 @@
%Error: The following cannot be used together: --binary, -E, --dpi-hdr-only, --lint-only, --xml-only, --json-only. Suggest see manual
%Error: The following cannot be used together: --binary, -E, --dpi-hdr-only, --lint-only, --json-only. Suggest see manual
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

2
test_regress/t/t_flag_only_bad.py
View File

@ -13,7 +13,7 @@ test.scenarios('vlt')
test.top_filename = "t/t_flag_main.v"
test.lint(
verilator_flags2=["-Wno-DEPRECATED --binary -E --dpi-hdr-only --xml-only --json-only -Wall"],
verilator_flags2=["-Wno-DEPRECATED --binary -E --dpi-hdr-only --lint-only --json-only -Wall"],
fails=True,
expect_filename=test.golden_filename)

2
test_regress/t/t_flag_only_bad2.out
View File

@ -1,3 +1,3 @@
%Error: The following cannot be used together: --build, -E, --dpi-hdr-only, --lint-only, --xml-only, --json-only. Suggest see manual
%Error: The following cannot be used together: --build, -E, --dpi-hdr-only, --lint-only, --json-only. Suggest see manual
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

2
test_regress/t/t_flag_only_bad2.py
View File

@ -13,7 +13,7 @@ test.scenarios('vlt')
test.top_filename = "t/t_flag_main.v"
test.lint(verilator_flags2=[
"-Wno-DEPRECATED --build -E -Wno-fatal --dpi-hdr-only --xml-only --json-only"
"-Wno-DEPRECATED --build -E -Wno-fatal --dpi-hdr-only --lint-only --json-only"
],
fails=True,
expect_filename=test.golden_filename)

2
test_regress/t/t_flag_only_bad3.out
View File

@ -1,3 +1,3 @@
%Error: The following cannot be used together: --dpi-hdr-only, --lint-only, --xml-only, --json-only. Suggest see manual
%Error: The following cannot be used together: --dpi-hdr-only, --lint-only, --json-only. Suggest see manual
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

2
test_regress/t/t_flag_only_bad3.py
View File

@ -13,7 +13,7 @@ test.scenarios('vlt')
test.top_filename = "t/t_flag_main.v"
test.lint(
verilator_flags2=["-Wall -Wno-DEPRECATED -Wno-fatal --dpi-hdr-only --xml-only --json-only"],
verilator_flags2=["-Wall -Wno-DEPRECATED -Wno-fatal --dpi-hdr-only --lint-only --json-only"],
fails=True,
expect_filename=test.golden_filename)

129
test_regress/t/t_var_port_xml.out
View File

@ -1,129 +0,0 @@
<?xml version="1.0" ?>
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml>
<files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_var_port_xml.v" language="1800-2023"/>
</files>
<module_files>
<file id="d" filename="t/t_var_port_xml.v" language="1800-2023"/>
</module_files>
<cells>
<cell loc="d,18,8,18,11" name="mh2" submodname="mh2" hier="mh2"/>
</cells>
<cells>
<cell loc="d,24,8,24,11" name="mh5" submodname="mh5" hier="mh5"/>
</cells>
<cells>
<cell loc="d,26,8,26,11" name="mh6" submodname="mh6" hier="mh6"/>
</cells>
<cells>
<cell loc="d,28,8,28,11" name="mh7" submodname="mh7" hier="mh7"/>
</cells>
<cells>
<cell loc="d,30,8,30,11" name="mh8" submodname="mh8" hier="mh8"/>
</cells>
<cells>
<cell loc="d,32,8,32,11" name="mh9" submodname="mh9" hier="mh9"/>
</cells>
<cells>
<cell loc="d,34,8,34,12" name="mh10" submodname="mh10" hier="mh10"/>
</cells>
<cells>
<cell loc="d,36,8,36,12" name="mh11" submodname="mh11" hier="mh11"/>
</cells>
<cells>
<cell loc="d,38,8,38,12" name="mh12" submodname="mh12" hier="mh12"/>
</cells>
<cells>
<cell loc="d,40,8,40,12" name="mh13" submodname="mh13" hier="mh13"/>
</cells>
<cells>
<cell loc="d,50,8,50,12" name="mh17" submodname="mh17" hier="mh17"/>
</cells>
<cells>
<cell loc="d,52,8,52,12" name="mh18" submodname="mh18" hier="mh18"/>
</cells>
<cells>
<cell loc="d,54,8,54,12" name="mh19" submodname="mh19" hier="mh19"/>
</cells>
<cells>
<cell loc="d,56,8,56,12" name="mh20" submodname="mh20" hier="mh20"/>
</cells>
<cells>
<cell loc="d,58,8,58,12" name="mh21" submodname="mh21" hier="mh21"/>
</cells>
<netlist>
<module loc="d,18,8,18,11" name="mh2" origName="mh2" topModule="1">
<var loc="d,18,27,18,47" name="x_inout_wire_integer" dtype_id="1" dir="inout" pinIndex="1" vartype="integer" origName="x_inout_wire_integer" public="true"/>
</module>
<module loc="d,24,8,24,11" name="mh5" origName="mh5" topModule="1">
<var loc="d,24,19,24,37" name="x_input_wire_logic" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="x_input_wire_logic" public="true"/>
</module>
<module loc="d,26,8,26,11" name="mh6" origName="mh6" topModule="1">
<var loc="d,26,23,26,40" name="x_input_var_logic" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="x_input_var_logic" public="true"/>
</module>
<module loc="d,28,8,28,11" name="mh7" origName="mh7" topModule="1">
<var loc="d,28,31,28,50" name="x_input_var_integer" dtype_id="1" dir="input" pinIndex="1" vartype="integer" origName="x_input_var_integer" public="true"/>
</module>
<module loc="d,30,8,30,11" name="mh8" origName="mh8" topModule="1">
<var loc="d,30,20,30,39" name="x_output_wire_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic" public="true"/>
</module>
<module loc="d,32,8,32,11" name="mh9" origName="mh9" topModule="1">
<var loc="d,32,24,32,42" name="x_output_var_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_var_logic" public="true"/>
</module>
<module loc="d,34,8,34,12" name="mh10" origName="mh10" topModule="1">
<var loc="d,34,33,34,62" name="x_output_wire_logic_signed_p6" dtype_id="3" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic_signed_p6" public="true"/>
</module>
<module loc="d,36,8,36,12" name="mh11" origName="mh11" topModule="1">
<var loc="d,36,28,36,48" name="x_output_var_integer" dtype_id="1" dir="output" pinIndex="1" vartype="integer" origName="x_output_var_integer" public="true"/>
</module>
<module loc="d,38,8,38,12" name="mh12" origName="mh12" topModule="1">
<var loc="d,38,23,38,37" name="x_ref_logic_p6" dtype_id="4" dir="ref" pinIndex="1" vartype="logic" origName="x_ref_logic_p6" public="true"/>
</module>
<module loc="d,40,8,40,12" name="mh13" origName="mh13" topModule="1">
<var loc="d,40,17,40,35" name="x_ref_var_logic_u6" dtype_id="5" dir="ref" pinIndex="1" vartype="port" origName="x_ref_var_logic_u6" public="true"/>
</module>
<module loc="d,50,8,50,12" name="mh17" origName="mh17" topModule="1">
<var loc="d,50,31,50,50" name="x_input_var_integer" dtype_id="1" dir="input" pinIndex="1" vartype="integer" origName="x_input_var_integer" public="true"/>
<var loc="d,50,57,50,75" name="y_input_wire_logic" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="y_input_wire_logic" public="true"/>
</module>
<module loc="d,52,8,52,12" name="mh18" origName="mh18" topModule="1">
<var loc="d,52,24,52,42" name="x_output_var_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_var_logic" public="true"/>
<var loc="d,52,50,52,68" name="y_input_wire_logic" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="y_input_wire_logic" public="true"/>
</module>
<module loc="d,54,8,54,12" name="mh19" origName="mh19" topModule="1">
<var loc="d,54,33,54,62" name="x_output_wire_logic_signed_p6" dtype_id="3" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic_signed_p6" public="true"/>
<var loc="d,54,72,54,92" name="y_output_var_integer" dtype_id="1" dir="output" pinIndex="2" vartype="integer" origName="y_output_var_integer" public="true"/>
</module>
<module loc="d,56,8,56,12" name="mh20" origName="mh20" topModule="1">
<var loc="d,56,23,56,41" name="x_ref_var_logic_p6" dtype_id="4" dir="ref" pinIndex="1" vartype="logic" origName="x_ref_var_logic_p6" public="true"/>
<var loc="d,56,43,56,61" name="y_ref_var_logic_p6" dtype_id="4" dir="ref" pinIndex="2" vartype="logic" origName="y_ref_var_logic_p6" public="true"/>
</module>
<module loc="d,58,8,58,12" name="mh21" origName="mh21" topModule="1">
<var loc="d,58,17,58,33" name="ref_var_logic_u6" dtype_id="6" dir="ref" pinIndex="1" vartype="port" origName="ref_var_logic_u6" public="true"/>
<var loc="d,58,41,58,56" name="y_ref_var_logic" dtype_id="2" dir="ref" pinIndex="2" vartype="logic" origName="y_ref_var_logic" public="true"/>
</module>
<typetable loc="a,0,0,0,0">
<unpackarraydtype loc="d,58,34,58,35" id="6" sub_dtype_id="2">
<range loc="d,58,34,58,35">
<const loc="d,58,35,58,36" name="32&apos;sh5" dtype_id="7"/>
<const loc="d,58,37,58,38" name="32&apos;sh0" dtype_id="7"/>
</range>
</unpackarraydtype>
<basicdtype loc="d,58,41,58,56" id="2" name="logic"/>
<unpackarraydtype loc="d,40,36,40,37" id="5" sub_dtype_id="2">
<range loc="d,40,36,40,37">
<const loc="d,40,37,40,38" name="32&apos;sh5" dtype_id="7"/>
<const loc="d,40,39,40,40" name="32&apos;sh0" dtype_id="7"/>
</range>
</unpackarraydtype>
<basicdtype loc="d,38,17,38,18" id="4" name="logic" left="5" right="0"/>
<basicdtype loc="d,34,27,34,28" id="3" name="logic" left="5" right="0" signed="true"/>
<basicdtype loc="d,18,19,18,26" id="1" name="integer" left="31" right="0" signed="true"/>
<basicdtype loc="d,40,37,40,38" id="7" name="logic" left="31" right="0" signed="true"/>
</typetable>
</netlist>
</verilator_xml>

23
test_regress/t/t_var_port_xml.py
View File

@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
out_filename = test.obj_dir + "/V" + test.name + ".xml"
test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--bbox-unsup'],
verilator_make_gmake=False,
make_top_shell=False,
make_main=False)
test.files_identical(out_filename, test.golden_filename)
test.passes()

59
test_regress/t/t_var_port_xml.v
View File

@ -1,59 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// This checks IEEE ports work correctly, we use XML output to make it easy to
// see all attributes are propagated
// verilator lint_off MULTITOP
`ifndef VERILATOR
module mh0 (wire x_inout_wire_logic);
endmodule
module mh1 (integer x_inout_wire_integer);
endmodule
`endif
module mh2 (inout integer x_inout_wire_integer);
endmodule
`ifndef VERILATOR
module mh3 ([5:0] x_inout_wire_logic_p6);
endmodule
`endif
module mh5 (input x_input_wire_logic);
endmodule
module mh6 (input var x_input_var_logic);
endmodule
module mh7 (input var integer x_input_var_integer);
endmodule
module mh8 (output x_output_wire_logic);
endmodule
module mh9 (output var x_output_var_logic);
endmodule
module mh10(output signed [5:0] x_output_wire_logic_signed_p6);
endmodule
module mh11(output integer x_output_var_integer);
endmodule
module mh12(ref [5:0] x_ref_logic_p6);
endmodule
module mh13(ref x_ref_var_logic_u6 [5:0]);
endmodule
`ifndef VERILATOR
module mh14(wire x_inout_wire_logic, y_inout_wire_logic_p8 [7:0]);
endmodule
module mh15(integer x_inout_wire_integer, signed [5:0] y_inout_wire_logic_signed6);
endmodule
module mh16([5:0] x_inout_wire_logic_p6, wire y_inout_wire_logic);
endmodule
`endif
module mh17(input var integer x_input_var_integer, wire y_input_wire_logic);
endmodule
module mh18(output var x_output_var_logic, input y_input_wire_logic);
endmodule
module mh19(output signed [5:0] x_output_wire_logic_signed_p6, integer y_output_var_integer);
endmodule
module mh20(ref [5:0] x_ref_var_logic_p6, y_ref_var_logic_p6);
endmodule
module mh21(ref ref_var_logic_u6 [5:0], y_ref_var_logic);
endmodule

82
test_regress/t/t_xml_begin_hier.out
View File

@ -1,82 +0,0 @@
<?xml version="1.0" ?>
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml>
<files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_begin_hier.v" language="1800-2023"/>
</files>
<module_files>
<file id="d" filename="t/t_xml_begin_hier.v" language="1800-2023"/>
</module_files>
<cells>
<cell loc="d,22,8,22,12" name="test" submodname="test" hier="test">
<cell loc="d,27,21,27,31" name="submod_for" submodname="submod" hier="test.FOR_GENERATE__BRA__0__KET__.submod_for">
<cell loc="d,15,21,15,34" name="submod_nested" submodname="submod2" hier="test.FOR_GENERATE__BRA__0__KET__.submod_for.submod_gen.nested_gen.submod_nested"/>
<cell loc="d,17,17,17,26" name="submod_l1" submodname="submod2" hier="test.FOR_GENERATE__BRA__0__KET__.submod_for.submod_gen.submod_l1"/>
<cell loc="d,19,13,19,22" name="submod_l0" submodname="submod2" hier="test.FOR_GENERATE__BRA__0__KET__.submod_for.submod_l0"/>
</cell>
<cell loc="d,29,25,29,33" name="submod_2" submodname="submod" hier="test.FOR_GENERATE__BRA__0__KET__.genblk1.submod_2">
<cell loc="d,15,21,15,34" name="submod_nested" submodname="submod2" hier="test.FOR_GENERATE__BRA__0__KET__.genblk1.submod_2.submod_gen.nested_gen.submod_nested"/>
<cell loc="d,17,17,17,26" name="submod_l1" submodname="submod2" hier="test.FOR_GENERATE__BRA__0__KET__.genblk1.submod_2.submod_gen.submod_l1"/>
<cell loc="d,19,13,19,22" name="submod_l0" submodname="submod2" hier="test.FOR_GENERATE__BRA__0__KET__.genblk1.submod_2.submod_l0"/>
</cell>
<cell loc="d,31,21,31,29" name="submod_3" submodname="submod" hier="test.FOR_GENERATE__BRA__0__KET__.submod_3">
<cell loc="d,15,21,15,34" name="submod_nested" submodname="submod2" hier="test.FOR_GENERATE__BRA__0__KET__.submod_3.submod_gen.nested_gen.submod_nested"/>
<cell loc="d,17,17,17,26" name="submod_l1" submodname="submod2" hier="test.FOR_GENERATE__BRA__0__KET__.submod_3.submod_gen.submod_l1"/>
<cell loc="d,19,13,19,22" name="submod_l0" submodname="submod2" hier="test.FOR_GENERATE__BRA__0__KET__.submod_3.submod_l0"/>
</cell>
<cell loc="d,27,21,27,31" name="submod_for" submodname="submod" hier="test.FOR_GENERATE__BRA__1__KET__.submod_for">
<cell loc="d,15,21,15,34" name="submod_nested" submodname="submod2" hier="test.FOR_GENERATE__BRA__1__KET__.submod_for.submod_gen.nested_gen.submod_nested"/>
<cell loc="d,17,17,17,26" name="submod_l1" submodname="submod2" hier="test.FOR_GENERATE__BRA__1__KET__.submod_for.submod_gen.submod_l1"/>
<cell loc="d,19,13,19,22" name="submod_l0" submodname="submod2" hier="test.FOR_GENERATE__BRA__1__KET__.submod_for.submod_l0"/>
</cell>
<cell loc="d,29,25,29,33" name="submod_2" submodname="submod" hier="test.FOR_GENERATE__BRA__1__KET__.genblk1.submod_2">
<cell loc="d,15,21,15,34" name="submod_nested" submodname="submod2" hier="test.FOR_GENERATE__BRA__1__KET__.genblk1.submod_2.submod_gen.nested_gen.submod_nested"/>
<cell loc="d,17,17,17,26" name="submod_l1" submodname="submod2" hier="test.FOR_GENERATE__BRA__1__KET__.genblk1.submod_2.submod_gen.submod_l1"/>
<cell loc="d,19,13,19,22" name="submod_l0" submodname="submod2" hier="test.FOR_GENERATE__BRA__1__KET__.genblk1.submod_2.submod_l0"/>
</cell>
<cell loc="d,31,21,31,29" name="submod_3" submodname="submod" hier="test.FOR_GENERATE__BRA__1__KET__.submod_3">
<cell loc="d,15,21,15,34" name="submod_nested" submodname="submod2" hier="test.FOR_GENERATE__BRA__1__KET__.submod_3.submod_gen.nested_gen.submod_nested"/>
<cell loc="d,17,17,17,26" name="submod_l1" submodname="submod2" hier="test.FOR_GENERATE__BRA__1__KET__.submod_3.submod_gen.submod_l1"/>
<cell loc="d,19,13,19,22" name="submod_l0" submodname="submod2" hier="test.FOR_GENERATE__BRA__1__KET__.submod_3.submod_l0"/>
</cell>
</cell>
</cells>
<netlist>
<module loc="d,22,8,22,12" name="test" origName="test" topModule="1">
<var loc="d,24,12,24,13" name="N" dtype_id="1" vartype="integer" origName="N"/>
<genblock loc="d,25,14,25,17" name="FOR_GENERATE"/>
<genblock loc="d,27,21,27,31" name="FOR_GENERATE[0]">
<instance loc="d,27,21,27,31" name="submod_for" defName="submod" origName="submod_for"/>
<genblock loc="d,28,19,28,24" name="genblk1">
<instance loc="d,29,25,29,33" name="submod_2" defName="submod" origName="submod_2"/>
</genblock>
<instance loc="d,31,21,31,29" name="submod_3" defName="submod" origName="submod_3"/>
</genblock>
<genblock loc="d,27,21,27,31" name="FOR_GENERATE[1]">
<instance loc="d,27,21,27,31" name="submod_for" defName="submod" origName="submod_for"/>
<genblock loc="d,28,19,28,24" name="genblk1">
<instance loc="d,29,25,29,33" name="submod_2" defName="submod" origName="submod_2"/>
</genblock>
<instance loc="d,31,21,31,29" name="submod_3" defName="submod" origName="submod_3"/>
</genblock>
</module>
<module loc="d,10,8,10,14" name="submod" origName="submod">
<genblock loc="d,12,19,12,29" name="submod_gen">
<var loc="d,13,14,13,20" name="l1_sig" dtype_id="2" vartype="logic" origName="l1_sig"/>
<genblock loc="d,14,23,14,33" name="nested_gen">
<instance loc="d,15,21,15,34" name="submod_nested" defName="submod2" origName="submod_nested"/>
</genblock>
<instance loc="d,17,17,17,26" name="submod_l1" defName="submod2" origName="submod_l1"/>
</genblock>
<instance loc="d,19,13,19,22" name="submod_l0" defName="submod2" origName="submod_l0"/>
</module>
<module loc="d,7,8,7,15" name="submod2" origName="submod2"/>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,24,12,24,13" id="1" name="integer" left="31" right="0" signed="true"/>
<basicdtype loc="d,13,14,13,20" id="2" name="logic"/>
</typetable>
</netlist>
</verilator_xml>

23
test_regress/t/t_xml_begin_hier.py
View File

@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
out_filename = test.obj_dir + "/V" + test.name + ".xml"
test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'],
verilator_make_gmake=False,
make_top_shell=False,
make_main=False)
test.files_identical(out_filename, test.golden_filename)
test.passes()

33
test_regress/t/t_xml_begin_hier.v
View File

@ -1,33 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Risto Pejasinovic.
// SPDX-License-Identifier: CC0-1.0
module submod2 ();
endmodule
module submod #(
)();
if(1) begin : submod_gen
wire l1_sig;
if(1) begin : nested_gen
submod2 submod_nested();
end
submod2 submod_l1();
end
submod2 submod_l0();
endmodule
module test(
);
genvar N;
generate for(N=0; N<2; N=N+1)
begin : FOR_GENERATE
submod submod_for();
if(1) begin
submod submod_2();
end
submod submod_3();
end endgenerate
endmodule

1854
test_regress/t/t_xml_debugcheck.out
View File

File diff suppressed because it is too large Load Diff

34
test_regress/t/t_xml_debugcheck.py
View File

@ -1,34 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_enum_type_methods.v"
out_filename = test.obj_dir + "/V" + test.name + ".xml"
test.compile(verilator_flags2=['--no-std', '--debug-check', '--flatten', '--inline-cfuncs', '0'],
verilator_make_gmake=False,
make_top_shell=False,
make_main=False)
test.files_identical(out_filename, test.golden_filename, 'logfile')
# make sure that certain tags are present in --debug-check
# that would not be present in --xml-only
test.file_grep(out_filename, r'<constpool')
test.file_grep(out_filename, r'<inititem')
test.file_grep(out_filename, r'<if')
test.file_grep(out_filename, r'<loop')
test.file_grep(out_filename, r'<begin>') # for <if> and <loop>
test.file_grep(out_filename, r' signed=') # for <basicdtype>
test.file_grep(out_filename, r' func=') # for <ccall>
test.passes()

4
test_regress/t/t_xml_deprecated_bad.out
View File

@ -1,4 +0,0 @@
%Warning-DEPRECATED: Option --xml-only is deprecated, move to --json-only
... For warning description see https://verilator.org/warn/DEPRECATED?v=latest
... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message.
%Error: Exiting due to

19
test_regress/t/t_xml_deprecated_bad.py
View File

@ -1,19 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = 't/t_EXAMPLE.v'
test.compile(verilator_flags2=["--xml-only --xml-output /dev/null"],
fails=True,
expect_filename=test.golden_filename)
test.passes()

88
test_regress/t/t_xml_first.out
View File

@ -1,88 +0,0 @@
<?xml version="1.0" ?>
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml>
<files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_first.v" language="1800-2023"/>
</files>
<module_files>
<file id="d" filename="t/t_xml_first.v" language="1800-2023"/>
</module_files>
<cells>
<cell loc="d,7,8,7,9" name="t" submodname="t" hier="t">
<cell loc="d,20,4,20,9" name="cell1" submodname="mod1__W4" hier="t.cell1"/>
<cell loc="d,25,6,25,11" name="cell2" submodname="mod2" hier="t.cell2"/>
</cell>
</cells>
<netlist>
<module loc="d,7,8,7,9" name="t" origName="t" topModule="1">
<var loc="d,15,22,15,23" name="q" dtype_id="1" dir="output" pinIndex="1" vartype="logic" origName="q" public="true"/>
<var loc="d,13,10,13,13" name="clk" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="clk" public="true"/>
<var loc="d,14,16,14,17" name="d" dtype_id="1" dir="input" pinIndex="3" vartype="logic" origName="d" public="true"/>
<var loc="d,17,22,17,29" name="between" dtype_id="1" vartype="logic" origName="between"/>
<instance loc="d,20,4,20,9" name="cell1" defName="mod1__W4" origName="cell1">
<port loc="d,20,12,20,13" name="q" direction="out" portIndex="1">
<varref loc="d,20,14,20,21" name="between" dtype_id="1"/>
</port>
<port loc="d,21,12,21,15" name="clk" direction="in" portIndex="2">
<varref loc="d,21,42,21,45" name="clk" dtype_id="2"/>
</port>
<port loc="d,22,12,22,13" name="d" direction="in" portIndex="3">
<varref loc="d,22,42,22,43" name="d" dtype_id="1"/>
</port>
</instance>
<instance loc="d,25,6,25,11" name="cell2" defName="mod2" origName="cell2">
<port loc="d,25,14,25,15" name="d" direction="in" portIndex="1">
<varref loc="d,25,16,25,23" name="between" dtype_id="1"/>
</port>
<port loc="d,26,14,26,15" name="q" direction="out" portIndex="2">
<varref loc="d,26,42,26,43" name="q" dtype_id="1"/>
</port>
<port loc="d,27,14,27,17" name="clk" direction="in" portIndex="3">
<varref loc="d,27,42,27,45" name="clk" dtype_id="2"/>
</port>
</instance>
</module>
<module loc="d,46,8,46,12" name="mod2" origName="mod2">
<var loc="d,48,10,48,13" name="clk" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="clk"/>
<var loc="d,49,16,49,17" name="d" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="d"/>
<var loc="d,50,22,50,23" name="q" dtype_id="1" dir="output" pinIndex="3" vartype="logic" origName="q"/>
<always loc="d,53,13,53,14">
<contassign loc="d,53,13,53,14" dtype_id="1">
<varref loc="d,49,16,49,17" name="d" dtype_id="1"/>
<varref loc="d,53,13,53,14" name="q" dtype_id="1"/>
</contassign>
</always>
</module>
<module loc="d,31,8,31,12" name="mod1__W4" origName="mod1">
<var loc="d,32,15,32,20" name="WIDTH" dtype_id="3" vartype="logic" origName="WIDTH" param="true">
<const loc="d,19,18,19,19" name="32&apos;sh4" dtype_id="3"/>
</var>
<var loc="d,34,24,34,27" name="clk" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="clk"/>
<var loc="d,35,30,35,31" name="d" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="d"/>
<var loc="d,36,30,36,31" name="q" dtype_id="1" dir="output" pinIndex="3" vartype="logic" origName="q"/>
<var loc="d,39,15,39,22" name="IGNORED" dtype_id="3" vartype="logic" origName="IGNORED" localparam="true">
<const loc="d,39,25,39,26" name="32&apos;sh1" dtype_id="3"/>
</var>
<always loc="d,41,4,41,10">
<sentree loc="d,41,11,41,12">
<senitem loc="d,41,13,41,20" edgeType="POS">
<varref loc="d,41,21,41,24" name="clk" dtype_id="2"/>
</senitem>
</sentree>
<assigndly loc="d,42,8,42,10" dtype_id="1">
<varref loc="d,42,11,42,12" name="d" dtype_id="1"/>
<varref loc="d,42,6,42,7" name="q" dtype_id="1"/>
</assigndly>
</always>
</module>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,34,24,34,27" id="2" name="logic"/>
<basicdtype loc="d,15,16,15,17" id="1" name="logic" left="3" right="0"/>
<basicdtype loc="d,19,18,19,19" id="3" name="logic" left="31" right="0" signed="true"/>
<voiddtype loc="a,0,0,0,0" id="4"/>
</typetable>
</netlist>
</verilator_xml>

23
test_regress/t/t_xml_first.py
View File

@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
out_filename = test.obj_dir + "/V" + test.name + ".xml"
test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'],
verilator_make_gmake=False,
make_top_shell=False,
make_main=False)
test.files_identical(out_filename, test.golden_filename)
test.passes()

55
test_regress/t/t_xml_first.v
View File

@ -1,55 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
q,
// Inputs
clk, d
);
input clk;
input [3:0] d;
output wire [3:0] q;
logic [3:0] between;
mod1 #(.WIDTH(4))
cell1 (.q(between),
.clk (clk),
.d (d[3:0]));
mod2
cell2 (.d(between),
.q (q[3:0]),
.clk (clk));
endmodule
module mod1
#(parameter WIDTH = 32)
(
input clk,
input [WIDTH-1:0] d,
output logic [WIDTH-1:0] q
);
localparam IGNORED = 1;
always @(posedge clk)
q <= d;
endmodule
module mod2
(
input clk,
input [3:0] d,
output wire [3:0] q
);
assign q = d;
endmodule

135
test_regress/t/t_xml_flat.out
View File

@ -1,135 +0,0 @@
<?xml version="1.0" ?>
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml>
<files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_first.v" language="1800-2023"/>
</files>
<module_files>
<file id="d" filename="t/t_xml_first.v" language="1800-2023"/>
</module_files>
<cells>
<cell loc="d,7,8,7,9" name="$root" submodname="$root" hier="$root"/>
</cells>
<netlist>
<module loc="d,7,8,7,9" name="$root" origName="$root" topModule="1" public="true">
<var loc="d,15,22,15,23" name="q" dtype_id="1" dir="output" pinIndex="1" vartype="logic" origName="q" public="true"/>
<var loc="d,13,10,13,13" name="clk" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="clk" public="true"/>
<var loc="d,14,16,14,17" name="d" dtype_id="1" dir="input" pinIndex="3" vartype="logic" origName="d" public="true"/>
<var loc="d,15,22,15,23" name="t.q" dtype_id="1" vartype="logic" origName="q"/>
<var loc="d,13,10,13,13" name="t.clk" dtype_id="2" vartype="logic" origName="clk"/>
<var loc="d,14,16,14,17" name="t.d" dtype_id="1" vartype="logic" origName="d"/>
<var loc="d,17,22,17,29" name="t.between" dtype_id="1" vartype="logic" origName="between"/>
<var loc="d,32,15,32,20" name="t.cell1.WIDTH" dtype_id="3" vartype="logic" origName="WIDTH" param="true">
<const loc="d,19,18,19,19" name="32&apos;sh4" dtype_id="3"/>
</var>
<var loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="2" vartype="logic" origName="clk"/>
<var loc="d,35,30,35,31" name="t.cell1.d" dtype_id="1" vartype="logic" origName="d"/>
<var loc="d,36,30,36,31" name="t.cell1.q" dtype_id="1" vartype="logic" origName="q"/>
<var loc="d,39,15,39,22" name="t.cell1.IGNORED" dtype_id="3" vartype="logic" origName="IGNORED" localparam="true">
<const loc="d,39,25,39,26" name="32&apos;sh1" dtype_id="3"/>
</var>
<var loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="2" vartype="logic" origName="clk"/>
<var loc="d,49,16,49,17" name="t.cell2.d" dtype_id="1" vartype="logic" origName="d"/>
<var loc="d,50,22,50,23" name="t.cell2.q" dtype_id="1" vartype="logic" origName="q"/>
<topscope loc="d,7,8,7,9">
<scope loc="d,7,8,7,9" name="TOP">
<varscope loc="d,15,22,15,23" name="q" dtype_id="1"/>
<varscope loc="d,13,10,13,13" name="clk" dtype_id="2"/>
<varscope loc="d,14,16,14,17" name="d" dtype_id="1"/>
<varscope loc="d,15,22,15,23" name="t.q" dtype_id="1"/>
<always loc="d,15,22,15,23">
<contassign loc="d,15,22,15,23" dtype_id="1">
<varref loc="d,15,22,15,23" name="q" dtype_id="1"/>
<varref loc="d,15,22,15,23" name="t.q" dtype_id="1"/>
</contassign>
</always>
<varscope loc="d,13,10,13,13" name="t.clk" dtype_id="2"/>
<always loc="d,13,10,13,13">
<contassign loc="d,13,10,13,13" dtype_id="2">
<varref loc="d,13,10,13,13" name="clk" dtype_id="2"/>
<varref loc="d,13,10,13,13" name="t.clk" dtype_id="2"/>
</contassign>
</always>
<varscope loc="d,14,16,14,17" name="t.d" dtype_id="1"/>
<always loc="d,14,16,14,17">
<contassign loc="d,14,16,14,17" dtype_id="1">
<varref loc="d,14,16,14,17" name="d" dtype_id="1"/>
<varref loc="d,14,16,14,17" name="t.d" dtype_id="1"/>
</contassign>
</always>
<varscope loc="d,17,22,17,29" name="t.between" dtype_id="1"/>
<varscope loc="d,32,15,32,20" name="t.cell1.WIDTH" dtype_id="3"/>
<varscope loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="2"/>
<always loc="d,34,24,34,27">
<contassign loc="d,34,24,34,27" dtype_id="2">
<varref loc="d,34,24,34,27" name="clk" dtype_id="2"/>
<varref loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="2"/>
</contassign>
</always>
<varscope loc="d,35,30,35,31" name="t.cell1.d" dtype_id="1"/>
<always loc="d,35,30,35,31">
<contassign loc="d,35,30,35,31" dtype_id="1">
<varref loc="d,35,30,35,31" name="d" dtype_id="1"/>
<varref loc="d,35,30,35,31" name="t.cell1.d" dtype_id="1"/>
</contassign>
</always>
<varscope loc="d,36,30,36,31" name="t.cell1.q" dtype_id="1"/>
<always loc="d,36,30,36,31">
<contassign loc="d,36,30,36,31" dtype_id="1">
<varref loc="d,36,30,36,31" name="t.between" dtype_id="1"/>
<varref loc="d,36,30,36,31" name="t.cell1.q" dtype_id="1"/>
</contassign>
</always>
<varscope loc="d,39,15,39,22" name="t.cell1.IGNORED" dtype_id="3"/>
<varscope loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="2"/>
<always loc="d,48,10,48,13">
<contassign loc="d,48,10,48,13" dtype_id="2">
<varref loc="d,48,10,48,13" name="clk" dtype_id="2"/>
<varref loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="2"/>
</contassign>
</always>
<varscope loc="d,49,16,49,17" name="t.cell2.d" dtype_id="1"/>
<always loc="d,49,16,49,17">
<contassign loc="d,49,16,49,17" dtype_id="1">
<varref loc="d,49,16,49,17" name="t.between" dtype_id="1"/>
<varref loc="d,49,16,49,17" name="t.cell2.d" dtype_id="1"/>
</contassign>
</always>
<varscope loc="d,50,22,50,23" name="t.cell2.q" dtype_id="1"/>
<always loc="d,50,22,50,23">
<contassign loc="d,50,22,50,23" dtype_id="1">
<varref loc="d,50,22,50,23" name="q" dtype_id="1"/>
<varref loc="d,50,22,50,23" name="t.cell2.q" dtype_id="1"/>
</contassign>
</always>
<always loc="d,41,4,41,10">
<sentree loc="d,41,11,41,12">
<senitem loc="d,41,13,41,20" edgeType="POS">
<varref loc="d,41,21,41,24" name="clk" dtype_id="2"/>
</senitem>
</sentree>
<assigndly loc="d,42,8,42,10" dtype_id="1">
<varref loc="d,42,11,42,12" name="d" dtype_id="1"/>
<varref loc="d,42,6,42,7" name="t.between" dtype_id="1"/>
</assigndly>
</always>
<always loc="d,53,13,53,14">
<contassign loc="d,53,13,53,14" dtype_id="1">
<varref loc="d,17,22,17,29" name="t.between" dtype_id="1"/>
<varref loc="d,53,13,53,14" name="q" dtype_id="1"/>
</contassign>
</always>
</scope>
</topscope>
</module>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,34,24,34,27" id="2" name="logic"/>
<basicdtype loc="d,15,16,15,17" id="1" name="logic" left="3" right="0"/>
<basicdtype loc="d,19,18,19,19" id="3" name="logic" left="31" right="0" signed="true"/>
<voiddtype loc="a,0,0,0,0" id="4"/>
</typetable>
</netlist>
</verilator_xml>

24
test_regress/t/t_xml_flat.py
View File

@ -1,24 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.top_filename = "t/t_xml_first.v"
out_filename = test.obj_dir + "/V" + test.name + ".xml"
test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--flatten'],
verilator_make_gmake=False,
make_top_shell=False,
make_main=False)
test.files_identical(out_filename, test.golden_filename)
test.passes()

45
test_regress/t/t_xml_flat_no_inline_mod.out
View File

@ -1,45 +0,0 @@
<?xml version="1.0" ?>
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml>
<files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_flat_no_inline_mod.v" language="1800-2023"/>
</files>
<module_files>
<file id="d" filename="t/t_xml_flat_no_inline_mod.v" language="1800-2023"/>
</module_files>
<cells>
<cell loc="d,11,8,11,11" name="$root" submodname="$root" hier="$root"/>
</cells>
<netlist>
<module loc="d,11,8,11,11" name="$root" origName="$root" topModule="1" public="true">
<var loc="d,11,24,11,29" name="i_clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="i_clk" public="true"/>
<var loc="d,11,24,11,29" name="top.i_clk" dtype_id="1" vartype="logic" origName="i_clk"/>
<var loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1" vartype="logic" origName="i_clk"/>
<topscope loc="d,11,8,11,11">
<scope loc="d,11,8,11,11" name="TOP">
<varscope loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<varscope loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
<always loc="d,11,24,11,29">
<contassign loc="d,11,24,11,29" dtype_id="1">
<varref loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<varref loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
</contassign>
</always>
<varscope loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
<always loc="d,7,24,7,29">
<contassign loc="d,7,24,7,29" dtype_id="1">
<varref loc="d,7,24,7,29" name="i_clk" dtype_id="1"/>
<varref loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
</contassign>
</always>
</scope>
</topscope>
</module>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,11,18,11,23" id="1" name="logic"/>
</typetable>
</netlist>
</verilator_xml>

23
test_regress/t/t_xml_flat_no_inline_mod.py
View File

@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
out_filename = test.obj_dir + "/V" + test.name + ".xml"
test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--flatten'],
verilator_make_gmake=False,
make_top_shell=False,
make_main=False)
test.files_identical(out_filename, test.golden_filename)
test.passes()

13
test_regress/t/t_xml_flat_no_inline_mod.v
View File

@ -1,13 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module foo(input logic i_clk); /* verilator no_inline_module */
endmodule
// --flatten forces inlining of 'no_inline_module' module foo.
module top(input logic i_clk);
foo f(.*);
endmodule

45
test_regress/t/t_xml_flat_pub_mod.out
View File

@ -1,45 +0,0 @@
<?xml version="1.0" ?>
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml>
<files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_flat_pub_mod.v" language="1800-2023"/>
</files>
<module_files>
<file id="d" filename="t/t_xml_flat_pub_mod.v" language="1800-2023"/>
</module_files>
<cells>
<cell loc="d,11,8,11,11" name="$root" submodname="$root" hier="$root"/>
</cells>
<netlist>
<module loc="d,11,8,11,11" name="$root" origName="$root" topModule="1" public="true">
<var loc="d,11,24,11,29" name="i_clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="i_clk" public="true"/>
<var loc="d,11,24,11,29" name="top.i_clk" dtype_id="1" vartype="logic" origName="i_clk"/>
<var loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1" vartype="logic" origName="i_clk"/>
<topscope loc="d,11,8,11,11">
<scope loc="d,11,8,11,11" name="TOP">
<varscope loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<varscope loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
<always loc="d,11,24,11,29">
<contassign loc="d,11,24,11,29" dtype_id="1">
<varref loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<varref loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
</contassign>
</always>
<varscope loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
<always loc="d,7,24,7,29">
<contassign loc="d,7,24,7,29" dtype_id="1">
<varref loc="d,7,24,7,29" name="i_clk" dtype_id="1"/>
<varref loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
</contassign>
</always>
</scope>
</topscope>
</module>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,11,18,11,23" id="1" name="logic"/>
</typetable>
</netlist>
</verilator_xml>

23
test_regress/t/t_xml_flat_pub_mod.py
View File

@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
out_filename = test.obj_dir + "/V" + test.name + ".xml"
test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--flatten'],
verilator_make_gmake=False,
make_top_shell=False,
make_main=False)
test.files_identical(out_filename, test.golden_filename)
test.passes()

13
test_regress/t/t_xml_flat_pub_mod.v
View File

@ -1,13 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module foo(input logic i_clk); /* verilator public_module */
endmodule
// --flatten forces inlining of public module foo.
module top(input logic i_clk);
foo f(.*);
endmodule

220
test_regress/t/t_xml_flat_vlvbound.out
View File

@ -1,220 +0,0 @@
<?xml version="1.0" ?>
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml>
<files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_flat_vlvbound.v" language="1800-2023"/>
</files>
<module_files>
<file id="d" filename="t/t_xml_flat_vlvbound.v" language="1800-2023"/>
</module_files>
<cells>
<cell loc="d,7,8,7,21" name="$root" submodname="$root" hier="$root"/>
</cells>
<netlist>
<module loc="d,7,8,7,21" name="$root" origName="$root" topModule="1" public="true">
<var loc="d,9,25,9,28" name="i_a" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="i_a" public="true"/>
<var loc="d,10,25,10,28" name="i_b" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="i_b" public="true"/>
<var loc="d,11,25,11,28" name="o_a" dtype_id="2" dir="output" pinIndex="3" vartype="logic" origName="o_a" public="true"/>
<var loc="d,12,25,12,28" name="o_b" dtype_id="2" dir="output" pinIndex="4" vartype="logic" origName="o_b" public="true"/>
<var loc="d,9,25,9,28" name="vlvbound_test.i_a" dtype_id="1" vartype="logic" origName="i_a"/>
<var loc="d,10,25,10,28" name="vlvbound_test.i_b" dtype_id="1" vartype="logic" origName="i_b"/>
<var loc="d,11,25,11,28" name="vlvbound_test.o_a" dtype_id="2" vartype="logic" origName="o_a"/>
<var loc="d,12,25,12,28" name="vlvbound_test.o_b" dtype_id="2" vartype="logic" origName="o_b"/>
<topscope loc="d,7,8,7,21">
<scope loc="d,7,8,7,21" name="TOP">
<varscope loc="d,9,25,9,28" name="i_a" dtype_id="1"/>
<varscope loc="d,10,25,10,28" name="i_b" dtype_id="1"/>
<varscope loc="d,11,25,11,28" name="o_a" dtype_id="2"/>
<varscope loc="d,12,25,12,28" name="o_b" dtype_id="2"/>
<varscope loc="d,9,25,9,28" name="vlvbound_test.i_a" dtype_id="1"/>
<always loc="d,9,25,9,28">
<contassign loc="d,9,25,9,28" dtype_id="1">
<varref loc="d,9,25,9,28" name="i_a" dtype_id="1"/>
<varref loc="d,9,25,9,28" name="vlvbound_test.i_a" dtype_id="1"/>
</contassign>
</always>
<varscope loc="d,10,25,10,28" name="vlvbound_test.i_b" dtype_id="1"/>
<always loc="d,10,25,10,28">
<contassign loc="d,10,25,10,28" dtype_id="1">
<varref loc="d,10,25,10,28" name="i_b" dtype_id="1"/>
<varref loc="d,10,25,10,28" name="vlvbound_test.i_b" dtype_id="1"/>
</contassign>
</always>
<varscope loc="d,11,25,11,28" name="vlvbound_test.o_a" dtype_id="2"/>
<always loc="d,11,25,11,28">
<contassign loc="d,11,25,11,28" dtype_id="2">
<varref loc="d,11,25,11,28" name="o_a" dtype_id="2"/>
<varref loc="d,11,25,11,28" name="vlvbound_test.o_a" dtype_id="2"/>
</contassign>
</always>
<varscope loc="d,12,25,12,28" name="vlvbound_test.o_b" dtype_id="2"/>
<always loc="d,12,25,12,28">
<contassign loc="d,12,25,12,28" dtype_id="2">
<varref loc="d,12,25,12,28" name="o_b" dtype_id="2"/>
<varref loc="d,12,25,12,28" name="vlvbound_test.o_b" dtype_id="2"/>
</contassign>
</always>
<varscope loc="d,15,34,15,37" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2"/>
<varscope loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1"/>
<varscope loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
<varscope loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
<varscope loc="d,15,34,15,37" name="__Vfunc_vlvbound_test.foo__1__Vfuncout" dtype_id="2"/>
<varscope loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1"/>
<varscope loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2"/>
<varscope loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
<always loc="d,24,14,24,15">
<comment loc="d,24,16,24,19" name="Function: foo"/>
<assign loc="d,24,20,24,23" dtype_id="1">
<varref loc="d,24,20,24,23" name="i_a" dtype_id="1"/>
<varref loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1"/>
</assign>
<creset loc="d,16,17,16,20">
<varref loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
</creset>
<creset loc="d,17,13,17,14">
<varref loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</creset>
<assign loc="d,18,11,18,12" dtype_id="3">
<const loc="d,18,12,18,13" name="32&apos;sh0" dtype_id="4"/>
<varref loc="d,18,10,18,11" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</assign>
<loop loc="d,18,5,18,8">
<begin>
<looptest loc="d,18,16,18,17">
<gts loc="d,18,18,18,19" dtype_id="5">
<const loc="d,18,20,18,21" name="32&apos;sh7" dtype_id="4"/>
<varref loc="d,18,16,18,17" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</gts>
</looptest>
<assign loc="d,19,14,19,15" dtype_id="5">
<eq loc="d,19,31,19,33" dtype_id="5">
<const loc="d,19,34,19,39" name="2&apos;h0" dtype_id="6"/>
<sel loc="d,19,20,19,21" dtype_id="6" widthConst="2">
<varref loc="d,19,17,19,20" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1"/>
<sel loc="d,19,22,19,23" dtype_id="7" widthConst="4">
<muls loc="d,19,22,19,23" dtype_id="4">
<const loc="d,19,23,19,24" name="32&apos;sh2" dtype_id="4"/>
<varref loc="d,19,21,19,22" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</muls>
<const loc="d,19,22,19,23" name="32&apos;h0" dtype_id="8"/>
</sel>
</sel>
</eq>
<sel loc="d,19,10,19,11" dtype_id="5" widthConst="1">
<varref loc="d,19,7,19,10" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
<sel loc="d,19,11,19,12" dtype_id="9" widthConst="3">
<varref loc="d,19,11,19,12" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
<const loc="d,19,11,19,12" name="32&apos;h0" dtype_id="8"/>
</sel>
</sel>
</assign>
<assign loc="d,18,24,18,26" dtype_id="3">
<add loc="d,18,24,18,26" dtype_id="8">
<const loc="d,18,24,18,26" name="32&apos;h1" dtype_id="8"/>
<varref loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</add>
<varref loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</assign>
</begin>
</loop>
<assign loc="d,21,5,21,11" dtype_id="2">
<varref loc="d,21,12,21,15" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
<varref loc="d,21,5,21,11" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2"/>
</assign>
<contassign loc="d,24,14,24,15" dtype_id="2">
<varref loc="d,24,16,24,19" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2"/>
<varref loc="d,24,10,24,13" name="o_a" dtype_id="2"/>
</contassign>
</always>
<always loc="d,25,14,25,15">
<comment loc="d,25,16,25,19" name="Function: foo"/>
<assign loc="d,25,20,25,23" dtype_id="1">
<varref loc="d,25,20,25,23" name="i_b" dtype_id="1"/>
<varref loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1"/>
</assign>
<creset loc="d,16,17,16,20">
<varref loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2"/>
</creset>
<creset loc="d,17,13,17,14">
<varref loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</creset>
<assign loc="d,18,11,18,12" dtype_id="3">
<const loc="d,18,12,18,13" name="32&apos;sh0" dtype_id="4"/>
<varref loc="d,18,10,18,11" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</assign>
<loop loc="d,18,5,18,8">
<begin>
<looptest loc="d,18,16,18,17">
<gts loc="d,18,18,18,19" dtype_id="5">
<const loc="d,18,20,18,21" name="32&apos;sh7" dtype_id="4"/>
<varref loc="d,18,16,18,17" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</gts>
</looptest>
<assign loc="d,19,14,19,15" dtype_id="5">
<eq loc="d,19,31,19,33" dtype_id="5">
<const loc="d,19,34,19,39" name="2&apos;h0" dtype_id="6"/>
<sel loc="d,19,20,19,21" dtype_id="6" widthConst="2">
<varref loc="d,19,17,19,20" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1"/>
<sel loc="d,19,22,19,23" dtype_id="7" widthConst="4">
<muls loc="d,19,22,19,23" dtype_id="4">
<const loc="d,19,23,19,24" name="32&apos;sh2" dtype_id="4"/>
<varref loc="d,19,21,19,22" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</muls>
<const loc="d,19,22,19,23" name="32&apos;h0" dtype_id="8"/>
</sel>
</sel>
</eq>
<sel loc="d,19,10,19,11" dtype_id="5" widthConst="1">
<varref loc="d,19,7,19,10" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2"/>
<sel loc="d,19,11,19,12" dtype_id="9" widthConst="3">
<varref loc="d,19,11,19,12" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
<const loc="d,19,11,19,12" name="32&apos;h0" dtype_id="8"/>
</sel>
</sel>
</assign>
<assign loc="d,18,24,18,26" dtype_id="3">
<add loc="d,18,24,18,26" dtype_id="8">
<const loc="d,18,24,18,26" name="32&apos;h1" dtype_id="8"/>
<varref loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</add>
<varref loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</assign>
</begin>
</loop>
<assign loc="d,21,5,21,11" dtype_id="2">
<varref loc="d,21,12,21,15" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2"/>
<varref loc="d,21,5,21,11" name="__Vfunc_vlvbound_test.foo__1__Vfuncout" dtype_id="2"/>
</assign>
<contassign loc="d,25,14,25,15" dtype_id="2">
<varref loc="d,25,16,25,19" name="__Vfunc_vlvbound_test.foo__1__Vfuncout" dtype_id="2"/>
<varref loc="d,25,10,25,13" name="o_b" dtype_id="2"/>
</contassign>
</always>
</scope>
</topscope>
<var loc="d,15,34,15,37" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__0__Vfuncout"/>
<var loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__0__val"/>
<var loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__0__ret"/>
<var loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3" vartype="integer" origName="__Vfunc_vlvbound_test__DOT__foo__0__i"/>
<var loc="d,15,34,15,37" name="__Vfunc_vlvbound_test.foo__1__Vfuncout" dtype_id="2" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__1__Vfuncout"/>
<var loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__1__val"/>
<var loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__1__ret"/>
<var loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3" vartype="integer" origName="__Vfunc_vlvbound_test__DOT__foo__1__i"/>
</module>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,18,18,18,19" id="5" name="logic"/>
<basicdtype loc="d,19,34,19,39" id="6" name="logic" left="1" right="0"/>
<basicdtype loc="d,9,11,9,16" id="1" name="logic" left="15" right="0"/>
<basicdtype loc="d,11,12,11,17" id="2" name="logic" left="6" right="0"/>
<basicdtype loc="d,17,5,17,12" id="3" name="integer" left="31" right="0" signed="true"/>
<basicdtype loc="d,19,10,19,11" id="9" name="logic" left="2" right="0" signed="true"/>
<basicdtype loc="d,19,11,19,12" id="8" name="logic" left="31" right="0"/>
<basicdtype loc="d,19,20,19,21" id="7" name="logic" left="3" right="0" signed="true"/>
<basicdtype loc="d,18,12,18,13" id="4" name="logic" left="31" right="0" signed="true"/>
<voiddtype loc="a,0,0,0,0" id="10"/>
</typetable>
</netlist>
</verilator_xml>

23
test_regress/t/t_xml_flat_vlvbound.py
View File

@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
out_filename = test.obj_dir + "/V" + test.name + ".xml"
test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--flatten'],
verilator_make_gmake=False,
make_top_shell=False,
make_main=False)
test.files_identical(out_filename, test.golden_filename)
test.passes()

27
test_regress/t/t_xml_flat_vlvbound.v
View File

@ -1,27 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module vlvbound_test
(
input logic [15:0] i_a,
input logic [15:0] i_b,
output logic [6:0] o_a,
output logic [6:0] o_b
);
function automatic logic [6:0] foo(input logic [15:0] val);
logic [6:0] ret;
integer i;
for (i=0 ; i < 7; i++) begin
ret[i] = (val[i*2 +: 2] == 2'b00);
end
return ret;
endfunction
assign o_a = foo(i_a);
assign o_b = foo(i_b);
endmodule

24
test_regress/t/t_xml_output.out
View File

@ -1,24 +0,0 @@
<?xml version="1.0" ?>
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml>
<files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_output.v" language="1800-2023"/>
</files>
<module_files>
<file id="d" filename="t/t_xml_output.v" language="1800-2023"/>
</module_files>
<cells>
<cell loc="d,7,8,7,9" name="m" submodname="m" hier="m"/>
</cells>
<netlist>
<module loc="d,7,8,7,9" name="m" origName="m" topModule="1">
<var loc="d,8,10,8,13" name="clk" tag="foo_op" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk" public="true"/>
</module>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,8,10,8,13" id="1" name="logic"/>
</typetable>
</netlist>
</verilator_xml>

31
test_regress/t/t_xml_output.py
View File

@ -1,31 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
out_filename = test.obj_dir + "/renamed-" + test.name + ".xml"
test.compile(
verilator_flags2=["--no-std", "-Wno-DEPRECATED --xml-only --xml-output", out_filename],
verilator_make_gmake=False,
make_top_shell=False,
make_main=False)
test.files_identical(out_filename, test.golden_filename)
for filename in test.glob_some(test.obj_dir + "/*"):
if (re.search(r'\.log', filename) # Made by driver.py, not Verilator sources
or re.search(r'\.status', filename) # Made by driver.py, not Verilator sources
or re.search(r'renamed-', filename)): # Requested output
continue
test.error("%Error: Created '" + filename + "', but --xml-only shouldn't create files")
test.passes()

10
test_regress/t/t_xml_output.v
View File

@ -1,10 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module m
(input clk); // verilator tag foo_op
endmodule

62
test_regress/t/t_xml_primary_io.out
View File

@ -1,62 +0,0 @@
<?xml version="1.0" ?>
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml>
<files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_primary_io.v" language="1800-2023"/>
</files>
<module_files>
<file id="d" filename="t/t_xml_primary_io.v" language="1800-2023"/>
</module_files>
<cells>
<cell loc="d,7,8,7,11" name="top" submodname="top" hier="top">
<cell loc="d,15,11,15,19" name="and_cell" submodname="and2_x1" hier="top.and_cell"/>
</cell>
</cells>
<netlist>
<module loc="d,7,8,7,11" name="top" origName="top" topModule="1">
<var loc="d,8,9,8,12" name="clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk" public="true"/>
<var loc="d,9,9,9,11" name="a1" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="a1" public="true"/>
<var loc="d,10,9,10,11" name="a2" dtype_id="1" dir="input" pinIndex="3" vartype="logic" origName="a2" public="true"/>
<var loc="d,11,10,11,15" name="ready" dtype_id="1" dir="output" pinIndex="4" vartype="logic" origName="ready" public="true"/>
<var loc="d,13,8,13,17" name="ready_reg" dtype_id="1" vartype="logic" origName="ready_reg"/>
<instance loc="d,15,11,15,19" name="and_cell" defName="and2_x1" origName="and_cell">
<port loc="d,16,6,16,8" name="a1" direction="in" portIndex="1">
<varref loc="d,16,9,16,11" name="a1" dtype_id="1"/>
</port>
<port loc="d,17,6,17,8" name="a2" direction="in" portIndex="2">
<varref loc="d,17,9,17,11" name="a2" dtype_id="1"/>
</port>
<port loc="d,18,6,18,8" name="zn" direction="out" portIndex="3">
<varref loc="d,18,9,18,18" name="ready_reg" dtype_id="1"/>
</port>
</instance>
<always loc="d,21,16,21,17">
<contassign loc="d,21,16,21,17" dtype_id="1">
<varref loc="d,13,8,13,17" name="ready_reg" dtype_id="1"/>
<varref loc="d,21,16,21,17" name="ready" dtype_id="1"/>
</contassign>
</always>
</module>
<module loc="d,24,8,24,15" name="and2_x1" origName="and2_x1">
<var loc="d,25,14,25,16" name="a1" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="a1"/>
<var loc="d,26,14,26,16" name="a2" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="a2"/>
<var loc="d,27,15,27,17" name="zn" dtype_id="1" dir="output" pinIndex="3" vartype="logic" origName="zn"/>
<always loc="d,29,15,29,16">
<contassign loc="d,29,15,29,16" dtype_id="1">
<and loc="d,29,21,29,22" dtype_id="1">
<varref loc="d,25,14,25,16" name="a1" dtype_id="1"/>
<varref loc="d,26,14,26,16" name="a2" dtype_id="1"/>
</and>
<varref loc="d,29,15,29,16" name="zn" dtype_id="1"/>
</contassign>
</always>
</module>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,25,14,25,16" id="1" name="logic"/>
<voiddtype loc="a,0,0,0,0" id="2"/>
</typetable>
</netlist>
</verilator_xml>

23
test_regress/t/t_xml_primary_io.py
View File

@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
out_filename = test.obj_dir + "/V" + test.name + ".xml"
test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'],
verilator_make_gmake=False,
make_top_shell=False,
make_main=False)
test.files_identical(out_filename, test.golden_filename)
test.passes()

30
test_regress/t/t_xml_primary_io.v
View File

@ -1,30 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module top(clk, a1, a2, ready);
input clk;
input a1;
input a2;
output ready;
wire ready_reg;
and2_x1 and_cell (
.a1(a1),
.a2(a2),
.zn(ready_reg)
);
assign ready = ready_reg;
endmodule
module and2_x1 (
input wire a1,
input wire a2,
output wire zn
);
assign zn = (a1 & a2);
endmodule

86
test_regress/t/t_xml_tag.out
View File

@ -1,86 +0,0 @@
<?xml version="1.0" ?>
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml>
<files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_tag.v" language="1800-2023"/>
</files>
<module_files>
<file id="d" filename="t/t_xml_tag.v" language="1800-2023"/>
</module_files>
<cells>
<cell loc="d,12,8,12,9" name="m" submodname="m" hier="m">
<cell loc="d,29,8,29,12" name="itop" submodname="ifc" hier="m.itop"/>
</cell>
</cells>
<netlist>
<module loc="d,12,8,12,9" name="m" origName="m" topModule="1">
<var loc="d,14,11,14,17" name="clk_ip" tag="clk_ip" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk_ip" public="true"/>
<var loc="d,15,11,15,17" name="rst_ip" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="rst_ip" public="true"/>
<var loc="d,16,11,16,17" name="foo_op" tag="foo_op" dtype_id="1" dir="output" pinIndex="3" vartype="logic" origName="foo_op" public="true"/>
<typedef loc="d,25,6,25,15" name="my_struct" tag="my_struct" dtype_id="2"/>
<instance loc="d,29,8,29,12" name="itop" defName="ifc" origName="itop"/>
<var loc="d,29,8,29,12" name="itop" dtype_id="3" vartype="ifaceref" origName="itop__Viftop"/>
<var loc="d,31,14,31,25" name="this_struct" tag="this_struct" dtype_id="4" vartype="" origName="this_struct"/>
<var loc="d,33,16,33,22" name="dotted" dtype_id="5" vartype="logic" origName="dotted"/>
<always loc="d,33,23,33,24">
<contassign loc="d,33,23,33,24" dtype_id="5">
<varxref loc="d,33,30,33,35" name="value" dtype_id="6" dotted="itop"/>
<varref loc="d,33,16,33,22" name="dotted" dtype_id="5"/>
</contassign>
</always>
<task loc="d,35,18,35,19" name="f">
<var loc="d,35,33,35,34" name="m" dtype_id="7" dir="input" vartype="string" origName="m"/>
<display loc="d,36,7,36,15" displaytype="$display">
<sformatf loc="d,36,7,36,15" name="%@" dtype_id="7">
<varref loc="d,36,22,36,23" name="m" dtype_id="7"/>
</sformatf>
</display>
</task>
<initial loc="d,39,4,39,11">
<begin loc="d,39,12,39,17">
<stmtexpr loc="d,41,7,41,8">
<taskref loc="d,41,7,41,8" name="f" dtype_id="8">
<arg loc="d,41,9,41,736">
<const loc="d,41,9,41,736" name="&quot;&#1;&#2;&#3;&#4;&#5;&#6;&#7;&#8;&#9;&#10;&#11;&#12;&#13;&#14;&#15;&#16;&#17;&#18;&#19;&#20;&#21;&#22;&#23;&#24;&#25;&#26;&#27;&#28;&#29;&#30;&#31; !&quot;#$%&amp;&apos;()*+,-./0123456789:;&lt;=&gt;?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~&#127;&#128;&#129;&#130;&#131;&#132;&#133;&#134;&#135;&#136;&#137;&#138;&#139;&#140;&#141;&#142;&#143;&#144;&#145;&#146;&#147;&#148;&#149;&#150;&#151;&#152;&#153;&#154;&#155;&#156;&#157;&#158;&#159;&#160;&#161;&#162;&#163;&#164;&#165;&#166;&#167;&#168;&#169;&#170;&#171;&#172;&#173;&#174;&#175;&#176;&#177;&#178;&#179;&#180;&#181;&#182;&#183;&#184;&#185;&#186;&#187;&#188;&#189;&#190;&#191;&#192;&#193;&#194;&#195;&#196;&#197;&#198;&#199;&#200;&#201;&#202;&#203;&#204;&#205;&#206;&#207;&#208;&#209;&#210;&#211;&#212;&#213;&#214;&#215;&#216;&#217;&#218;&#219;&#220;&#221;&#222;&#223;&#224;&#225;&#226;&#227;&#228;&#229;&#230;&#231;&#232;&#233;&#234;&#235;&#236;&#237;&#238;&#239;&#240;&#241;&#242;&#243;&#244;&#245;&#246;&#247;&#248;&#249;&#250;&#251;&#252;&#253;&#254;&#255;&quot;" dtype_id="7"/>
</arg>
</taskref>
</stmtexpr>
</begin>
</initial>
</module>
<iface loc="d,7,11,7,14" name="ifc" origName="ifc">
<var loc="d,8,12,8,17" name="value" dtype_id="6" vartype="integer" origName="value"/>
<modport loc="d,9,12,9,23" name="out_modport">
<modportvarref loc="d,9,32,9,37" name="value" direction="out"/>
</modport>
</iface>
<typetable loc="a,0,0,0,0">
<voiddtype loc="d,41,7,41,8" id="8"/>
<basicdtype loc="d,8,4,8,11" id="6" name="integer" left="31" right="0" signed="true"/>
<basicdtype loc="d,14,11,14,17" id="1" name="logic"/>
<basicdtype loc="d,21,7,21,12" id="9" name="logic"/>
<basicdtype loc="d,22,7,22,12" id="10" name="logic"/>
<basicdtype loc="d,23,7,23,12" id="11" name="logic"/>
<basicdtype loc="d,24,7,24,12" id="12" name="logic"/>
<structdtype loc="d,20,12,20,18" id="2" name="m.my_struct">
<memberdtype loc="d,21,19,21,22" id="13" name="clk" tag="this is clk" sub_dtype_id="9"/>
<memberdtype loc="d,22,19,22,20" id="14" name="k" sub_dtype_id="10"/>
<memberdtype loc="d,23,19,23,25" id="15" name="enable" tag="enable" sub_dtype_id="11"/>
<memberdtype loc="d,24,19,24,23" id="16" name="data" tag="data" sub_dtype_id="12"/>
</structdtype>
<ifacerefdtype loc="d,29,8,29,12" id="3" modportname=""/>
<basicdtype loc="d,31,27,31,28" id="5" name="logic" left="31" right="0"/>
<refdtype loc="d,31,4,31,13" id="17" name="my_struct" sub_dtype_id="2"/>
<unpackarraydtype loc="d,31,26,31,27" id="4" sub_dtype_id="2">
<range loc="d,31,26,31,27">
<const loc="d,31,27,31,28" name="32&apos;h0" dtype_id="5"/>
<const loc="d,31,27,31,28" name="32&apos;h1" dtype_id="5"/>
</range>
</unpackarraydtype>
<basicdtype loc="d,35,26,35,32" id="7" name="string"/>
</typetable>
</netlist>
</verilator_xml>

23
test_regress/t/t_xml_tag.py
View File

@ -1,23 +0,0 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
out_filename = test.obj_dir + "/V" + test.name + ".xml"
test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'],
verilator_make_gmake=False,
make_top_shell=False,
make_main=False)
test.files_identical(out_filename, test.golden_filename)
test.passes()

44
test_regress/t/t_xml_tag.v
View File

@ -1,44 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Chris Randall.
// SPDX-License-Identifier: CC0-1.0
interface ifc;
integer value;
modport out_modport (output value);
endinterface
module m
(
input clk_ip, // verilator tag clk_ip
input rst_ip,
output foo_op); // verilator tag foo_op
// This is a comment
typedef struct packed {
logic clk; /* verilator tag this is clk */
logic k; /* verilator lint_off UNUSED */
logic enable; // verilator tag enable
logic data; // verilator tag data
} my_struct; // verilator tag my_struct
// This is a comment
ifc itop();
my_struct this_struct [2]; // verilator tag this_struct
wire [31:0] dotted = itop.value;
function void f(input string m);
$display("%s", m);
endfunction
initial begin
// Contains all 256 characters except 0 (null character)
f("\x01\x02\x03\x04\x05\x06\a\x08\t\n\v\f\r\x0e\x0f\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f !\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~\x7f\x80\x81\x82\x83\x84\x85\x86\x87\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90\x91\x92\x93\x94\x95\x96\x97\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8\xa9\xaa\xab\xac\xad\xae\xaf\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8\xe9\xea\xeb\xec\xed\xee\xef\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff");
end
endmodule