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Support clocking output delay `1step` (#6681).

This commit is contained in:
Wilson Snyder 2025-11-22 17:40:40 -05:00
parent 24117bc599
commit 087ca15138
4 changed files with 4 additions and 18 deletions
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1
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@ -23,6 +23,7 @@ Verilator 5.043 devel
* Support this.randomize() with constraints (#6634). [Artur Bieniek, Antmicro Ltd.]
* Support multi-expression sequences (#6639). [Bartłomiej Chmiel, Antmicro Ltd.]
* Support `#1step` delay as statement (#6671). [Pawel Kojma, Antmicro Ltd.]
* Support clocking output delay `1step` (#6681). [Ondrej Ille]
* Support parsing of dotted bins_expression (#6683). [Pawel Kojma, Antmicro Ltd.]
* Support constant expression cycle delays in sequences (#6691). [Ryszard Rozak, Antmicro Ltd.]
* Support general global constraints (#6709) (#6711). [Yilou Wang]

9
src/V3LinkParse.cpp
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@ -902,11 +902,6 @@ class LinkParseVisitor final : public VNVisitor {
}
m_defaultInSkewp = itemp->skewp();
} else if (itemp->direction() == VDirection::OUTPUT) {
if (AstConst* const constp = VN_CAST(itemp->skewp(), Const)) {
if (constp->num().is1Step()) {
itemp->skewp()->v3error("1step not allowed as output skew");
}
}
// Disallow default redefinition; note some simulators allow this
if (m_defaultOutSkewp) {
itemp->skewp()->v3error("Multiple default output skews not allowed");
@ -930,10 +925,6 @@ class LinkParseVisitor final : public VNVisitor {
// Default is 0 (IEEE 1800-2023 14.3)
nodep->skewp(new AstConst{nodep->fileline(), 0});
}
} else if (AstConst* const constp = VN_CAST(nodep->skewp(), Const)) {
if (constp->num().is1Step()) {
nodep->skewp()->v3error("1step not allowed as output skew");
}
}
} else if (nodep->direction() == VDirection::INPUT) {
if (!nodep->skewp()) {

8
test_regress/t/t_clocking_bad2.out
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@ -1,16 +1,10 @@
%Error: t/t_clocking_bad2.v:15:33: 1step not allowed as output skew
15 | default input #1 output #1step;
| ^~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_clocking_bad2.v:16:23: Multiple default input skews not allowed
16 | default input #2 output #2;
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_clocking_bad2.v:16:33: Multiple default output skews not allowed
16 | default input #2 output #2;
| ^
%Error: t/t_clocking_bad2.v:17:16: 1step not allowed as output skew
17 | output #1step out;
| ^~~~~
%Error: t/t_clocking_bad2.v:18:8: Multiple clockvars with the same name not allowed
18 | output out;
| ^~~~~~

4
test_regress/t/t_clocking_bad2.v
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@ -12,9 +12,9 @@ module t(/*AUTOARG*/
logic in, out;
clocking cb @(posedge clk);
default input #1 output #1step;
default input #1 output #1step; // Now allowed
default input #2 output #2;
output #1step out;
output #1step out; // Now allowed
output out;
endclocking
endmodule