Don't pick initial random values for verilator-created variables (#6611)

src/V3EmitCFunc.cpp

@@ -670,6 +670,7 @@ string EmitCFunc::emitVarResetRecurse(const AstVar* varp, bool constructing,
                || varp->isFuncLocal()  // Randomization too slow
                || (basicp && basicp->isZeroInit())
                || (v3Global.opt.underlineZero() && !varp->name().empty() && varp->name()[0] == '_')
+               || (varp->varType().isTemp() && !varp->isXTemp())
                || (varp->isXTemp()
                        ? (v3Global.opt.xAssign() != "unique")
                        : (v3Global.opt.xInitial() == "fast" || v3Global.opt.xInitial() == "0")));

test_regress/t/t_split_var_issue.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios("simulator_st")
+
+test.compile(verilator_flags2=["--assert", "-fno-localize"])
+
+test.execute(all_run_flags=["+verilator+rand+reset+2"])
+
+test.passes()

test_regress/t/t_split_var_issue.v

@@ -0,0 +1,50 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module other_sub (
+    input wire clk,
+    input wire      foo,
+    output logic     [5:0] bar
+);
+    always_comb bar[0] = foo;
+`ifndef NO_ASSERT
+    assert property (@(posedge clk) (foo == bar[0]));
+`endif
+    always_ff @(posedge clk) bar[5:1] <= bar[4:0];
+endmodule
+
+interface intf
+    (input wire clk);
+endinterface
+
+module sub (
+    input logic clk
+);
+    for (genvar k = 0; k < 4; k++) begin
+        logic     [5:0] bar;
+        other_sub
+        the_other_sub (
+            .clk,
+            .foo ('1),
+            .bar
+        );
+    end
+endmodule
+
+module t (/*AUTOARG*/
+    clk
+    );
+    input clk;
+    int cyc = 0;
+    always @ (posedge clk) begin
+        cyc <= cyc + 1;
+        if (cyc == 9) begin
+            $write("*-* All Finished *-*\n");
+            $finish;
+        end
+    end
+    sub the_sub (.*);
+endmodule