Verilog format

test_regress/t/t_case_unique_overlap.v

@@ -4,12 +4,9 @@
 // any use, without warranty, 2025 by Luca Colagrande.
 // SPDX-License-Identifier: CC0-1.0
 
-module t (/*AUTOARG*/
-  // Inputs
-  clk
-  );
-
-  input clk;
+module t (
+    input clk
+);
 
   localparam logic [1:0] INST1 = 2'b0?;
   localparam logic [1:0] INST2 = 2'b0?;
@@ -32,7 +29,7 @@ module t (/*AUTOARG*/
     endcase
   end
 
-  always @ (posedge clk) begin
+  always @(posedge clk) begin
 `ifdef TEST_VERBOSE
     $write("[%0t] in=%x out=%x\n", $time, in, out);
 `endif

test_regress/t/t_init_array_bad.out

@@ -1,5 +1,5 @@
-%Error: t/t_init_array_bad.v:8:35: Array initialization has too few elements, need element 2
-    8 |     bit [7:0] r[3] = {{8'h1, 8'h2}, 8'h5};
-      |                                   ^
+%Error: t/t_init_array_bad.v:8:33: Array initialization has too few elements, need element 2
+    8 |   bit [7:0] r[3] = {{8'h1, 8'h2}, 8'h5};
+      |                                 ^
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_init_array_bad.v

@@ -5,6 +5,6 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t;
-    bit [7:0] r[3] = {{8'h1, 8'h2}, 8'h5};
-    initial $finish;
+  bit [7:0] r[3] = {{8'h1, 8'h2}, 8'h5};
+  initial $finish;
 endmodule

test_regress/t/t_interface_virtual_do_while.v

@@ -11,7 +11,7 @@ interface Bus;
 endinterface
 
 module t;
-  Bus intf();
+  Bus intf ();
   virtual Bus vif = intf;
   bit ok = 0;
 
@@ -28,8 +28,11 @@ module t;
     do begin
       if (!first) $stop;
       first = 0;
-    end while(!write_data(vif.data));
-    #1 if (ok != 1) $stop;
+    end while (!write_data(
+        vif.data
+    ));
+    #1;
+    if (ok != 1) $stop;
     $write("*-* All Finished *-*\n");
     $finish;
   end

test_regress/t/t_interface_virtual_for.v

@@ -11,7 +11,7 @@ interface Bus;
 endinterface
 
 module t;
-  Bus intf();
+  Bus intf ();
   virtual Bus vif = intf;
   bit ok = 0;
 

test_regress/t/t_interface_virtual_if.v

@@ -11,7 +11,7 @@ interface Bus;
 endinterface
 
 module t;
-  Bus intf();
+  Bus intf ();
   virtual Bus vif = intf;
   bit ok = 0;
 

test_regress/t/t_interface_virtual_while.v

@@ -11,7 +11,7 @@ interface Bus;
 endinterface
 
 module t;
-  Bus intf();
+  Bus intf ();
   virtual Bus vif = intf;
   bit ok = 0;