luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Support `extern module` as a forward-declaration that is ignored.

This commit is contained in:
Wilson Snyder 2026-01-22 19:00:26 -05:00
parent 86cd249816
commit ddbcd66722
5 changed files with 28 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Changes
View File

@ -22,6 +22,7 @@ Verilator 5.045 devel
* Support complex expressions as std::randomize arguments (#6860). [Jakub Wasilewski, Antmicro Ltd.]
* Support dynamic array elements in std::randomize (#6896). [Ryszard Rozak, Antmicro Ltd.]
* Support unbounded '$' in inside range expressions (#6935) (#6938). [Wei-Lun Chiu]
* Support `extern module` as a forward-declaration that is ignored.
* Remove deprecated `--xml-only`.
* Remove deprecated `--make cmake`.
* Fix variable reference lookup for module-level variables (#6741) (#6882). [Yilou Wang]

9
src/verilog.y
View File

@ -1212,7 +1212,8 @@ module_declaration: // ==IEEE: module_declaration
GRAMMARP->endLabel($<fl>6, $1, $6); }
//
| yEXTERN modFront parameter_port_listE portsStarE ';'
{ BBUNSUP($<fl>1, "Unsupported: extern module"); }
{ DEL($2->unlinkFrBack()); }
// We allow modules to be declared after instantiations, so harmless
;
modFront<nodeModulep>:
@ -1508,7 +1509,8 @@ interface_declaration: // IEEE: interface_declaration + interface_nonan
if ($5) $1->addStmtsp($5);
$1->hasParameterList($<flag>2); }
| yEXTERN intFront parameter_port_listE portsStarE ';'
{ BBUNSUP($<fl>1, "Unsupported: extern interface"); }
{ DEL($2->unlinkFrBack()); }
// We allow interfaces to be declared after instantiations, so harmless
;
intFront<nodeModulep>:
@ -1598,7 +1600,8 @@ program_declaration: // IEEE: program_declaration + program_nonansi_h
if ($5) $1->addStmtsp($5);
GRAMMARP->endLabel($<fl>7, $1, $7); }
| yEXTERN pgmFront parameter_port_listE portsStarE ';'
{ BBUNSUP($<fl>1, "Unsupported: extern program"); }
{ DEL($2->unlinkFrBack()); }
// We allow programs to be declared after instantiations, so harmless
;
pgmFront<nodeModulep>:

11
test_regress/t/t_program_extern.out
View File

@ -1,11 +0,0 @@
%Error-UNSUPPORTED: t/t_program_extern.v:7:1: Unsupported: extern program
7 | extern program ex_pgm;
| ^~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_program_extern.v:8:1: Unsupported: extern interface
8 | extern interface ex_ifc;
| ^~~~~~
%Error-UNSUPPORTED: t/t_program_extern.v:9:1: Unsupported: extern module
9 | extern module ex_mod;
| ^~~~~~
%Error: Exiting due to

9
test_regress/t/t_program_extern.py
View File

@ -1,7 +1,7 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# Copyright 2026 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
@ -9,11 +9,10 @@
import vltest_bootstrap
test.scenarios('simulator')
test.scenarios('simulator_st')
test.compile(fails=test.vlt_all, expect_filename=test.golden_filename)
test.compile()
if not test.vlt_all:
test.execute()
test.execute()
test.passes()

25
test_regress/t/t_program_extern.v
View File

@ -10,14 +10,23 @@ extern module ex_mod;
module t;
ex_pgm u_pgm();
ex_ifc u_ifc();
ex_mod u_mod();
ex_pgm u_pgm();
ex_ifc u_ifc();
ex_mod u_mod();
initial begin
ex_task();
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
// Could be in another compile run, but we don't support that
program ex_pgm;
endprogram
interface ex_ifc;
endinterface
module ex_mod;
endmodule