Commentary: Changes update

Changes

@@ -19,8 +19,10 @@ Verilator 5.047 devel
 **Other:**
 
 * Support inout inside SV interface (#3466) (#7134). [Nick Brereton]
+* Support `##0` cycle delays (#4263) (#7298). [Yilou Wang]
 * Support array reduction methods with 'with' clause in constraints (#6455) (#6999). [Rahul Behl]
 * Support constraint imperfect distributions (#6811) (#7168). [Yilou Wang]
+* Support disable task by name (#6853) (#7136). [Nick Brereton]
 * Support procedural concurrent assertion simple cases (#6944).
 * Support force assignments to array elements of real type (#7048). [Ryszard Rozak, Antmicro Ltd.]
 * Support VPI array indexing in signal names (#7097) (#7187) (#7214) (#7289). [Christian Hecken, Heidelberg University]
@@ -33,25 +35,37 @@ Verilator 5.047 devel
 * Support dist and solve...before inside foreach constraints (#7245) (#7253). [Yilou Wang]
 * Support array and struct info metadata in FST traces (#7255). [Geza Lore, Testorrent USA, Inc.]
 * Support dynamic array .size in inline randomize() with constraints (#7258) (#7266). [Yilou Wang]
+* Support defparam with more than one dot (#7262). [Artur Bieniek, Antmicro Ltd.]
 * Support modport export/import task prototypes and out-of-block definitions (#7277). [Yilou Wang]
+* Support very wide $display arguments (#7280). [Jakub Michalski]
 * Support named sequence declarations and instances in assertions  (#7283). [Yilou Wang]
 * Support `##` delay on implication RHS in SVA properties (#7284). [Yilou Wang]
-* Support `##0` cycle delays (#4263) (#7298). [Yilou Wang]
+* Support boolean and/or in sequence expressions (#7285). [Yilou Wang]
+* Support property-local variables and sequence match items (#7286). [Yilou Wang]
+* Support `##[M:N]` range cycle delay in SVA sequences (#7312). [Yilou Wang]
+* Support array map() method (#7307) (#7316). [Wei-Lun Chiu]
 * Add VPI callback support to --main (#7145).
 * Add V3LiftExpr pass to lower impure expressions and calls (#7141) (#7164). [Geza Lore, Testorrent USA, Inc.]
 * Add --func-recursion-depth CLI option (#7175) (#7179).
+* Add MacOS support for address sanitizer memory limit (#7308). [Marco Bartoli]
 * Deprecate `--structs-packed` (#7222).
 * Improve assignment-compatibility type check (#2843) (#5666) (#7052). [Pawel Kojma, Antmicro Ltd.]
+* Improve error message when variable used as data type (#7318). [Ryszard Rozak, Antmicro Ltd.]
+* Improve E_UNSUPPORTED warning messages (#7329). [Eunseo Song]
 * Change array tracing to dump left index to right index (#7205). [Geza Lore, Testorrent USA, Inc.]
 * Change `--converge-limit` default to 10000 (#7209).
 * Optimize size of trace declaration object code (#7150). [Szymon Gizler, Antmicro Ltd.]
 * Optimize function call return value temporaries (#7152). [Geza Lore, Testorrent USA, Inc.]
 * Optimize conditional merging across some impure statements (#7159). [Geza Lore, Testorrent USA, Inc.]
 * Optimize reuse of existing associative terms in DfgPeephole. [Geza Lore, Testorrent USA, Inc.]
+* Optimize duplicate vertices in DfgPeephole (#7305). [Geza Lore, Testorrent USA, Inc.]
+* Optimize commutative vertex operands in DFG for better combining. [Geza Lore, Testorrent USA, Inc.]
+* Optimize DFG peephole until a fixed point (#7309). [Geza Lore, Testorrent USA, Inc.]
 * Fix recursive default assignment for sub-arrays (#4589) (#7202). [Julian Carrier]
 * Fix shift width mismatch in constraint solver SMT emission (#5420) (#7265). [Yilou Wang]
 * Fix randomize size+element queue constraints (#5582) (#7225). [Rahul Behl, Testorrent USA, Inc.]
 * Fix null assignment to virtual interfaces (#5974) (#5990). [Maxim Fonarev]
+* Fix typedef scope resolution for parameterized class aliases (#5977) (#7319). [Nick Brereton]
 * Fix lambda coroutines (#6106) (#7135). [Nick Brereton]
 * Fix super constructor calls with local variables (#6214) (#6933). [Igor Zaworski, Antmicro Ltd.]
 * Fix `local::` false error in randomize() with on parameterized class (#6680) (#7293). [Yilou Wang]
@@ -59,6 +73,7 @@ Verilator 5.047 devel
 * Fix interface localparam dependencies and arbitrary nesting (#6936) (#7128) (#7188) (#7190). [em2machine]
 * Fix errant integer promotion (#7012). [Todd Strader]
 * Fix randc solver hang with wide variables (#7068) (#7248). [Yilou Wang]
+* Fix coroutine trace setters (#7078 repair) (#7296). [Igor Zaworski, Antmicro Ltd.]
 * Fix scheduling non-determinism (#7120) (#7162) (#7165). [Geza Lore, Testorrent USA, Inc.]
 * Fix parameters inside std::randomize `with` clause  (#7140). [Kamil Danecki, Antmicro Ltd.]
 * Fix forcing unpacked variables (#7149). [Ryszard Rozak, Antmicro Ltd.]
@@ -80,9 +95,13 @@ Verilator 5.047 devel
 * Fix rand variable used as array index in constraint evaluated as constant (#7238) (#7247). [Yilou Wang]
 * Fix --hierarchical dropping arguments in -f/-F files (#7240). [Clara Sparks]
 * Fix `final` asserts and $stop (#7249). [Artur Bieniek, Antmicro Ltd.]
+* Fix MacOS clang PCH compile error with -o flag (#7251) (#7327). [Eunseo Song]
 * Fix vpi_put_value with vpiIntVal on VlWide data (#7256). [Christian Hecken]
 * Fix streaming with descending unpacked arrays and unpacked-to-queue (#7287). [Yilou Wang]
-* Fix coroutine trace setters (#7078 repair) (#7296). [Igor Zaworski, Antmicro Ltd.]
+* Fix MacOs lexer compile error (#7314) (#7315). [Tracy Narine]
+* Fix linking shared library with its dependencies (#7320). [Artur Bieniek, Antmicro Ltd.]
+* Fix modport selection of virtual interface handle (#7321). [Yilou Wang]
+* Fix false ASSIGNIN on interface input ports driven from outside (#7322). [Yilou Wang]
 
 
 Verilator 5.046 2026-02-28

test_regress/t/t_class_param_typedef8.v

@@ -15,7 +15,7 @@ package axi_test;
       parameter IW = 8,
       parameter UW = 1
   );
-    rand logic [IW-1:0] ax_id   = '0;
+    rand logic [IW-1:0] ax_id = '0;
     rand logic [AW-1:0] ax_addr = '0;
     rand logic [UW-1:0] ax_user = '0;
   endclass
@@ -25,13 +25,19 @@ package axi_test;
       parameter int IW = 8,
       parameter int UW = 1
   );
-    typedef axi_ax_beat #(.AW(AW), .IW(IW), .UW(UW)) ax_beat_t;
+    typedef axi_ax_beat#(
+        .AW(AW),
+        .IW(IW),
+        .UW(UW)
+    ) ax_beat_t;
   endclass
 endpackage
 
 module t;
-  typedef axi_test::axi_driver #(
-    .AW(64), .IW(6), .UW(2)
+  typedef axi_test::axi_driver#(
+      .AW(64),
+      .IW(6),
+      .UW(2)
   ) drv_t;
 
   initial begin

test_regress/t/t_defparam_hier.v

@@ -4,8 +4,10 @@
 // SPDX-FileCopyrightText: 2026 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
+// verilog_format: on
 
 module M0 #(parameter PRMTR = 1) (
     output int value
@@ -17,30 +19,30 @@ module M1 #(parameter PRMTR = 1)(
     output int value
 );
   int v0, v1;
-  M0 m0a(.value(v0));
-  M0 m0b(.value(v1));
+  M0 m0a (.value(v0));
+  M0 m0b (.value(v1));
   assign value = v0 + v1;
 endmodule
 
 module M2 #(parameter PRMTR = 1)(
     output int value
 );
-  M1 m1(.value(value));
+  M1 m1 (.value(value));
 endmodule
 
 module M3 #(parameter PRMTR = 1)(
     output int value
 );
   int v0, v1;
-  M2 m2a(.value(v0));
-  M2 m2b(.value(v1));
+  M2 m2a (.value(v0));
+  M2 m2b (.value(v1));
   assign value = v0 * v1;
 endmodule
 
 module top;
   int value;
 
-  M3 m3(.value(value));
+  M3 m3 (.value(value));
 
   defparam m3.m2a.m1.m0a.PRMTR = 2;
   defparam m3.m2a.m1.m0b.PRMTR = 3;
@@ -70,7 +72,7 @@ module top;
     `checkh(m3.PRMTR, 10);
 
     #1;
-    `checkh(value, 45); // (2+3) * (4+5)
+    `checkh(value, 45);  // (2+3) * (4+5)
     $write("*-* All Finished *-*\n");
     $finish;
   end

test_regress/t/t_disable_task_by_name.v

@@ -220,9 +220,9 @@ module WorkerMod;
 endmodule
 
 module t;
-  Ifc ifc1();
-  Prog prog1();
-  WorkerMod mod1();
+  Ifc ifc1 ();
+  Prog prog1 ();
+  WorkerMod mod1 ();
 
   always #6 disable always_foo;
 

test_regress/t/t_disable_task_scope_bad.v

@@ -24,13 +24,13 @@ module Inner;
 endmodule
 
 module Outer;
-  Inner inner();
+  Inner inner ();
 endmodule
 
 module t;
-  Ifc ifc1();
-  Prog prog1();
-  Outer outer1();
+  Ifc ifc1 ();
+  Prog prog1 ();
+  Outer outer1 ();
 
   initial begin
     disable ifc1.missing_task;

test_regress/t/t_interface_input_port_assign.v

@@ -14,21 +14,29 @@
 // All three forms below default to net for input ports.
 
 // Scenario 1: bare input (defaults to net)
-interface bare_if (input clk);
+interface bare_if (
+    input clk
+);
   logic data;
 endinterface
 
 // Scenario 2: input with explicit data type (still net for input)
-interface logic_if (input logic clk);
+interface logic_if (
+    input logic clk
+);
   logic data;
 endinterface
 
 // Scenario 3: input with explicit net kind
-interface wire_if (input wire clk);
+interface wire_if (
+    input wire clk
+);
   logic data;
 endinterface
 
-module consumer (bare_if cif);
+module consumer (
+    bare_if cif
+);
   logic sampled;
   always @(posedge cif.clk) sampled <= cif.data;
 endmodule
@@ -38,19 +46,19 @@ module t;
   always #5 clk = ~clk;
   integer cyc = 0;
 
-  bare_if bif(.clk());
+  bare_if bif (.clk());
   assign bif.clk = clk;
   assign bif.data = 1'b1;
 
-  logic_if lif(.clk());
+  logic_if lif (.clk());
   assign lif.clk = clk;
   assign lif.data = 1'b1;
 
-  wire_if wif(.clk());
+  wire_if wif (.clk());
   assign wif.clk = clk;
   assign wif.data = 1'b1;
 
-  consumer cons(.cif(bif));
+  consumer cons (.cif(bif));
 
   always @(posedge clk) begin
     cyc <= cyc + 1;

test_regress/t/t_interface_input_port_assign_bad.out

@@ -1,10 +1,10 @@
-%Error-ASSIGNIN: t/t_interface_input_port_assign_bad.v:16:10: Assigning to input/const variable: 'clk'
+%Error-ASSIGNIN: t/t_interface_input_port_assign_bad.v:20:10: Assigning to input/const variable: 'clk'
                                                             : ... note: In instance 't'
-   16 |   assign clk = 1'b0;   
+   20 |   assign clk = 1'b0;   
       |          ^~~
                  ... For error description see https://verilator.org/warn/ASSIGNIN?v=latest
-%Error-ASSIGNIN: t/t_interface_input_port_assign_bad.v:23:14: Assigning to input/const variable: 'clk'
+%Error-ASSIGNIN: t/t_interface_input_port_assign_bad.v:27:14: Assigning to input/const variable: 'clk'
                                                             : ... note: In instance 't'
-   23 |   assign vif.clk = sig;   
+   27 |   assign vif.clk = sig;   
       |              ^~~
 %Error: Exiting due to

test_regress/t/t_interface_input_port_assign_bad.v

@@ -7,19 +7,23 @@
 // Case 1: Assigning to explicit var input port from OUTSIDE (illegal).
 // Only 'input var' ports are variable kind (IEEE 1800-2023 23.2.2.3).
 // Variable input ports cannot be assigned (IEEE 1800-2023 23.3.3.2).
-interface var_if (input var logic clk);
+interface var_if (
+    input var logic clk
+);
 endinterface
 
 // Case 2: Assigning to net-type input port from INSIDE (illegal).
 // Internal assign creates a second driver within the port's own scope.
-interface internal_if (input wire clk);
+interface internal_if (
+    input wire clk
+);
   assign clk = 1'b0;  // ASSIGNIN: internal assign to net input
 endinterface
 
 module t;
   logic sig;
-  internal_if iif(.clk(sig));
-  var_if vif(.clk());
+  internal_if iif (.clk(sig));
+  var_if vif (.clk());
   assign vif.clk = sig;  // ASSIGNIN: external assign to var input
   initial begin
     $write("*-* All Finished *-*\n");

test_regress/t/t_interface_virtual_modport_sel.v

@@ -13,16 +13,18 @@
 //   vif.modport_name   (direct)
 //   obj.vif.modport_name  (chained through class member)
 
-interface my_if (input logic clk);
+interface my_if (
+    input logic clk
+);
   logic [7:0] data;
 
   clocking mon_cb @(posedge clk);
     input data;
   endclocking
 
-  modport passive_mp (clocking mon_cb);
-  modport active_mp (output data);
-  modport signal_mp (input data);
+  modport passive_mp(clocking mon_cb);
+  modport active_mp(output data);
+  modport signal_mp(input data);
 endinterface
 
 class Context;

test_regress/t/t_property_sexpr_range_delay.v

@@ -25,8 +25,7 @@ module t (
 
   always_ff @(posedge clk) begin
 `ifdef TEST_VERBOSE
-    $write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b\n",
-           $time, cyc, crc, a, b, c);
+    $write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b\n", $time, cyc, crc, a, b, c);
 `endif
     cyc <= cyc + 1;
     crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
@@ -35,9 +34,11 @@ module t (
     if (cyc == 0) begin
       crc <= 64'h5aef0c8d_d70a4497;
       sum <= '0;
-    end else if (cyc < 10) begin
+    end
+    else if (cyc < 10) begin
       sum <= '0;
-    end else if (cyc == 99) begin
+    end
+    else if (cyc == 99) begin
       `checkh(crc, 64'hc77bb9b3784ea091);
       `checkh(sum, 64'h38c614665c6b71ad);
       $write("*-* All Finished *-*\n");

test_regress/t/t_trace_lib.v

@@ -5,56 +5,64 @@
 // SPDX-License-Identifier: CC0-1.0
 
 `ifdef TOP
-module t(
-   input clk
+module t (
+    input clk
 );
 
-   logic [7:0] in0 = 8'd020;
-   logic [7:0] in1 = 8'd100;
-   wire [7:0] out0;
-   wire [7:0] out1;
-   int count = 0;
+  logic [7:0] in0 = 8'd020;
+  logic [7:0] in1 = 8'd100;
+  wire [7:0] out0;
+  wire [7:0] out1;
+  int count = 0;
 
-   sub0 i_sub0(.clk(clk), .in(in0), .out(out0));
-   sub1 i_sub1(.clk(clk), .in(in1), .out(out1));
+  sub0 i_sub0 (
+      .clk(clk),
+      .in(in0),
+      .out(out0)
+  );
+  sub1 i_sub1 (
+      .clk(clk),
+      .in(in1),
+      .out(out1)
+  );
 
-   always_ff @(posedge clk) begin
-      count <= count + 1;
-      in0 <= in0 + 8'd1;
-      in1 <= in1 + 8'd2;
-      if (count == 3) begin
-         $write("*-* All Finished *-*\n");
-         $finish;
-      end
-   end
+  always_ff @(posedge clk) begin
+    count <= count + 1;
+    in0 <= in0 + 8'd1;
+    in1 <= in1 + 8'd2;
+    if (count == 3) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
+  end
 
 endmodule
 `endif
 
 `ifdef SUB0
-module sub0(
-   input wire clk,
-   input wire [7:0] in,
-   output wire [7:0] out
+module sub0 (
+    input wire clk,
+    input wire [7:0] in,
+    output wire [7:0] out
 );
 
-   logic [7:0] ff;
-   always_ff @(posedge clk) ff <= in + 8'd1;
-   assign out = ff;
+  logic [7:0] ff;
+  always_ff @(posedge clk) ff <= in + 8'd1;
+  assign out = ff;
 
 endmodule
 `endif
 
 `ifdef SUB1
-module sub1(
-   input wire clk,
-   input wire [7:0] in,
-   output wire [7:0] out
+module sub1 (
+    input wire clk,
+    input wire [7:0] in,
+    output wire [7:0] out
 );
 
-   logic [7:0] ff;
-   always_ff @(posedge clk) ff <= in + 8'd2;
-   assign out = ff;
+  logic [7:0] ff;
+  always_ff @(posedge clk) ff <= in + 8'd2;
+  assign out = ff;
 
 endmodule
 `endif