Fix coroutine trace setters (#7078 repair) (#7296)

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Igor Zaworski 2026-03-20 17:23:32 +01:00 committed by GitHub
parent 331cac2054
commit c3fc0d9f0f
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4 changed files with 82 additions and 4 deletions

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@ -467,10 +467,8 @@ class TraceVisitor final : public VNVisitor {
} else if (AstCFunc* const funcp = VN_CAST(insertp, CFunc)) {
// If there are awaits, insert the setter after each await
if (funcp->isCoroutine() && funcp->stmtsp()) {
funcp->stmtsp()->foreachAndNext([&](AstCAwait* awaitp) {
AstNode* stmtp = awaitp->backp();
while (VN_IS(stmtp, NodeExpr)) stmtp = stmtp->backp();
stmtp->addNextHere(setterp->cloneTree(false));
funcp->stmtsp()->foreachAndNext([setterp](AstCAwait* awaitp) {
awaitp->addNextHere(setterp->cloneTree(false));
});
}
funcp->addStmtsp(setterp);

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@ -0,0 +1,35 @@
$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module t $end
$var wire 129 " x [128:0] $end
$upscope $end
$enddefinitions $end
#1
b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "
#6
b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 "
#10
b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 "
#20
b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 "
#30
b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 "
#40
b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 "
#50
b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 "
#60
b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 "
#70
b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 "
#80
b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 "
#90
b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 "
#100
b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 "
#110
b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 "
#111

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@ -0,0 +1,20 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=['--binary', '--trace-vcd'])
test.execute()
test.vcd_identical(test.trace_filename, test.golden_filename)
test.passes()

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@ -0,0 +1,25 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 Antmicro
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t;
logic [128:0] x = 0;
always #10 x = ~x;
initial begin
#1;
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
$dumpvars();
#5;
x = 442093479423423857275364882039482723489;
#5;
#100;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule