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38
README.rst
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@ -4,19 +4,19 @@
|badge1| |badge2| |badge3| |badge4| |badge5| |badge7| |badge8|
.. |badge1| image:: https://img.shields.io/badge/Website-Verilator.org-181717.svg
:target: https://verilator.org
:target: https://verilator.org
.. |badge2| image:: https://img.shields.io/badge/License-LGPL%20v3-blue.svg
:target: https://www.gnu.org/licenses/lgpl-3.0
:target: https://www.gnu.org/licenses/lgpl-3.0
.. |badge3| image:: https://img.shields.io/badge/License-Artistic%202.0-0298c3.svg
:target: https://opensource.org/licenses/Artistic-2.0
:target: https://opensource.org/licenses/Artistic-2.0
.. |badge4| image:: https://repology.org/badge/tiny-repos/verilator.svg?header=distro%20packages
:target: https://repology.org/project/verilator/versions
:target: https://repology.org/project/verilator/versions
.. |badge5| image:: https://img.shields.io/docker/pulls/verilator/verilator
:target: https://hub.docker.com/r/verilator/verilator
:target: https://hub.docker.com/r/verilator/verilator
.. |badge7| image:: https://github.com/verilator/verilator/workflows/build/badge.svg
:target: https://github.com/verilator/verilator/actions?query=workflow%3Abuild
:target: https://github.com/verilator/verilator/actions?query=workflow%3Abuild
.. |badge8| image:: https://img.shields.io/github/actions/workflow/status/verilator/verilator/rtlmeter.yml?branch=master&event=schedule&label=benchmarks
:target: https://verilator.github.io/verilator-rtlmeter-results
:target: https://verilator.github.io/verilator-rtlmeter-results
Welcome to Verilator
@ -54,7 +54,7 @@ Welcome to Verilator
What Verilator Does
===================
Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It
Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It
"Verilates" the specified Verilog or SystemVerilog code by reading it,
performing lint checks, and optionally inserting assertion checks and
coverage-analysis points. It outputs single- or multithreaded .cpp and .h
@ -69,21 +69,21 @@ Verilated generated libraries, optionally encrypted, into other simulators.
Verilator may not be the best choice if you are expecting a full-featured
replacement for a closed-source Verilog simulator, need SDF annotation,
mixed-signal simulation, or are doing a quick class project (we recommend
`Icarus Verilog`_ for classwork). However, if you are looking for a path
to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of
`Icarus Verilog`_ for classwork). However, if you are looking for a path to
migrate SystemVerilog to C++/SystemC, or want high-speed simulation of
designs, Verilator is the tool for you.
Performance
===========
Verilator does not directly translate Verilog HDL to C++ or SystemC. Rather,
Verilator compiles your code into a much faster optimized and optionally
thread-partitioned model, which is in turn wrapped inside a C++/SystemC
module. The results are a compiled Verilog model that executes even on a
single thread over 10x faster than standalone SystemC, and on a single
thread is about 100 times faster than interpreted Verilog simulators such
as `Icarus Verilog`_. Another 2-10x speedup might be gained from
Verilator does not directly translate Verilog HDL to C++ or SystemC.
Rather, Verilator compiles your code into a much faster optimized and
optionally thread-partitioned model, which is in turn wrapped inside a
C++/SystemC module. The results are a compiled Verilog model that executes
even on a single thread over 10x faster than standalone SystemC, and on a
single thread is about 100 times faster than interpreted Verilog simulators
such as `Icarus Verilog`_. Another 2-10x speedup might be gained from
multithreading (yielding 200-1000x total over interpreted simulators).
Verilator has typically similar or better performance versus closed-source
@ -101,8 +101,8 @@ For more information:
- `Verilator installation and package directory structure
<https://verilator.org/install>`_
- `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_,
or `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_
- `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_, or
`Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_
- `Subscribe to Verilator announcements
<https://github.com/verilator/verilator-announce>`_

11
ci/docker/buildenv/README.rst
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@ -9,11 +9,11 @@ Verilator Build Docker Container
This Verilator Build Docker Container is set up to compile and test a
Verilator build. It uses the following parameters:
- Source repository (default: https://github.com/verilator/verilator)
- Source repository (default: https://github.com/verilator/verilator)
- Source revision (default: master)
- Source revision (default: master)
- Compiler (GCC 13.3.0, clang 18.1.3, default: 13.3.0)
- Compiler (GCC 13.3.0, clang 18.1.3, default: 13.3.0)
The container is published as ``verilator/verilator-buildenv`` on `docker
hub
@ -37,8 +37,9 @@ To change the compiler use the `-e` switch to pass environment variables:
docker run -ti -e CXX=clang++-18 verilator/verilator-buildenv test
The tests, that involve numactl are not working due to security restrictions.
To run those too, add the CAP_SYS_NICE capability during the start of the container:
The tests, that involve numactl are not working due to security
restrictions. To run those too, add the CAP_SYS_NICE capability during the
start of the container:
::

20
ci/docker/run/README.rst
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@ -11,12 +11,12 @@ easily as a docker image, e.g.:
docker run -ti verilator/verilator:latest --version
This will pull the container from `docker hub
<https://hub.docker.com/r/verilator/verilator>`_, run the latest Verilator and print
Verilator's version.
This will pull the container from `Docker Hub
<https://hub.docker.com/r/verilator/verilator>`_, run the latest Verilator
and print Verilator's version.
Containers are automatically built and pushed to docker hub for all released versions, so you may
easily compare results across versions, e.g.:
Containers are automatically built and pushed to docker hub for all
released versions, so you may easily compare results across versions, e.g.:
::
@ -38,7 +38,7 @@ or
./verilator-docker 4.030 --cc test.v
If you prefer not to use ``verilator-docker`` you must give the container
access to your files as a volume with appropriate user rights. For example
access to your files as a volume with appropriate user rights. For example
to Verilate test.v:
::
@ -68,9 +68,9 @@ Internals
The Dockerfile builds Verilator and removes the tree when completed to
reduce the image size. The entrypoint is a wrapper script
(``verilator-wrap.sh``). That script 1. calls Verilator, and 2. copies the
Verilated runtime files to the ``obj_dir`` or the ``-Mdir``
respectively. This allows the user to have the files to they may later
build the C++ output with the matching runtime files. The wrapper also
patches the Verilated Makefile accordingly.
Verilated runtime files to the ``obj_dir`` or the ``-Mdir`` respectively.
This allows the user to have the files to they may later build the C++
output with the matching runtime files. The wrapper also patches the
Verilated Makefile accordingly.
A hook is also defined and run by Docker Hub via automated builds.

28
docs/CONTRIBUTING.rst
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@ -23,8 +23,8 @@ Did you find a Verilator bug?
demonstrating the bug and expected behavior that is not occurring.
- The ideal example works against other simulators, and is in the
test_regress/t test format, as described in
`Verilator Internals Documentation
test_regress/t test format, as described in `Verilator Internals
Documentation
<https://github.com/verilator/verilator/blob/master/docs/internals.rst>`__.
@ -38,18 +38,18 @@ Did you write a patch that fixes a Verilator bug?
<https://github.com/verilator/verilator/pulls>`__.
- See the coding conventions, and other developer information in
``docs/internals.rst`` in the distribution, or as rendered at
`Verilator Internals Documentation
``docs/internals.rst`` in the distribution, or as rendered at `Verilator
Internals Documentation
<https://github.com/verilator/verilator/blob/master/docs/internals.rst>`__.
- Verilator uses GitHub Actions to provide continuous integration. You
may want to enable Actions on your GitHub branch to ensure your changes
keep the tests passing.
- Verilator uses GitHub Actions to provide continuous integration. You may
want to enable Actions on your GitHub branch to ensure your changes keep
the tests passing.
- Your source-code contributions must be certified as open source,
under the `Developer Certificate of
Origin <https://developercertificate.org/>`__. On your first
contribution, you must either:
- Your source-code contributions must be certified as open source, under
the `Developer Certificate of Origin
<https://developercertificate.org/>`__. On your first contribution, you
must either:
- Have your patch include the addition of your name to `docs/CONTRIBUTORS
<CONTRIBUTORS>`__ (preferred).
@ -75,9 +75,9 @@ Did you write a patch that fixes a Verilator bug?
Do you have questions on Verilator?
-----------------------------------
- Please see FAQ section and rest of the `Verilator
manual <https://verilator.org/verilator_doc.html>`__, or `Verilator
manual (PDF) <https://verilator.org/verilator_doc.pdf>`__.
- Please see FAQ section and rest of the `Verilator manual
<https://verilator.org/verilator_doc.html>`__, or `Verilator manual (PDF)
<https://verilator.org/verilator_doc.pdf>`__.
- Ask any question in the `Verilator forum
<https://verilator.org/forum>`__.

4
docs/README.rst
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@ -10,8 +10,8 @@ For formatted documentation see:
- `Verilator installation and package directory structure
<https://verilator.org/install>`_
- `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_,
or `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_
- `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_, or
`Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_
- `Subscribe to Verilator announcements
<https://github.com/verilator/verilator-announce>`_

5
docs/guide/changes.rst
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@ -5,12 +5,13 @@
Revision History
****************
.. COMMENT above header must use ### so there is an extra level of headers
..
COMMENT above header must use *** so there is an extra level of headers
here so the index won't show the huge list of revisions when clicking on
"Revision History" in the sidebar.
Changes are contained in the :file:`Changes` file of the distribution, and
also summarized below. To subscribe to new versions, see `Verilator
also summarized below. To subscribe to new versions, see `Verilator
Announcements <https://github.com/verilator/verilator-announce>`_.
.. include:: ../_build/gen/Changes

428
docs/guide/connecting.rst
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@ -11,13 +11,13 @@ Structure of the Verilated Model
================================
Verilator outputs a :file:`{prefix}.h` header file which defines a class
named :code:`{prefix}` which represents the generated model the user is
supposed to instantiate. This model class defines the interface of the
named ``{prefix}`` which represents the generated model the user is
supposed to instantiate. This model class defines the interface of the
Verilated model.
Verilator will additionally create a :file:`{prefix}.cpp` file, together
with additional .h and .cpp files for internals. See the :file:`examples`
directory in the kit for examples. See :ref:`Files Read/Written` for
with additional .h and .cpp files for internals. See the :file:`examples`
directory in the kit for examples. See :ref:`Files Read/Written` for
information on all the files Verilator might output.
The output of Verilator will contain a :file:`{prefix}.mk` file that may be
@ -32,91 +32,89 @@ model:
equivalents.
* Public top level module instances are exposed as pointers to allow access
to :code:`/* verilator public */` items.
to ``/* verilator public */`` items.
* The root of the design hierarchy (as in SystemVerilog :code:`$root`) is
exposed via the :code:`rootp` member pointer to allow access to model
internals, including :code:`/* verilator public_flat */` items.
* The root of the design hierarchy (as in SystemVerilog ``$root``) is
exposed via the ``rootp`` member pointer to allow access to model
internals, including ``/* verilator public_flat */`` items.
.. _porting from pre 4.210:
Model interface changes in version 4.210
------------------------------------------
----------------------------------------
Starting from version 4.210, the model class is an interface object.
Up until Verilator version 4.204 inclusive, the generated model class was
also the instance of the top level instance in the design hierarchy (what
you would refer to with :code:`$root` in SystemVerilog). This meant that
all internal variables that were implemented by Verilator in the root scope
were accessible as members of the model class itself. Note there were often
many such variable due to module inlining, including
:code:`/* verilator public_flat */` items.
you would refer to with ``$root`` in SystemVerilog). This meant that all
internal variables that were implemented by Verilator in the root scope
were accessible as members of the model class itself. Note there were often
many such variable due to module inlining, including ``/* verilator
public_flat */`` items.
This means that user code that accesses internal signals in the model
(likely including :code:`/* verilator public_flat */` signals, as they are
(likely including ``/* verilator public_flat */`` signals, as they are
often inlined into the root scope) will need to be updated as follows:
* No change required for accessing top level IO signals. These are directly
accessible in the model class via references.
* No change required for accessing :code:`/* verilator public */` items.
These are directly accessible via sub-module pointers in the model class.
* No change required for accessing ``/* verilator public */`` items. These
are directly accessible via sub-module pointers in the model class.
* Accessing any other internal members, including
:code:`/* verilator public_flat */` items requires the following changes:
``/* verilator public_flat */`` items requires the following changes:
* Additionally include :file:`{prefix}___024root.h`. This header defines
type of the :code:`rootp` pointer within the model class. Note the
:code:`__024` substring is the Verilator escape sequence for the
:code:`$` character, i.e.: :code:`rootp` points to the Verilated
SystemVerilog :code:`$root` scope.
type of the ``rootp`` pointer within the model class. Note the
``__024`` substring is the Verilator escape sequence for the ``$``
character, i.e.: ``rootp`` points to the Verilated SystemVerilog
``$root`` scope.
* Replace :code:`modelp->internal->member` references with
:code:`modelp->rootp->internal->member` references, which
contain one additional indirection via the :code:`rootp` pointer.
* Replace ``modelp->internal->member`` references with
``modelp->rootp->internal->member`` references, which contain one
additional indirection via the ``rootp`` pointer.
.. _connecting to C++:
.. _connecting to c++:
Connecting to C++
=================
In C++ output mode (:vlopt:`--cc`), the Verilator generated model class is a
simple C++ class. The user must write a C++ wrapper and main loop for the
In C++ output mode (:vlopt:`--cc`), the Verilator generated model class is
a simple C++ class. The user must write a C++ wrapper and main loop for the
simulation, which instantiates the model class, and link with the Verilated
model.
Refer to ``examples/make_tracing_c`` in the distribution for a detailed
commented example.
Top level IO signals are read and written as members of the model. You
call the model's :code:`eval()` method to evaluate the model. When the
simulation is complete call the model's :code:`final()` method to execute
any SystemVerilog final blocks, and complete any assertions. If using
:vlopt:`--timing`, there are two additional functions for checking if
there are any events pending in the simulation due to delays, and for
retrieving the simulation time of the next delayed event. See
:ref:`Evaluation Loop`.
Top level IO signals are read and written as members of the model. You call
the model's ``eval()`` method to evaluate the model. When the simulation is
complete call the model's ``final()`` method to execute any SystemVerilog
final blocks, and complete any assertions. If using :vlopt:`--timing`,
there are two additional functions for checking if there are any events
pending in the simulation due to delays, and for retrieving the simulation
time of the next delayed event. See :ref:`Evaluation Loop`.
Connecting to SystemC
=====================
In SystemC output mode (:vlopt:`--sc`), the Verilator generated model class
is a SystemC SC_MODULE. This module will attach directly into a SystemC
is a SystemC SC_MODULE. This module will attach directly into a SystemC
netlist as an instantiation.
The SC_MODULE gets the same pinout as the Verilog module, with the
following type conversions: Pins of a single bit become bool. Pins 2-32
bits wide become uint32_t's. Pins 33-64 bits wide become sc_bv's or
uint64_t's depending on the :vlopt:`--no-pins64` option. Wider pins
become sc_bv's. (Uints simulate the fastest so are used where possible.)
following type conversions: Pins of a single bit become bool. Pins 2-32
bits wide become uint32_t's. Pins 33-64 bits wide become sc_bv's or
uint64_t's depending on the :vlopt:`--no-pins64` option. Wider pins become
sc_bv's. (Uints simulate the fastest so are used where possible.)
Model internals, including lower level sub-modules are not pure SystemC
code. This is a feature, as using the SystemC pin interconnect scheme
code. This is a feature, as using the SystemC pin interconnect scheme
everywhere would reduce performance by an order of magnitude.
@ -124,41 +122,42 @@ Verilated API
=============
The API to a Verilated model is the C++ headers in the include/ directory
in the distribution. These headers use Doxygen comments, `///` and `//<`,
in the distribution. These headers use Doxygen comments, `///` and `//<`,
to indicate and document those functions that are part of the Verilated
public API.
Process-Level Clone APIs
--------------------------
------------------------
Modern operating systems support process-level clone (a.k.a copying, forking)
with system call interfaces in C/C++, e.g., :code:`fork()` in Linux.
Modern operating systems support process-level clone (a.k.a copying,
forking) with system call interfaces in C/C++, e.g., ``fork()`` in Linux.
However, after cloning a parent process, some resources cannot be inherited
in the child process. For example, in POSIX systems, when you fork a process,
the child process inherits all the memory of the parent process. However,
only the thread that called fork is replicated in the child process. Other
threads are not.
in the child process. For example, in POSIX systems, when you fork a
process, the child process inherits all the memory of the parent process.
However, only the thread that called fork is replicated in the child
process. Other threads are not.
Therefore, to support the process-level clone mechanisms, Verilator supports
:code:`prepareClone()` and :code:`atClone()` APIs to allow the user to manually
re-construct the model in the child process. The two APIs handle all necessary
resources required for releasing and re-initializing before and after cloning.
Therefore, to support the process-level clone mechanisms, Verilator
supports ``prepareClone()`` and ``atClone()`` APIs to allow the user to
manually re-construct the model in the child process. The two APIs handle
all necessary resources required for releasing and re-initializing before
and after cloning.
The two APIs are supported in the verilated models. Here is an example of usage
with Linux :code:`fork()` and :code:`pthread_atfork` APIs:
The two APIs are supported in the verilated models. Here is an example of
usage with Linux ``fork()`` and ``pthread_atfork`` APIs:
.. code-block:: C++
// static function pointers to fit pthread_atfork
static auto prepareClone = [](){ topp->prepareClone(); };
static auto atClone = [](){ topp->atClone(); };
// static function pointers to fit pthread_atfork
static auto prepareClone = [](){ topp->prepareClone(); };
static auto atClone = [](){ topp->atClone(); };
// in main function, register the handlers:
pthread_atfork(prepareClone, atClone, atClone);
// in main function, register the handlers:
pthread_atfork(prepareClone, atClone, atClone);
For better flexibility, you can also manually call the handlers before and
after :code:`fork()`.
after ``fork()``.
With the process-level clone APIs, users can create process-level snapshots
for the verilated models. While the Verilator save/restore option provides
@ -170,7 +169,7 @@ Direct Programming Interface (DPI)
==================================
Verilator supports SystemVerilog Direct Programming Interface import and
export statements. Only the SystemVerilog form ("DPI-C") is supported, not
export statements. Only the SystemVerilog form ("DPI-C") is supported, not
the original Synopsys-only DPI.
DPI Example
@ -181,76 +180,76 @@ Verilog, put in our.v:
.. code-block::
import "DPI-C" function int add (input int a, input int b);
import "DPI-C" function int add (input int a, input int b);
initial begin
$display("%x + %x = %x", 1, 2, add(1,2));
endtask
initial begin
$display("%x + %x = %x", 1, 2, add(1,2));
endtask
Then after Verilating, Verilator will create a file Vour__Dpi.h with the
prototype to call this function:
.. code-block:: C++
extern int add(int a, int b);
extern int add(int a, int b);
From the sc_main.cpp file (or another .cpp file passed to the Verilator
command line, or the link), you'd then:
.. code-block:: C++
#include "svdpi.h"
#include "Vour__Dpi.h"
int add(int a, int b) { return a+b; }
#include "svdpi.h"
#include "Vour__Dpi.h"
int add(int a, int b) { return a+b; }
DPI System Task/Functions
-------------------------
Verilator extends the DPI format to allow using the same scheme to
efficiently add system functions. Use a dollar-sign prefixed system
efficiently add system functions. Use a dollar-sign prefixed system
function name for the import, but note it must be escaped.
.. code-block:: sv
export "DPI-C" function integer \$myRand;
export "DPI-C" function integer \$myRand;
initial $display("myRand=%d", $myRand());
initial $display("myRand=%d", $myRand());
Going the other direction, you can export Verilog tasks so they can be
called from C++:
.. code-block:: sv
export "DPI-C" task publicSetBool;
export "DPI-C" task publicSetBool;
task publicSetBool;
input bit in_bool;
var_bool = in_bool;
endtask
task publicSetBool;
input bit in_bool;
var_bool = in_bool;
endtask
Then after Verilating, Verilator will create a file Vour__Dpi.h with the
prototype to call this function:
.. code-block:: C++
extern void publicSetBool(svBit in_bool);
extern void publicSetBool(svBit in_bool);
From the sc_main.cpp file, you'd then:
.. code-block:: C++
#include "Vour__Dpi.h"
publicSetBool(value);
#include "Vour__Dpi.h"
publicSetBool(value);
Or, alternatively, call the function under the design class. This isn't
DPI compatible but is easier to read and better supports multiple designs.
Or, alternatively, call the function under the design class. This isn't DPI
compatible but is easier to read and better supports multiple designs.
.. code-block:: C++
#include "Vour__Dpi.h"
Vour::publicSetBool(value);
// or top->publicSetBool(value);
#include "Vour__Dpi.h"
Vour::publicSetBool(value);
// or top->publicSetBool(value);
Note that if the DPI task or function accesses any register or net within
the RTL, it will require a scope to be set. This can be done using the
@ -263,11 +262,11 @@ with respect to that top level module, then the scope could be set with
.. code-block:: C++
#include "svdpi.h"
...
const svScope scope = svGetScopeFromName("TOP.dut");
assert(scope); // Check for nullptr if scope not found
svSetScope(scope);
#include "svdpi.h"
...
const svScope scope = svGetScopeFromName("TOP.dut");
assert(scope); // Check for nullptr if scope not found
svSetScope(scope);
(Remember that Verilator adds a "TOP" to the top of the module hierarchy.)
@ -282,24 +281,24 @@ DPI Imports that access signals
If a DPI import accesses a signal through the VPI Verilator will not be
able to know what variables are accessed and may schedule the code
inappropriately. Ideally pass the values as inputs/outputs so the VPI is
not required. Alternatively a workaround is to use a non-inlined task as a
inappropriately. Ideally pass the values as inputs/outputs so the VPI is
not required. Alternatively a workaround is to use a non-inlined task as a
wrapper:
.. code-block::
logic din;
logic din;
// This DPI function will read "din"
import "DPI-C" context function void dpi_that_accesses_din();
// This DPI function will read "din"
import "DPI-C" context function void dpi_that_accesses_din();
always @(...)
dpi_din_args(din);
always @(...)
dpi_din_args(din);
task dpi_din_args(input din);
// verilator no_inline_task
dpi_that_accesses_din();
endtask
task dpi_din_args(input din);
// verilator no_inline_task
dpi_that_accesses_din();
endtask
DPI Display Functions
@ -309,8 +308,8 @@ Verilator allows writing $display like functions using this syntax:
.. code-block::
import "DPI-C" function void
\$my_display(input string formatted /*verilator sformat*/ );
import "DPI-C" function void
\$my_display(input string formatted /*verilator sformat*/ );
The :option:`/*verilator&32;sformat*/` metacomment indicates that this
function accepts a $display like format specifier followed by any number of
@ -320,14 +319,14 @@ arguments to satisfy the format.
DPI Context Functions
---------------------
Verilator supports IEEE DPI Context Functions. Context imports pass the
Verilator supports IEEE DPI Context Functions. Context imports pass the
simulator context, including calling scope name, and filename and line
number to the C code. For example, in Verilog:
number to the C code. For example, in Verilog:
.. code-block::
import "DPI-C" context function int dpic_line();
initial $display("This is line %d, again, line %d\n", `line, dpic_line());
import "DPI-C" context function int dpic_line();
initial $display("This is line %d, again, line %d\n", `line, dpic_line());
This will call C++ code which may then use the svGet\* functions to read
information, in this case the line number of the Verilog statement that
@ -335,22 +334,22 @@ invoked the dpic_line function:
.. code-block:: C++
int dpic_line() {
// Get a scope: svScope scope = svGetScope();
int dpic_line() {
// Get a scope: svScope scope = svGetScope();
const char* scopenamep = svGetNameFromScope(scope);
assert(scopenamep);
const char* scopenamep = svGetNameFromScope(scope);
assert(scopenamep);
const char* filenamep = "";
int lineno = 0;
if (svGetCallerInfo(&filenamep, &lineno)) {
printf("dpic_line called from scope %s on line %d\n",
scopenamep, lineno);
return lineno;
} else {
return 0;
}
}
const char* filenamep = "";
int lineno = 0;
if (svGetCallerInfo(&filenamep, &lineno)) {
printf("dpic_line called from scope %s on line %d\n",
scopenamep, lineno);
return lineno;
} else {
return 0;
}
}
See the IEEE Standard for more information.
@ -359,13 +358,12 @@ DPI Header Isolation
--------------------
Verilator places the IEEE standard header files such as svdpi.h into a
separate include directory, vltstd (VeriLaTor STandarD). When compiling
separate include directory, vltstd (VeriLaTor STandarD). When compiling
most applications $VERILATOR_ROOT/include/vltstd would be in the include
path along with the normal $VERILATOR_ROOT/include. However, when
compiling Verilated models into other simulators which have their own
svdpi.h and similar standard files with different contents, the vltstd
directory should not be included to prevent picking up incompatible
definitions.
path along with the normal $VERILATOR_ROOT/include. However, when compiling
Verilated models into other simulators which have their own svdpi.h and
similar standard files with different contents, the vltstd directory should
not be included to prevent picking up incompatible definitions.
Public Functions
@ -378,24 +376,23 @@ are slightly faster, but less compatible.
Verification Procedural Interface (VPI)
=======================================
Verilator supports a limited subset of the VPI. This subset allows
Verilator supports a limited subset of the VPI. This subset allows
inspection, examination, value change callbacks, and depositing of values
to public signals only.
VPI is enabled with the Verilator :vlopt:`--vpi` option.
To access signals via the VPI, Verilator must be told exactly which signals
are to be accessed. This is done using the Verilator public pragmas
are to be accessed. This is done using the Verilator public pragmas
documented below.
Verilator has an important difference from an event based simulator; signal
values that are changed by the VPI will not immediately propagate their
values, instead the top level header file's :code:`eval()` method must be
called. Normally this would be part of the normal evaluation (i.e. the
next clock edge), not as part of the value change. This makes the
performance of VPI routines extremely fast compared to event based
simulators, but can confuse some test-benches that expect immediate
propagation.
values, instead the top level header file's ``eval()`` method must be
called. Normally this would be part of the normal evaluation (i.e. the next
clock edge), not as part of the value change. This makes the performance of
VPI routines extremely fast compared to event based simulators, but can
confuse some test-benches that expect immediate propagation.
Note the VPI by its specified implementation will always be much slower
than accessing the Verilator values by direct reference
@ -405,17 +402,18 @@ while the direct references are evaluated by the compiler and result in
only a couple of instructions.
For signal callbacks to work the main loop of the program must call
:code:`VerilatedVpi::callValueCbs()`.
``VerilatedVpi::callValueCbs()``.
Verilator also tracks when the model state has been modified via the VPI with
an :code:`evalNeeded` flag. This flag can be checked with :code:`VerilatedVpi::evalNeeded()`
and it can be cleared with :code:`VerilatedVpi::clearEvalNeeded()`. Used together
it is possible to skip :code:`eval()` calls if no model state has been changed
since the last :code:`eval()`.
Verilator also tracks when the model state has been modified via the VPI
with an ``evalNeeded`` flag. This flag can be checked with
``VerilatedVpi::evalNeeded()`` and it can be cleared with
``VerilatedVpi::clearEvalNeeded()``. Used together it is possible to skip
``eval()`` calls if no model state has been changed since the last
``eval()``.
Any data written via :code:`vpi_put_value` with :code:`vpiInertialDelay` will
be deferred for later. These delayed values can be flushed to the model with
:code:`VerilatedVpi::doInertialPuts()`.
Any data written via ``vpi_put_value`` with ``vpiInertialDelay`` will be
deferred for later. These delayed values can be flushed to the model with
``VerilatedVpi::doInertialPuts()``.
.. _vpi example:
@ -424,62 +422,62 @@ VPI Example
-----------
In the below example, we have readme marked read-only, and writeme marked
read-write which if written from outside the model will have the same semantics
as if it was a top level input.
read-write which if written from outside the model will have the same
semantics as if it was a top level input.
.. code-block:: bash
cat >our.v <<'EOF'
module our #(
parameter WIDTH /*verilator public_flat_rd*/ = 32
) (input clk);
reg [WIDTH-1:0] readme /*verilator public_flat_rd*/;
reg [WIDTH-1:0] writeme /*verilator public_flat_rw*/;
initial $finish;
endmodule
EOF
cat >our.v <<'EOF'
module our #(
parameter WIDTH /*verilator public_flat_rd*/ = 32
) (input clk);
reg [WIDTH-1:0] readme /*verilator public_flat_rd*/;
reg [WIDTH-1:0] writeme /*verilator public_flat_rw*/;
initial $finish;
endmodule
EOF
There are many online tutorials and books on the VPI, but an example that
accesses the above signal "readme" would be:
.. code-block:: bash
cat >sim_main.cpp <<'EOF'
#include "Vour.h"
#include "verilated.h"
#include "verilated_vpi.h" // Required to get definitions
cat >sim_main.cpp <<'EOF'
#include "Vour.h"
#include "verilated.h"
#include "verilated_vpi.h" // Required to get definitions
uint64_t main_time = 0; // See comments in first example
double sc_time_stamp() { return main_time; }
uint64_t main_time = 0; // See comments in first example
double sc_time_stamp() { return main_time; }
void read_and_check() {
vpiHandle vh1 = vpi_handle_by_name((PLI_BYTE8*)"TOP.our.readme", NULL);
if (!vh1) vl_fatal(__FILE__, __LINE__, "sim_main", "No handle found");
const char* name = vpi_get_str(vpiName, vh1);
const char* type = vpi_get_str(vpiType, vh1);
const int size = vpi_get(vpiSize, vh1);
printf("register name: %s, type: %s, size: %d\n", name, type, size); // Prints "register name: readme, type: vpiReg, size: 32"
void read_and_check() {
vpiHandle vh1 = vpi_handle_by_name((PLI_BYTE8*)"TOP.our.readme", NULL);
if (!vh1) vl_fatal(__FILE__, __LINE__, "sim_main", "No handle found");
const char* name = vpi_get_str(vpiName, vh1);
const char* type = vpi_get_str(vpiType, vh1);
const int size = vpi_get(vpiSize, vh1);
printf("register name: %s, type: %s, size: %d\n", name, type, size); // Prints "register name: readme, type: vpiReg, size: 32"
s_vpi_value v;
v.format = vpiIntVal;
vpi_get_value(vh1, &v);
printf("Value of %s: %d\n", name, v.value.integer); // Prints "Value of readme: 0"
}
s_vpi_value v;
v.format = vpiIntVal;
vpi_get_value(vh1, &v);
printf("Value of %s: %d\n", name, v.value.integer); // Prints "Value of readme: 0"
}
int main(int argc, char** argv) {
Verilated::commandArgs(argc, argv);
const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
const std::unique_ptr<Vour> top{new Vour{contextp.get()}};
int main(int argc, char** argv) {
Verilated::commandArgs(argc, argv);
const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
const std::unique_ptr<Vour> top{new Vour{contextp.get()}};
contextp->internalsDump(); // See scopes to help debug
while (!contextp->gotFinish()) {
top->eval();
VerilatedVpi::callValueCbs(); // For signal callbacks
read_and_check();
}
return 0;
}
EOF
contextp->internalsDump(); // See scopes to help debug
while (!contextp->gotFinish()) {
top->eval();
VerilatedVpi::callValueCbs(); // For signal callbacks
read_and_check();
}
return 0;
}
EOF
.. _evaluation loop:
@ -488,49 +486,47 @@ Wrappers and Model Evaluation Loop
==================================
When using SystemC, evaluation of the Verilated model is managed by the
SystemC kernel, and for the most part can be ignored. When using C++, the
user must call :code:`eval()`, or :code:`eval_step()` and
:code:`eval_end_step()`.
SystemC kernel, and for the most part can be ignored. When using C++, the
user must call ``eval()``, or ``eval_step()`` and ``eval_end_step()``.
1. When there is a single design instantiated at the C++ level that needs
to evaluate within a given context, call :code:`designp->eval()`.
to evaluate within a given context, call ``designp->eval()``.
2. When there are multiple designs instantiated at the C++ level that need
to evaluate within a context, call :code:`first_designp->eval_step()` then
:code:`->eval_step()` on all other designs. Then call
:code:`->eval_end_step()` on the first design then all other designs. If
there is only a single design, you would call :code:`eval_step()` then
:code:`eval_end_step()`; in fact :code:`eval()` described above is just a
wrapper which calls these two functions.
to evaluate within a context, call ``first_designp->eval_step()`` then
``->eval_step()`` on all other designs. Then call ``->eval_end_step()`` on
the first design then all other designs. If there is only a single design,
you would call ``eval_step()`` then ``eval_end_step()``; in fact ``eval()``
described above is just a wrapper which calls these two functions.
3. If using delays and :vlopt:`--timing`, there are two additional methods
the user should call:
* :code:`designp->eventsPending()`, which returns :code:`true` if there are
* ``designp->eventsPending()``, which returns ``true`` if there are
any delayed events pending,
* :code:`designp->nextTimeSlot()`, which returns the simulation time of the
* ``designp->nextTimeSlot()``, which returns the simulation time of the
next delayed event. This method can only be called if
:code:`designp->eventsPending()` returned :code:`true`.
``designp->eventsPending()`` returned ``true``.
Call :code:`eventsPending()` to check if you should continue with the
simulation, and then :code:`nextTimeSlot()` to move simulation time forward.
Call ``eventsPending()`` to check if you should continue with the
simulation, and then ``nextTimeSlot()`` to move simulation time forward.
:vlopt:`--main` can be used with :vlopt:`--timing` to generate a basic example
of a timing-enabled eval loop.
When :code:`eval()` (or :code:`eval_step()`) is called Verilator looks for
changes in clock signals and evaluates related sequential always blocks,
such as computing always_ff @ (posedge...) outputs. With :vlopt:`--timing`, it
When ``eval()`` (or ``eval_step()``) is called Verilator looks for changes
in clock signals and evaluates related sequential always blocks, such as
computing always_ff @ (posedge...) outputs. With :vlopt:`--timing`, it
resumes any delayed processes awaiting the current simulation time. Then
Verilator evaluates combinational logic.
Note combinatorial logic is not computed before sequential always blocks
are computed (for speed reasons). Therefore it is best to set any non-clock
inputs up with a separate :code:`eval()` call before changing clocks.
inputs up with a separate ``eval()`` call before changing clocks.
Alternatively, if all always_ff statements use only the posedge of clocks,
or all inputs go directly to always_ff statements, as is typical, then you
can change non-clock inputs on the negative edge of the input clock, which
will be faster as there will be fewer :code:`eval()` calls.
will be faster as there will be fewer ``eval()`` calls.
For more information on evaluation, see :file:`docs/internals.rst` in the
distribution.
@ -540,18 +536,18 @@ Verilated and VerilatedContext
==============================
Multiple C++ Verilated models may be part of the same simulation context,
that is share a VPI interface, sense of time, and common settings. This
that is share a VPI interface, sense of time, and common settings. This
common simulation context information is stored in a ``VerilatedContext``
structure. If a ``VerilatedContext`` is not created prior to creating a
model, a default global one is created automatically. SystemC requires
structure. If a ``VerilatedContext`` is not created prior to creating a
model, a default global one is created automatically. SystemC requires
using only the single, default VerilatedContext.
The ``Verilated::`` methods, including the ``Verilated::commandArgs`` call
shown above, call VerilatedContext methods using the default global
VerilatedContext. (Technically they operate on the last one used by a
given thread.) If you are using multiple simulation contexts you should
not use the Verilated:: methods, and instead always use VerilatedContext
methods called on the appropriate VerilatedContext object.
VerilatedContext. (Technically they operate on the last one used by a given
thread.) If you are using multiple simulation contexts you should not use
the Verilated:: methods, and instead always use VerilatedContext methods
called on the appropriate VerilatedContext object.
For methods available under Verilated and VerilatedContext see
:file:`include/verilated.h` in the distribution.

43
docs/guide/contributing.rst
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@ -19,47 +19,47 @@ Reporting Bugs
First, check the :ref:`Language Limitations` section.
Next, try the :vlopt:`--debug` option. This will enable additional
internal assertions, and may help identify the problem.
Next, try the :vlopt:`--debug` option. This will enable additional internal
assertions, and may help identify the problem.
Finally, reduce your code to the smallest possible routine that exhibits
the bug (see: :ref:`Minimizing bug-inducing code`). Even better, create
a test in the :file:`test_regress/t` directory, as follows:
the bug (see: :ref:`Minimizing bug-inducing code`). Even better, create a
test in the :file:`test_regress/t` directory, as follows:
.. code-block:: bash
cd test_regress
cp -p t/t_EXAMPLE.py t/t_BUG.py
cp -p t/t_EXAMPLE.v t/t_BUG.v
cd test_regress
cp -p t/t_EXAMPLE.py t/t_BUG.py
cp -p t/t_EXAMPLE.v t/t_BUG.v
There are many hints on how to write a good test in the
:file:`test_regress/driver.py` documentation which can be seen by running:
.. code-block:: bash
cd $VERILATOR_ROOT # Need the original distribution kit
test_regress/driver.py --help
cd $VERILATOR_ROOT # Need the original distribution kit
test_regress/driver.py --help
Edit :file:`t/t_BUG.py` to suit your example; you can do anything you want
in the Verilog code there; just make sure it retains the single clk input
and no outputs. Now, the following should fail:
and no outputs. Now, the following should fail:
.. code-block:: bash
cd $VERILATOR_ROOT # Need the original distribution kit
cd test_regress
t/t_BUG.py # Run on Verilator
t/t_BUG.py --debug # Run on Verilator, passing --debug to Verilator
t/t_BUG.py --vcs # Run on VCS simulator
t/t_BUG.py --nc|--iv|--ghdl # Likewise on other simulators
cd $VERILATOR_ROOT # Need the original distribution kit
cd test_regress
t/t_BUG.py # Run on Verilator
t/t_BUG.py --debug # Run on Verilator, passing --debug to Verilator
t/t_BUG.py --vcs # Run on VCS simulator
t/t_BUG.py --nc|--iv|--ghdl # Likewise on other simulators
The test driver accepts a number of options, many of which mirror the main
Verilator options. For example the previous test could have been run with
debugging enabled. The full set of test options can be seen by running
debugging enabled. The full set of test options can be seen by running
:command:`driver.py --help` as shown above.
Finally, report the bug at `Verilator Issues
<https://verilator.org/issues>`_. The bug will become publicly visible; if
<https://verilator.org/issues>`_. The bug will become publicly visible; if
this is unacceptable, mail the bug report to ``wsnyder@wsnyder.org``.
.. _minimizing bug-inducing code:
@ -73,12 +73,12 @@ caused by a complex interaction of many parts of the design, and it is not
clear which parts are necessary to reproduce the bug. In these cases, an
Open Source tool called `sv-bugpoint
<https://github.com/antmicro/sv-bugpoint>`_ can be used to automatically
reduce a SystemVerilog design to the smallest possible reproducer.
It can be used to automatically reduce a design with hundreds of thousands of
reduce a SystemVerilog design to the smallest possible reproducer. It can
be used to automatically reduce a design with hundreds of thousands of
lines to a minimal test case while preserving the bug-inducing behavior.
With :vlopt:`--debug` or :vlopt:`--dump-inputs`, Verilator will write a
*{prefix}*\ __inputs\ .vpp file which has all of the individual input files
*{prefix}*\ __inputs.vpp file which has all of the individual input files
combined and pre-processed, this is often useful as the input design into
`sv-bugpoint`.
@ -88,4 +88,5 @@ information on how to use `sv-bugpoint`.
.. Contributing
.. ============
.. include:: ../CONTRIBUTING.rst

20
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View File

@ -177,24 +177,24 @@ Historical Origins
==================
Verilator was conceived in 1994 by Paul Wasson at the Core Logic Group at
Digital Equipment Corporation. The Verilog code that was converted to C
was then merged with a C-based CPU model of the Alpha processor and
simulated in a C-based environment called CCLI.
Digital Equipment Corporation. The Verilog code that was converted to C was
then merged with a C-based CPU model of the Alpha processor and simulated
in a C-based environment called CCLI.
In 1995 Verilator started being used for Multimedia and Network Processor
development inside Digital. Duane Galbi took over the active development
of Verilator, and added several performance enhancements, and CCLI was
still being used as the shell.
development inside Digital. Duane Galbi took over the active development of
Verilator, and added several performance enhancements, and CCLI was still
being used as the shell.
In 1998, through the efforts of existing DECies, mainly Duane Galbi,
Digital graciously agreed to release the source code. (Subject to the code
Digital graciously agreed to release the source code. (Subject to the code
not being resold, which is compatible with the GNU Public License.)
In 2001, Wilson Snyder took the kit, added a SystemC mode, and called
it Verilator2. This was the first packaged public release.
In 2001, Wilson Snyder took the kit, added a SystemC mode, and called it
Verilator2. This was the first packaged public release.
In 2002, Wilson Snyder created Verilator 3.000 by rewriting Verilator from
scratch in C++. This added many optimizations, yielding about a 2-5x
scratch in C++. This added many optimizations, yielding about a 2-5x
performance gain.
In 2009, major SystemVerilog and DPI language support was added.

3
docs/guide/copyright.rst
View File

@ -5,8 +5,7 @@
Copyright
*********
The latest version of Verilator is available from `https://verilator.org
<https://verilator.org>`_.
The latest version of Verilator is available from https://verilator.org.
Copyright 2003-2025 by Wilson Snyder. This program is free software; you
can redistribute it and/or modify the Verilator internals under the terms

29
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View File

@ -7,22 +7,23 @@ Deprecations
The following deprecated items are scheduled for future removal:
C++14 compiler support
Verilator currently requires a C++20 or newer compiler for timing, and a
C++14 or newer compiler for both compiling Verilator and compiling
Verilated models with --no-timing.
Verilator currently requires a C++20 or newer compiler for timing, and a
C++14 or newer compiler for both compiling Verilator and compiling
Verilated models with --no-timing.
Verilator will require C++20 or newer compilers for both compiling
Verilator and compiling all Verilated models no sooner than May 2025.
(Likely to be removed shortly after GitHub removes Ubuntu 20.04
continuous-integration action runners, which are used to test the older
C++ standard).
Verilator will require C++20 or newer compilers for both compiling
Verilator and compiling all Verilated models no sooner than May 2025.
(Likely to be removed shortly after GitHub removes Ubuntu 20.04
continuous-integration action runners, which are used to test the older
C++ standard).
XML output
Verilator currently supports XML parser output (enabled with `--xml-only`).
Support for `--xml-*` options will be deprecated no sooner than January 2026.
Verilator currently supports XML parser output (enabled with
`--xml-only`). Support for `--xml-*` options will be deprecated no
sooner than January 2026.
`--make cmake`
The `--make cmake` options is deprecated and will be removed no sooner than
January 2026. Use `--make json` instead. Note that the CMake integration
shipping with Verilator (verilator-config.mk) already uses `--make json` so
no changes are necessary if using that.
The `--make cmake` options is deprecated and will be removed no sooner
than January 2026. Use `--make json` instead. Note that the CMake
integration shipping with Verilator (verilator-config.mk) already uses
`--make json` so no changes are necessary if using that.

64
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@ -10,14 +10,14 @@ associated programs.
.. option:: LD_LIBRARY_PATH
A generic Linux/OS variable specifying what directories have shared
object (.so) files. This path should include SystemC and other
shared objects needed at simulation runtime.
object (.so) files. This path should include SystemC and other shared
objects needed at simulation runtime.
.. option:: MAKE
Names the executable of the make command invoked when using the
:vlopt:`--build` option. Some operating systems may require "gmake" to
this variable to launch GNU make. If this variable is not specified,
:vlopt:`--build` option. Some operating systems may require "gmake" to
this variable to launch GNU make. If this variable is not specified,
"make" is used.
.. option:: MAKEFLAGS
@ -29,33 +29,33 @@ associated programs.
.. option:: OBJCACHE
Optionally specifies a caching or distribution program to place in front
of all runs of the C++ compiler. For example, "ccache" or "sccache". If using
:command:`distcc` or :command:`icecc`/:command:`icecream`, they would
generally be run under :command:`ccache`; see the documentation for
those programs. If OBJCACHE is not set, and at configure time ccache
of all runs of the C++ compiler. For example, "ccache" or "sccache". If
using :command:`distcc` or :command:`icecc`/:command:`icecream`, they
would generally be run under :command:`ccache`; see the documentation
for those programs. If OBJCACHE is not set, and at configure time ccache
was present, ccache will be used as a default.
.. option:: SYSTEMC
Deprecated. Used only if :option:`SYSTEMC_INCLUDE` or
:option:`SYSTEMC_LIBDIR` is not set. If set, specifies the directory
containing the SystemC distribution. If not specified, it will come
from a default optionally specified at configure time (before Verilator
was compiled).
Deprecated. Used only if :option:`SYSTEMC_INCLUDE` or
:option:`SYSTEMC_LIBDIR` is not set. If set, specifies the directory
containing the SystemC distribution. If not specified, it will come from
a default optionally specified at configure time (before Verilator was
compiled).
.. option:: SYSTEMC_ARCH
Deprecated. Used only if :option:`SYSTEMC_LIBDIR` is not set.
Specifies the architecture name used by the SystemC kit. This is the
part after the dash in the "lib-{...}" directory name created by a
:command:`make` in the SystemC distribution. If not set, Verilator will
try to intuit the proper setting, or use the default optionally
specified at configure time (before Verilator was compiled).
Deprecated. Used only if :option:`SYSTEMC_LIBDIR` is not set. Specifies
the architecture name used by the SystemC kit. This is the part after
the dash in the "lib-{...}" directory name created by a :command:`make`
in the SystemC distribution. If not set, Verilator will try to intuit
the proper setting, or use the default optionally specified at configure
time (before Verilator was compiled).
.. option:: SYSTEMC_CXX_FLAGS
Specifies additional flags that are required to be passed to GCC when
building the SystemC model. System 2.3.0 may need this set to
building the SystemC model. System 2.3.0 may need this set to
"-pthread".
.. option:: SYSTEMC_INCLUDE
@ -67,27 +67,27 @@ associated programs.
.. option:: SYSTEMC_LIBDIR
If set, specifies the directory containing the libsystemc.a library. If
If set, specifies the directory containing the libsystemc.a library. If
not specified, it will come from a default optionally specified at
configure time (before Verilator was compiled), or computed from
SYSTEMC/lib-SYSTEMC_ARCH.
.. option:: VERILATOR_BIN
If set, specifies an alternative name of the ``verilator`` binary. May
If set, specifies an alternative name of the ``verilator`` binary. May
be used for debugging and selecting between multiple operating system
builds.
.. option:: VERILATOR_COVERAGE_BIN
If set, specifies an alternative name of the ``verilator_coverage``
binary. May be used for debugging and selecting between multiple
binary. May be used for debugging and selecting between multiple
operating system builds.
.. option:: VERILATOR_GDB
If set, the command to run when using the :vlopt:`--gdb` option, such as
"ddd". If not specified, it will use "gdb".
"ddd". If not specified, it will use "gdb".
.. option:: VERILATOR_ROOT
@ -110,7 +110,7 @@ associated programs.
If you are using a pre-compiled Verilator package, you should not need
to set ``VERILATOR_ROOT`` - the value embedded in the binary should be
correct. In fact this option *does not work* with Verilator packages
correct. In fact this option *does not work* with Verilator packages
that have been installed with ``make install``. If a Verilator package
has been installed using ``./configure --prefix=/some/path && make
install`` and then moved to another location, you cannot use
@ -121,13 +121,15 @@ associated programs.
.. option:: VERILATOR_SOLVER
If set, the command to run as a constrained randomization backend, such
as :command:`cvc4 --lang=smt2 --incremental`. If not specified, it will use
the one supplied or found during configure, or :command:`z3 --in` if empty.
as :command:`cvc4 --lang=smt2 --incremental`. If not specified, it will
use the one supplied or found during configure, or :command:`z3 --in` if
empty.
.. option:: VERILATOR_VALGRIND
If set, the command to run when using the :vlopt:`--valgrind` option, such as
"valgrind --tool=callgrind". If not specified, it will use "valgrind".
If set, the command to run when using the :vlopt:`--valgrind` option,
such as "valgrind --tool=callgrind". If not specified, it will use
"valgrind".
Make Variables
@ -146,7 +148,7 @@ set by passing them to make e.g. ``make CXX=my-gcc ...``.
Optionally overrides the default compiler binary used by the Verilated
makefiles. If CXX is not set, the version found at configure time is
used. Note the default flags passed to the compiler are determined at
used. Note the default flags passed to the compiler are determined at
configuration time, so changing the CXX compiler version using this
variable, as opposed to passing it at configuration time, may not give
desired results.
@ -155,7 +157,7 @@ set by passing them to make e.g. ``make CXX=my-gcc ...``.
Optionally overrides the default linker binary used by the Verilated
makefiles. If LINK is not set, the version found at configure time is
used. Note the default flags passed to the linker are determined at
used. Note the default flags passed to the linker are determined at
configuration time, so changing the LINK version using this variable, as
opposed to passing it at configuration time, may not give desired
results.

32
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@ -6,9 +6,9 @@
Example Create-Binary Execution
===============================
We'll compile this SystemVerilog example into a Verilated simulation binary. For
an example that discusses the next level of detail see :ref:`Example C++
Execution`.
We'll compile this SystemVerilog example into a Verilated simulation
binary. For an example that discusses the next level of detail see
:ref:`Example C++ Execution`.
.. include:: example_common_install.rst
@ -16,20 +16,20 @@ Now, let's create an example Verilog file:
.. code-block:: bash
mkdir test_our
cd test_our
mkdir test_our
cd test_our
cat >our.v <<'EOF'
module our;
initial begin $display("Hello World"); $finish; end
endmodule
EOF
cat >our.v <<'EOF'
module our;
initial begin $display("Hello World"); $finish; end
endmodule
EOF
Now we run Verilator on our little example.
.. code-block:: bash
verilator --binary -j 0 -Wall our.v
verilator --binary -j 0 -Wall our.v
Breaking this command down:
@ -48,16 +48,16 @@ And now we run it:
.. code-block:: bash
obj_dir/Vour
obj_dir/Vour
And we get as output:
.. code-block:: bash
Hello World
- our.v:2: Verilog $finish
Hello World
- our.v:2: Verilog $finish
You're better off using a Makefile to run the steps for you, so when your
source changes, it will automatically run all of the appropriate steps. To
aid this, Verilator can create a makefile dependency file. For examples
source changes, it will automatically run all of the appropriate steps. To
aid this, Verilator can create a makefile dependency file. For examples
that do this, see the :file:`examples` directory in the distribution.

56
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@ -6,7 +6,7 @@
Example C++ Execution
=====================
We'll compile this example into C++. For an extended and commented version
We'll compile this example into C++. For an extended and commented version
of what this C++ code is doing, see
:file:`examples/make_tracing_c/sim_main.cpp` in the distribution.
@ -16,34 +16,34 @@ Now, let's create an example Verilog and C++ wrapper file:
.. code-block:: bash
mkdir test_our
cd test_our
mkdir test_our
cd test_our
cat >our.v <<'EOF'
module our;
initial begin $display("Hello World"); $finish; end
endmodule
EOF
cat >our.v <<'EOF'
module our;
initial begin $display("Hello World"); $finish; end
endmodule
EOF
cat >sim_main.cpp <<'EOF'
#include "Vour.h"
#include "verilated.h"
int main(int argc, char** argv) {
VerilatedContext* contextp = new VerilatedContext;
contextp->commandArgs(argc, argv);
Vour* top = new Vour{contextp};
while (!contextp->gotFinish()) { top->eval(); }
delete top;
delete contextp;
return 0;
}
EOF
cat >sim_main.cpp <<'EOF'
#include "Vour.h"
#include "verilated.h"
int main(int argc, char** argv) {
VerilatedContext* contextp = new VerilatedContext;
contextp->commandArgs(argc, argv);
Vour* top = new Vour{contextp};
while (!contextp->gotFinish()) { top->eval(); }
delete top;
delete contextp;
return 0;
}
EOF
Now we run Verilator on our little example;
.. code-block:: bash
verilator --cc --exe --build -j 0 -Wall sim_main.cpp our.v
verilator --cc --exe --build -j 0 -Wall sim_main.cpp our.v
Breaking this command down:
@ -70,7 +70,7 @@ Once Verilator completes we can see the generated C++ code under the
.. code-block:: bash
ls -l obj_dir
ls -l obj_dir
(See :ref:`Files Read/Written` for descriptions of some of the files that
were created.)
@ -79,16 +79,16 @@ And now we run it:
.. code-block:: bash
obj_dir/Vour
obj_dir/Vour
And we get as output:
.. code-block:: bash
Hello World
- our.v:2: Verilog $finish
Hello World
- our.v:2: Verilog $finish
You're better off using a Makefile to run the steps for you, so when your
source changes, it will automatically run all of the appropriate steps. To
aid this, Verilator can create a makefile dependency file. For examples
source changes, it will automatically run all of the appropriate steps. To
aid this, Verilator can create a makefile dependency file. For examples
that do this, see the :file:`examples` directory in the distribution.

10
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@ -1,16 +1,16 @@
.. Copyright 2003-2025 by Wilson Snyder.
.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
First you need Verilator installed, see :ref:`Installation`. In brief, if
First you need Verilator installed, see :ref:`Installation`. In brief, if
you installed Verilator using the package manager of your operating system,
or did a :command:`make install` to place Verilator into your default path,
you do not need anything special in your environment, and should not have
VERILATOR_ROOT set. However, if you installed Verilator from sources and
VERILATOR_ROOT set. However, if you installed Verilator from sources and
want to run Verilator out of where you compiled Verilator, you need to
point to the kit:
.. code-block:: bash
# See above; don't do this if using an OS-distributed Verilator
export VERILATOR_ROOT=/path/to/where/verilator/was/installed
export PATH=$VERILATOR_ROOT/bin:$PATH
# See above; don't do this if using an OS-distributed Verilator
export VERILATOR_ROOT=/path/to/where/verilator/was/installed
export PATH=$VERILATOR_ROOT/bin:$PATH

24
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@ -6,37 +6,47 @@
Examples in the Distribution
============================
See the ``examples/`` directory that is part of the distribution, and
is installed (in an OS-specific place, often in e.g.
``/usr/local/share/verilator/examples``). These examples include:
See the ``examples/`` directory that is part of the distribution, and is
installed (in an OS-specific place, often in e.g.
``/usr/local/share/verilator/examples``). These examples include:
examples/make_hello_binary
Example GNU-make simple Verilog->binary conversion
examples/make_hello_c
Example GNU-make simple Verilog->C++ conversion
examples/make_hello_sc
Example GNU-make simple Verilog->SystemC conversion
examples/make_tracing_c
Example GNU-make Verilog->C++ with tracing
examples/make_tracing_sc
Example GNU-make Verilog->SystemC with tracing
examples/make_protect_lib
Example using --protect-lib
examples/cmake_hello_c
Example building make_hello_c with CMake
examples/cmake_hello_sc
Example building make_hello_sc with CMake
examples/cmake_tracing_c
Example building make_tracing_c with CMake
examples/cmake_tracing_sc
Example building make_tracing_sc with CMake
examples/cmake_protect_lib
Example building make_protect_lib with CMake
To run an example copy the example to a new directory and run it.
::
.. code-block:: bash
cp -rp {path_to}/examples/make_hello_c make_hello_c
cd make_hello_c
make
cp -rp {path_to}/examples/make_hello_c make_hello_c
cd make_hello_c
make

56
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@ -15,58 +15,58 @@ Now, let's create an example Verilog, and SystemC wrapper file:
.. code-block:: bash
mkdir test_our_sc
cd test_our_sc
mkdir test_our_sc
cd test_our_sc
cat >our.v <<'EOF'
module our (clk);
input clk; // Clock is required to get initial activation
always @(posedge clk)
begin $display("Hello World"); $finish; end
endmodule
EOF
cat >our.v <<'EOF'
module our (clk);
input clk; // Clock is required to get initial activation
always @(posedge clk)
begin $display("Hello World"); $finish; end
endmodule
EOF
cat >sc_main.cpp <<'EOF'
#include "Vour.h"
using namespace sc_core;
int sc_main(int argc, char** argv) {
Verilated::commandArgs(argc, argv);
sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true};
Vour* top = new Vour{"top"};
top->clk(clk);
while (!Verilated::gotFinish()) { sc_start(1, SC_NS); }
delete top;
return 0;
}
EOF
cat >sc_main.cpp <<'EOF'
#include "Vour.h"
using namespace sc_core;
int sc_main(int argc, char** argv) {
Verilated::commandArgs(argc, argv);
sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true};
Vour* top = new Vour{"top"};
top->clk(clk);
while (!Verilated::gotFinish()) { sc_start(1, SC_NS); }
delete top;
return 0;
}
EOF
Now we run Verilator on our little example:
.. code-block:: bash
verilator --sc --exe -Wall sc_main.cpp our.v
verilator --sc --exe -Wall sc_main.cpp our.v
This example does not use --build, therefore we need to explicitly compile
it:
.. code-block:: bash
make -j -C obj_dir -f Vour.mk Vour
make -j -C obj_dir -f Vour.mk Vour
And now we run it:
.. code-block:: bash
obj_dir/Vour
obj_dir/Vour
And we get, after the SystemC banner, the same output as the C++ example:
.. code-block:: bash
SystemC 2.3.3-Accellera
SystemC 2.3.3-Accellera
Hello World
- our.v:4: Verilog $finish
Hello World
- our.v:4: Verilog $finish
Really, you're better off using a Makefile to run the steps for you so when
your source changes it will automatically run all of the appropriate steps.

29
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@ -8,7 +8,7 @@ Simulation Runtime Arguments
The following are the arguments that may be passed to a Verilated
executable, provided that executable calls
:code:`VerilatedContext*->commandArgs(argc, argv)`.
``VerilatedContext*->commandArgs(argc, argv)``.
All simulation runtime arguments begin with "+verilator", so that the
user's executable may skip over all "+verilator" arguments when parsing its
@ -18,15 +18,16 @@ Summary:
.. include:: ../_build/gen/args_verilated.rst
Options:
.. option:: +verilator+coverage+file+<filename>
When a model was Verilated using :vlopt:`--coverage`, sets the filename
to write coverage data into. Defaults to :file:`coverage.dat`.
to write coverage data into. Defaults to :file:`coverage.dat`.
.. option:: +verilator+debug
Enable simulation runtime debugging. Equivalent to
Enable simulation runtime debugging. Equivalent to
:vlopt:`+verilator+debugi+4 <+verilator+debugi+\<value\>>`.
To be useful, the model typically must first be compiled with debug
@ -50,12 +51,12 @@ Summary:
.. option:: +verilator+noassert
Disable assert checking per runtime argument. This is the same as
calling :code:`VerilatedContext*->assertOn(false)` in the model.
calling ``VerilatedContext*->assertOn(false)`` in the model.
.. option:: +verilator+prof+exec+file+<filename>
When a model was Verilated using :vlopt:`--prof-exec`, sets the
simulation runtime filename to dump to. Defaults to
simulation runtime filename to dump to. Defaults to
:file:`profile_exec.dat`.
.. option:: +verilator+prof+exec+start+<value>
@ -72,9 +73,9 @@ Summary:
When a model was Verilated using :vlopt:`--prof-exec`, after $time
reaches :vlopt:`+verilator+prof+exec+start+\<value\>`, Verilator will
warm up the profiling for this number of eval() calls, then will capture
the profiling of this number of eval() calls. Defaults to 2, which
makes sense for a single-clock-domain module where it's typical to want
to capture one posedge eval() and one negedge eval().
the profiling of this number of eval() calls. Defaults to 2, which makes
sense for a single-clock-domain module where it's typical to want to
capture one posedge eval() and one negedge eval().
.. option:: +verilator+prof+threads+file+<filename>
@ -94,7 +95,7 @@ Summary:
.. option:: +verilator+prof+vlt+file+<filename>
When a model was Verilated using :vlopt:`--prof-pgo`, sets the
profile-guided optimization data runtime filename to dump to. Defaults
profile-guided optimization data runtime filename to dump to. Defaults
to :file:`profile.vlt`.
.. option:: +verilator+quiet
@ -104,15 +105,15 @@ Summary:
.. option:: +verilator+rand+reset+<value>
When a model was Verilated using
:vlopt:`--x-initial unique <--x-initial>`, sets the simulation runtime
initialization technique. 0 = Reset to zeros. 1 = Reset to all-ones. 2
= Randomize. See :ref:`Unknown States`.
When a model was Verilated using :vlopt:`--x-initial unique
<--x-initial>`, sets the simulation runtime initialization technique. 0
= Reset to zeros. 1 = Reset to all-ones. 2 = Randomize. See
:ref:`Unknown States`.
.. option:: +verilator+seed+<value>
For $random and :vlopt:`--x-initial unique <--x-initial>`, set the
simulation runtime random seed value. If zero or not specified picks a
simulation runtime random seed value. If zero or not specified picks a
value from the system random number generator.
.. option:: +verilator+V

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@ -7,7 +7,7 @@ verilator_coverage
Verilator_coverage processes Verilated model-generated coverage reports.
With `--annotate`, it reads the specified coverage data file and generates
annotated source code with coverage metrics annotated. With
annotated source code with coverage metrics annotated. With
`--annotate-points` the coverage points corresponding to each line are also
shown.
@ -21,25 +21,26 @@ those statistics of interest and save to a new .dat file.
For Verilog conditions that should never occur, either add a $stop
statement to the appropriate statement block, or see
:option:`/*verilator&32;coverage_off*/`. This will remove the coverage
:option:`/*verilator&32;coverage_off*/`. This will remove the coverage
points after the model is re-Verilated.
For an overview of the use of verilator_coverage, see :ref:`Coverage Analysis`.
For an overview of the use of verilator_coverage, see :ref:`Coverage
Analysis`.
verilator_coverage Example Usage
--------------------------------
..
.. code-block:: bash
verilator_coverage --help
verilator_coverage --version
verilator_coverage --help
verilator_coverage --version
verilator_coverage --annotate obj_dir coverage.dat
verilator_coverage --annotate obj_dir coverage.dat
verilator_coverage --write merged.dat coverage.dat ...
verilator_coverage --write merged.dat coverage.dat ...
verilator_coverage --write-info merged.info coverage.dat ...
verilator_coverage --write-info merged.info coverage.dat ...
verilator_coverage Arguments
@ -49,8 +50,8 @@ verilator_coverage Arguments
.. option:: <filename>
Specifies the input coverage data file. Multiple filenames may be
provided to read multiple inputs. If no data file is specified, by
Specifies the input coverage data file. Multiple filenames may be
provided to read multiple inputs. If no data file is specified, by
default, "coverage.dat" will be read.
.. option:: --annotate <output_directory>
@ -59,8 +60,8 @@ verilator_coverage Arguments
coverage data should be written.
Points are children of each line coverage- branches, expressions or
toggle points. When point counts are aggregated into a line, the
minimum and maximum counts are used to determine the status of the line
toggle points. When point counts are aggregated into a line, the minimum
and maximum counts are used to determine the status of the line
(complete, partial, failing) The count is equal to the maximum of the
points.
@ -73,7 +74,8 @@ verilator_coverage Arguments
* "%" indicates that all points on the line are below the coverage min.
* "~" indicates that some points on the line are above the coverage min and some are below.
* "+" coverage point was at or above the min. Only used with :option:`--annotate-points`.
* "-" coverage point was below the min. Only used with :option:`--annotate-points`.
* "-" coverage point was below the min. Only used with
:option:`--annotate-points`.
.. code-block::
@ -92,8 +94,8 @@ verilator_coverage Arguments
.. option:: --annotate-all
Specifies all files should be shown. By default, only those source
files with low coverage are written to the output directory.
Specifies all files should be shown. By default, only those source files
with low coverage are written to the output directory.
This option should be used together with :option:`--annotate`.
@ -111,8 +113,8 @@ verilator_coverage Arguments
.. option:: --annotate-points
Specifies all coverage points should be shown after each line of text. By
default, only source lines are shown.
Specifies all coverage points should be shown after each line of text.
By default, only source lines are shown.
.. code-block::
@ -137,7 +139,7 @@ verilator_coverage Arguments
.. option:: --rank
Prints an experimental report listing the relative importance of each
test in covering all of the coverage points. The report shows "Covered"
test in covering all of the coverage points. The report shows "Covered"
which indicates the number of points the test covers; a test is
considered to cover a point if it has a bucket count of at least 1. The
"rank" column has a higher number t indicate the test is more critical,
@ -159,7 +161,7 @@ verilator_coverage Arguments
Specifies the aggregate coverage results, summed across all the files,
should be written to the given filename in verilator_coverage data
format. This is useful in scripts to combine many coverage data files
format. This is useful in scripts to combine many coverage data files
(likely generated from random test runs) into one master coverage file.
.. option:: --write-info <filename.info>

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@ -31,50 +31,50 @@ In waveforms, there are the following signals. In GTKWave, use "decimal"
data format to remove the leading zeros and make the traces easier to read.
trace/section
Shows the name of the current top of the execution section stack.
Set GTKWave data format to "ASCII".
Shows the name of the current top of the execution section stack. Set
GTKWave data format to "ASCII".
trace/depth
Shows the depth of the execution section stack.
Set GTKWave data format to "Analog".
Shows the depth of the execution section stack. Set GTKWave data format
to "Analog".
measured_parallelism
The number of mtasks active at this time, for best performance, this will
match the thread count. In GTKWave, use a data format of "analog step" to
view this signal.
The number of mtasks active at this time, for best performance, this
will match the thread count. In GTKWave, use a data format of "analog
step" to view this signal.
predicted_parallelism
The number of mtasks Verilator predicted would be active at this time,
for best performance this will match the thread count. In GTKWave, use a
data format of "analog step" to view this signal.
The number of mtasks Verilator predicted would be active at this time,
for best performance this will match the thread count. In GTKWave, use a
data format of "analog step" to view this signal.
cpu#_thread
For the given CPU number, the thread number measured to be executing.
For the given CPU number, the thread number measured to be executing.
cpu#_waiting
For the given CPU number, aggregated waiting time for mtask dependencies.
Visualized as `X` values.
For the given CPU number, aggregated waiting time for mtask
dependencies. Visualized as `X` values.
mtask#_cpu
For the given mtask id, the CPU it was measured to execute on.
For the given mtask id, the CPU it was measured to execute on.
thread#_mtask
For the given thread number, the mtask id it was executing.
For the given thread number, the mtask id it was executing.
predicted_thread#_mtask
For the given thread number, the mtask id Verilator predicted would be
executing.
For the given thread number, the mtask id Verilator predicted would be
executing.
verilator_gantt Example Usage
-----------------------------
..
.. code-block:: bash
verilator_gantt --help
verilator_gantt --version
verilator_gantt --help
verilator_gantt --version
verilator_gantt profile_exec.dat
verilator_gantt profile_exec.dat
verilator_gantt Arguments

14
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@ -4,26 +4,26 @@
verilator_profcfunc
===================
Verilator_profcfunc reads a profile report created by gprof. The names of
Verilator_profcfunc reads a profile report created by gprof. The names of
the functions are then transformed, assuming the user used Verilator's
--prof-cfuncs, and a report printed showing the percentage of the time,
etc., in each Verilog block.
Due to rounding errors in gprof reports, the input report's percentages may
not total 100%. In the verilator_profcfunc report this will get
reported as a rounding error.
not total 100%. In the verilator_profcfunc report this will get reported as
a rounding error.
For an overview of the use of verilator_profcfunc, see :ref:`Profiling`.
verilator_profcfunc Example Usage
---------------------------------
..
.. code-block:: bash
verilator_profcfunc --help
verilator_profcfunc --version
verilator_profcfunc --help
verilator_profcfunc --version
verilator_profcfunc gprof.out
verilator_profcfunc gprof.out
verilator_profcfunc Arguments

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@ -6,30 +6,30 @@
=====================
The following additional constructs are the extensions Verilator supports
on top of standard Verilog code. Using these features outside of comments
on top of standard Verilog code. Using these features outside of comments
or "`ifdef`"'s may break other tools.
.. option:: """ [string] """
A triple-quoted block specifies a string that may include newlines and
single quotes. This extension was standardized in IEEE 1800-2023.
single quotes. This extension was standardized in IEEE 1800-2023.
.. option:: `__FILE__
The :option:`\`__FILE__` define expands to the current filename as a
string, like C++'s __FILE__. This Verilator feature, added in 2006, was
string, like C++'s __FILE__. This Verilator feature, added in 2006, was
incorporated into IEEE 1800-2009.
.. option:: `__LINE__
The :option:`\`__LINE__` define expands to the current line number like
C++'s __LINE__. This Verilator feature added in 2006 was incorporated
C++'s __LINE__. This Verilator feature added in 2006 was incorporated
into IEEE 1800-2009.
.. option:: `coverage_block_off
Specifies the entire begin/end block should be ignored for coverage
analysis. Must be inside a code block, e.g., within a begin/end pair.
analysis. Must be inside a code block, e.g., within a begin/end pair.
Same as :option:`coverage_block_off` in :ref:`Verilator Control Files`.
.. option:: `error [string]
@ -50,14 +50,14 @@ or "`ifdef`"'s may break other tools.
blocks, replaced with the C++ class name generated for the given
containing SystemVerilog class or module. Currently this is replaced
blindly, ignoring quoting or other escapes; this behavior may change in
the future. This attribute is indented only to be used internally in
the future. This attribute is indented only to be used internally in
`verilated_std.sv`.
.. option:: `systemc_ctor
Take the remaining text up to the next :option:`\`verilog` or
:option:`\`systemc_... <\`systemc_header>` mode switch and place it
verbatim into the C++ class constructor. Must be placed as a module or
verbatim into the C++ class constructor. Must be placed as a module or
class item, e.g., directly inside a module/endmodule or class/endclass
pair. Despite the name of this macro, this also works in pure C++ code.
@ -65,7 +65,7 @@ or "`ifdef`"'s may break other tools.
Take the remaining text up to the next :option:`\`verilog` or
:option:`\`systemc_... <\`systemc_header>` mode switch and place it
verbatim into the C++ class destructor. Must be placed as a module or
verbatim into the C++ class destructor. Must be placed as a module or
class item, e.g., directly inside a module/endmodule or class/endclass
pair. Despite the name of this macro, this also works in pure C++ code.
@ -73,10 +73,9 @@ or "`ifdef`"'s may break other tools.
Take the remaining text up to the next :option:`\`verilog` or
:option:`\`systemc_... <\`systemc_header>` mode switch and place it
verbatim into the output .h file's header. Must be placed as a module
or class item, e.g., directly inside a module/endmodule or
class/endclass pair. Despite the name of this macro, this also works in
pure C++ code.
verbatim into the output .h file's header. Must be placed as a module or
class item, e.g., directly inside a module/endmodule or class/endclass
pair. Despite the name of this macro, this also works in pure C++ code.
.. option:: `systemc_header_post
@ -100,21 +99,21 @@ or "`ifdef`"'s may break other tools.
Take the remaining text up to the next :option:`\`verilog` or
:option:`\`systemc_... <\`systemc_header>` mode switch and place it
verbatim into a single file of the C++ class implementation. Must be
verbatim into a single file of the C++ class implementation. Must be
placed as a module or class item, e.g., directly inside a
module/endmodule or class/endclass pair. Despite the name of this macro,
this also works in pure C++ code.
If you will be reading or writing any Verilog variables in the C++
functions, the Verilog signals must be declared with a
:option:`/*verilator&32;public*/` metacomment. See also the public task
:option:`/*verilator&32;public*/` metacomment. See also the public task
feature; writing an accessor may result in cleaner code.
.. option:: `systemc_interface
Take the remaining text up to the next :option:`\`verilog` or
:option:`\`systemc_... <\`systemc_header>` mode switch and place it
verbatim into the C++ class interface. Must be placed as a module or
verbatim into the C++ class interface. Must be placed as a module or
class item, e.g., directly inside a module/endmodule or class/endclass
pair. Despite the name of this macro, this also works in pure C++ code.
@ -136,22 +135,22 @@ or "`ifdef`"'s may break other tools.
.. option:: `verilator_config
Take the remaining text up to the next :option:`\`verilog` mode switch
and treat it as Verilator Control File commands. See :ref:`Verilator
and treat it as Verilator Control File commands. See :ref:`Verilator
Control Files`.
.. option:: `VERILATOR_TIMING
The VERILATOR_TIMING define is set when :vlopt:`--timing` is used to
allow an "\`ifdef" of code dependent on this feature. Note that this define
is not affected by the :option:`timing_off` control file option
allow an "\`ifdef" of code dependent on this feature. Note that this
define is not affected by the :option:`timing_off` control file option
nor timing metacomments.
.. option:: `verilog
Switch back to processing Verilog code after a
:option:`\`systemc_... <\`systemc_header>` mode switch. The Verilog
code returns to the last language mode specified with
"\`begin_keywords", or SystemVerilog if none was specified.
Switch back to processing Verilog code after a :option:`\`systemc_...
<\`systemc_header>` mode switch. The Verilog code returns to the last
language mode specified with "\`begin_keywords", or SystemVerilog if
none was specified.
.. t_dist_docs_style restart_sort
@ -159,7 +158,7 @@ or "`ifdef`"'s may break other tools.
.. option:: $c([string], ...);, $cpure([string], ...);
The string will be embedded directly in the output C++ code at the point
where the surrounding Verilog code is compiled. It may either be a
where the surrounding Verilog code is compiled. It may either be a
standalone statement (with a trailing ; in the string), or a function
that returns up to a 32-bit number (without a trailing ;). This can be
used to call C++ functions from your Verilog code.
@ -171,28 +170,27 @@ or "`ifdef`"'s may break other tools.
via an explicit 'this->' pointer dereference.
Expression arguments will have the code to evaluate the expression
inserted. Thus to call a C++ function, :code:`$c("func(",a,")")` will
result in :code:`func(a)` in the output C++ code. For input arguments,
rather than hard-coding variable names in the string
:code:`$c("func(a)")`, instead pass the variable as an expression
::code:`$c("func(",a,")")`. This will allow the call to work inside
Verilog functions where the variable is flattened out and enable other
optimizations.
inserted. Thus to call a C++ function, ``$c("func(",a,")")`` will result
in ``func(a)`` in the output C++ code. For input arguments, rather than
hard-coding variable names in the string ``$c("func(a)")``, instead pass
the variable as an expression :``$c("func(",a,")")``. This will allow
the call to work inside Verilog functions where the variable is
flattened out and enable other optimizations.
Verilator does not use any text inside the quotes for
ordering/scheduling. If you need the $c to be called at a specific
time, e.g., when a variable changes, then the $c must be under an
appropriate sensitivity statement, e.g.,
:code:`always @(posedge clk) $c("func()")` to call it on every edge, or,
e.g., :code:`always @* c("func(",a,")")` to call it when :code:`a`
changes (the latter working because :code:`a` is outside the quotes).
ordering/scheduling. If you need the $c to be called at a specific time,
e.g., when a variable changes, then the $c must be under an appropriate
sensitivity statement, e.g., ``always @(posedge clk) $c("func()")`` to
call it on every edge, or, e.g., ``always @* c("func(",a,")")`` to call
it when ``a`` changes (the latter working because ``a`` is outside the
quotes).
If you will be reading or writing any Verilog variables inside the C++
functions, the Verilog signals must be declared with
:option:`/*verilator&32;public*/` metacomments.
You may also append a number to $c, which specifies the bit width of
the output, e.g., :code:`signal_32_bits = $c32("...");`. This allows for
You may also append a number to $c, which specifies the bit width of the
output, e.g., ``signal_32_bits = $c32("...");``. This allows for
compatibility with other simulators, which require a differently named
PLI function name for each different output width.
@ -203,31 +201,31 @@ or "`ifdef`"'s may break other tools.
.. option:: $display, $write, $fdisplay, $fwrite, $sformat, $swrite
Format arguments may use C fprintf sizes after the % escape. Per the
Format arguments may use C fprintf sizes after the % escape. Per the
Verilog standard, %x prints a number with the natural width, and %0x
prints a number with minimum width. Verilator extends this so %5x
prints 5 digits per the C standard. This extension was standardized into
prints a number with minimum width. Verilator extends this so %5x prints
5 digits per the C standard. This extension was standardized into
1800-2009.
.. option:: $stacktrace
Called as a task, print a stack trace. Called as a function, return a
string with a stack trace. This relies on the C++ system trace, which
Called as a task, print a stack trace. Called as a function, return a
string with a stack trace. This relies on the C++ system trace, which
may give less meaningful results if the model is not compiled with debug
symbols. Also, the data represents the C++ stack; the SystemVerilog
symbols. Also, the data represents the C++ stack; the SystemVerilog
functions/tasks involved may be renamed and/or inlined before becoming
the C++ functions that may be visible in the stack trace. This
extension was standardized in IEEE 1800-2023.
the C++ functions that may be visible in the stack trace. This extension
was standardized in IEEE 1800-2023.
.. option:: $timeprecision
Returns the timeprecision of the model as an integer. This extension is
Returns the timeprecision of the model as an integer. This extension is
experimental and may be removed without deprecation.
.. option:: $timeunit
Returns the timeunit of the current module as an integer. This
extension is experimental and may be removed without deprecation.
Returns the timeunit of the current module as an integer. This extension
is experimental and may be removed without deprecation.
.. option:: /*verilator&32;clock_enable*/
@ -242,10 +240,10 @@ or "`ifdef`"'s may break other tools.
.. code-block:: sv
reg enable_r /*verilator clock_enable*/;
wire gated_clk = clk & enable_r;
always_ff @(posedge clk)
enable_r <= enable_early;
reg enable_r /*verilator clock_enable*/;
wire gated_clk = clk & enable_r;
always_ff @(posedge clk)
enable_r <= enable_early;
The clock_enable attribute will cause the clock gate to be ignored in
the scheduling algorithm, sometimes required for correct clock behavior,
@ -306,10 +304,10 @@ or "`ifdef`"'s may break other tools.
.. option:: /*verilator&32;hier_block*/
Specifies that the module is a unit of hierarchical Verilation. This
metacomment must be between :code:`module module_name(...);` and
:code:`endmodule`. The module will not be inlined nor uniquified for
each instance in hierarchical Verilation. Note that the metacomment is
Specifies that the module is a unit of hierarchical Verilation. This
metacomment must be between ``module module_name(...);`` and
``endmodule``. The module will not be inlined nor uniquified for each
instance in hierarchical Verilation. Note that the metacomment is
ignored unless the :vlopt:`--hierarchical` option is specified.
See :ref:`Hierarchical Verilation`.
@ -317,17 +315,17 @@ or "`ifdef`"'s may break other tools.
.. option:: /*verilator&32;inline_module*/
Specifies the module the comment appears in may be inlined into any
modules that use this module. This is useful to speed up simulation
runtime. Note if using :vlopt:`--public` that signals under inlined
submodules will be named :code:`{submodule}__DOT__{subsignal}` as C++
does not allow "." in signal names.
modules that use this module. This is useful to speed up simulation
runtime. Note if using :vlopt:`--public` that signals under inlined
submodules will be named ``{submodule}__DOT__{subsignal}`` as C++ does
not allow "." in signal names.
Same as :option:`inline` control file option.
.. option:: /*verilator&32;isolate_assignments*/
Used after a signal declaration to indicate the assignments to this
signal in any blocks should be isolated into new blocks. When large
signal in any blocks should be isolated into new blocks. When large
combinatorial block results in a :option:`UNOPTFLAT` warning, attaching
this to the signal that was causing a false loop may work around the
warning.
@ -336,14 +334,14 @@ or "`ifdef`"'s may break other tools.
.. code-block:: sv
reg splitme /* verilator isolate_assignments*/;
// Note the placement of the semicolon above
always_comb begin
if (....) begin
splitme = ....;
other assignments
end
end
reg splitme /* verilator isolate_assignments*/;
// Note the placement of the semicolon above
always_comb begin
if (....) begin
splitme = ....;
other assignments
end
end
Verilator will internally split the block that assigns to "splitme" into
two blocks:
@ -370,36 +368,36 @@ or "`ifdef`"'s may break other tools.
.. option:: /*verilator&32;lint_off <msgs>*/
Disable the specified warning message(s) for any warnings following the
comment. Multiple messages may be specified, separated with commas.
comment. Multiple messages may be specified, separated with commas.
If a one-line slash-slash-format comment is used, then the metacomment
ends at the newline or at an earlier next slash-slash. This allow
commenting the reason for the disable, e.g. :code:`// verilator lint_off
MSG // Because...`.
commenting the reason for the disable, e.g. ``// verilator lint_off
MSG // Because...``.
.. option:: /*verilator&32;lint_on <msgs>*/
Re-enable the specified warning message(s) for any warnings following
the comment. Multiple messages may be specified, separated with commas.
the comment. Multiple messages may be specified, separated with commas.
.. option:: /*verilator&32;lint_restore*/
After a :code:`/*verilator&32;lint_save*/`, pop the stack containing lint
message state. Often this is useful at the bottom of include files.
After a ``/*verilator&32;lint_save*/``, pop the stack containing lint
message state. Often this is useful at the bottom of include files.
.. option:: /*verilator&32;lint_save*/
Push the current state of what lint messages are turned on or off
to a stack. Later meta-comments may then lint_on or lint_off specific
Push the current state of what lint messages are turned on or off to a
stack. Later meta-comments may then lint_on or lint_off specific
messages, then return to the earlier message state by using
:code:`/*verilator&32;lint_restore*/`. For example:
``/*verilator&32;lint_restore*/``. For example:
.. code-block:: sv
// verilator lint_save
// verilator lint_off WIDTH
... // code needing WIDTH turned off
// verilator lint_restore
// verilator lint_save
// verilator lint_off WIDTH
... // code needing WIDTH turned off
// verilator lint_restore
If WIDTH was on before the lint_off, it would now be restored to on, and
if it was off before the lint_off it would remain off.
@ -414,11 +412,10 @@ or "`ifdef`"'s may break other tools.
.. option:: /*verilator&32;no_inline_task*/
Used in a function or task variable definition section to specify the
function or task should not be inlined into where it is used. This may
function or task should not be inlined into where it is used. This may
reduce the size of the final executable when a task is used a very large
number of times. For this flag to work, the task and tasks below it
must be pure; they cannot reference any variables outside the task
itself.
number of times. For this flag to work, the task and tasks below it must
be pure; they cannot reference any variables outside the task itself.
Same as :option:`no_inline` control file option.
@ -430,21 +427,21 @@ or "`ifdef`"'s may break other tools.
.. code-block:: sv
parameter [2:0] PARAM /*verilator public*/ = 2'b0;
parameter [2:0] PARAM /*verilator public*/ = 2'b0;
.. option:: /*verilator&32;public*/ (on task/function)
Used inside the declaration section of a function or task declaration to
indicate the function or task should be made into a C++ function, public
to outside callers. Public tasks will be declared as a void C++
to outside callers. Public tasks will be declared as a void C++
function, public functions will get the appropriate non-void (bool,
uint32_t, etc.) return type. Any input arguments will become C++
arguments to the function. Any output arguments will become C++
reference arguments. Any local registers/integers will become function
uint32_t, etc.) return type. Any input arguments will become C++
arguments to the function. Any output arguments will become C++
reference arguments. Any local registers/integers will become function
automatic variables on the stack.
Wide variables over 64 bits cannot be function returns, to avoid
exposing complexities. However, wide variables can be input/outputs;
exposing complexities. However, wide variables can be input/outputs;
they will be passed as references to an array of 32-bit numbers.
Generally, only the values of stored state (flops) should be written, as
@ -464,17 +461,17 @@ or "`ifdef`"'s may break other tools.
.. code-block:: sv
typedef enum logic [2:0] { ZERO = 3'b0 } pub_t /*verilator public*/;
typedef enum logic [2:0] { ZERO = 3'b0 } pub_t /*verilator public*/;
.. option:: /*verilator&32;public*/ (on variable)
Used after an input, output, register, or wire declaration to indicate
the signal should be declared so that C code may read or write the value
of the signal. This will also declare this module public; otherwise, use
:code:`/*verilator&32;public_flat*/`.
of the signal. This will also declare this module public; otherwise, use
``/*verilator&32;public_flat*/``.
Instead of using public variables, consider making a DPI or public
function that accesses the variable. This is nicer as it provides an
function that accesses the variable. This is nicer as it provides an
obvious entry point compatible across simulators.
Same as :option:`public` control file option.
@ -484,30 +481,30 @@ or "`ifdef`"'s may break other tools.
Used to wrap multiple signals and parameters with the respective public attribute.
See attribute above for their respective behavior. Cannot be nested. e.g:
.. code-block:: sv
.. code-block:: sv
/*verilator public_flat_rw_on*/
logic clk;
logic rst;
parameter width = 8;
/* verilator public_off*/
logic data;
/*verilator public_flat_rw_on*/
logic clk;
logic rst;
parameter width = 8;
/* verilator public_off*/
logic data;
Is equivalent to:
.. code-block:: sv
.. code-block:: sv
logic clk /*verilator public_flat_rw*/;
logic rst /*verilator public_flat_rw*/;
parameter width /*verilator public_flat_rw*/ = 8;
logic data;
logic clk /*verilator public_flat_rw*/;
logic rst /*verilator public_flat_rw*/;
parameter width /*verilator public_flat_rw*/ = 8;
logic data;
.. option:: /*verilator&32;public_flat*/ (on variable)
Used after an input, output, register, or wire declaration to indicate
the signal should be declared so that C code may read or write the value
of the signal. This will not declare this module public, which means
the name of the signal or path to it may change based upon the module
of the signal. This will not declare this module public, which means the
name of the signal or path to it may change based upon the module
inlining which takes place.
Same as :option:`public_flat` control file option.
@ -536,9 +533,9 @@ or "`ifdef`"'s may break other tools.
Used after a module statement to indicate the module should not be
inlined (unless specifically requested) so that C code may access the
module. Verilator automatically sets this attribute when the module
contains public signals or \`systemc_ directives. Use of this is
implied when using the :vlopt:`--public` option.
module. Verilator automatically sets this attribute when the module
contains public signals or \`systemc_ directives. Use of this is implied
when using the :vlopt:`--public` option.
Same as :option:`public` control file option.
@ -548,38 +545,38 @@ or "`ifdef`"'s may break other tools.
.. option:: /*verilator&32;sc_biguint*/
Used after a port declaration. It sets the port to be of
:code:`sc_biguint<{width}>` type, for signals of any width.
This may be useful if the port width is parameterized and the
instantiating C++ code always wants to have a sc_biguint accept any width.
In general, you should avoid using this attribute when unnecessary, as
the performance decreases significantly with increasing usage of sc_biguint.
Used after a port declaration. It sets the port to be of
``sc_biguint<{width}>`` type, for signals of any width. This may be
useful if the port width is parameterized and the instantiating C++ code
always wants to have a sc_biguint accept any width. In general, you
should avoid using this attribute when unnecessary, as the performance
decreases significantly with increasing usage of sc_biguint.
.. option:: /*verilator&32;sc_bv*/
Used after a port declaration. It sets the port to be of
:code:`sc_bv<{width}>` type, instead of bool, uint32_t, or uint64_t.
This may be useful if the port width is parameterized and the
instantiating C++ code always wants to have a sc_bv accept any width.
In general, you should avoid using this attribute when unnecessary, as
the performance decreases significantly with increasing usage of sc_bv.
Used after a port declaration. It sets the port to be of
``sc_bv<{width}>`` type, instead of bool, uint32_t, or uint64_t. This
may be useful if the port width is parameterized and the instantiating
C++ code always wants to have a sc_bv accept any width. In general, you
should avoid using this attribute when unnecessary, as the performance
decreases significantly with increasing usage of sc_bv.
Same as :option:`sc_bv` control file option.
.. option:: /*verilator&32;sc_clock*/
Deprecated and ignored. Previously used after an input declaration to
Deprecated and ignored. Previously used after an input declaration to
indicate the signal should be declared in SystemC as a sc_clock instead
of a bool. This was needed in SystemC 1.1 and 1.2 only; versions 2.0
and later do not require clock pins to be sc_clocks, and this is no
longer needed and is ignored.
of a bool. This was needed in SystemC 1.1 and 1.2 only; versions 2.0 and
later do not require clock pins to be sc_clocks, and this is no longer
needed and is ignored.
.. option:: /*verilator&32;sformat*/
Attached to the final argument of type "input string" of a function or
task to indicate that the function or task should pass all remaining
arguments through $sformatf. This allows creation of DPI functions with
$display-like behavior. See the :file:`test_regress/t/t_dpi_display.v`
arguments through $sformatf. This allows creation of DPI functions with
$display-like behavior. See the :file:`test_regress/t/t_dpi_display.v`
file for an example.
Same as :option:`sformat` control file option.
@ -596,14 +593,14 @@ or "`ifdef`"'s may break other tools.
.. code-block:: sv
logic [7:0] x [0:1] /*verilator split_var*/;
logic [7:0] x [0:1] /*verilator split_var*/;
To:
.. code-block:: sv
logic [7:0] x__BRA__0__KET__ /*verilator split_var*/;
logic [7:0] x__BRA__1__KET__ /*verilator split_var*/;
logic [7:0] x__BRA__0__KET__ /*verilator split_var*/;
logic [7:0] x__BRA__1__KET__ /*verilator split_var*/;
Note that the generated packed variables retain the split_var
metacomment because they may be split into smaller pieces according to
@ -611,7 +608,7 @@ or "`ifdef`"'s may break other tools.
This only supports unpacked arrays, packed arrays, and packed structs of
integer types (reg, logic, bit, byte, int...); otherwise, if a split was
requested but cannot occur, a SPLITVAR warning is issued. Splitting
requested but cannot occur, a SPLITVAR warning is issued. Splitting
large arrays may slow down the Verilation speed, so use this only on
variables that require it.
@ -622,12 +619,11 @@ or "`ifdef`"'s may break other tools.
.. code-block:: sv
logic [1:0][31:0] tmp;
assign tmp[0] = foo + a;
assign tmp[1] = tmp[1] + b;
assign bar = tmp[1] + c;
logic [1:0][31:0] tmp;
assign tmp[0] = foo + a;
assign tmp[1] = tmp[1] + b;
assign bar = tmp[1] + c;
Same as :option:`split_var` control file option.
@ -641,8 +637,8 @@ or "`ifdef`"'s may break other tools.
Ignore all timing constructs after this metacomment. All timing controls
behave as if they were not there (the same way as with
:option:`--no-timing`), and :code:`fork`/:code:`join*` blocks are
converted into :code:`begin`/:code:`end` blocks.
:option:`--no-timing`), and ``fork``/``join*`` blocks are
converted into ``begin``/``end`` blocks.
Same as :option:`timing_off` control file option.
@ -667,7 +663,7 @@ or "`ifdef`"'s may break other tools.
.. option:: /*verilator&32;tracing_off*/
Disable waveform tracing for all future signals declared in this module,
or instances below this module. Often this is placed just after a
or instances below this module. Often this is placed just after a
primitive's module statement, so that the entire module and instances
below it are not traced.
@ -680,7 +676,7 @@ or "`ifdef`"'s may break other tools.
Used in a statement position to indicate the immediately following loop
at the same statement level should not be unrolled by Verilator,
ignoring :vlopt:`--unroll-count`. This is similar to clang's ``#pragma
ignoring :vlopt:`--unroll-count`. This is similar to clang's ``#pragma
clang loop unroll(disable)``.
This option does not currently disable the C++ compiler's unrolling (or
@ -690,5 +686,5 @@ or "`ifdef`"'s may break other tools.
Rarely needed. Used in a statement position to indicate the immediately
following loop at the same statement level should always be fully
unrolled by Verilator, ignoring :vlopt:`--unroll-count`. This is
similar to clang's ``#pragma clang loop unroll(full)``.
unrolled by Verilator, ignoring :vlopt:`--unroll-count`. This is similar
to clang's ``#pragma clang loop unroll(full)``.

268
docs/guide/faq.rst
View File

@ -13,9 +13,9 @@ Questions
Can I contribute?
"""""""""""""""""
Please contribute! Just submit a pull request, or raise an issue to
discuss if you are looking for something to help on. For more information
see our contributor agreement.
Please contribute! Just submit a pull request, or raise an issue to discuss
if you are looking for something to help on. For more information see our
contributor agreement.
How widely is Verilator used?
@ -25,10 +25,10 @@ Verilator is used by many of the largest silicon design companies, large
organizations such as CERN, and even by college student projects.
Verilator is one of the "big 4" simulators, meaning one of the four leading
SystemVerilog simulators available, namely the closed-source products Synopsys
VCS (tm), Mentor Questa/ModelSim (tm), Cadence
Xcelium/Incisive/NC-Verilog/NC-Sim (tm), and the open-source Verilator.
The three closed-source offerings are often collectively called the "big 3"
SystemVerilog simulators available, namely the closed-source products
Synopsys VCS (tm), Mentor Questa/ModelSim (tm), Cadence
Xcelium/Incisive/NC-Verilog/NC-Sim (tm), and the open-source Verilator. The
three closed-source offerings are often collectively called the "big 3"
simulators.
@ -37,7 +37,7 @@ Does Verilator run under Windows?
Yes, ideally, run Ubuntu under Windows Subsystem for Linux (WSL2).
Alternatively, use Cygwin, though this tends to be slower and is not
regularly tested. Verilated output also compiles under Microsoft Visual
regularly tested. Verilated output also compiles under Microsoft Visual
C++, but this is also not regularly tested.
@ -46,8 +46,8 @@ Can you provide binaries?
You can install Verilator via the system package manager (apt, yum, etc.)
on many Linux distributions, including Debian, Ubuntu, SuSE, Red Hat, and
others. These packages are provided by the Linux distributions and
generally will lag the version of the mainline Verilator repository. If no
others. These packages are provided by the Linux distributions and
generally will lag the version of the mainline Verilator repository. If no
binary package is available for your distribution, how about you set one
up?
@ -59,24 +59,25 @@ Generally, the implied part of the question is "... with all of the
manpower they can put into developing it."
Most simulators must comply with the complete IEEE 1364 (Verilog) and IEEE
1800 (SystemVerilog) standards, meaning they have to be event-driven. This
1800 (SystemVerilog) standards, meaning they have to be event-driven. This
prevents them from being able to reorder blocks and make netlist-style
optimizations, which are where most of the gains come from.
You should not be scared by non-compliance. Your synthesis tool isn't
You should not be scared by non-compliance. Your synthesis tool isn't
compliant with the whole standard to start with, so your simulator need not
be either. Verilator is closer to the synthesis interpretation, which is
a good thing for getting working silicon.
be either. Verilator is closer to the synthesis interpretation, which is a
good thing for getting working silicon.
Will Verilator output remain under my own license/copyright?
""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
Your SystemVerilog, VPI/DPI, or main() C++ code remains under your own license.
Your SystemVerilog, VPI/DPI, or main() C++ code remains under your own
license.
It's just like how using GCC on your programs does not change the copyright
of your program; this is why Verilator uses the "GNU **Lesser** Public
License Version 3" instead of the more typical "GNU Public License". See
License Version 3" instead of the more typical "GNU Public License". See
the licenses for details.
Some examples:
@ -98,15 +99,15 @@ Some examples:
You also have the option of using the Perl Artistic License, which again
does not require you to release your Verilog, C++, or generated code. This
license also allows you to modify Verilator for internal use without
distributing the modified version. But please contribute back to the
distributing the modified version. But please contribute back to the
community!
Under both licenses, you can offer a commercial product based on
Verilator directly or embedded within. However, under both licenses,
any changes you make to Verilator for such a product must be open-sourced.
Under both licenses, you can offer a commercial product based on Verilator
directly or embedded within. However, under both licenses, any changes you
make to Verilator for such a product must be open-sourced.
As is standard with Open Source, contributions back to Verilator will be
placed under the Verilator copyright and LGPL/Artistic license. Small test
placed under the Verilator copyright and LGPL/Artistic license. Small test
cases will be released into the public domain so they can be used anywhere,
and large tests under the LGPL/Artistic, unless requested otherwise.
@ -114,13 +115,13 @@ and large tests under the LGPL/Artistic, unless requested otherwise.
Why is running Verilator (to create a model) so slow?
"""""""""""""""""""""""""""""""""""""""""""""""""""""
Verilator may require more memory than the resulting simulation,
as Verilator internally creates all of the state of the resulting
generated simulator to optimize it. If it takes more than a few
minutes or so (and you're not using :vlopt:`--debug` since debug mode is
disk bound), see if your machine is paging; most likely, you need to run it
on a machine with more memory. Very large designs are known to have topped
64 GB resident set size. Alternatively, see :ref:`Hierarchical Verilation`.
Verilator may require more memory than the resulting simulation, as
Verilator internally creates all of the state of the resulting generated
simulator to optimize it. If it takes more than a few minutes or so (and
you're not using :vlopt:`--debug` since debug mode is disk bound), see if
your machine is paging; most likely, you need to run it on a machine with
more memory. Very large designs are known to have topped 64 GB resident set
size. Alternatively, see :ref:`Hierarchical Verilation`.
How do I generate waveforms (traces) in C++?
@ -128,16 +129,16 @@ How do I generate waveforms (traces) in C++?
See also the next question for tracing in SystemC mode.
A. Pass the :vlopt:`--trace-vcd` option to Verilator. Then you may use ``$dumpfile`` and
``$dumpvars`` to enable traces, the same as with any Verilog simulator,
although Verilator ignores the arguments to ``$dumpvars``. See
``examples/make_tracing_c`` in the distribution.
A. Pass the :vlopt:`--trace-vcd` option to Verilator. Then you may use
``$dumpfile`` and ``$dumpvars`` to enable traces, the same as with any
Verilog simulator, although Verilator ignores the arguments to
``$dumpvars``. See ``examples/make_tracing_c`` in the distribution.
If writing the top-level C code, call ``Verilated::traceEverOn(true)``;
this is done for you if using :vlopt:`--binary`.
B. Or, for finer-grained control, or C++ files with multiple Verilated
modules, you may also create the trace purely from C++. Create a
modules, you may also create the trace purely from C++. Create a
VerilatedVcdC object, and in your main loop, right after ``eval()`` call
``trace_object->dump(contextp->time())`` every time step, and finally
call ``trace_object->close()``.
@ -166,27 +167,26 @@ B. Or, for finer-grained control, or C++ files with multiple Verilated
You also need to compile :file:`verilated_vcd_c.cpp` and add it to your
link, preferably by adding the dependencies in your Makefile's
:code:`$(VK_GLOBAL_OBJS)` link rule. This is done for you if you are using
the Verilator :vlopt:`--binary` or :vlopt:`--exe` option.
``$(VK_GLOBAL_OBJS)`` link rule. This is done for you if you are using the
Verilator :vlopt:`--binary` or :vlopt:`--exe` option.
you can call :code:`trace_object->trace()` on multiple Verilated objects
with the same trace file if you want all data to land in the same output
file.
you can call ``trace_object->trace()`` on multiple Verilated objects with
the same trace file if you want all data to land in the same output file.
How do I generate waveforms (traces) in SystemC?
""""""""""""""""""""""""""""""""""""""""""""""""
A. Pass the :vlopt:`--trace-vcd` option to Verilator, and in your top-level
:code:`sc_main()`, call :code:`Verilated::traceEverOn(true)`. Then you
may use :code:`$dumpfile` and code:`$dumpvars` to enable traces, as
with any Verilog simulator; see the non-SystemC example in
``sc_main()``, call ``Verilated::traceEverOn(true)``. Then you may use
``$dumpfile`` and code:`$dumpvars` to enable traces, as with any Verilog
simulator; see the non-SystemC example in
:file:`examples/make_tracing_c`. This will trace only the module
containing the :code:`$dumpvar`.
containing the ``$dumpvar``.
B. Or, you may create a trace purely from SystemC, which may trace all
Verilated designs in the SystemC model. Create a VerilatedVcdSc object
as you would create a standard SystemC trace file. For an example, see
as you would create a standard SystemC trace file. For an example, see
the call to ``VerilatedVcdSc`` in the
:file:`examples/make_tracing_sc/sc_main.cpp` file of the distribution,
and below.
@ -212,57 +212,53 @@ C. Alternatively, you may use the C++ trace mechanism described in the
tfp->close();
}
You also need to compile :file:`verilated_vcd_sc.cpp` and
:file:`verilated_vcd_c.cpp` and add them to your link, preferably by adding
the dependencies in your Makefile's :code:`$(VK_GLOBAL_OBJS)` link rule.
This is done for you if you are using the Verilator :vlopt:`--binary` or
the dependencies in your Makefile's ``$(VK_GLOBAL_OBJS)`` link rule. This
is done for you if you are using the Verilator :vlopt:`--binary` or
:vlopt:`--exe` option.
You can call :code:`->trace()` on multiple Verilated objects with the same
You can call ``->trace()`` on multiple Verilated objects with the same
trace file if you want all data to land in the same output file.
How do I generate FST waveforms (traces) in C++ or SystemC?
"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
FST is a trace file format developed by GTKWave. Verilator provides basic
FST support. To dump traces in FST format, add the :vlopt:`--trace-fst`
FST is a trace file format developed by GTKWave. Verilator provides basic
FST support. To dump traces in FST format, add the :vlopt:`--trace-fst`
option to Verilator and either:
Use :code:`$dumpfile & $dumpvars` in Verilog as described in the VCD
example above,
Use ``$dumpfile & $dumpvars`` in Verilog as described in the VCD example
above,
Or, in C++ change the include described in the VCD example above:
.. code-block:: C++
#include "verilated_fst_c.h"
VerilatedFstC* tfp = new VerilatedFstC;
.. code-block:: C++
#include "verilated_fst_c.h"
VerilatedFstC* tfp = new VerilatedFstC;
Or, in SystemC, change the include described in the VCD example above:
.. code-block:: C++
#include "verilated_fst_sc.h"
VerilatedFstC* tfp = new VerilatedFstSc;
.. code-block:: C++
#include "verilated_fst_sc.h"
VerilatedFstC* tfp = new VerilatedFstSc;
Currently, supporting FST and VCD in a single simulation is not supported,
but such usage should be unlikely. You can however ifdef around the trace
but such usage should be unlikely. You can however ifdef around the trace
format in your C++ main loop, and select VCD or FST at compile time.
How do I view waveforms (aka dumps or traces)?
""""""""""""""""""""""""""""""""""""""""""""""
Verilator creates standard VCD (Value Change Dump) and FST files. VCD
files are viewable with the open-source
`GTKWave <https://gtkwave.sourceforge.net/>`_,
`Surfer <https://surfer-project.org/>`_, Dinotrace (legacy), or any of the
many closed-source viewer offerings; FST is supported only by GTKWave and
Verilator creates standard VCD (Value Change Dump) and FST files. VCD files
are viewable with the open-source `GTKWave
<https://gtkwave.sourceforge.net/>`_, `Surfer
<https://surfer-project.org/>`_, Dinotrace (legacy), or any of the many
closed-source viewer offerings; FST is supported only by GTKWave and
Surfer.
@ -287,24 +283,24 @@ D. You can also consider using FST tracing instead of VCD. FST dumps are a
is prohibitively large.
E. Write your trace files to a machine-local solid-state drive instead of a
network drive. Network drives are generally far slower.
network drive. Network drives are generally far slower.
Where is the translate_off command? (How do I ignore a construct?)
"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
Where is the translate_off command? (How do I ignore a construct?)
""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
Translate on/off pragmas are generally a bad idea, as it's easy to have
mismatched pairs, and you can't see what another tool sees by just
preprocessing the code. Instead, use the preprocessor; Verilator defines
preprocessing the code. Instead, use the preprocessor; Verilator defines
the ``\`VERILATOR`` define for you, so just wrap the code in an ifndef
region:
.. code-block:: sv
:emphasize-lines: 1
.. code-block:: sv
:emphasize-lines: 1
`ifndef VERILATOR
Something_Verilator_Dislikes;
`endif
`ifndef VERILATOR
Something_Verilator_Dislikes;
`endif
Most synthesis tools similarly define SYNTHESIS for you.
@ -312,10 +308,10 @@ Most synthesis tools similarly define SYNTHESIS for you.
Why do I get "unexpected 'do'" or "unexpected 'bit'" errors?
""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
The words \ ``do``\ , \ ``bit``\ , \ ``ref``\ , \ ``return``\ , and others
are reserved keywords in SystemVerilog. Older Verilog code might use these
as identifiers, and you should change your code to not use them to ensure it
works with newer tools. Alternatively, surround them by the Verilog
The words ``do``, ``bit``, ``ref``, ``return``, and others are reserved
keywords in SystemVerilog. Older Verilog code might use these as
identifiers, and you should change your code to not use them to ensure it
works with newer tools. Alternatively, surround them by the Verilog
2005/SystemVerilog begin_keywords pragma to indicate Verilog 2001 code.
.. code-block:: sv
@ -325,7 +321,6 @@ works with newer tools. Alternatively, surround them by the Verilog
integer bit; initial bit = 1;
`end_keywords
If you want the whole design parsed as Verilog 2001, see the
:vlopt:`--default-language` option.
@ -333,8 +328,8 @@ If you want the whole design parsed as Verilog 2001, see the
How do I prevent my assertions from firing during reset?
""""""""""""""""""""""""""""""""""""""""""""""""""""""""
Call :code:`Verilated::assertOn(false)` before you first call the model,
then turn it back on after reset. It defaults to true. When false, all
Call ``Verilated::assertOn(false)`` before you first call the model, then
turn it back on after reset. It defaults to true. When false, all
assertions are disabled.
@ -342,36 +337,36 @@ Why do I get "undefined reference to sc_time_stamp()?
"""""""""""""""""""""""""""""""""""""""""""""""""""""
In Verilator 4.200 and later, using the timeInc function is recommended
instead. See the :ref:`Connecting to C++` examples. Some linkers (MSVC++)
still require :code:`sc_time_stamp()` to be defined; either define this
with :code:`double sc_time_stamp() { return 0; }` or compile the Verilated
code with :code:`-CFLAGS -DVL_TIME_CONTEXT`.
instead. See the :ref:`Connecting to C++` examples. Some linkers (MSVC++)
still require ``sc_time_stamp()`` to be defined; either define this with
``double sc_time_stamp() { return 0; }`` or compile the Verilated code with
``-CFLAGS -DVL_TIME_CONTEXT``.
Before Verilator 4.200, the :code:`sc_time_stamp()` function needs to be
Before Verilator 4.200, the ``sc_time_stamp()`` function needs to be
defined in C++ (non SystemC) to return the current simulation time.
Why do I get "undefined reference to \`VL_RAND_RESET_I' or \`Verilated::...'"?
""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
You need to link your compiled Verilated code against the
:code:`verilated.cpp` file found in the include directory of the Verilator
kit. This is one target in the ``$(VK_GLOBAL_OBJS)`` make variable, which
should be part of your Makefile's link rule. If you use :vlopt:`--exe` or
:vlopt:`--binary`, this is done for you.
You need to link your compiled Verilated code against the ``verilated.cpp``
file found in the include directory of the Verilator kit. This is one
target in the ``$(VK_GLOBAL_OBJS)`` make variable, which should be part of
your Makefile's link rule. If you use :vlopt:`--exe` or :vlopt:`--binary`,
this is done for you.
Is the PLI supported?
"""""""""""""""""""""
Only somewhat. More specifically, the common PLI-ish calls $display,
$finish, $stop, $time, $write are converted to C++ equivalents. You can
Only somewhat. More specifically, the common PLI-ish calls $display,
$finish, $stop, $time, $write are converted to C++ equivalents. You can
also use the "import DPI" SystemVerilog feature to call C code (see the
chapter above). There is also limited VPI access to public signals.
chapter above). There is also limited VPI access to public signals.
If you want something more complex, since Verilator emits standard C++
code, you can write C++ routines that can access and modify signal
values without needing any PLI interface code, and call it with
code, you can write C++ routines that can access and modify signal values
without needing any PLI interface code, and call it with
$c("{any_c++_statement}").
See the :ref:`Connecting` section.
@ -380,8 +375,8 @@ See the :ref:`Connecting` section.
How do I make a Verilog module that contains a C++ object?
""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
You need to add the object to the structure Verilator creates, then
use $c to call a method inside your object. The
You need to add the object to the structure Verilator creates, then use $c
to call a method inside your object. The
:file:`test_regress/t/t_extend_class` files in the distribution show an
example of how to do this.
@ -399,12 +394,12 @@ How do I get faster build times?
disabled on these routines. See the OPT_FAST and OPT_SLOW make variables
and :ref:`Benchmarking & Optimization`.
* Use a recent compiler. Newer compilers tend to be faster.
* Use a recent compiler. Newer compilers tend to be faster.
* Compile in parallel on many machines and use caching; see the web for the
ccache, sccache, distcc, or icecream packages. ccache will skip GCC runs between
identical source builds, even across different users. If ccache was
installed when Verilator was built, it is used, or see OBJCACHE
ccache, sccache, distcc, or icecream packages. ccache will skip GCC runs
between identical source builds, even across different users. If ccache
was installed when Verilator was built, it is used, or see OBJCACHE
environment variable to override this. Also see the
:vlopt:`--output-split` option and :ref: `Profiling ccache efficiency`.
@ -421,27 +416,27 @@ How do I get faster build times?
Why do so many files need to recompile when I add a signal?
"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
Adding a new signal requires the symbol table to be recompiled. Verilator
uses one large symbol table, resulting in 2-3 fewer assembly
instructions for each signal access. This makes the execution time 10-15%
faster, but can result in more compilations when something changes.
Adding a new signal requires the symbol table to be recompiled. Verilator
uses one large symbol table, resulting in 2-3 fewer assembly instructions
for each signal access. This makes the execution time 10-15% faster, but
can result in more compilations when something changes.
How do I access Verilog functions/tasks in C?
"""""""""""""""""""""""""""""""""""""""""""""
Use the SystemVerilog Direct Programming Interface. You write a Verilog
Use the SystemVerilog Direct Programming Interface. You write a Verilog
function or task with input/outputs that match what you want to call in
with C. Then mark that function as a DPI export function. See the DPI
with C. Then mark that function as a DPI export function. See the DPI
chapter in the IEEE Standard.
How do I access C++ functions/tasks in Verilog?
"""""""""""""""""""""""""""""""""""""""""""""""
Use the SystemVerilog Direct Programming Interface. You write a Verilog
Use the SystemVerilog Direct Programming Interface. You write a Verilog
function or task with input/outputs that match what you want to call in
with C. Then mark that function as a DPI import function. See the DPI
with C. Then mark that function as a DPI import function. See the DPI
chapter in the IEEE Standard.
@ -450,44 +445,43 @@ How do I access signals in C?
The best thing to do is to make a SystemVerilog "export DPI" task or
function that accesses that signal, as described in the DPI chapter in the
manual and DPI tutorials on the web. This will allow Verilator to
optimize the model better and should be portable across simulators.
manual and DPI tutorials on the web. This will allow Verilator to optimize
the model better and should be portable across simulators.
If you really want raw access to the signals, declare the signals you will
be accessing with a :option:`/*verilator&32;public*/` metacomment before
the closing semicolon. Then scope into the C++ class to read the value of
the closing semicolon. Then scope into the C++ class to read the value of
the signal, as you would any other member variable.
Signals are the smallest of 8-bit unsigned chars (equivalent to uint8_t),
16-bit unsigned shorts (uint16_t), 32-bit unsigned longs (uint32_t), or
64-bit unsigned long longs (uint64_t) that fit the width of the signal.
Generally, you can use just uint32_t's for 1 to 32 bits, or uint64_t for
1 to 64 bits, and the compiler will properly up-convert smaller entities.
Generally, you can use just uint32_t's for 1 to 32 bits, or uint64_t for 1
to 64 bits, and the compiler will properly up-convert smaller entities.
Note that even signed ports are declared as unsigned; you must sign extend
yourself to the appropriate signal width.
Signals wider than 64 bits are stored as an array of 32-bit uint32_t's.
Thus, to read bits 31:0, access signal[0], and for bits 63:32, access
signal[1]. Unused bits (for example, bit numbers 65-96 of a 65-bit vector)
will always be zero. If you change the value, you must pack
zeros in the unused bits, or core-dumps may result because Verilator strips
array bound checks where it believes them to be unnecessary to improve
performance.
signal[1]. Unused bits (for example, bit numbers 65-96 of a 65-bit vector)
will always be zero. If you change the value, you must pack zeros in the
unused bits, or core-dumps may result because Verilator strips array bound
checks where it believes them to be unnecessary to improve performance.
In the SYSTEMC example above, if you had in our.v:
.. code-block:: sv
.. code-block:: sv
input clk /*verilator public*/;
// Note the placement of the semicolon above
input clk /*verilator public*/;
// Note the placement of the semicolon above
From the sc_main.cpp file, you'd then:
.. code-block:: C++
.. code-block:: C++
#include "Vour.h"
#include "Vour_our.h"
std::cout << "clock is " << top->our->clk << std::endl;
#include "Vour.h"
#include "Vour_our.h"
std::cout << "clock is " << top->our->clk << std::endl;
In this example, clk is a bool you can read or set as any other variable.
@ -498,11 +492,11 @@ clocks, or you'll get strange results.
Should a module be in Verilog or SystemC?
"""""""""""""""""""""""""""""""""""""""""
Sometimes there is a block that only interconnects instances, and you have a
choice if you write it in Verilog or SystemC. Everything else being
equal, the best performance is when Verilator sees all of the design. So, look
at the hierarchy of your design, labeling instances as to if they are
SystemC or Verilog. Then:
Sometimes there is a block that only interconnects instances, and you have
a choice if you write it in Verilog or SystemC. Everything else being
equal, the best performance is when Verilator sees all of the design. So,
look at the hierarchy of your design, labeling instances as to if they are
SystemC or Verilog. Then:
* A module with only SystemC instances below must be SystemC.
@ -510,7 +504,7 @@ SystemC or Verilog. Then:
SystemC. (As Verilator cannot connect to lower-level SystemC instances.)
* A module with only Verilog instances below can be either, but for best
performance should be Verilog. (The exception is if you have a design
that is instantiated many times; in this case, Verilating one of the lower
modules and instantiating that Verilated instances multiple times into a
SystemC module *may* be faster.)
performance should be Verilog. (The exception is if you have a design
that is instantiated many times; in this case, Verilating one of the
lower modules and instantiating that Verilated instances multiple times
into a SystemC module *may* be faster.)

60
docs/guide/install-cmake.rst
View File

@ -8,7 +8,8 @@ CMake Installation
******************
This section discusses how to build and install Verilator using cmake.
Currently cmake is only officially supported for Windows builds (not Linux).
Currently cmake is only officially supported for Windows builds (not
Linux).
.. _tools install:
@ -16,21 +17,27 @@ Quick Install
=============
1. Install Python for your platform from https://www.python.org/downloads/.
2. Install CMake for your platform from https://cmake.org/download/ or build it from source.
3. If the compiler of your choice is MSVC, then install https://visualstudio.microsoft.com/downloads/.
If the compiler of your choice is Clang, then install https://releases.llvm.org/download.html or build it from source.
4. For flex and bison use https://github.com/lexxmark/winflexbison to build and install.
5. For build on Windows using MSVC set environment variable WIN_FLEX_BISON to install directory.
For build on Windows/Linux/OS-X using ninja set the environment variable
FLEX_INCLUDE to the directory containing FlexLexer.h and ensure that flex/bison
is available within the PATH.
2. Install CMake for your platform from https://cmake.org/download/ or
build it from source.
3. If the compiler of your choice is MSVC, then install
https://visualstudio.microsoft.com/downloads/. If the compiler of your
choice is Clang, then install https://releases.llvm.org/download.html or
build it from source.
4. For flex and bison use https://github.com/lexxmark/winflexbison to build
and install.
5. For build on Windows using MSVC set environment variable WIN_FLEX_BISON
to install directory. For build on Windows/Linux/OS-X using ninja set
the environment variable FLEX_INCLUDE to the directory containing
FlexLexer.h and ensure that flex/bison is available within the PATH.
To obtain verilator sources download https://github.com/verilator/verilator/archive/refs/heads/master.zip
or clone https://github.com/verilator/verilator using git :ref:`Obtain Sources`.
To obtain Verilator sources download
https://github.com/verilator/verilator/archive/refs/heads/master.zip or
clone https://github.com/verilator/verilator using git :ref:`Obtain
Sources`.
To build using MSVC:
::
.. code-block:: bash
cd verilator # directory containing source files of verilator
mkdir build
@ -38,16 +45,15 @@ To build using MSVC:
cmake --build . --config Release
cmake --install . --prefix $PWD/../install
To build using ninja:
::
.. code-block:: bash
cd verilator
mkdir build
cmake -G Ninja .. -DCMAKE_BUILD_TYPE=Release --install-prefix $PWD/../install -DCMAKE_MAKE_PROGRAM=<path to ninja binary> -DBISON_EXECUTABLE=<path to bison> -DFLEX_EXECUTABLE=<path to flex>
<path to ninja binary> #execute ninja
cmake --install . --prefix $PWD/../install
cd verilator
mkdir build
cmake -G Ninja .. -DCMAKE_BUILD_TYPE=Release --install-prefix $PWD/../install -DCMAKE_MAKE_PROGRAM=<path to ninja binary> -DBISON_EXECUTABLE=<path to bison> -DFLEX_EXECUTABLE=<path to flex>
<path to ninja binary> #execute ninja
cmake --install . --prefix $PWD/../install
.. _cmake usage:
@ -61,12 +67,12 @@ install directory specified in the above build.
Example
=======
::
.. code-block:: bash
cd verilator/examples
cd cmake_hello_c
mkdir build
cd build
cmake .. # cmake -G Ninja ..
cmake --build . --config Release # ninja
# execute the generated binary
cd verilator/examples
cd cmake_hello_c
mkdir build
cd build
cmake .. # cmake -G Ninja ..
cmake --build . --config Release # ninja
# execute the generated binary

49
docs/guide/install.rst
View File

@ -14,10 +14,10 @@ This section discusses how to install Verilator.
Package Manager Quick Install
=============================
Using a distribution's package manager is the easiest way to get
started. (Note distribution packages almost never have the most recent
Verilator version, so we recommend following :ref:`Git Install` below,
instead.) To install as a package:
Using a distribution's package manager is the easiest way to get started.
(Note distribution packages almost never have the most recent Verilator
version, so we recommend following :ref:`Git Install` below, instead.) To
install as a package:
.. code-block:: bash
@ -28,15 +28,16 @@ For other distributions, refer to `Repology Verilator Distro Packages
.. _pre-commit quick install:
pre-commit Quick Install
=============================
Pre-commit Quick Install
========================
You can use Verilator's `pre-commit <https://pre-commit.com/>`__ hook to
lint your code before committing it. It encapsulates the :ref:`Verilator
Build Docker Container`, so you need docker on your system to use it. The
lint your code before committing it. It encapsulates the :ref:`Verilator
Build Docker Container`, so you need docker on your system to use it. The
verilator image will be downloaded automatically.
To use the hook, add the following entry to your :code:`.pre-commit-config.yaml`:
To use the hook, add the following entry to your
``.pre-commit-config.yaml``:
.. code-block:: yaml
@ -129,15 +130,15 @@ For constraints:
sudo apt-get install z3 # Optional solver
The following is optional but is recommended for nicely rendered command line
help when running Verilator:
The following is optional but is recommended for nicely rendered command
line help when running Verilator:
.. code-block:: bash
sudo apt-get install perl-doc
To build or run Verilator, the following are optional but should be installed
for good performance:
To build or run Verilator, the following are optional but should be
installed for good performance:
.. code-block:: bash
@ -176,7 +177,7 @@ SystemC code can be generated from Verilator (with :vlopt:`--sc`) if it is
installed as a package (see above).
Alternatively, from their sources, download `SystemC
<https://www.accellera.org/downloads/standards/systemc>`__. Follow their
<https://www.accellera.org/downloads/standards/systemc>`__. Follow their
installation instructions. You will need to set the
:option:`SYSTEMC_INCLUDE` environment variable to point to the include
directory with ``systemc.h`` in it, and set the :option:`SYSTEMC_LIBDIR`
@ -192,18 +193,18 @@ required at Verilator build time.
.. code-block:: bash
sudo apt-get install gtkwave # Optional Waveform viewer
sudo apt-get install gtkwave # Optional Waveform viewer
Install Z3
^^^^^^^^^^
In order to use constrained randomization the `Z3 Theorem Prover
<https://github.com/z3prover/z3>`__ must be installed, however this is
not required at Verilator build time. There are other compatible SMT solvers,
like CVC5/CVC4, but they are not guaranteed to work. Since different solvers are
faster for different scenarios, the solver to use at run-time can be specified
by the environment variable :option:`VERILATOR_SOLVER`.
<https://github.com/z3prover/z3>`__ must be installed, however this is not
required at Verilator build time. There are other compatible SMT solvers,
like CVC5/CVC4, but they are not guaranteed to work. Since different
solvers are faster for different scenarios, the solver to use at run-time
can be specified by the environment variable :option:`VERILATOR_SOLVER`.
.. _obtain sources:
@ -269,7 +270,7 @@ co-exist on a system.
./configure
# Running will use files from $VERILATOR_ROOT, so no install needed
Note after installing (see `Installation`_), a calling program or shell
Note after installing (see ref:`Installation`), a calling program or shell
must set the environment variable :option:`VERILATOR_ROOT` to point to this
Git directory, then execute ``$VERILATOR_ROOT/bin/verilator``, which will
find the path to all needed files.
@ -281,7 +282,7 @@ find the path to all needed files.
You may be an OS package maintainer building a Verilator package, or you
may eventually be installing onto a project/company-wide "CAD" tools disk
that may support multiple versions of every tool. Tell configure the
eventual destination directory name. We recommend that the destination
eventual destination directory name. We recommend that the destination
location include the Verilator version name:
.. code-block:: bash
@ -291,7 +292,7 @@ location include the Verilator version name:
# For the tarball, use the version number instead of git describe
./configure --prefix /CAD_DISK/verilator/`git describe | sed "s/verilator_//"`
Note after installing (see `Installation`_), you need to add the path to
Note after installing (see ref:`Installation`), you need to add the path to
the ``bin`` directory to your ``PATH``. Or, if you use `modulecmd
<https://modules.sourceforge.net/>`__, you'll want a module file like the
following:
@ -317,7 +318,7 @@ configure's default system paths:
unsetenv VERILATOR_ROOT # if your shell is csh
./configure
Then after installing (see `Installation`_), the binaries should be in a
Then after installing (see ref:`Installation`), the binaries should be in a
location already in your ``$PATH`` environment variable.

294
docs/guide/languages.rst
View File

@ -5,7 +5,7 @@
Input Languages
***************
This section describes the languages Verilator takes as input. See also
This section describes the languages Verilator takes as input. See also
:ref:`Verilator Control Files`.
@ -15,7 +15,7 @@ Language Standard Support
Verilog 2001 (IEEE 1364-2001) Support
-------------------------------------
Verilator supports most Verilog 2001 language features. This includes
Verilator supports most Verilog 2001 language features. This includes
signed numbers, "always @\*", generate statements, multidimensional arrays,
localparam, and C-style declarations inside port lists.
@ -23,7 +23,7 @@ localparam, and C-style declarations inside port lists.
Verilog 2005 (IEEE 1364-2005) Support
-------------------------------------
Verilator supports most Verilog 2005 language features. This includes the
Verilator supports most Verilog 2005 language features. This includes the
\`begin_keywords and \`end_keywords compiler directives, $clog2, and the
uwire keyword.
@ -77,8 +77,8 @@ Verilog AMS Support
Verilator implements a very small subset of Verilog AMS (Verilog Analog and
Mixed-Signal Extensions) with the subset corresponding to those VMS
keywords with near-equivalents in Verilog IEEE 1364 or SystemVerilog
IEEE 1800.
keywords with near-equivalents in Verilog IEEE 1364 or SystemVerilog IEEE
1800.
AMS parsing is enabled with :vlopt:`--language VAMS <--language>` or
:vlopt:`--language 1800+VAMS <--language>`.
@ -90,10 +90,9 @@ wreal.
Synthesis Directive Assertion Support
-------------------------------------
Verilator reads any :code:`//synopsys full_case` or :code:`//synopsys
parallel_case` directives. The same applies to any :code:`//ambit
synthesis`, :code:`//cadence` or :code:`//pragma` directives of the same
form.
Verilator reads any ``//synopsys full_case`` or ``//synopsys
parallel_case`` directives. The same applies to any ``//ambit synthesis``,
``//cadence`` or ``//pragma`` directives of the same form.
When these synthesis directives are discovered, unless
:vlopt:`--no-assert-case` option is used, Verilator will either formally
@ -102,7 +101,7 @@ appropriate code to detect failing cases at simulation runtime and print an
"Assertion failed" error message.
Verilator likewise also asserts any "unique" or "priority" SystemVerilog
keywords on case statements, as well as "unique" on if statements. However,
keywords on case statements, as well as "unique" on if statements. However,
"priority if" is currently ignored.
@ -115,17 +114,17 @@ With :vlopt:`--timing`, all timing controls are supported:
* event control statements not only at the top of a process,
* intra-assignment timing controls,
* net delays,
* :code:`wait` statements,
* ``wait`` statements,
as well as all flavors of :code:`fork`.
as well as all flavors of ``fork``.
Compiling a Verilated design that uses these features requires a
compiler with C++20 coroutine support, e.g. Clang 5, GCC 10, or newer.
Compiling a Verilated design that uses these features requires a compiler
with C++20 coroutine support, e.g. Clang 5, GCC 10, or newer.
:code:`#0` delays cause Verilator to issue the :option:`ZERODLY` warning, as
they work differently than described in the LRM. They do not schedule process
resumption in the Inactive region, though the process will get resumed in the
same time slot.
``#0`` delays cause Verilator to issue the :option:`ZERODLY` warning, as
they work differently than described in the LRM. They do not schedule
process resumption in the Inactive region, though the process will get
resumed in the same time slot.
Rising/falling/turn-off delays are currently unsupported and cause the
:option:`RISEFALLDLY` warning.
@ -135,8 +134,8 @@ is always the one chosen. Such expressions cause the :option:`MINTYPMAXDLY`
warning.
Another consequence of using :vlopt:`--timing` is that the :vlopt:`--main`
option generates a main file with a proper timing eval loop, eliminating the
need for writing any driving C++ code. You can simply compile the
option generates a main file with a proper timing eval loop, eliminating
the need for writing any driving C++ code. You can simply compile the
simulation (perhaps using :vlopt:`--build`) and run it.
With :vlopt:`--no-timing`, all timing controls cause the :option:`NOTIMING`
@ -152,7 +151,7 @@ error, except:
Forks cause this error as well, except:
* forks with no statements,
* :code:`fork..join` or :code:`fork..join_any` with one statement,
* ``fork..join`` or ``fork..join_any`` with one statement,
* forks with :vlopt:`--bbox-unsup`.
If neither :vlopt:`--timing` nor :vlopt:`--no-timing` is specified, all
@ -160,16 +159,16 @@ timing controls cause the :option:`NEEDTIMINGOPT` error, except event
controls at the top of the process. Forks cause this error as well, except:
* forks with no statements,
* :code:`fork..join` or :code:`fork..join_any` with one statement,
* ``fork..join`` or ``fork..join_any`` with one statement,
* forks with :vlopt:`--bbox-unsup`.
Timing controls and forks can also be ignored in specific files or parts of
files. The :option:`/*verilator&32;timing_off*/` and
:option:`/*verilator&32;timing_off*/` metacomments will make Verilator ignore
the encompassed timing controls and forks, regardless of the chosen
:option:`/*verilator&32;timing_off*/` metacomments will make Verilator
ignore the encompassed timing controls and forks, regardless of the chosen
:vlopt:`--timing` or :vlopt:`--no-timing` option. This can also be achieved
using the :option:`timing_off` and :option:`timing_off` options in Verilator
Control Files.
using the :option:`timing_off` and :option:`timing_off` options in
Verilator Control Files.
.. _language limitations:
@ -189,38 +188,38 @@ Compiler would, namely given a block of the form:
.. code-block:: sv
always @(x) y = x & z;
always @(x) y = x & z;
This will recompute y when there is a potential for change in x or a change
in z; that is when the flops computing x or z evaluate (which is what
Design Compiler will synthesize.) A compliant simulator will only
calculate y if x changes. We recommend using always_comb to make the code
run the same everywhere. Also avoid putting $displays in combo blocks, as
they may print multiple times when not desired, even on compliant
simulators as event ordering is not specified.
Design Compiler will synthesize.) A compliant simulator will only calculate
y if x changes. We recommend using always_comb to make the code run the
same everywhere. Also avoid putting $displays in combo blocks, as they may
print multiple times when not desired, even on compliant simulators as
event ordering is not specified.
Signal Naming
-------------
To avoid conflicts with C symbol naming, any character in a signal name
that is not alphanumeric nor a single underscore will be replaced by __0hh
where hh is the hex code of the character. To avoid conflicts with
Verilator's internal symbols, any double underscore is replaced with
___05F (5F is the hex code of an underscore.)
that is not alphanumeric nor a single underscore will be replaced by
`__0hh` where `hh` is the hex code of the character. To avoid conflicts
with Verilator's internal symbols, any double underscore is replaced with
`___05F` (5F is the hex code of an underscore.)
Bind
----
Verilator only supports bind to a target module name, not to an
instance path.
Verilator only supports bind to a target module name, not to an instance
path.
Class
-----
Verilator class support is limited but in active development. Verilator
Verilator class support is limited but in active development. Verilator
supports members, methods, class extend, and class parameters.
@ -241,7 +240,7 @@ code.
Latches
-------
Verilator is optimized for edge-sensitive (flop-based) designs. It will
Verilator is optimized for edge-sensitive (flop-based) designs. It will
attempt to do the correct thing for latches, but most performance
optimizations will be disabled around the latch.
@ -264,33 +263,32 @@ However, it has two features that uncover most initialization bugs
(including many that a four-state simulator will miss.)
Identity comparisons (=== or !==) are converted to standard ==/!= when
neither side is a constant. This may make the expression yield a different
result than a four-state simulator. An === comparison to X will
always be false, so that Verilog code which checks for uninitialized logic
will not fire.
neither side is a constant. This may make the expression yield a different
result than a four-state simulator. An === comparison to X will always be
false, so that Verilog code which checks for uninitialized logic will not
fire.
Assigning X to a variable will assign a constant value as determined by the
:vlopt:`--x-assign` option. This allows runtime randomization; thus, if
the value is used, the random value should cause downstream errors.
Integers also get randomized, even though the Verilog 2001 specification
says they initialize to zero. However, randomization happens at
initialization time; hence, during a single simulation run, the same
constant (but random) value will be used every time the assignment is
executed.
:vlopt:`--x-assign` option. This allows runtime randomization; thus, if the
value is used, the random value should cause downstream errors. Integers
also get randomized, even though the Verilog 2001 specification says they
initialize to zero. However, randomization happens at initialization time;
hence, during a single simulation run, the same constant (but random) value
will be used every time the assignment is executed.
All variables, depending on :vlopt:`--x-initial` setting, are typically
randomly initialized using a function. You can determine that reset is
working correctly by running several random simulation runs. On the first
run, have the function initialize variables to zero. On the second, have
it initialize variables to one. On the third and following runs, have it
initialize them randomly. If the results match, reset works. (Note that
this is what the hardware will do.) In practice, setting all variables to
randomly initialized using a function. You can determine that reset is
working correctly by running several random simulation runs. On the first
run, have the function initialize variables to zero. On the second, have it
initialize variables to one. On the third and following runs, have it
initialize them randomly. If the results match, reset works. (Note that
this is what the hardware will do.) In practice, setting all variables to
one at startup finds the most problems (since control signals are typically
active-high).
:vlopt:`--x-assign` applies to variables explicitly initialized or assigned
an X. Uninitialized clocks are initialized to zero, while all other state
holding variables are initialized to a random value. Event-driven
holding variables are initialized to a random value. Event-driven
simulators will generally trigger an edge on a transition from X to 1
(posedge) or X to 0 (negedge). However, by default, since clocks are
initialized to zero, Verilator will not trigger an initial negedge. Some
@ -302,25 +300,24 @@ and without this option will find such problems.
Tri/Inout
---------
Verilator converts some simple tristate structures into two state. Pullup,
Verilator converts some simple tristate structures into two state. Pullup,
pulldown, bufif0, bufif1, notif0, notif1, pmos, nmos, tri0 and tri1 are
also supported. Simple comparisons with :code:`=== 1'bz` are also
supported.
also supported. Simple comparisons with ``=== 1'bz`` are also supported.
An assignment of the form:
.. code-block:: sv
inout driver;
wire driver = (enable) ? output_value : 1'bz;
inout driver;
wire driver = (enable) ? output_value : 1'bz;
Will be converted to:
.. code-block:: sv
input driver; // Value being driven in from "external" drivers
output driver__en; // True if driven from this module
output driver__out; // Value being driven from this module
input driver; // Value being driven in from "external" drivers
output driver__en; // True if driven from this module
output driver__out; // Value being driven from this module
External logic will be needed to combine these signals with any external
drivers.
@ -334,8 +331,8 @@ Gate Primitives
---------------
The 2-state gate primitives (and, buf, nand, nor, not, or, xnor, xor) are
directly converted to behavioral equivalents. The 3-state and MOS gate
primitives are not supported. User-defined primitive (UDP) tables are
directly converted to behavioral equivalents. The 3-state and MOS gate
primitives are not supported. User-defined primitive (UDP) tables are
supported.
@ -360,10 +357,10 @@ Array Out of Bounds
Writing a memory element outside the bounds specified for the array may
cause a different memory element inside the array to be written instead.
For power-of-2 sized arrays, Verilator will give a width warning and the
address. For non-power-of-2-sizes arrays, index 0 will be written.
address. For non-power-of-2-sizes arrays, index 0 will be written.
Reading a memory element outside the bounds specified for the array will
give a width warning and wrap around the power-of-2 size. For
give a width warning and wrap around the power-of-2 size. For
non-power-of-2 sizes, it will return an unspecified constant of the
appropriate width.
@ -371,21 +368,21 @@ appropriate width.
Assertions
----------
Verilator is beginning to add support for assertions. Verilator currently
only converts assertions to simple :code:`if (...) error` statements, and
Verilator is beginning to add support for assertions. Verilator currently
only converts assertions to simple ``if (...) error`` statements, and
coverage statements to increment the line counters described in the
coverage section.
Verilator does not support SEREs yet. All assertion and coverage
statements must be simple expressions that complete in one cycle.
Verilator does not support SEREs yet. All assertion and coverage statements
must be simple expressions that complete in one cycle.
Encrypted Verilog
-----------------
Open-source simulators like Verilator cannot use encrypted RTL
(i.e. IEEE P1735). Talk to your IP vendor about delivering IP blocks via
Verilator's :vlopt:`--protect-lib` feature.
Open-source simulators like Verilator cannot use encrypted RTL (i.e. IEEE
P1735). Talk to your IP vendor about delivering IP blocks using Verilator's
:vlopt:`--protect-lib` feature.
Language Keyword Limitations
@ -394,6 +391,7 @@ Language Keyword Limitations
This section describes specific limitations for each language keyword.
.. Hack to get long definition list:
.. |cmdslong1| replace:: \`__FILE__, \`__LINE__, \`begin_keywords,
\`begin_keywords, \`begin_keywords, \`begin_keywords, \`begin_keywords,
\`define, \`else, \`elsif, \`end_keywords, \`endif, \`error, \`ifdef,
@ -402,8 +400,7 @@ This section describes specific limitations for each language keyword.
\`systemc_implementation, \`systemc_interface, \`undef, \`verilog
|cmdslong1|
Fully supported.
Fully supported.
.. Hack to get long definition list:
@ -417,125 +414,126 @@ This section describes specific limitations for each language keyword.
tri, typedef, var, vectored, while, wire, xnor, xor
|cmdslong2|
Generally supported.
Generally supported.
++, -- operators
Increment/decrement can only be used as standalone statements or in
certain limited cases.
Increment/decrement can only be used as standalone statements or in
certain limited cases.
'{} operator
Assignment patterns with an order based, default, constant integer (array)
or member identifier (struct/union) keys are supported. Data type keys
and keys computed from a constant expression are not supported.
Assignment patterns with an order based, default, constant integer
(array) or member identifier (struct/union) keys are supported. Data
type keys and keys computed from a constant expression are not
supported.
\`uselib
Uselib, a vendor-specific library specification method, is ignored along
with anything following it until the end of that line.
Uselib, a vendor-specific library specification method, is ignored along
with anything following it until the end of that line.
cast operator
Casting is supported only between simple scalar types, signed and
unsigned, not arrays nor structs.
Casting is supported only between simple scalar types, signed and
unsigned, not arrays nor structs.
chandle
Treated as a "longint"; does not yet warn about operations specified as
illegal on chandles.
Treated as a "longint"; does not yet warn about operations specified as
illegal on chandles.
checker
Treated as a "module"; does not yet warn about many constructs illegal
inside a checker.
Treated as a "module"; does not yet warn about many constructs illegal
inside a checker.
disable
Disable statements may be used only if the block being disabled is a
block the disable statement itself is inside. This was commonly used to
provide loop break and continue functionality before SystemVerilog added
the break and continue keywords.
Disable statements may be used only if the block being disabled is a
block the disable statement itself is inside. This was commonly used to
provide loop break and continue functionality before SystemVerilog added
the break and continue keywords.
force, release
Verilator supports the procedural `force` (and corresponding `release`)
statement. However, the behavior of the `force` statement does not
entirely comply with IEEE 1800-2023:
Verilator supports the procedural `force` (and corresponding `release`)
statement. However, the behavior of the `force` statement does not
entirely comply with IEEE 1800-2023:
#. Using forced variable as a value to another force statement is
currently not supported. The dependent force statement is forced by an
initial constant value.
#. Using forced variable as a value to another force statement is
currently not supported. The dependent force statement is forced by
an initial constant value.
#. Force/release with procedural continuous assignment is not supported.
The assignment is treated as procedural.
#. Force/release with procedural continuous assignment is not supported.
The assignment is treated as procedural.
#. Expressions using multiple variable references or function calls on
forced right-hand side are not sensitive to dependency changes.
#. Expressions using multiple variable references or function calls on
forced right-hand side are not sensitive to dependency changes.
inside
Inside expressions may not include unpacked array traversal or $ as an
upper bound. Case inside and case matches are also unsupported.
Inside expressions may not include unpacked array traversal or $ as an
upper bound. Case inside and case matches are also unsupported.
interface
Interfaces and modports, including generated data types are
supported. Generate blocks around modports are not supported, nor are
virtual interfaces nor unnamed interfaces.
Interfaces and modports, including generated data types are supported.
Generate blocks around modports are not supported, nor are virtual
interfaces nor unnamed interfaces.
shortreal
Short floating point (shortreal) numbers are converted to real. Most
other simulators either do not support float, or convert likewise.
Short floating point (shortreal) numbers are converted to real. Most
other simulators either do not support float, or convert likewise.
specify specparam
All timing checks and specify blocks (except specparam, which is
supported) are ignored.
All timing checks and specify blocks (except specparam, which is
supported) are ignored.
uwire
Verilator does not perform warning checking on uwires; it treats the
uwire keyword as if it were the normal wire keyword.
Verilator does not perform warning checking on uwires; it treats the
uwire keyword as if it were the normal wire keyword.
$bits, $countbits, $countones, $finish, $isunknown, $onehot, $onehot0, $signed, $stime, $stop, $time, $unsigned,
Generally supported.
Generally supported.
$dump/$dumpports and related
$dumpfile or $dumpports will create a VCD or FST file (based on
the :vlopt:`--trace-vcd` option given when the model was Verilated). This
will take effect starting at the next eval() call. If you have multiple
Verilated designs under the same C model, this will dump signals
only from the design containing the $dumpvars.
$dumpfile or $dumpports will create a VCD or FST file (based on the
:vlopt:`--trace-vcd` option given when the model was Verilated). This
will take effect starting at the next eval() call. If you have multiple
Verilated designs under the same C model, this will dump signals only
from the design containing the $dumpvars.
$dumpvars and $dumpports module identifier is ignored; the traced
instances will always start at the top of the design. The levels argument
is also ignored; use tracing_on/tracing_off pragmas instead.
$dumpvars and $dumpports module identifier is ignored; the traced
instances will always start at the top of the design. The levels
argument is also ignored; use tracing_on/tracing_off pragmas instead.
$dumpportson/$dumpportsoff/$dumpportsall/$dumpportslimit filename
argument is ignored; only a single trace file may be active at once.
$dumpportson/$dumpportsoff/$dumpportsall/$dumpportslimit filename
argument is ignored; only a single trace file may be active at once.
$dumpall/$dumpportsall, $dumpon/$dumpportson, $dumpoff/$dumpportsoff, and
$dumplimit/$dumpportlimit are currently ignored.
$dumpall/$dumpportsall, $dumpon/$dumpportson, $dumpoff/$dumpportsoff,
and $dumplimit/$dumpportlimit are currently ignored.
$error, $fatal, $info, $warning.
Generally supported.
Generally supported.
$exit, $finish, $stop
The rarely used optional parameter to $finish and $stop is ignored; $exit
is aliased to $finish.
The rarely used optional parameter to $finish and $stop is ignored;
$exit is aliased to $finish.
$fopen, $fclose, $fdisplay, $ferror, $feof, $fflush, $fgetc, $fgets, $fscanf, $fwrite, $fscanf, $sscanf
Generally supported.
Generally supported.
$fullskew, $hold, $nochange, $period, $recovery, $recrem, $removal, $setup, $setuphold, $skew, $timeskew, $width
All specify blocks and timing checks are ignored.
All specify blocks and timing checks are ignored.
$random, $urandom, $urandom_range
Use :vlopt:`+verilator+seed+\<value\>` runtime option to set the seed if
there is no $random nor $urandom optional argument to set the seed.
There is one random seed per C thread, not per module for $random, nor
per object for random stability of $urandom/$urandom_range.
Use :vlopt:`+verilator+seed+\<value\>` runtime option to set the seed if
there is no $random nor $urandom optional argument to set the seed.
There is one random seed per C thread, not per module for $random, nor
per object for random stability of $urandom/$urandom_range.
$readmemb, $readmemh
Read memory commands are supported. Verilator and the Verilog
specification do not include support for readmem to multi-dimensional
arrays.
Read memory commands are supported. Verilator and the Verilog
specification do not include support for readmem to multi-dimensional
arrays.
$test$plusargs, $value$plusargs
Supported, but the instantiating C++/SystemC wrapper must call
Supported, but the instantiating C++/SystemC wrapper must call
.. code-block:: C++
.. code-block:: C++
{VerilatedContext*} ->commandArgs(argc, argv);
{VerilatedContext*} ->commandArgs(argc, argv);
to register the command line before calling $test$plusargs or
$value$plusargs. Or use :vlopt:`--binary` or :vlopt:`--main`.
to register the command line before calling $test$plusargs or
$value$plusargs. Or use :vlopt:`--binary` or :vlopt:`--main`.

28
docs/guide/overview.rst
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@ -9,22 +9,22 @@ Welcome to Verilator!
The Verilator package converts Verilog [#]_ and SystemVerilog [#]_ hardware
description language (HDL) designs into a C++ or SystemC model that, after
compiling, can be executed. Verilator is not a traditional simulator but a
compiling, can be executed. Verilator is not a traditional simulator but a
compiler.
Verilator is typically used as follows:
1. The :command:`verilator` executable is invoked with parameters similar
to GCC or other simulators such as Cadence Verilog-XL/NC-Verilog, or
Synopsys VCS. Verilator reads the specified SystemVerilog code, lints it,
Synopsys VCS. Verilator reads the specified SystemVerilog code, lints it,
optionally adds coverage and waveform tracing support, and compiles the
design into a source-level multithreaded C++ or SystemC "model". The
design into a source-level multithreaded C++ or SystemC "model". The
resulting model's C++ or SystemC code is output as .cpp and .h files. This
is referred to as "Verilating", and the process is "to Verilate"; the
output is a "Verilated" model.
2. For simulation, a small user-written C++ wrapper file is required, the
"wrapper". This wrapper defines the C++ standard function "main()", which
"wrapper". This wrapper defines the C++ standard function "main()", which
instantiates the Verilated model as a C++/SystemC object.
3. The user C++ wrapper, the files created by Verilator, a "runtime
@ -35,21 +35,21 @@ then compiled using a C++ compiler to create a simulation executable.
"simulation runtime".
5. If appropriately enabled, the executable may also generate waveform
traces of the design that may be viewed. It may also create coverage
traces of the design that may be viewed. It may also create coverage
analysis data for post-analysis.
The best place to get started is to try the :ref:`Examples`.
.. [#] Verilog is defined by the `Institute of Electrical and Electronics
Engineers (IEEE) Standard for Verilog Hardware Description
Language`, Std. 1364, released in 1995, 2001, and 2005. The
Verilator documentation uses the shorthand, e.g., "IEEE 1364-2005",
to refer to the, e.g., 2005 version of this standard.
Engineers (IEEE) Standard for Verilog Hardware Description Language`,
Std. 1364, released in 1995, 2001, and 2005. The Verilator documentation
uses the shorthand, e.g., "IEEE 1364-2005", to refer to the, e.g., 2005
version of this standard.
.. [#] SystemVerilog is defined by the `Institute of Electrical and
Electronics Engineers (IEEE) Standard for SystemVerilog - Unified
Hardware Design, Specification, and Verification Language`, Standard
1800, released in 2005, 2009, 2012, 2017, and 2023. The Verilator
documentation uses the shorthand e.g., "IEEE 1800-2023", to refer to
the, e.g., 2023 version of this standard.
Electronics Engineers (IEEE) Standard for SystemVerilog - Unified
Hardware Design, Specification, and Verification Language`, Standard
1800, released in 2005, 2009, 2012, 2017, and 2023. The Verilator
documentation uses the shorthand e.g., "IEEE 1800-2023", to refer to
the, e.g., 2023 version of this standard.

234
docs/guide/simulating.rst
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@ -8,7 +8,7 @@ Simulating (Verilated-Model Runtime)
************************************
This section describes items related to simulating, that is, using a
Verilated model's executable. For the runtime arguments to a simulated
Verilated model's executable. For the runtime arguments to a simulated
model, see :ref:`Simulation Runtime Arguments`.
@ -49,9 +49,9 @@ The information in this report is:
Simulated time (if non-zero) divided by wall time. e.g. `123 ns/s` means
123 simulated nanoseconds took 1 second of wall time; for a model with
only a 1 GHz clock that would be equivalent to 123.1 cycles per
second. The units are automatically selected to give a number between 1
and 1000. The wall time includes initialization, initial and final
only a 1 GHz clock that would be equivalent to 123.1 cycles per second.
The units are automatically selected to give a number between 1
and 1000. The wall time includes initialization, initial and final
process blocks, so indicates a slower speed than if the model had a
longer runtime.
@ -74,24 +74,22 @@ Benchmarking & Optimization
===========================
For best performance, run Verilator with the :vlopt:`-O3`
:vlopt:`--x-assign fast <--x-assign>`
:vlopt:`--x-initial fast <--x-initial>`
:vlopt:`--no-assert` options. The :vlopt:`-O3`
option will require a longer time to run Verilator, and
:vlopt:`--x-assign fast <--x-assign>`
:vlopt:`--x-initial fast <--x-assign>`
may increase the risk of reset bugs in trade for performance. The
:vlopt:`--no-assert` will suppress checking assertions, which is faster and
appropriate for known-good models running software, but may hide design
errors. See the above documentation for these options.
:vlopt:`--x-assign fast <--x-assign>` :vlopt:`--x-initial fast
<--x-initial>` :vlopt:`--no-assert` options. The :vlopt:`-O3` option will
require a longer time to run Verilator, and :vlopt:`--x-assign fast
<--x-assign>` :vlopt:`--x-initial fast <--x-assign>` may increase the risk
of reset bugs in trade for performance. The :vlopt:`--no-assert` will
suppress checking assertions, which is faster and appropriate for
known-good models running software, but may hide design errors. See the
above documentation for these options.
If using Verilated multithreaded, consider overriding Verilator's default
thread-to-processor assignment by using ``numactl``; see
:ref:`Multithreading`. Also, consider using profile-guided optimization;
see :ref:`Thread PGO`.
Minor Verilog code changes can also give big wins. You should not have any
:option:`UNOPTFLAT` warnings from Verilator. Fixing these warnings can
Minor Verilog code changes can also give big wins. You should not have any
:option:`UNOPTFLAT` warnings from Verilator. Fixing these warnings can
result in huge improvements; one user fixed their one UNOPTFLAT warning by
making a simple change to a clocked latch used to gate clocks and gained a
60% performance improvement.
@ -108,14 +106,14 @@ example:
.. code-block:: bash
make OPT_FAST="-Os -march=native" -f Vour.mk Vour__ALL.a
make OPT_FAST="-Os -march=native" -f Vour.mk Vour__ALL.a
OPT_FAST specifies optimization options for those parts of the model
on the fast path. This is mostly code that is executed every
cycle. OPT_SLOW applies to slow-path code, which rarely executes, often
only once at the beginning or end of the simulation. OPT_SLOW is
ignored if VM_PARALLEL_BUILDS is not 1, in which case all generated code
will be compiled in a single compilation unit using OPT_FAST. See also the
OPT_FAST specifies optimization options for those parts of the model on the
fast path. This is mostly code that is executed every cycle. OPT_SLOW
applies to slow-path code, which rarely executes, often only once at the
beginning or end of the simulation. OPT_SLOW is ignored if
VM_PARALLEL_BUILDS is not 1, in which case all generated code will be
compiled in a single compilation unit using OPT_FAST. See also the
Verilator :vlopt:`--output-split` option. The OPT_GLOBAL variable applies
to common code in the runtime library used by Verilated models (shipped in
$VERILATOR_ROOT/include). Additional C++ files passed on the verilator
@ -134,10 +132,10 @@ benefit), but compile times may be excessively large even with medium-sized
designs. Compilation times can be improved at the expense of simulation
speed by reducing optimization, for example, with OPT_FAST="-O0". Often
good simulation speed can be achieved with OPT_FAST="-O1 -fstrict-aliasing"
but with improved compilation times. Files controlled by OPT_SLOW have
but with improved compilation times. Files controlled by OPT_SLOW have
little effect on performance, and therefore OPT_SLOW is empty by default
(equivalent to "-O0") for improved compilation speed. In common use cases,
there should be little benefit in changing OPT_SLOW. OPT_GLOBAL is set to
there should be little benefit in changing OPT_SLOW. OPT_GLOBAL is set to
"-Os" by default, and there should rarely be a need to change it. As the
runtime library is small compared to many Verilated models, disabling
optimization on the runtime library should not seriously affect overall
@ -169,7 +167,7 @@ inlined functions that drive the compiler nuts.)
You may uncover further tuning possibilities by profiling the Verilog code.
See :ref:`profiling`.
When done optimizing, please let the author know the results. We like to
When done optimizing, please let the author know the results. We like to
keep tabs on how Verilator compares and may be able to suggest additional
improvements.
@ -180,7 +178,7 @@ Coverage Analysis
=================
Verilator supports adding code to the Verilated model to support
SystemVerilog code coverage. With :vlopt:`--coverage`, Verilator enables
SystemVerilog code coverage. With :vlopt:`--coverage`, Verilator enables
all forms of coverage:
- :ref:`User Coverage`
@ -205,7 +203,7 @@ point under the coverage name "DefaultClock":
.. code-block:: sv
DefaultClock: cover property (@(posedge clk) cyc==3);
DefaultClock: cover property (@(posedge clk) cyc==3);
.. _line coverage:
@ -215,8 +213,8 @@ Line Coverage
With :vlopt:`--coverage` or :vlopt:`--coverage-line`, Verilator will
automatically add coverage analysis at each code flow change point (e.g.,
at branches). At each such branch, a counter is incremented. At the end
of a test, the counters, filename, and line number corresponding to each
at branches). At each such branch, a counter is incremented. At the end of
a test, the counters, filename, and line number corresponding to each
counter are written into the coverage file.
Verilator may over-count combinatorial (non-clocked) blocks when those
@ -231,32 +229,32 @@ Toggle Coverage
---------------
With :vlopt:`--coverage` or :vlopt:`--coverage-toggle`, Verilator will
automatically add toggle coverage analysis into the Verilated model.
automatically add toggle coverage analysis into the Verilated model.
Every bit of every signal in a module has a counter inserted, and the
counter will increment on every edge change of the corresponding bit.
Signals that are part of tasks or begin/end blocks are considered local
variables and are not covered. Signals that begin with underscores (see
variables and are not covered. Signals that begin with underscores (see
:vlopt:`--coverage-underscore`), are integers, or are very wide (>256 bits
total storage across all dimensions, see :vlopt:`--coverage-max-width`) are
also not covered.
Hierarchy is compressed, so if a module is instantiated multiple times,
coverage will be summed for that bit across **all** instantiations of that
module with the same parameter set. A module instantiated with different
module with the same parameter set. A module instantiated with different
parameter values is considered a different module and will get counted
separately.
Verilator makes a minimally-intelligent decision about what clock domain
the signal goes to, and only looks for edges in that clock domain. This
the signal goes to, and only looks for edges in that clock domain. This
means that edges may be ignored if it is known that the receiving logic
could never see the edge. This algorithm may improve in the future. The
net result is that coverage may be lower than what would be seen by looking
at traces, but the coverage is a more accurate representation of the
quality of stimulus into the design.
could never see the edge. This algorithm may improve in the future. The net
result is that coverage may be lower than what would be seen by looking at
traces, but the coverage is a more accurate representation of the quality
of stimulus into the design.
There may be edges counted near time zero while the model stabilizes. It's
There may be edges counted near time zero while the model stabilizes. It's
a good practice to zero all coverage just before releasing reset to prevent
counting such behavior.
@ -276,20 +274,20 @@ truth table how every Boolean truth-table possibility in the expression
occurred.
Multi-bit expressions are ignored, but sub-expressions with are entirely
Boolean are analyzed. Expression coverage does not fully explore the truth
table of an expression, rather is looks at each term's contribution. E.g.
Boolean are analyzed. Expression coverage does not fully explore the truth
table of an expression, rather is looks at each term's contribution. E.g.
an AND operation will check coverage for TT, XF and FX.
Some expressions may produce too many cover points. Verilator limits the
Some expressions may produce too many cover points. Verilator limits the
maximum number of cover points per expression to 32, but this may be
controlled with :vlopt:`--coverage-expr-max`.
Below is an example showing expression coverage produced from `verilator_coverage`
as applied to the condition expression inside an if statement. Each line
shows the minimum number of terms and their values (e.g. `(t1==0 && t2==1)`) needed
to reach a result for the overall expression (e.g. `=> 1`). Each line also
shows the number of times this combination was hit. Note that individual lines
are not mutually exclusive.
Below is an example showing expression coverage produced from
`verilator_coverage` as applied to the condition expression inside an if
statement. Each line shows the minimum number of terms and their values
(e.g. `(t1==0 && t2==1)`) needed to reach a result for the overall
expression (e.g. `=> 1`). Each line also shows the number of times this
combination was hit. Note that individual lines are not mutually exclusive.
.. code-block::
@ -313,7 +311,7 @@ and enable coverage respectively around that block. Or, use the
Verilator automatically disables coverage of lines and branches with a
$stop in them, as it is assumed that $stop branches contain an error check
that should not occur. A :option:`/*verilator&32;coverage_block_off*/`
that should not occur. A :option:`/*verilator&32;coverage_block_off*/`
metacomment will perform a similar function on any code in that block or
below.
@ -332,17 +330,17 @@ To get the coverage data from the model, write the coverage with either:
:vlopt:`+verilator+coverage+file+\<filename\>`.
2. In the user wrapper code, typically at the end once a test passes, call
:code:`Verilated::threadContextp()->coveragep()->write` with an argument
of the filename for the coverage data file to write coverage data to
``Verilated::threadContextp()->coveragep()->write`` with an argument of
the filename for the coverage data file to write coverage data to
(typically "logs/coverage.dat").
Run each of your tests in different directories, potentially in parallel.
Each test will create the file specified above,
e.g. :file:`logs/coverage.dat`.
Each test will create the file specified above, e.g.
:file:`logs/coverage.dat`.
After running all of the tests, execute the :command:`verilator_coverage`
command, passing arguments pointing to the filenames of all the
individual coverage files. :command:`verilator_coverage` will read the
command, passing arguments pointing to the filenames of all the individual
coverage files. :command:`verilator_coverage` will read the
:file:`logs/coverage.dat` file(s), and create an annotated source code
listing showing code coverage details.
@ -357,9 +355,8 @@ Additional options of :command:`verilator_coverage` allow for the merging
of coverage data files or other transformations.
Info files can be written by verilator_coverage for import to
:command:`lcov`. This enables using :command:`genhtml` for HTML reports
and importing reports to sites such as `https://codecov.io
<https://codecov.io>`_.
:command:`lcov`. This enables using :command:`genhtml` for HTML reports and
importing reports to sites such as https://codecov.io.
.. _profiling:
@ -368,7 +365,7 @@ Code Profiling
==============
The Verilated model may be code-profiled using GCC or Clang's C++ profiling
mechanism. Verilator provides additional flags to help map the resulting
mechanism. Verilator provides additional flags to help map the resulting
C++ profiling results back to the original Verilog code responsible for the
profiled C++ code functions.
@ -392,8 +389,8 @@ To use profiling:
Execution Profiling
===================
For performance optimization, it is helpful to see statistics and visualize how
execution time is distributed in a verilated model.
For performance optimization, it is helpful to see statistics and visualize
how execution time is distributed in a verilated model.
With the :vlopt:`--prof-exec` option, Verilator will:
@ -403,7 +400,7 @@ With the :vlopt:`--prof-exec` option, Verilator will:
specified with :vlopt:`+verilator+prof+exec+file+\<filename\>`.
* In multithreaded models, add code to record each macro-task's start and
end time across several calls to eval. (What is a macro-task? See the
end time across several calls to eval. (What is a macro-task? See the
Verilator internals document (:file:`docs/internals.rst` in the
distribution.)
@ -414,11 +411,14 @@ saved profiling file into a visual format and produce related statistics.
Example verilator_gantt output, as viewed with GTKWave.
The measured_parallelism shows the number of CPUs being used at a given moment.
The measured_parallelism shows the number of CPUs being used at a given
moment.
The cpu_thread section shows which thread is executing on each physical CPU.
The cpu_thread section shows which thread is executing on each physical
CPU.
The thread_mtask section shows which macro-task is running on a given thread.
The thread_mtask section shows which macro-task is running on a given
thread.
For more information, see :command:`verilator_gantt`.
@ -438,15 +438,16 @@ target when invoking the generated Makefile:
.. code-block:: bash
make -C obj_dir -f Vout.mk Vout ccache-report
make -C obj_dir -f Vout.mk Vout ccache-report
This will print a report based on all executions of ccache during this
invocation of Make. The report is also written to a file, in this example
`obj_dir/Vout__cache_report.txt`.
To use the `ccache-report` target, OBJCACHE must be set to 'ccache' (this is
done by `configure` if 'ccache' is installed). If no other explicit build
targets are specified, `cchache-report` will build the `default` target.
To use the `ccache-report` target, OBJCACHE must be set to 'ccache' (this
is done by `configure` if 'ccache' is installed). If no other explicit
build targets are specified, `cchache-report` will build the `default`
target.
This feature is currently experimental and might change in subsequent
releases.
@ -459,32 +460,32 @@ Save/Restore
The intermediate state of a Verilated model may be saved so that it may
later be restored.
To enable this feature, use :vlopt:`--savable`. There are limitations in
To enable this feature, use :vlopt:`--savable`. There are limitations in
what language features are supported along with :vlopt:`--savable`; if you
attempt to use an unsupported feature, Verilator will throw an error.
To use save/restore, the user wrapper code must create a VerilatedSerialize
or VerilatedDeserialze object and then call the :code:`<<` or :code:`>>`
operators on the generated model and any other data the process needs to be
saved/restored. These functions are not thread-safe and are typically
or VerilatedDeserialze object and then call the ``<<`` or ``>>`` operators
on the generated model and any other data the process needs to be
saved/restored. These functions are not thread-safe and are typically
called only by a main thread.
For example:
.. code-block:: C++
void save_model(const char* filenamep) {
VerilatedSave os;
os.open(filenamep);
os << main_time; // user code must save the timestamp
os << *topp;
}
void restore_model(const char* filenamep) {
VerilatedRestore os;
os.open(filenamep);
os >> main_time;
os >> *topp;
}
void save_model(const char* filenamep) {
VerilatedSave os;
os.open(filenamep);
os << main_time; // user code must save the timestamp
os << *topp;
}
void restore_model(const char* filenamep) {
VerilatedRestore os;
os.open(filenamep);
os >> main_time;
os >> *topp;
}
Profile-Guided Optimization
@ -494,9 +495,9 @@ Profile-guided optimization is the technique where profiling data is
collected by running your simulation executable; then this information is
used to guide the next Verilation or compilation.
There are two forms of profile-guided optimizations. Unfortunately, for
best results, they must each be performed from the highest level code to the
lowest, which means performing them separately and in this order:
There are two forms of profile-guided optimizations. Unfortunately, for
best results, they must each be performed from the highest level code to
the lowest, which means performing them separately and in this order:
* :ref:`Thread PGO`
* :ref:`Compiler PGO`
@ -511,20 +512,20 @@ others, as they prove beneficial.
Thread Profile-Guided Optimization
----------------------------------
Verilator supports profile-guided optimization (Verilation) of multithreaded
models (Thread PGO) to improve performance.
Verilator supports profile-guided optimization (Verilation) of
multithreaded models (Thread PGO) to improve performance.
When using multithreading, Verilator computes how long macro tasks take and
tries to balance those across threads. (What is a macro-task? See the
tries to balance those across threads. (What is a macro-task? See the
Verilator internals document (:file:`docs/internals.rst` in the
distribution.) If the estimations are incorrect, the threads will not be
balanced, leading to decreased performance. Thread PGO allows collecting
distribution.) If the estimations are incorrect, the threads will not be
balanced, leading to decreased performance. Thread PGO allows collecting
profiling data to replace the estimates and better optimize these
decisions.
To use Thread PGO, Verilate the model with the :vlopt:`--prof-pgo` option. This
will code to the verilated model to save profiling data for profile-guided
optimization.
To use Thread PGO, Verilate the model with the :vlopt:`--prof-pgo` option.
This will code to the verilated model to save profiling data for
profile-guided optimization.
Run the model executable. When the executable exits, it will create a
profile.vlt file.
@ -532,20 +533,20 @@ profile.vlt file.
Rerun Verilator, optionally omitting the :vlopt:`--prof-pgo` option and
adding the :file:`profile.vlt` generated earlier to the command line.
Note there is no Verilator equivalent to GCC's --fprofile-use. Verilator's
Note there is no Verilator equivalent to GCC's --fprofile-use. Verilator's
profile data file (:file:`profile.vlt`) can be placed directly on the
verilator command line without any option prefix.
If results from multiple simulations are to be used in generating the
optimization, multiple simulation's profile.vlt may be concatenated
externally, or each file may be fed as separate command line options into
Verilator. Verilator will sum the profile results, so a long-running test
Verilator. Verilator will sum the profile results, so a long-running test
will have more weight for optimization proportionally than a
shorter-running test.
If you provide any profile feedback data to Verilator and it cannot use
it, it will issue the :option:`PROFOUTOFDATE` warning that threads were
scheduled using estimated costs. This usually indicates that the profile
If you provide any profile feedback data to Verilator and it cannot use it,
it will issue the :option:`PROFOUTOFDATE` warning that threads were
scheduled using estimated costs. This usually indicates that the profile
data was generated from a different Verilog source code than Verilator is
currently running against. Therefore, repeat the data collection phase to
create new profiling data, then rerun Verilator with the same input source
@ -558,12 +559,12 @@ Compiler Profile-Guided Optimization
------------------------------------
GCC and Clang support compiler profile-guided optimization (PGO). This
optimizes any C/C++ program, including Verilated code. Using compiler PGO
optimizes any C/C++ program, including Verilated code. Using compiler PGO
typically yields improvements of 5-15% on both single-threaded and
multithreaded models.
Please see the appropriate compiler documentation to use PGO with GCC or
Clang. The process in GCC 10 was as follows:
Clang. The process in GCC 10 was as follows:
1. Compile the Verilated model with the compiler's "-fprofile-generate"
flag:
@ -573,8 +574,8 @@ Clang. The process in GCC 10 was as follows:
verilator [whatever_flags] --make \
-CFLAGS -fprofile-generate -LDFLAGS -fprofile-generate
Or, if calling make yourself, add -fprofile-generate appropriately to your
Makefile.
Or, if calling make yourself, add -fprofile-generate appropriately to
your Makefile.
2. Run your simulation. This will create \*.gcda file(s) in the same
directory as the source files.
@ -601,8 +602,7 @@ Clang. The process in GCC 10 was as follows:
your Makefile.
Clang and GCC also support -fauto-profile, which uses sample-based
feedback-directed optimization. See the appropriate compiler
documentation.
feedback-directed optimization. See the appropriate compiler documentation.
.. _runtime debugging:
@ -612,8 +612,8 @@ Runtime Debugging
To debug a Verilated executable, Verilate with :vlopt:`--runtime-debug`.
This will instruct the compiler to insert debugger, and enable various
library assertions. These options slow down the executable, so do this
only when debugging.
library assertions. These options slow down the executable, so do this only
when debugging.
If you are using your own Makefiles, adapt appropriately to pass the
options documented under :vlopt:`--runtime-debug` to the compiler and
@ -622,18 +622,18 @@ linker.
Once you have a debugging-enabled executable, run it using the the standard
GNU debugger ``gdb`` or a similar tool, and create a backtrace; e.g.:
.. code-block:: bash
.. code-block:: bash
gdb obj_dir/Vtop
run {Vtop_command_arguments}
{Vtop prints output, perhaps a segmentation faults}
bt
gdb obj_dir/Vtop
run {Vtop_command_arguments}
{Vtop prints output, perhaps a segmentation faults}
bt
Rarely the bug may disappear with :vlopt:`--runtime-debug`; if so, try
instead using the sub-options that :vlopt:`--runtime-debug` documents, to
find the maximum subset that still shows the issue. E.g. it is likely that
find the maximum subset that still shows the issue. E.g. it is likely that
using `-CFLAGS -D_GLIBCXX_DEBUG` will not hide any bug, so may be used.
Using :vlopt:`--runtime-debug` or `-CFLAGS -DVL_DEBUG=1` will only print a
message if something goes wrong. To enable debug print messages at
runtime, additionally use the :vlopt:`+verilator+debug` runtime option.
message if something goes wrong. To enable debug print messages at runtime,
additionally use the :vlopt:`+verilator+debug` runtime option.

169
docs/guide/verilating.rst
View File

@ -8,11 +8,11 @@ Verilating
Verilator may be used in five major ways:
* With the :vlopt:`--binary` option, Verilator will translate the design
into an executable, via generating C++ and compiling it. See
into an executable, via generating C++ and compiling it. See
:ref:`Binary, C++ and SystemC Generation`.
* With the :vlopt:`--cc` or :vlopt:`--sc` options, Verilator will translate
the design into C++ or SystemC code, respectively. See :ref:`Binary, C++
the design into C++ or SystemC code, respectively. See :ref:`Binary, C++
and SystemC Generation`.
* With the :vlopt:`--lint-only` option, Verilator will lint the design to
@ -33,17 +33,17 @@ Binary, C++ and SystemC Generation
==================================
Verilator will translate a SystemVerilog design into C++ with the
:vlopt:`--cc` option, or into SystemC with the :vlopt:`--sc` option. It
:vlopt:`--cc` option, or into SystemC with the :vlopt:`--sc` option. It
will translate into C++ and compile it into an executable binary with the
:vlopt:`--binary` option.
When using these options:
#. Verilator reads the input Verilog code and determines all "top modules", that
is, modules or programs that are not used as instances under other cells.
If :vlopt:`--top-module` is used, then that determines the top module, and
all other top modules are removed; otherwise a :vlopt:`MULTITOP` warning
is given.
#. Verilator reads the input Verilog code and determines all "top modules",
that is, modules or programs that are not used as instances under other
cells. If :vlopt:`--top-module` is used, then that determines the top
module, and all other top modules are removed; otherwise a
:vlopt:`MULTITOP` warning is given.
#. Verilator writes the C++/SystemC code to output files into the
:vlopt:`--Mdir` option-specified directory, or defaults to "obj_dir".
@ -72,12 +72,12 @@ Finding and Binding Modules
Verilator provides several mechanisms to find the source code containing a
module, primitive, interface, or program ("module" in this section) and
bind them to an instantiation. These capabilities are similar to the
bind them to an instantiation. These capabilities are similar to the
"Precompiling in a single-pass" use model described in IEEE 1800-2023
33.5.1, although `config` is not yet supported.
Verilator first reads all files provided on the command line and
:vlopt:`-f` files, and parses all modules within. Each module is assigned
:vlopt:`-f` files, and parses all modules within. Each module is assigned
to the most recent library specified with :vlopt:`-work`, thus `-work liba
a.v -work libb b.v` will assign modules in `a.v` to `liba` and modules in
`b.v` to `libb`.
@ -93,9 +93,9 @@ tops result a :option:`MULTITOP` warning is issued which may be suppressed
Verilator will attempt to bind lower unresolved instances first in the same
library name as the parent's instantiation library, and if not found search
globally across all libraries in the order modules were declared. This
globally across all libraries in the order modules were declared. This
allows otherwise conflicting duplicate module names between libraries to
coexist uniquely within each library name. When IEEE `config use` is
coexist uniquely within each library name. When IEEE `config use` is
supported, more complicated selections will be able to be specified.
@ -105,13 +105,13 @@ Hierarchical Verilation
=======================
Large designs may take long (e.g., 10+ minutes) and huge memory (e.g., 100+
GB) to Verilate. In hierarchical mode, the user manually selects some
large lower-level hierarchy blocks to separate from the larger design. For
GB) to Verilate. In hierarchical mode, the user manually selects some large
lower-level hierarchy blocks to separate from the larger design. For
example, a core may be the hierarchy block separated out of a multi-core
SoC design.
Verilator is run in hierarchical mode on the whole SoC. Verilator will
make two models, one for the CPU hierarchy block and one for the SoC. The
Verilator is run in hierarchical mode on the whole SoC. Verilator will make
two models, one for the CPU hierarchy block and one for the SoC. The
Verilated code for the SoC will automatically call the CPU Verilated model.
The current hierarchical Verilation is based on :vlopt:`--lib-create`. Each
@ -135,7 +135,7 @@ The compilation is the same as when not using hierarchical mode.
.. code-block:: bash
make -C obj_dir -f Vtop_module_name.mk
make -C obj_dir -f Vtop_module_name.mk
Limitations
@ -165,7 +165,7 @@ But, the following usage is supported:
hierarchy blocks.
* Parameterized hierarchy block. Parameters of a hierarchy block can be
overridden using :code:`#(.param_name(value))` construct.
overridden using ``#(.param_name(value))`` construct.
.. _overlapping verilation and compilation:
@ -175,10 +175,10 @@ Overlapping Verilation and Compilation
Verilator needs to run 2 + *N* times in hierarchical Verilation, where *N*
is the number of hierarchy blocks. One of the two is for the top module,
which refers to the wrappers of all other hierarchy blocks. The second of the
two is the initial run that searches modules marked with
which refers to the wrappers of all other hierarchy blocks. The second of
the two is the initial run that searches modules marked with
:option:`/*verilator&32;hier_block*/` metacomment and creates a plan and
write in :file:`{prefix}_hier.mk`. This initial run internally invokes
write in :file:`{prefix}_hier.mk`. This initial run internally invokes
other *N* + 1 runs, so you don't have to care about these *N* + 1 times of
run. The additional *N* is the Verilator run for each hierarchical block.
@ -193,25 +193,25 @@ hierarchy blocks run simultaneously.
Cross Compilation
=================
Verilator supports cross-compiling Verilated code. This is generally used
to run Verilator on a Linux system and produce C++ code that is then compiled
on Windows.
Verilator supports cross-compiling Verilated code. This is generally used
to run Verilator on a Linux system and produce C++ code that is then
compiled on Windows.
Cross-compilation involves up to three different OSes. The build system is
Cross-compilation involves up to three different OSes. The build system is
where you configure and compile Verilator, the host system is where you run
Verilator, and the target system is where you compile the Verilated code
and run the simulation.
Verilator requires the build and host system types to be the
same, though the target system type may be different. To support this,
:command:`./configure` and make Verilator on the build system. Then, run
Verilator on the host system. Finally, the output of Verilator may be
Verilator requires the build and host system types to be the same, though
the target system type may be different. To support this,
:command:`./configure` and make Verilator on the build system. Then, run
Verilator on the host system. Finally, the output of Verilator may be
compiled on the different target system.
To support this, none of the files that Verilator produces will reference
any configure-generated build-system-specific files, such as
:file:`config.h` (which is renamed in Verilator to :file:`config_package.h`
to reduce confusion.) The disadvantage of this approach is that
to reduce confusion.) The disadvantage of this approach is that
:file:`include/verilatedos.h` must self-detect the requirements of the
target system, rather than using configure.
@ -243,7 +243,7 @@ however, you can expect performance to be far worse than it would be with
the proper ratio of threads and CPU cores.
The thread used for constructing a model must be the same thread that calls
:code:`eval()` into the model; this is called the "eval thread". The thread
``eval()`` into the model; this is called the "eval thread". The thread
used to perform certain global operations, such as saving and tracing, must
be done by a "main thread". In most cases, the eval thread and main thread
are the same thread (i.e. the user's top C++ testbench runs on a single
@ -257,12 +257,13 @@ time of DPI imports.
When using :vlopt:`--trace-vcd` to perform VCD tracing, the VCD trace
construction is parallelized using the same number of threads as specified
with :vlopt:`--threads`, and is executed on the same thread pool as the model.
with :vlopt:`--threads`, and is executed on the same thread pool as the
model.
The :vlopt:`--trace-threads` options can be used with :vlopt:`--trace-fst`
to offload FST tracing using multiple threads. If :vlopt:`--trace-threads` is
given without :vlopt:`--threads`, then :vlopt:`--trace-threads` will imply
:vlopt:`--threads 1 <--threads>`, i.e., the support libraries will be
to offload FST tracing using multiple threads. If :vlopt:`--trace-threads`
is given without :vlopt:`--threads`, then :vlopt:`--trace-threads` will
imply :vlopt:`--threads 1 <--threads>`, i.e., the support libraries will be
thread safe.
With :vlopt:`--trace-threads 0 <--trace-threads>`, trace dumps are produced
@ -271,8 +272,8 @@ on the main thread. This again gives the highest single-thread performance.
With :vlopt:`--trace-threads {N} <--trace-threads>`, where N is at least 1,
up to N additional threads will be created and managed by the trace files
(e.g., VerilatedFstC), to offload construction of the trace dump. The main
thread will be released to proceed with execution as soon as possible, though
some main thread blocking is still necessary while capturing the
thread will be released to proceed with execution as soon as possible,
though some main thread blocking is still necessary while capturing the
trace. FST tracing can utilize up to 2 offload threads, so there is no use
of setting :vlopt:`--trace-threads` higher than 2 at the moment.
@ -286,34 +287,34 @@ For best performance, use the :command:`numactl` program to (when the
threading count fits) select unique physical cores on the same socket. The
same applies for :vlopt:`--trace-threads` as well.
As an example, if a model was Verilated with
:vlopt:`--threads 4 <--threads>`, we consult:
As an example, if a model was Verilated with :vlopt:`--threads 4
<--threads>`, we consult:
.. code-block:: bash
egrep 'processor|physical id|core id' /proc/cpuinfo
egrep 'processor|physical id|core id' /proc/cpuinfo
To select cores 0, 1, 2, and 3 that are all located on the same socket (0)
but have different physical cores. (Also useful is
:command:`numactl --hardware`, or :command:`lscpu`, but those don't show
hyperthreading cores.) Then we execute:
but have different physical cores. (Also useful is :command:`numactl
--hardware`, or :command:`lscpu`, but those don't show hyperthreading
cores.) Then we execute:
.. code-block:: bash
numactl -m 0 -C 0,1,2,3 -- verilated_executable_name
numactl -m 0 -C 0,1,2,3 -- verilated_executable_name
This will limit memory to socket 0, and threads to cores 0, 1, 2, 3,
(presumably on socket 0), optimizing performance. Of course, this must be
(presumably on socket 0), optimizing performance. Of course, this must be
adjusted if you want another simulator to use, e.g., socket 1, or if you
Verilated with a different number of threads. To see what CPUs are
actually used, use :vlopt:`--prof-exec`.
Verilated with a different number of threads. To see what CPUs are actually
used, use :vlopt:`--prof-exec`.
Multithreaded Verilog and Library Support
-----------------------------------------
$display/$stop/$finish are delayed until the end of an eval() call
to maintain ordering between threads. This may result in additional tasks
$display/$stop/$finish are delayed until the end of an eval() call to
maintain ordering between threads. This may result in additional tasks
completing after the $stop or $finish.
If using :vlopt:`--coverage`, the coverage routines are fully thread-safe.
@ -340,7 +341,7 @@ from the main thread.
GNU Make
========
Verilator defaults to creating GNU Make makefiles for the model. Verilator
Verilator defaults to creating GNU Make makefiles for the model. Verilator
will call make automatically when the :vlopt:`--build` option is used.
If calling Verilator from a makefile, the :vlopt:`--MMD` option will create
@ -359,13 +360,13 @@ would build the code listed in :ref:`Example C++ Execution`
.. code-block:: CMake
project(cmake_example)
find_package(verilator HINTS $ENV{VERILATOR_ROOT})
add_executable(Vour sim_main.cpp)
verilate(Vour SOURCES our.v)
project(cmake_example)
find_package(verilator HINTS $ENV{VERILATOR_ROOT})
add_executable(Vour sim_main.cpp)
verilate(Vour SOURCES our.v)
:code:`find_package` will automatically find an installed copy of
Verilator, or use a local build if VERILATOR_ROOT is set.
``find_package`` will automatically find an installed copy of Verilator, or
use a local build if VERILATOR_ROOT is set.
Using CMake >= 3.12 and the Ninja generator is recommended, though other
combinations should work. To build with CMake, change to the folder
@ -373,42 +374,42 @@ containing CMakeLists.txt and run:
.. code-block:: bash
mkdir build
cd build
cmake -GNinja ..
ninja
mkdir build
cd build
cmake -GNinja ..
ninja
Or to build with your system default generator:
.. code-block:: bash
mkdir build
cd build
cmake ..
cmake --build .
mkdir build
cd build
cmake ..
cmake --build .
If you're building the example, you should have an executable to run:
.. code-block:: bash
./Vour
./Vour
The package sets the CMake variables verilator_FOUND, VERILATOR_ROOT,
and VERILATOR_BIN to the appropriate values and creates a verilate()
function. verilate() will automatically create custom commands to run
Verilator and add the generated C++ sources to the target specified.
The package sets the CMake variables verilator_FOUND, VERILATOR_ROOT, and
VERILATOR_BIN to the appropriate values and creates a verilate() function.
verilate() will automatically create custom commands to run Verilator and
add the generated C++ sources to the target specified.
Verilate in CMake
-----------------
.. code-block:: CMake
verilate(target SOURCES source ... [TOP_MODULE top] [PREFIX name]
[COVERAGE] [SYSTEMC]
[TRACE_FST] [TRACE_SAIF] [TRACE_VCD] [TRACE_THREADS num]
[INCLUDE_DIRS dir ...] [OPT_SLOW ...] [OPT_FAST ...]
[OPT_GLOBAL ..] [DIRECTORY dir] [THREADS num]
[VERILATOR_ARGS ...])
verilate(target SOURCES source ... [TOP_MODULE top] [PREFIX name]
[COVERAGE] [SYSTEMC]
[TRACE_FST] [TRACE_SAIF] [TRACE_VCD] [TRACE_THREADS num]
[INCLUDE_DIRS dir ...] [OPT_SLOW ...] [OPT_FAST ...]
[OPT_GLOBAL ..] [DIRECTORY dir] [THREADS num]
[VERILATOR_ARGS ...])
Lowercase and ... should be replaced with arguments; the uppercase parts
delimit the arguments and can be passed in any order or left out entirely
@ -417,8 +418,8 @@ if optional.
verilate(target ...) can be called multiple times to add other Verilog
modules to an executable or library target.
When generating Verilated SystemC sources, you should list the
SystemC include directories and link to the SystemC libraries.
When generating Verilated SystemC sources, you should list the SystemC
include directories and link to the SystemC libraries.
.. describe:: target
@ -519,11 +520,11 @@ SystemC Link in CMake
---------------------
Verilator's CMake support provides a convenience function to automatically
find and link to the SystemC library. It can be used as:
find and link to the SystemC library. It can be used as:
.. code-block:: CMake
verilator_link_systemc(target)
verilator_link_systemc(target)
where target is the name of your target.
@ -557,11 +558,11 @@ will print a report to stdout summarizing the build. For example:
.. code-block::
- V e r i l a t i o n R e p o r t: Verilator ....
- Verilator: Built from 354 MB sources in 247 modules,
into 74 MB in 89 C++ files needing 0.192 MB
- Verilator: Walltime 26.580 s (elab=2.096, cvt=18.268,
bld=2.100); cpu 26.548 s on 1 threads; alloced 2894.672 MB
- V e r i l a t i o n R e p o r t: Verilator ....
- Verilator: Built from 354 MB sources in 247 modules,
into 74 MB in 89 C++ files needing 0.192 MB
- Verilator: Walltime 26.580 s (elab=2.096, cvt=18.268,
bld=2.100); cpu 26.548 s on 1 threads; alloced 2894.672 MB
The information in this report is:

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@ -32,9 +32,9 @@ The XML document consists of 4 sections within the top level
``<files>``... ``</files>``
This section contains a list of all design files read, including the
built-in constructs and the command line as their own entries. Each
``<file>`` has an attribute ``id`` which is a short ASCII string
unique to that file. Other elements' ``loc`` attributes use this id
to refer to a particular file.
``<file>`` has an attribute ``id`` which is a short ASCII string unique
to that file. Other elements' ``loc`` attributes use this id to refer to
a particular file.
``<module_files>``... ``</module_files>``
All files containing Verilog module definitions are listed in this
@ -43,28 +43,27 @@ The XML document consists of 4 sections within the top level
``<cells>``... ``</cells>``
The cells section of the XML document contains the design instance
hierarchy. Each instance is represented with the ``<cell>`` element
with the following attributes:
hierarchy. Each instance is represented with the ``<cell>`` element with
the following attributes:
- ``loc``: The file id, first line number, last line number, first
column number and last column number of the identifier where the
module was instanced, separated by commas.
- ``loc``: The file id, first line number, last line number, first
column number and last column number of the identifier where the
module was instanced, separated by commas.
- ``name``: The instance name.
- ``name``: The instance name.
- ``submodname``: The module name uniquified with particular
parameter values (if any).
- ``submodname``: The module name uniquified with particular parameter
values (if any).
- ``hier``: The full hierarchy path.
- ``hier``: The full hierarchy path.
``<netlist>``... ``</netlist>``
The netlist section contains a number of
``<module>``... ``</module>`` elements, each describing the
contents of that module, and a single ``<typetable>``...
``</typetable>`` element which lists all used types used within the
modules. Each type has a numeric ``id`` attribute that is referred to
by elements in the ``<module>`` elements using the ``dtype_id``
attribute.
The netlist section contains a number of ``<module>``... ``</module>``
elements, each describing the contents of that module, and a single
``<typetable>``... ``</typetable>`` element which lists all used types
used within the modules. Each type has a numeric ``id`` attribute that
is referred to by elements in the ``<module>`` elements using the
``dtype_id`` attribute.
Distribution