Add UNSUPPORTED on $sampled in sensitivity list (#7093)

src/V3AssertPre.cpp

@@ -382,6 +382,14 @@ private:
             nodep->v3error("Event controls cannot be used in "
                            "synchronous drives (IEEE 1800-2023 14.16)");
         }
+
+        const AstSampled* sampledp;
+        if (nodep->exists([&sampledp](const AstSampled* const sp) {
+                sampledp = sp;
+                return true;
+            })) {
+            sampledp->v3warn(E_UNSUPPORTED, "Unsupported: $sampled inside sensitivity list");
+        }
     }
     void visit(AstNodeVarRef* nodep) override {
         UINFO(8, " -varref:  " << nodep);

test_regress/t/t_sampled_sensitivity.out

@@ -0,0 +1,6 @@
+%Error-UNSUPPORTED: t/t_sampled_sensitivity.v:14:20: Unsupported: $sampled inside sensitivity list
+                                                   : ... note: In instance 't'
+   14 |   always @(posedge $sampled(clk)) begin
+      |                    ^~~~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to

test_regress/t/t_sampled_sensitivity.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2024 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_sampled_sensitivity.v

@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+module t (  /*AUTOARG*/
+    // Inputs
+    clk
+);
+
+  input clk;
+
+  always @(posedge $sampled(clk)) begin
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule