Tests: Cover deassign

This commit is contained in:
Wilson Snyder 2026-02-03 20:22:10 -05:00
parent 4e9792c34c
commit 1adedd0bfa
3 changed files with 22 additions and 1 deletions

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@ -146,7 +146,6 @@ for s in [
'Unsupported: Stream operation on a variable of a type',
'Unsupported: Unclocked assertion',
'Unsupported: Using --protect-ids with public function',
'Unsupported: Verilog 1995 deassign',
'Unsupported: Verilog 1995 gate primitive:',
'Unsupported: [] dimensions',
'Unsupported: \'default :/\' constraint',

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@ -0,0 +1,5 @@
%Error-UNSUPPORTED: t/t_lint_unsup_deassign.v:19:8: Unsupported: Verilog 1995 deassign
19 | deassign q;
| ^~~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

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@ -0,0 +1,17 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.top_filename = "t/t_lint_unsup_deassign.v"
test.lint(fails=True, expect_filename=test.golden_filename)
test.passes()