Tests: Cover deassign
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@ -146,7 +146,6 @@ for s in [
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'Unsupported: Stream operation on a variable of a type',
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'Unsupported: Unclocked assertion',
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'Unsupported: Using --protect-ids with public function',
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'Unsupported: Verilog 1995 deassign',
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'Unsupported: Verilog 1995 gate primitive:',
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'Unsupported: [] dimensions',
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'Unsupported: \'default :/\' constraint',
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@ -0,0 +1,5 @@
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%Error-UNSUPPORTED: t/t_lint_unsup_deassign.v:19:8: Unsupported: Verilog 1995 deassign
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19 | deassign q;
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| ^~~~~~~~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error: Exiting due to
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@ -0,0 +1,17 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2024 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('linter')
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test.top_filename = "t/t_lint_unsup_deassign.v"
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test.lint(fails=True, expect_filename=test.golden_filename)
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test.passes()
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