Fix false ASSIGNIN on interface input ports driven from outside (#7322)
This commit is contained in:
Yilou Wang
GitHub
parent
fbc3b3618d
commit
e0963bd587
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@ -241,6 +241,7 @@ class WidthVisitor final : public VNVisitor {
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std::map<const AstNode*, const AstClass*>
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m_containingClassp; // Containing class cache for containingClass() function
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std::unordered_set<AstVar*> m_aliasedVars; // Variables referenced in alias
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std::unordered_set<const AstVar*> m_curModVars; // Variables declared in current module
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static constexpr int ENUM_LOOKUP_BITS = 16; // Maximum # bits to make enum lookup table
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@ -2835,7 +2836,18 @@ class WidthVisitor final : public VNVisitor {
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&& (!m_ftaskp || !m_ftaskp->isConstructor())
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&& !VN_IS(m_procedurep, InitialAutomatic) && !VN_IS(m_procedurep, InitialStatic)
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&& !VN_IS(nodep->abovep(), AssignForce) && !VN_IS(nodep->abovep(), Release)) {
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nodep->v3warn(ASSIGNIN, "Assigning to input/const variable: " << nodep->prettyNameQ());
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// Skip ASSIGNIN for continuous assignments to net-type input ports
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// via hierarchical reference. Net ports allow multiple continuous
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// drivers (IEEE 1800-2023 23.3.3.3). Input ports default to net
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// when port kind is omitted (23.2.2.3, PORT type).
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const bool hierRef = !m_curModVars.count(nodep->varp());
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const bool netPort
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= nodep->varp()->isNet() || nodep->varp()->varType() == VVarType::PORT;
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const bool contAssign = VN_IS(nodep->abovep(), AssignW);
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if (!(hierRef && netPort && contAssign)) {
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nodep->v3warn(ASSIGNIN,
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"Assigning to input/const variable: " << nodep->prettyNameQ());
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}
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} else if (nodep->access().isWriteOrRW() && nodep->varp()->isConst() && !m_paramsOnly
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&& (!m_ftaskp || !m_ftaskp->isConstructor())
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&& !VN_IS(m_procedurep, InitialAutomatic)
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@ -7374,6 +7386,9 @@ class WidthVisitor final : public VNVisitor {
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} else {
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VL_RESTORER(m_modep);
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m_modep = nodep;
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// Collect local variables for ASSIGNIN hierarchical reference check
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m_curModVars.clear();
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nodep->foreach([this](const AstVar* varp) { m_curModVars.insert(varp); });
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userIterateChildren(nodep, nullptr);
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}
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}
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@ -1437,16 +1437,16 @@ port<nodep>: // ==IEEE: port
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{ $$ = $3; VARDTYPE($2); VARIOANSI();
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if (AstVar* vp = VARDONEP($$, $4, $5)) { addNextNull($$, vp); vp->valuep($7); } }
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| portDirNetE yVAR data_type portSig variable_dimensionListE sigAttrListE
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{ $$ = $4; VARDTYPE($3); VARIOANSI();
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{ $$ = $4; VARDECL(VAR); VARDTYPE($3); VARIOANSI();
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addNextNull($$, VARDONEP($$, $5, $6)); }
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| portDirNetE yVAR data_type portSig variable_dimensionListE sigAttrListE '=' constExpr
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{ $$ = $4; VARDTYPE($3); VARIOANSI();
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{ $$ = $4; VARDECL(VAR); VARDTYPE($3); VARIOANSI();
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if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } }
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| portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE
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{ $$ = $4; VARDTYPE($3); VARIOANSI();
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{ $$ = $4; VARDECL(VAR); VARDTYPE($3); VARIOANSI();
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addNextNull($$, VARDONEP($$, $5, $6)); }
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| portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE '=' constExpr
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{ $$ = $4; VARDTYPE($3); VARIOANSI();
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{ $$ = $4; VARDECL(VAR); VARDTYPE($3); VARIOANSI();
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if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } }
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| portDirNetE signing portSig variable_dimensionListE sigAttrListE
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{ $$ = $3;
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@ -1955,10 +1955,10 @@ port_declaration<nodep>: // ==IEEE: port_declaration
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/*mid*/ { VARDTYPE($3); }
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/*cont*/ list_of_variable_decl_assignments { $$ = $5; }
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| port_directionReset port_declNetE yVAR data_type
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/*mid*/ { VARDTYPE($4); }
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/*mid*/ { VARDECL(VAR); VARDTYPE($4); }
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/*cont*/ list_of_variable_decl_assignments { $$ = $6; }
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| port_directionReset port_declNetE yVAR implicit_typeE
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/*mid*/ { VARDTYPE($4); }
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/*mid*/ { VARDECL(VAR); VARDTYPE($4); }
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/*cont*/ list_of_variable_decl_assignments { $$ = $6; }
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| port_directionReset port_declNetE signingE rangeList
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/*mid*/ { AstNodeDType* const dtp = GRAMMARP->addRange(
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(timing_loop=True, verilator_flags2=['--timing'])
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test.execute()
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test.passes()
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@ -0,0 +1,68 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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// Driving input ports from the instantiating scope via continuous assign
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// is legal when port kind defaults to net (IEEE 1800-2023 23.2.2.3).
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// All three forms below default to net for input ports.
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// Scenario 1: bare input (defaults to net)
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interface bare_if (input clk);
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logic data;
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endinterface
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// Scenario 2: input with explicit data type (still net for input)
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interface logic_if (input logic clk);
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logic data;
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endinterface
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// Scenario 3: input with explicit net kind
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interface wire_if (input wire clk);
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logic data;
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endinterface
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module consumer (bare_if cif);
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logic sampled;
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always @(posedge cif.clk) sampled <= cif.data;
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endmodule
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module t;
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logic clk = 0;
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always #5 clk = ~clk;
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integer cyc = 0;
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bare_if bif(.clk());
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assign bif.clk = clk;
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assign bif.data = 1'b1;
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logic_if lif(.clk());
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assign lif.clk = clk;
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assign lif.data = 1'b1;
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wire_if wif(.clk());
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assign wif.clk = clk;
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assign wif.data = 1'b1;
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consumer cons(.cif(bif));
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 10) begin
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`checkh(bif.clk, clk);
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`checkh(bif.data, 1'b1);
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`checkh(lif.clk, clk);
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`checkh(lif.data, 1'b1);
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`checkh(wif.clk, clk);
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`checkh(wif.data, 1'b1);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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@ -0,0 +1,10 @@
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%Error-ASSIGNIN: t/t_interface_input_port_assign_bad.v:16:10: Assigning to input/const variable: 'clk'
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: ... note: In instance 't'
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16 | assign clk = 1'b0;
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| ^~~
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... For error description see https://verilator.org/warn/ASSIGNIN?v=latest
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%Error-ASSIGNIN: t/t_interface_input_port_assign_bad.v:23:14: Assigning to input/const variable: 'clk'
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: ... note: In instance 't'
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23 | assign vif.clk = sig;
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| ^~~
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%Error: Exiting due to
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@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('linter')
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test.lint(fails=test.vlt_all, expect_filename=test.golden_filename)
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test.passes()
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@ -0,0 +1,28 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// Case 1: Assigning to explicit var input port from OUTSIDE (illegal).
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// Only 'input var' ports are variable kind (IEEE 1800-2023 23.2.2.3).
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// Variable input ports cannot be assigned (IEEE 1800-2023 23.3.3.2).
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interface var_if (input var logic clk);
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endinterface
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// Case 2: Assigning to net-type input port from INSIDE (illegal).
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// Internal assign creates a second driver within the port's own scope.
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interface internal_if (input wire clk);
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assign clk = 1'b0; // ASSIGNIN: internal assign to net input
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endinterface
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module t;
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logic sig;
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internal_if iif(.clk(sig));
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var_if vif(.clk());
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assign vif.clk = sig; // ASSIGNIN: external assign to var input
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -0,0 +1,19 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.top_filename = "t/t_interface_input_port_assign.v"
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test.compile(timing_loop=True, verilator_flags2=['--timing'], v_flags2=['-fno-inline'])
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test.execute()
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test.passes()
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@ -10,11 +10,11 @@
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]},
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{"type":"MODULE","name":"mh6","addr":"(K)","loc":"d,26:8,26:11","origName":"mh6","verilogName":"mh6","level":1,"timeunit":"1ps","inlinesp": [],
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"stmtsp": [
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{"type":"VAR","name":"x_input_var_logic","addr":"(L)","loc":"d,26:23,26:40","dtypep":"(J)","origName":"x_input_var_logic","verilogName":"x_input_var_logic","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}
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{"type":"VAR","name":"x_input_var_logic","addr":"(L)","loc":"d,26:23,26:40","dtypep":"(J)","origName":"x_input_var_logic","verilogName":"x_input_var_logic","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}
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]},
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{"type":"MODULE","name":"mh7","addr":"(M)","loc":"d,28:8,28:11","origName":"mh7","verilogName":"mh7","level":1,"timeunit":"1ps","inlinesp": [],
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"stmtsp": [
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{"type":"VAR","name":"x_input_var_integer","addr":"(N)","loc":"d,28:31,28:50","dtypep":"(G)","origName":"x_input_var_integer","verilogName":"x_input_var_integer","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"integer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}
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{"type":"VAR","name":"x_input_var_integer","addr":"(N)","loc":"d,28:31,28:50","dtypep":"(G)","origName":"x_input_var_integer","verilogName":"x_input_var_integer","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"integer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}
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]},
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{"type":"MODULE","name":"mh8","addr":"(O)","loc":"d,30:8,30:11","origName":"mh8","verilogName":"mh8","level":1,"timeunit":"1ps","inlinesp": [],
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"stmtsp": [
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@ -22,7 +22,7 @@
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]},
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{"type":"MODULE","name":"mh9","addr":"(Q)","loc":"d,32:8,32:11","origName":"mh9","verilogName":"mh9","level":1,"timeunit":"1ps","inlinesp": [],
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"stmtsp": [
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{"type":"VAR","name":"x_output_var_logic","addr":"(R)","loc":"d,32:24,32:42","dtypep":"(J)","origName":"x_output_var_logic","verilogName":"x_output_var_logic","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}
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{"type":"VAR","name":"x_output_var_logic","addr":"(R)","loc":"d,32:24,32:42","dtypep":"(J)","origName":"x_output_var_logic","verilogName":"x_output_var_logic","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}
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]},
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{"type":"MODULE","name":"mh10","addr":"(S)","loc":"d,34:8,34:12","origName":"mh10","verilogName":"mh10","level":1,"timeunit":"1ps","inlinesp": [],
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"stmtsp": [
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@ -42,12 +42,12 @@
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]},
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{"type":"MODULE","name":"mh17","addr":"(DB)","loc":"d,50:8,50:12","origName":"mh17","verilogName":"mh17","level":1,"timeunit":"1ps","inlinesp": [],
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"stmtsp": [
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{"type":"VAR","name":"x_input_var_integer","addr":"(EB)","loc":"d,50:31,50:50","dtypep":"(G)","origName":"x_input_var_integer","verilogName":"x_input_var_integer","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"integer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
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{"type":"VAR","name":"x_input_var_integer","addr":"(EB)","loc":"d,50:31,50:50","dtypep":"(G)","origName":"x_input_var_integer","verilogName":"x_input_var_integer","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"integer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
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{"type":"VAR","name":"y_input_wire_logic","addr":"(FB)","loc":"d,50:57,50:75","dtypep":"(J)","origName":"y_input_wire_logic","verilogName":"y_input_wire_logic","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}
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]},
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{"type":"MODULE","name":"mh18","addr":"(GB)","loc":"d,52:8,52:12","origName":"mh18","verilogName":"mh18","level":1,"timeunit":"1ps","inlinesp": [],
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"stmtsp": [
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{"type":"VAR","name":"x_output_var_logic","addr":"(HB)","loc":"d,52:24,52:42","dtypep":"(J)","origName":"x_output_var_logic","verilogName":"x_output_var_logic","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
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{"type":"VAR","name":"x_output_var_logic","addr":"(HB)","loc":"d,52:24,52:42","dtypep":"(J)","origName":"x_output_var_logic","verilogName":"x_output_var_logic","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
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{"type":"VAR","name":"y_input_wire_logic","addr":"(IB)","loc":"d,52:50,52:68","dtypep":"(J)","origName":"y_input_wire_logic","verilogName":"y_input_wire_logic","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}
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]},
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{"type":"MODULE","name":"mh19","addr":"(JB)","loc":"d,54:8,54:12","origName":"mh19","verilogName":"mh19","level":1,"timeunit":"1ps","inlinesp": [],
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