parent
913cf933e9
commit
e6be548f72
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@ -281,5 +281,6 @@ dependabot[bot]
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february cozzocrea
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sumpster
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em2machine
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emmettifelts
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Àlex Torregrosa
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Ícaro Lima
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@ -4868,6 +4868,10 @@ class WidthVisitor final : public VNVisitor {
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nodep->v3warn(E_UNSUPPORTED, "Unsupported/Illegal: Assignment pattern"
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" member not underneath a supported construct: "
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<< nodep->backp()->prettyTypeName());
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if (nodep->backp() && (VN_IS(nodep->backp(), Eq) || VN_IS(nodep->backp(), Neq))) return;
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nodep->replaceWith(new AstConst{nodep->fileline(), AstConst::BitFalse{}});
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VL_DO_DANGLING(pushDeletep(nodep), nodep);
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return;
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}
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{
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@ -0,0 +1,6 @@
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%Error-UNSUPPORTED: t/t_pattern_unsup_xor.v:13:25: Unsupported/Illegal: Assignment pattern member not underneath a supported construct: XOR
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: ... note: In instance 't'
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13 | status_t status_reg = '{bit_field: 1'b0} ^ 1'b0;
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| ^~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error: Exiting due to
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@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('linter')
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test.lint(fails=True, expect_filename=test.golden_filename)
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test.passes()
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@ -0,0 +1,14 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Test for issue where assignment pattern with XOR caused segfault
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module t;
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typedef struct {
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logic bit_field;
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} status_t;
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status_t status_reg = '{bit_field: 1'b0} ^ 1'b0;
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endmodule
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