Fix segfault after assignment pattern XOR error (#6928) (#6931)

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emmettifelts 2026-01-17 23:34:36 +08:00 committed by GitHub
parent 913cf933e9
commit e6be548f72
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5 changed files with 41 additions and 0 deletions

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@ -281,5 +281,6 @@ dependabot[bot]
february cozzocrea
sumpster
em2machine
emmettifelts
Àlex Torregrosa
Ícaro Lima

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@ -4868,6 +4868,10 @@ class WidthVisitor final : public VNVisitor {
nodep->v3warn(E_UNSUPPORTED, "Unsupported/Illegal: Assignment pattern"
" member not underneath a supported construct: "
<< nodep->backp()->prettyTypeName());
if (nodep->backp() && (VN_IS(nodep->backp(), Eq) || VN_IS(nodep->backp(), Neq))) return;
nodep->replaceWith(new AstConst{nodep->fileline(), AstConst::BitFalse{}});
VL_DO_DANGLING(pushDeletep(nodep), nodep);
return;
}
{

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@ -0,0 +1,6 @@
%Error-UNSUPPORTED: t/t_pattern_unsup_xor.v:13:25: Unsupported/Illegal: Assignment pattern member not underneath a supported construct: XOR
: ... note: In instance 't'
13 | status_t status_reg = '{bit_field: 1'b0} ^ 1'b0;
| ^~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

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@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.lint(fails=True, expect_filename=test.golden_filename)
test.passes()

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@ -0,0 +1,14 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// Test for issue where assignment pattern with XOR caused segfault
module t;
typedef struct {
logic bit_field;
} status_t;
status_t status_reg = '{bit_field: 1'b0} ^ 1'b0;
endmodule