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Fix WIDTHEXTEND suppression on add/sub with single-bit signal.

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Wilson Snyder 2026-01-09 00:25:12 -05:00
parent b0fdea5535
commit 3b1a7af74d
3 changed files with 11 additions and 0 deletions
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@ -20,6 +20,7 @@ Verilator 5.045 devel
* Fix MULTIDRIVEN with task and default driver (#4045) (#6858). [em2machine]
* Fix use-after-free error (#6846). [Matthew Ballance]
* Fix dynamic array elements passed to ref argument (#6877). [Ryszard Rozak, Antmicro Ltd.]
* Fix WIDTHEXTEND suppression on add/sub with single-bit signal. [Dan Katz]
Verilator 5.044 2026-01-01

5
src/V3Width.cpp
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@ -7694,6 +7694,11 @@ class WidthVisitor final : public VNVisitor {
// Warn if user wants extra bit from carry
if (subDTypep->widthMin() == (nodep->lhsp()->widthMin() + 1)) lhsWarn = false;
if (subDTypep->widthMin() == (nodep->rhsp()->widthMin() + 1)) rhsWarn = false;
if (VN_IS(nodep, Add) && nodep->lhsp()->width() == 1
&& nodep->rhsp()->width() != 1)
lhsWarn = false; // do_increment + ...
if (nodep->rhsp()->width() == 1 && nodep->lhsp()->width() != 1)
rhsWarn = false; // ... + do_increment
} else if (VN_IS(nodep, Mul) || VN_IS(nodep, MulS)) {
if (subDTypep->widthMin() >= (nodep->lhsp()->widthMin())) lhsWarn = false;
if (subDTypep->widthMin() >= (nodep->rhsp()->widthMin())) rhsWarn = false;

5
test_regress/t/t_lint_width.v
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@ -16,6 +16,11 @@ module t ();
wire [4:0] neg5 = - five;
wire [5:0] neg6 = - five;
wire inc = 1'b1;
wire [4:0] sumd = inc + five;
wire [4:0] sume = five + inc;
wire [4:0] nege = five - inc;
// Relatively harmless < or <= compared with something less wide
localparam [1:0] THREE = 3;
int a;