Fix parameterized virtual interface references that have no model references (#4286).
Fixes #4286.
This commit is contained in:
parent
41b131389e
commit
1b9f38f78f
1
Changes
1
Changes
|
|
@ -26,6 +26,7 @@ Verilator 5.045 devel
|
|||
* Support `extern module` as a forward-declaration that is ignored.
|
||||
* Remove deprecated `--xml-only`.
|
||||
* Remove deprecated `--make cmake`.
|
||||
* Fix parameterized virtual interface references that have no model references (#4286).
|
||||
* Fix variable reference lookup for module-level variables (#6741) (#6882). [Yilou Wang]
|
||||
* Fix MULTIDRIVEN with task and default driver (#4045) (#6858). [em2machine]
|
||||
* Fix false CASEOVERLAP case item expression lint (#6825) (#6886). [Luca Colagrande]
|
||||
|
|
|
|||
|
|
@ -1076,8 +1076,8 @@ class LinkDotFindVisitor final : public VNVisitor {
|
|||
void visit(AstTypeTable*) override {} // FindVisitor::
|
||||
void visit(AstConstPool*) override {} // FindVisitor::
|
||||
void visit(AstIfaceRefDType* nodep) override { // FindVisitor::
|
||||
if (m_statep->forPrimary() && nodep->isVirtual() && nodep->ifacep()
|
||||
&& !nodep->ifacep()->user3()) {
|
||||
if ((m_statep->forPrimary() || m_statep->forParamed()) && nodep->isVirtual()
|
||||
&& nodep->ifacep() && !nodep->ifacep()->user3()) {
|
||||
m_virtIfaces.push_back(nodep->ifacep());
|
||||
nodep->ifacep()->user3(true);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,18 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile()
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2026 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
interface mem_if #(
|
||||
int unsigned ADDR_SIZE = 16
|
||||
);
|
||||
endinterface
|
||||
|
||||
module t;
|
||||
class Cls #(
|
||||
type T = int
|
||||
);
|
||||
endclass
|
||||
|
||||
// Note the referred-to virtual class is only used here, not instantiated
|
||||
typedef Cls#(virtual mem_if #(8)) cls_mem_if_t;
|
||||
typedef Cls#(virtual mem_if #()) cls_def_if_t;
|
||||
|
||||
initial begin
|
||||
cls_mem_if_t c;
|
||||
cls_def_if_t d;
|
||||
c = new;
|
||||
d = new;
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue