Allow constant expressions without parentheses in PATHPULSE$ declaration (#7199)
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@ -3038,13 +3038,9 @@ delay_value<nodeExprp>: // ==IEEE:delay_value
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| y1STEP { $$ = new AstConst{$<fl>1, AstConst::OneStep{}}; }
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;
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delayExpr<nodeExprp>:
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expr { $$ = $1; }
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;
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minTypMax<nodeExprp>: // IEEE: mintypmax_expression and constant_mintypmax_expression
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delayExpr { $$ = $1; }
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| delayExpr ':' delayExpr ':' delayExpr { $$ = $3; MINTYPMAXDLYUNSUP($3); DEL($1); DEL($5); }
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expr { $$ = $1; }
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| expr ':' expr ':' expr { $$ = $3; MINTYPMAXDLYUNSUP($3); DEL($1); DEL($5); }
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;
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minTypMaxE<nodeExprp>:
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@ -5935,10 +5931,13 @@ specparam_assignment<varp>: // ==IEEE: specparam_assignment
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idNotPathpulse sigAttrListE '=' minTypMax
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{ $$ = VARDONEA($<fl>1, *$1, nullptr, $2);
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if ($4) $$->valuep($4); }
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// // IEEE: pulse_control_specparam
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| idPathpulse sigAttrListE '=' '(' minTypMax ')'
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// // IEEE: pulse_control_specparam
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// // LRM grammar requires '(' as the first token after assignment,
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// // but IEEE provides an example in 30.7.1 where it is omitted.
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// // Other simulators also support it.
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| idPathpulse sigAttrListE '=' minTypMax
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{ $$ = VARDONEA($<fl>1, *$1, nullptr, $2);
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if ($5) $$->valuep($5); }
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if ($4) $$->valuep($4); }
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| idPathpulse sigAttrListE '=' '(' minTypMax ',' minTypMax ')'
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{ $$ = VARDONEA($<fl>1, *$1, nullptr, $2);
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if ($5) $$->valuep($5);
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@ -1,9 +1,10 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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specify
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specparam tdevice_PU = 3e8;
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@ -13,6 +14,10 @@ module t;
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specparam PATHPULSE$a$b = (3.0:3.1:3.2, 4.0:4.1:4.2);
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specparam PATHPULSE$a$c = (3.0:3.1:3.2);
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specparam randomize = 1; // Special parser corner-case
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// Not allowed by the grammar in LRM section 30.7.1,
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// but used in an example at the end in the same section
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specparam PATHPULSE$ = 0;
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endspecify
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// Support in other simulators is limited for module specparams
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