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Verilog format

This commit is contained in:
Veripool API Bot 2026-02-24 21:03:32 -05:00 committed by Wilson Snyder
parent 10eafb9b3f
commit c28200c53a
4 changed files with 27 additions and 27 deletions
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18
test_regress/t/t_concat_large.v
View File

@ -6,15 +6,15 @@
module t;
reg [32767:0] a;
reg [32767:0] a;
initial begin
a = {32768{1'b1}};
if (a[32000] != 1'b1) $stop;
a = '0;
if (a[32000] != 1'b0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
a = {32768{1'b1}};
if (a[32000] != 1'b1) $stop;
a = '0;
if (a[32000] != 1'b0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

12
test_regress/t/t_concat_large_bad.out
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@ -1,11 +1,11 @@
%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:10:23: Replication of more that --replication-limit 8192 is suspect: 32768
%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:10:22: Replication of more that --replication-limit 8192 is suspect: 32768
: ... note: In instance 't'
10 | wire [32767:0] b = '0;
| ^~
10 | wire [32767:0] b = '0;
| ^~
... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest
... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.
%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:9:29: Replication of more that --replication-limit 8192 is suspect: 32768
%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:9:28: Replication of more that --replication-limit 8192 is suspect: 32768
: ... note: In instance 't'
9 | wire [32767:0] a = {32768{1'b1}};
| ^
9 | wire [32767:0] a = {32768{1'b1}};
| ^
%Error: Exiting due to

10
test_regress/t/t_concat_large_bad.v
View File

@ -6,11 +6,11 @@
module t;
wire [32767:0] a = {32768{1'b1}};
wire [32767:0] b = '0;
wire [32767:0] a = {32768{1'b1}};
wire [32767:0] b = '0;
initial begin
$stop;
end
initial begin
$stop;
end
endmodule

14
test_regress/t/t_reloop_inlined.v
View File

@ -10,12 +10,12 @@ module t;
always #5 clk1 = ~clk1;
always #10 clk2 = ~clk2;
int iarray [63:0];
int oarray1 [63:0];
int oarray2 [63:0];
int iarray[63:0];
int oarray1[63:0];
int oarray2[63:0];
initial begin
for (int i = 0; i < 64 ; i = i + 1) begin
for (int i = 0; i < 64; i = i + 1) begin
iarray[i] = i;
end
@ -30,13 +30,13 @@ module t;
end
always @(posedge clk1) begin
for (int i = 0; i < 64 ; i = i + 1) begin
for (int i = 0; i < 64; i = i + 1) begin
oarray1[i] = iarray[i];
end
end
always @(posedge clk2) begin
for (int i = 0; i < 64 ; i = i + 1) begin
oarray2[i] =iarray[i];
for (int i = 0; i < 64; i = i + 1) begin
oarray2[i] = iarray[i];
end
end