Tests: Rename tests to proper categories

test_regress/t/t_benchmark_mux4k_onecpu.py

@@ -10,7 +10,7 @@
 import vltest_bootstrap
 
 test.scenarios('simulator')
-test.top_filename = "t/t_bench_mux4k.v"
+test.top_filename = "t/t_benchmark_mux4k.v"
 
 test.compile(v_flags2=["--stats", test.wno_unopthreads_for_few_cores])
 

test_regress/t/t_display_format_wide_decimal.py

@@ -11,7 +11,7 @@ import vltest_bootstrap
 
 test.scenarios('simulator')
 
-test.compile(verilator_flags2=["-Wall"])
+test.compile(verilator_flags2=["-Wall -Wno-DECLFILENAME"])
 
 test.execute(expect_filename=test.golden_filename)
 

test_regress/t/t_display_format_wide_decimal.v

@@ -6,7 +6,7 @@
 // Version 2.0.
 // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-module t_format_wide_decimal(/*AUTOARG*/
+module t(/*AUTOARG*/
    // Inputs
    clk
    );

test_regress/t/t_do_while_continue_bad.out

@@ -1,4 +1,4 @@
-%Warning-INFINITELOOP: t/t_continue_do_while_bad.v:14:7: Infinite loop (condition always true)
+%Warning-INFINITELOOP: t/t_do_while_continue_bad.v:14:7: Infinite loop (condition always true)
    14 |       do begin
       |       ^~
                        ... For warning description see https://verilator.org/warn/INFINITELOOP?v=latest

test_regress/t/t_dump_dfg.py

@@ -12,7 +12,7 @@ import vltest_bootstrap
 test.scenarios('vlt')
 
 # For code coverage of graph dumping, so does not matter much what the input is
-test.top_filename = "t/t_bench_mux4k.v"
+test.top_filename = "t/t_benchmark_mux4k.v"
 
 test.compile(verilator_flags2=["--dump-dfg", "--dumpi-dfg 9"])
 

test_regress/t/t_gen_duplicated_blocks_bad.out

@@ -1,16 +1,16 @@
-%Error: t/t_duplicated_gen_blocks_bad.v:11:12: Duplicate declaration of generate block: 'block'
+%Error: t/t_gen_duplicated_blocks_bad.v:11:12: Duplicate declaration of generate block: 'block'
                                              : ... note: In instance 't'
    11 |    begin : block
       |            ^~~~~
-        t/t_duplicated_gen_blocks_bad.v:9:12: ... Location of original declaration
+        t/t_gen_duplicated_blocks_bad.v:9:12: ... Location of original declaration
     9 |    begin : block
       |            ^~~~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: t/t_duplicated_gen_blocks_bad.v:15:23: Duplicate declaration of generate block: 'block1'
+%Error: t/t_gen_duplicated_blocks_bad.v:15:23: Duplicate declaration of generate block: 'block1'
                                              : ... note: In instance 't'
    15 |    if (X > 1) begin : block1
       |                       ^~~~~~
-        t/t_duplicated_gen_blocks_bad.v:13:23: ... Location of original declaration
+        t/t_gen_duplicated_blocks_bad.v:13:23: ... Location of original declaration
    13 |    if (X > 0) begin : block1
       |                       ^~~~~~
 %Error: Exiting due to

test_regress/t/t_mem_big_bad.out

@@ -1,10 +1,10 @@
-%Error: t/t_bigmem_bad.v:14:19: Width of bit extract must be positive (IEEE 1800-2023 11.5.1)
-                              : ... note: In instance 't_bigmem'
+%Error: t/t_mem_big_bad.v:14:19: Width of bit extract must be positive (IEEE 1800-2023 11.5.1)
+                               : ... note: In instance 't_bigmem'
    14 |       if (wen) mem[addr] <= data;
       |                   ^
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Warning-WIDTHTRUNC: t/t_bigmem_bad.v:14:26: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'data' generates 256 bits.
-                                           : ... note: In instance 't_bigmem'
+%Warning-WIDTHTRUNC: t/t_mem_big_bad.v:14:26: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'data' generates 256 bits.
+                                            : ... note: In instance 't_bigmem'
    14 |       if (wen) mem[addr] <= data;
       |                          ^~
                      ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest

test_regress/t/t_opt_dedupe_clk_gate_off.py

@@ -10,7 +10,7 @@
 import vltest_bootstrap
 
 test.scenarios('simulator_st')
-test.top_filename = "t/t_dedupe_clk_gate.v"
+test.top_filename = "t/t_opt_dedupe_clk_gate.v"
 
 test.compile(verilator_flags2=["--stats", "-fno-dedup"])
 

test_regress/t/t_scope_cxx_equal_to.py

@@ -10,7 +10,6 @@
 import vltest_bootstrap
 
 test.scenarios('simulator')
-test.top_filename = "t/t_cxx_equal_to.v"
 
 test.compile(verilator_flags2=['--binary --trace-vcd'])
 

test_regress/t/t_trace_jumps_do_while_saif.py

@@ -10,7 +10,7 @@
 import vltest_bootstrap
 
 test.scenarios('vlt')
-test.top_filename = "t/t_jumps_do_while.v"
+test.top_filename = "t/t_do_while_jumps.v"
 
 test.compile(verilator_flags2=['--trace-saif'])