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Tests: Misc string format test improvements

This commit is contained in:
Wilson Snyder 2026-03-11 19:58:52 -04:00
parent aca2c05ad9
commit cbf8d97a76
12 changed files with 40 additions and 22 deletions
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2
test_regress/t/t_display.out
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@ -3,7 +3,7 @@
[0] In top.t.sub.write_m.subblock (work.sub)
[0] In top.t.sub2.write_m (work.sub2)
[0] In top.t.sub2.write_m.subblock2 (work.sub2)
a: -0.4=> 0.4 0 0 0
a: -2.4=> 2.4 2 2 10
[0] Back \ Quote "
[0] %b=000001100 %0b=1100 %b=00000101010111011101110111100110011001100 %0b=101010111011101110111100110011001100 %b=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0b=1010101111000001001000110100010101100111100000010010001101000101011001111000
[0] %B=000001100 %0B=1100 %B=00000101010111011101110111100110011001100 %0B=101010111011101110111100110011001100 %B=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0B=1010101111000001001000110100010101100111100000010010001101000101011001111000

4
test_regress/t/t_display.v
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@ -262,9 +262,9 @@ module sub3;
real a, d;
task write_m;
a = 0.4;
a = 2.4;
// verilator lint_off REALCVT
$display("a: -0.4=> %.1f %0d %0x %0b", copyr(a), copyr(a), copyr(a), copyr(a));
$display("a: -2.4=> %.1f %0d %0x %0b", copyr(a), copyr(a), copyr(a), copyr(a));
// verilator lint_on REALCVT
endtask
endmodule

20
test_regress/t/t_display_string_noopt.py Executable file
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@ -0,0 +1,20 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_display_string.v"
test.golden_filename = "t/t_display_string.out"
test.compile(verilator_flags2=["-O0"])
test.execute(expect_filename=test.golden_filename)
test.passes()

16
test_regress/t/t_display_type_bad.out
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@ -1,22 +1,22 @@
%Error: t/t_display_type_bad.v:10:29: $display-line format of '%d' illegal with string argument
%Error: t/t_display_type_bad.v:11:29: $display-line format of '%d' illegal with string argument
: ... note: In instance 't'
: ... Suggest use '%s'
10 | $display("%d %x %f %t", s, s, s, s);
11 | $display("%d %x %f %t", s, s, s, s);
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_display_type_bad.v:10:32: $display-line format of '%x' illegal with string argument
%Error: t/t_display_type_bad.v:11:32: $display-line format of '%x' illegal with string argument
: ... note: In instance 't'
: ... Suggest use '%s'
10 | $display("%d %x %f %t", s, s, s, s);
11 | $display("%d %x %f %t", s, s, s, s);
| ^
%Error: t/t_display_type_bad.v:10:35: $display-line format of '%f' illegal with string argument
%Error: t/t_display_type_bad.v:11:35: $display-line format of '%f' illegal with string argument
: ... note: In instance 't'
: ... Suggest use '%s'
10 | $display("%d %x %f %t", s, s, s, s);
11 | $display("%d %x %f %t", s, s, s, s);
| ^
%Error: t/t_display_type_bad.v:10:38: $display-line format of '%t' illegal with string argument
%Error: t/t_display_type_bad.v:11:38: $display-line format of '%t' illegal with string argument
: ... note: In instance 't'
: ... Suggest use '%s'
10 | $display("%d %x %f %t", s, s, s, s);
11 | $display("%d %x %f %t", s, s, s, s);
| ^
%Error: Exiting due to

2
test_regress/t/t_display_type_bad.v
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@ -6,8 +6,10 @@
module t;
string s = "a string";
int vec[2];
initial begin
$display("%d %x %f %t", s, s, s, s);
$display("%d %x %f %t", vec, vec, vec, vec);
$write("*-* All Finished *-*\n");
$finish;
end

2
test_regress/t/t_dpi_arg_inout_unpack.v
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@ -107,7 +107,7 @@
`define CHECK_DOUBLE_VAL(act, exp) if ((act) == (exp)) begin \
if (ENABLE_VERBOSE_MESSAGE)$display("%s:%f as expected", `"act`", (act)); \
end else begin \
$display("Mismatch %s expected:%d actual:%f at %f", `"act`", (exp), (act), `__LINE__); \
$display("Mismatch %s expected:%f actual:%f at %d", `"act`", (exp), (act), `__LINE__); \
$stop; \
end

2
test_regress/t/t_lib_prot.v
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@ -10,7 +10,7 @@ sig``_in <= {8{crc}}; \
/* verilator lint_on WIDTH */
`define CHECK(sig) \
if (cyc > 0 && sig``_in != sig``_out) begin \
$display(`"%%Error (%m) sig``_in (0x%0x) != sig``_out (0x%0x)`", \
$display(`"%%Error (%m) sig``_in (%p) != sig``_out (%p)`", \
sig``_in, sig``_out); \
$stop; \
end

4
test_regress/t/t_math_shortcircuit_dynsel.v
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@ -15,10 +15,6 @@ module t;
if (dict_size != dict.size) begin
$display("Assertion failed: dict_size mismatch");
$display("Initial size: %0d, New size: %0d", dict_size, dict.size);
$display("Dictionary contents:");
foreach (dict[key]) begin
$display(" Key: %0d, Value: %0d", key, dict[key]);
end
$error;
end
return next_nonzero;

2
test_regress/t/t_public_unpacked_port.v
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@ -38,7 +38,7 @@ module t (
if (cyc == 10) begin
if (s1up_out[0] != 9) begin
$display("%%Error: got %0d instead of 9", s1up_out);
$display("%%Error: got %0d instead of 9", s1up_out[0]);
$stop;
end
if (the_sub.sub_s1up_in[0] != 10) begin

2
test_regress/t/t_sys_file_scan.out Normal file
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@ -0,0 +1,2 @@
# a
1

4
test_regress/t/t_sys_file_scan.py
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@ -17,8 +17,6 @@ test.compile()
test.execute()
test.file_grep(test.obj_dir + "/t_sys_file_scan_test.log", r"""# a
1
""")
test.files_identical(test.obj_dir + "/t_sys_file_scan_test.log", test.golden_filename)
test.passes()

2
test_regress/t/t_sys_file_scan.v
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@ -23,7 +23,7 @@ module t;
// Ifdefing this out gave bug248
$display("-count == %0d, infile %d, outfile %d", count, infile, outfile);
`endif
if (count == 0) $stop;
if (count != 1) $stop;
$fwrite(outfile, "# a\n");
$fwrite(outfile, "%d\n", a);
$fclose(infile);