Fix variable conflict when multiple cells with unused input defaults

This commit is contained in:
Wilson Snyder 2026-02-07 18:11:55 -05:00
parent bbb231dfe2
commit 0c83594e1e
2 changed files with 19 additions and 2 deletions

View File

@ -342,7 +342,8 @@ class InlineRelinkVisitor final : public VNVisitor {
// variable that will later be pruned (it will otherwise be unreferenced).
if (!nodep->access().isReadOnly()) {
AstVar* const varp = nodep->varp();
const std::string name = "__vInlPlaceholder_" + std::to_string(++m_nPlaceholders);
const std::string name
= m_cellp->name() + "__vInlPlaceholder_" + std::to_string(++m_nPlaceholders);
AstVar* const holdep = new AstVar{varp->fileline(), VVarType::VAR, name, varp};
m_modp->addStmtsp(holdep);
AstVarRef* const newp = new AstVarRef{nodep->fileline(), holdep, nodep->access()};

View File

@ -82,6 +82,12 @@ module t
/*.i(),*/
.o(dut0_o_default));
logic dut0_o_default_b;
dut_default_input0 u_dut0_default_b
(.required_input(1),
/*.i(),*/
.o(dut0_o_default_b));
logic dut1_o_default;
dut_default_input1 u_dut1_default
(/*.i(),*/
@ -101,6 +107,11 @@ module t
(.required_input(1),
.i(), // open
.o(dut0_o_open));
logic dut0_o_open_b;
dut_default_input0 u_dut0_open_b
(.required_input(1),
.i(), // open
.o(dut0_o_open_b));
logic dut1_o_open;
dut_default_input1 u_dut1_open
@ -122,11 +133,16 @@ module t
// 3. DUT instances with overriden values
// instance names are u_dut*_overriden
// Have u_dut0_overriden get its overriden value from a signal
logic dut0_o_overriden;
logic dut0_o_overriden;
dut_default_input0 u_dut0_overriden
(.required_input(1),
.i(logic1), // from wire
.o(dut0_o_overriden));
logic dut0_o_overriden_b;
dut_default_input0 u_dut0_overriden_b
(.required_input(1),
.i(logic1), // from wire
.o(dut0_o_overriden_b));
// Have u_dut1_overriden get its overriden value from a function.
logic dut1_o_overriden;