Fix errant integer promotion (#7012)

src/V3Clean.cpp

@@ -18,7 +18,7 @@
 // Each module:
 //      For each expression, if it requires a clean operand,
 //      and the operand is dirty, insert a CLEAN node.
-//      Resize operands to C++ 32/64/wide types.
+//      Resize operands (but not variables or variable selects) to C++ 32/64/wide types.
 //      Copy all width() values to widthMin() so RANGE, etc can still see orig widths
 //
 //*************************************************************************
@@ -83,6 +83,7 @@ class CleanVisitor final : public VNVisitor {
             if (VN_IS(nodep, Var)  //
                 || VN_IS(nodep, ConsPackMember)  //
                 || VN_IS(nodep, NodeDType)  // Don't want to change variable widths!
+                || VN_IS(nodep, NodeSel)  // Array selects should reflect variable widths
                 || VN_IS(nodep->dtypep()->skipRefp(), AssocArrayDType)  // Or arrays
                 || VN_IS(nodep->dtypep()->skipRefp(), WildcardArrayDType)
                 || VN_IS(nodep->dtypep()->skipRefp(), DynArrayDType)

src/Verilator.cpp

@@ -527,7 +527,8 @@ static void process() {
             // Bits between widthMin() and width() are irrelevant, but may be non zero.
             v3Global.widthMinUsage(VWidthMinUsage::VERILOG_WIDTH);
 
-            // Make all expressions either 8, 16, 32 or 64 bits
+            // Make all expressions 32, 64, or 32*N bits
+            // Variables and selects-of-variables remain verilog-width
             V3Clean::cleanAll(v3Global.rootp());
 
             // Move wide constants to BLOCK temps / ConstPool.

test_regress/t/t_array_sel_short.py

@@ -0,0 +1,23 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2024 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios("simulator")
+
+test.compile(verilator_flags2=["--dump-tree"])
+
+if test.vlt_all:
+    # Test for correct array select width, see: #7012
+    clean_tree = test.glob_one(test.obj_dir + "/V*_clean.tree")
+    test.file_grep_count(clean_tree, r"ARRAYSEL.*G\/w16", 2)
+
+test.execute()
+
+test.passes()

test_regress/t/t_array_sel_short.v

@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+   logic [15:0] foo [8];
+
+   initial begin
+      if (foo[1] != foo[1]) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule