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Commentary: Changes update

This commit is contained in:
Wilson Snyder 2026-04-11 17:47:39 -04:00
parent d2c3d134c9
commit 0891d51c75
6 changed files with 81 additions and 35 deletions
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9
Changes
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@ -42,6 +42,7 @@ Verilator 5.047 devel
* Support `##` delay on implication RHS in SVA properties (#7284). [Yilou Wang]
* Support boolean and/or in sequence expressions (#7285). [Yilou Wang]
* Support property-local variables and sequence match items (#7286). [Yilou Wang]
* Support 'until' property (partial #7290) (#7399). [Ryszard Rozak, Antmicro Ltd.]
* Support array map() method (#7307) (#7316) (#7344). [Wei-Lun Chiu]
* Support SVA goto repetition `[->N]` in concurrent assertions (#7310). [Yilou Wang]
* Support consecutive repetition `[\*N]` in SVA properties (#7311). [Yilou Wang]
@ -51,6 +52,7 @@ Verilator 5.047 devel
* Support sequence 'throughout' operator (#7378). [Yilou Wang]
* Support sequence consecutive repetition `[*N:M]`, `[+]`, and `[*]` (#7379). [Yilou Wang]
* Support sequence `first_match` operator (#7392). [Yilou Wang]
* Support nonconsecutive repetition [=N] in sequence expressions (#7397). [Yilou Wang]
* Add VPI callback support to --main (#7145).
* Add V3LiftExpr pass to lower impure expressions and calls (#7141) (#7164). [Geza Lore, Testorrent USA, Inc.]
* Add --func-recursion-depth CLI option (#7175) (#7179).
@ -62,6 +64,7 @@ Verilator 5.047 devel
* Improve E_UNSUPPORTED warning messages (#7329). [Eunseo Song]
* Change array tracing to dump left index to right index (#7205). [Geza Lore, Testorrent USA, Inc.]
* Change `--converge-limit` default to 10000 (#7209).
* Remove DFG extract optimization pass (#7394). [Geza Lore, Testorrent USA, Inc.]
* Optimize size of trace declaration object code (#7150). [Szymon Gizler, Antmicro Ltd.]
* Optimize function call return value temporaries (#7152). [Geza Lore, Testorrent USA, Inc.]
* Optimize conditional merging across some impure statements (#7159). [Geza Lore, Testorrent USA, Inc.]
@ -76,6 +79,7 @@ Verilator 5.047 devel
* Fix recursive default assignment for sub-arrays (#4589) (#7202). [Julian Carrier]
* Fix virtual interface member trigger convergence (#5116) (#7323). [Yilou Wang]
* Fix shift width mismatch in constraint solver SMT emission (#5420) (#7265). [Yilou Wang]
* Fix returning wrong type from static function in parameterized class (#5479) (#7387). [em2machine]
* Fix randomize size+element queue constraints (#5582) (#7225). [Rahul Behl, Testorrent USA, Inc.]
* Fix null assignment to virtual interfaces (#5974) (#5990). [Maxim Fonarev]
* Fix typedef scope resolution for parameterized class aliases (#5977) (#7319). [Nick Brereton]
@ -89,13 +93,14 @@ Verilator 5.047 devel
* Fix errant integer promotion (#7012). [Todd Strader]
* Fix randc solver hang with wide variables (#7068) (#7248). [Yilou Wang]
* Fix coroutine trace setters (#7078 repair) (#7296). [Igor Zaworski, Antmicro Ltd.]
* Fix vpi_put_value not updating forced read value (#7092) (#7395) (#7092). [Christian Hecken, Heidelberg University]
* Fix scheduling non-determinism (#7120) (#7162) (#7165). [Geza Lore, Testorrent USA, Inc.]
* Fix parameters inside std::randomize `with` clause (#7140). [Kamil Danecki, Antmicro Ltd.]
* Fix forcing unpacked variables (#7149). [Ryszard Rozak, Antmicro Ltd.]
* Fix wide conditional short circuiting (#7155).
* Fix eliminating assignments to DPI-read variables (#7158). [Geza Lore, Testorrent USA, Inc.]
* Fix std::randomize() in static function with static class members (#7167) (#7169). [Yilou Wang]
* Fix resolving default/non-default type parameters (#7171) (#7346) (#7380) (#7385). [em2machine]
* Fix resolving default/non-default type parameters (#7171) (#7346) (#7380) (#7385) (#7398) (#7406) (#7398). [em2machine]
* Fix recursive constant function in $unit scope (#7173) (#7174).
* Fix class extend references between queues (#7195).
* Fix library/hier_block tracing when top name is empty (#7200). [Geza Lore, Testorrent USA, Inc.]
@ -134,6 +139,8 @@ Verilator 5.047 devel
* Fix string `inside` queue (#7373).
* Fix VPI access to Verilog `force`-ed signals (#7381). [Christian Hecken, Heidelberg University]
* Fix sampling of hierarchical references (#7386). [Ryszard Rozak, Antmicro Ltd.]
* Fix virtual class inheritance false error (#7403) (#7405). [Nikolay Puzanov]
* Fix CMake compiler coroutine flags (#7404). [Shogo Yamazaki]
Verilator 5.046 2026-02-28

17
test_regress/t/t_class_param_comparator.v
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@ -9,26 +9,31 @@
package pkg;
class builtin_comp #(type T = int);
class builtin_comp #(
type T = int
);
static function bit comp(T a, T b);
return 1;
endfunction
endclass
class class_comp #(type T = int);
class class_comp #(
type T = int
);
static function bit comp(T a, T b);
return 1;
endfunction
endclass
virtual class comparator #(
type T = int,
type comp_type = builtin_comp #(T)
type T = int,
type comp_type = builtin_comp#(T)
);
endclass
class class_comparator #(type T = int)
extends comparator #(T, class_comp #(T));
class class_comparator #(
type T = int
) extends comparator #(T, class_comp #(T));
endclass
endpackage

36
test_regress/t/t_class_param_typedef_extends.v
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@ -16,24 +16,37 @@ module t;
endclass
// Inner parameterized classes
virtual class if_base #(type T1 = int, type T2 = T1);
virtual class if_base #(
type T1 = int,
type T2 = T1
);
endclass
virtual class port_base #(type IF = if_base#());
function void connect(port_base #(IF) other);
virtual class port_base #(
type IF = if_base#()
);
function void connect(port_base#(IF) other);
endfunction
endclass
class pull_port #(type REQ = int, type RSP = REQ)
extends port_base #(if_base #(REQ, RSP));
class pull_port #(
type REQ = int,
type RSP = REQ
) extends port_base #(if_base #(REQ, RSP));
endclass
class pull_imp #(type REQ = int, type RSP = REQ, type IMP = int)
extends port_base #(if_base #(REQ, RSP));
class pull_imp #(
type REQ = int,
type RSP = REQ,
type IMP = int
) extends port_base #(if_base #(REQ, RSP));
endclass
// Outer parameterized class with member using the type param
class driver #(type REQ = int, type RSP = REQ);
class driver #(
type REQ = int,
type RSP = REQ
);
pull_port #(REQ, RSP) seq_port;
function new;
seq_port = new;
@ -41,7 +54,10 @@ module t;
endclass
// Outer parameterized class on the other side
class sequencer #(type REQ = int, type RSP = REQ);
class sequencer #(
type REQ = int,
type RSP = REQ
);
pull_imp #(REQ, RSP, sequencer #(REQ, RSP)) seq_export;
function new;
seq_export = new;
@ -49,7 +65,7 @@ module t;
endclass
// Typedef specialization + extends
typedef driver #(my_item) my_driver;
typedef driver#(my_item) my_driver;
class low_driver extends my_driver;
function new;

8
test_regress/t/t_uvm_return_type.v
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@ -9,15 +9,17 @@
module t;
class cls #(bit T = 1);
class cls #(
bit T = 1
);
static function cls#(T) f();
cls#(T) c = new();
cls #(T) c = new();
return c;
endfunction
endclass
initial begin
static cls#(0) c = cls#(0)::f();
static cls #(0) c = cls#(0)::f();
if (c == null) $stop;
$write("*-* All Finished *-*\n");
$finish;

8
test_regress/t/t_uvm_return_type2.v
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@ -13,15 +13,17 @@
module t;
class cls #(logic [7:0] T = 8'd1);
class cls #(
logic [7:0] T = 8'd1
);
static function cls#(T) f();
cls#(T) c = new();
cls #(T) c = new();
return c;
endfunction
endclass
initial begin
static cls#(8'd0) c = cls#(8'd0)::f();
static cls #(8'd0) c = cls#(8'd0)::f();
if (c == null) $stop;
$write("*-* All Finished *-*\n");
$finish;

38
test_regress/t/t_uvm_return_type3.v
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@ -10,60 +10,74 @@
module t;
// Keyword type: bit (1-bit unsigned)
class cls_bit #(bit P = 1);
class cls_bit #(
bit P = 1
);
static function cls_bit#(P) f();
cls_bit#(P) c = new();
cls_bit #(P) c = new();
return c;
endfunction
endclass
// Keyword type: byte (8-bit signed)
class cls_byte #(byte P = 8'd1);
class cls_byte #(
byte P = 8'd1
);
static function cls_byte#(P) f();
cls_byte#(P) c = new();
cls_byte #(P) c = new();
return c;
endfunction
endclass
// Keyword type: shortint (16-bit signed)
class cls_shortint #(shortint P = 16'd1);
class cls_shortint #(
shortint P = 16'd1
);
static function cls_shortint#(P) f();
cls_shortint#(P) c = new();
cls_shortint #(P) c = new();
return c;
endfunction
endclass
// Keyword type: integer (32-bit signed)
class cls_integer #(integer P = 1);
class cls_integer #(
integer P = 1
);
static function cls_integer#(P) f();
cls_integer#(P) c = new();
cls_integer #(P) c = new();
return c;
endfunction
endclass
// Explicit range: logic [15:0] (16-bit unsigned)
class cls_logic16 #(logic [15:0] P = 16'd1);
class cls_logic16 #(
logic [15:0] P = 16'd1
);
static function cls_logic16#(P) f();
cls_logic16#(P) c = new();
cls_logic16 #(P) c = new();
return c;
endfunction
endclass
// Explicit range: logic [31:0] (32-bit unsigned)
class cls_logic32 #(logic [31:0] P = 1);
class cls_logic32 #(
logic [31:0] P = 1
);
static function cls_logic32#(P) f();
cls_logic32#(P) c = new();
cls_logic32 #(P) c = new();
return c;
endfunction
endclass
initial begin
// verilog_format: off
static cls_bit#(0) c1 = cls_bit#(0)::f();
static cls_byte#(8'd0) c2 = cls_byte#(8'd0)::f();
static cls_shortint#(16'd0) c3 = cls_shortint#(16'd0)::f();
static cls_integer#(0) c4 = cls_integer#(0)::f();
static cls_logic16#(16'd0) c5 = cls_logic16#(16'd0)::f();
static cls_logic32#(0) c6 = cls_logic32#(0)::f();
// verilog_format: off
if (c1 == null || c2 == null || c3 == null
|| c4 == null || c5 == null || c6 == null) $stop;