Fix `final` asserts and $stop (#7249)
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@ -164,7 +164,10 @@ void vl_finish(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE
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#ifndef VL_USER_STOP ///< Define this to override the vl_stop function
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void vl_stop(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE {
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// $stop or $fatal reporting; would break current API to add param as to which
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if (Verilated::threadContextp()->gotFinish()) return;
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if (Verilated::threadContextp()->gotFinish()
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&& !Verilated::threadContextp()->executingFinal()) {
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return;
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}
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const char* const msg = "Verilog $stop";
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Verilated::threadContextp()->gotError(true);
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Verilated::threadContextp()->gotFinish(true);
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@ -2831,6 +2834,14 @@ void VerilatedContext::gotFinish(bool flag) VL_MT_SAFE {
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const VerilatedLockGuard lock{m_mutex};
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m_s.m_gotFinish = flag;
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}
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bool VerilatedContext::executingFinal() const VL_MT_SAFE {
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const VerilatedLockGuard lock{m_mutex};
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return m_ns.m_executingFinal;
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}
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void VerilatedContext::executingFinal(bool flag) VL_MT_SAFE {
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const VerilatedLockGuard lock{m_mutex};
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m_ns.m_executingFinal = flag;
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}
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void VerilatedContext::profExecStart(uint64_t flag) VL_MT_SAFE {
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const VerilatedLockGuard lock{m_mutex};
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m_ns.m_profExecStart = flag;
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@ -408,6 +408,7 @@ protected:
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struct NonSerialized final { // Non-serialized information
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// These are reloaded from on command-line settings, so do not need to persist
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// Fast path
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bool m_executingFinal = false; // Running generated final() code
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uint64_t m_profExecStart = 1; // +prof+exec+start time
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uint32_t m_profExecWindow = 2; // +prof+exec+window size
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// Slow path
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@ -530,6 +531,10 @@ public:
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bool gotFinish() const VL_MT_SAFE { return m_s.m_gotFinish; }
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/// Set if got a $finish or $stop/error
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void gotFinish(bool flag) VL_MT_SAFE;
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/// Check if generated final() code is executing
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bool executingFinal() const VL_MT_SAFE;
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/// Set if generated final() code is executing
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void executingFinal(bool flag) VL_MT_SAFE;
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/// Return if quiet enabled
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bool quiet() const VL_MT_SAFE { return m_s.m_quiet; }
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/// Enable quiet (also prevents need for OS calls to get CPU time)
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@ -489,7 +489,9 @@ class EmitCModel final : public EmitCFunc {
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"void " + topModNameProtected + "__" + protect("_eval_final") + selfDecl + ";\n");
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// ::final
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puts("\nVL_ATTR_COLD void " + EmitCUtil::topClassName() + "::final() {\n");
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puts("contextp()->executingFinal(true);\n");
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puts(/**/ topModNameProtected + "__" + protect("_eval_final") + "(&(vlSymsp->TOP));\n");
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puts("contextp()->executingFinal(false);\n");
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puts("}\n");
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putSectionDelimiter("Implementations of abstract methods from VerilatedModel\n");
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@ -0,0 +1,3 @@
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[10] %Error: t_final_assert.v:12: Assertion failed in top.tb: 'assert' failed.
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%Error: t/t_final_assert.v:12: Verilog $stop
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Aborting...
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2024 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.execute(fails=True, expect_filename=test.golden_filename)
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test.passes()
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@ -0,0 +1,14 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module tb();
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initial begin
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$finish();
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end
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final begin
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assert(1 == 0);
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end
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endmodule
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