Support rise/fall delays (#7368)
Signed-off-by: Artur Bieniek <abieniek@antmicro.com>
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Artur Bieniek
GitHub
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@ -1855,8 +1855,11 @@ List Of Warnings
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and #(1,2,3) AND (out, a, b);
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Warns that rising, falling, and turn-off delays are currently unsupported.
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The first (rising) delay is used for all cases.
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Warns that the third (turn-off) delay is currently unsupported and is
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ignored. Rising and falling delays are supported.
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In versions before 5.048, warned that rising, falling, and turn-off delays were
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unsupported. The first (rising) delay was used for all cases.
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.. option:: SELRANGE
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@ -543,11 +543,10 @@ class AstDelay final : public AstNodeStmt {
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// Delay statement
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// @astgen op1 := lhsp : AstNodeExpr // Delay value (or min for range)
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// @astgen op2 := stmtsp : List[AstNode] // Statements under delay
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// @astgen op3 := rhsp : Optional[AstNodeExpr] // Max delay value (range delay only)
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// @astgen op3 := rhsp : Optional[AstNodeExpr] // Max bound for cycle range or fall delay
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// @astgen op4 := throughoutp : Optional[AstNodeExpr] // Throughout condition (IEEE 16.9.9)
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VTimescale m_timeunit; // Delay's time unit
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const bool m_isCycle; // True if it is a cycle delay
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public:
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AstDelay(FileLine* fl, AstNodeExpr* lhsp, bool isCycle)
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: ASTGEN_SUPER_Delay(fl)
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@ -562,8 +561,10 @@ public:
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void timeunit(const VTimescale& flag) { m_timeunit = flag; }
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VTimescale timeunit() const { return m_timeunit; }
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bool isCycleDelay() const { return m_isCycle; }
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bool isRangeDelay() const { return rhsp() != nullptr; }
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bool isUnbounded() const { return rhsp() && VN_IS(rhsp(), Unbounded); }
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bool isRangeDelay() const { return m_isCycle && rhsp() != nullptr; }
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bool isUnbounded() const { return isRangeDelay() && VN_IS(rhsp(), Unbounded); }
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void fallDelay(AstNodeExpr* const fallDelayp) { rhsp(fallDelayp); }
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AstNodeExpr* fallDelay() const { return m_isCycle ? nullptr : rhsp(); }
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};
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class AstDisable final : public AstNodeStmt {
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// @astgen op1 := targetRefp : Optional[AstNodeExpr] // Reference to link in V3LinkDot
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@ -1127,7 +1127,15 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public VNVisitorConst {
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}
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VL_RESTORER(m_prefixed);
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m_prefixed = false;
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iterateConst(nodep->lhsp());
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if (AstNodeExpr* const fallDelayp = nodep->fallDelay()) {
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puts("(");
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iterateConst(nodep->lhsp());
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puts(", ");
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iterateConst(fallDelayp);
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puts(")");
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} else {
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iterateConst(nodep->lhsp());
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}
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if (!m_suppressSemi) {
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puts(";\n");
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} else {
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@ -542,6 +542,20 @@ class TimingControlVisitor final : public VNVisitor {
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= timeunit.powerOfTen() - m_netlistp->timeprecision().powerOfTen();
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return std::pow(10.0, scalePowerOfTen);
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}
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static bool staticallyNonZeroDelay(const AstNodeExpr* valuep) {
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if (const AstConst* const constp = VN_CAST(valuep, Const)) return !constp->isZero();
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if (const AstCond* const condp = VN_CAST(valuep, Cond)) {
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return staticallyNonZeroDelay(condp->thenp())
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&& staticallyNonZeroDelay(condp->elsep());
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}
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if (const AstMul* const mulp = VN_CAST(valuep, Mul)) {
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const AstConst* const lhsConstp = VN_CAST(mulp->lhsp(), Const);
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const AstConst* const rhsConstp = VN_CAST(mulp->rhsp(), Const);
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if (lhsConstp && !lhsConstp->isZero()) return staticallyNonZeroDelay(mulp->rhsp());
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if (rhsConstp && !rhsConstp->isZero()) return staticallyNonZeroDelay(mulp->lhsp());
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}
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return false;
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}
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// Creates the global delay scheduler variable
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AstVarScope* getCreateDelayScheduler() {
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if (m_delaySchedp) return m_delaySchedp;
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@ -1022,6 +1036,9 @@ class TimingControlVisitor final : public VNVisitor {
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m_hasStaticZeroDelay = true;
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// Don't warn on variable delays, as no point
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m_unknownDelayFlps.clear();
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} else if (staticallyNonZeroDelay(valuep)) {
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// Delay is dynamic, but every statically known outcome is non-zero.
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// So we don't need #0 delay support and there should be no warning.
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} else if (!VN_IS(valuep, Const)) {
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// Delay is not known at compiile time. Conservatively schedule for #0 support,
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// but warn if no static #0 delays used as performance might be improved
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@ -1250,6 +1267,15 @@ class TimingControlVisitor final : public VNVisitor {
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AstNodeExpr* const lhs1p = nodep->lhsp()->unlinkFrBack();
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AstNodeExpr* const rhs1p = nodep->rhsp()->unlinkFrBack();
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AstNode* const controlp = nodep->timingControlp()->unlinkFrBack();
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if (AstDelay* const delayp = VN_CAST(controlp, Delay)) {
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if (AstNodeExpr* fallDelayp = delayp->fallDelay()) {
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fallDelayp = fallDelayp->unlinkFrBack();
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// Use fall only for an all-zero value, rise otherwise.
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delayp->lhsp(
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new AstCond{flp, new AstEq{flp, rhs1p->cloneTree(false), new AstConst{flp, 0}},
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fallDelayp, delayp->lhsp()->unlinkFrBack()});
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}
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}
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AstAssign* const assignp = new AstAssign{nodep->fileline(), lhs1p, rhs1p, controlp};
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// Put the assignment in a fork..join_none.
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AstFork* const forkp = new AstFork{flp, VJoinType::JOIN_NONE};
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@ -731,6 +731,11 @@ class WidthVisitor final : public VNVisitor {
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iterateCheckBool(nodep, "default disable iff condition", nodep->condp(), BOTH);
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}
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void visit(AstDelay* nodep) override {
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if (AstNodeExpr* const fallDelayp = nodep->fallDelay()) {
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iterateCheckDelay(nodep, "delay", nodep->lhsp(), BOTH);
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iterateCheckDelay(nodep, "delay", fallDelayp, BOTH);
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return;
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}
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if (VN_IS(m_procedurep, Final)) {
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nodep->v3error("Delays are not legal in final blocks (IEEE 1800-2023 9.2.3)");
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VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
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@ -38,8 +38,7 @@
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{ BBUNSUP((fl), "Unsupported: Verilog 1995 gate primitive: " << (tok)); }
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#define RISEFALLDLYUNSUP(nodep) \
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if (nodep->fileline()->timingOn() && v3Global.opt.timing().isSetTrue()) { \
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nodep->v3warn(RISEFALLDLY, \
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"Unsupported: rising/falling/turn-off delays. Using the first delay"); \
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nodep->v3warn(RISEFALLDLY, "Unsupported: turn-off delays. Ignoring the third delay"); \
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}
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#define MINTYPMAXDLYUNSUP(nodep) \
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if (nodep->fileline()->timingOn() && v3Global.opt.timing().isSetTrue()) { \
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@ -3043,9 +3042,10 @@ delay_control<delayp>: //== IEEE: delay_control
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| '#' '(' minTypMax ')'
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{ $$ = new AstDelay{$<fl>1, $3, false}; }
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| '#' '(' minTypMax ',' minTypMax ')'
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{ $$ = new AstDelay{$<fl>1, $3, false}; RISEFALLDLYUNSUP($3); DEL($5); }
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{ $$ = new AstDelay{$<fl>1, $3, false};
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$$->fallDelay($5); }
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| '#' '(' minTypMax ',' minTypMax ',' minTypMax ')'
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{ $$ = new AstDelay{$<fl>1, $5, false}; RISEFALLDLYUNSUP($5); DEL($3); DEL($7); }
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{ $$ = new AstDelay{$<fl>1, $3, false}; $$->fallDelay($5); RISEFALLDLYUNSUP($7); DEL($7); }
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;
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delay_value<nodeExprp>: // ==IEEE:delay_value
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@ -6883,7 +6883,7 @@ cycle_delay_range<delayp>: // IEEE: ==cycle_delay_range
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// // the sv-ac committee has been asked to clarify (Mantis 1901)
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| yP_POUNDPOUND '[' constExpr ':' constExpr ']'
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{ $$ = new AstDelay{$1, $3, true};
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$$->rhsp($5); }
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$$->rhsp($5); }
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| yP_POUNDPOUND yP_BRASTAR ']'
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{ $$ = new AstDelay{$1, new AstConst{$1, 0}, true};
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$$->rhsp(new AstUnbounded{$1}); }
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@ -22,7 +22,7 @@ module t (
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// verilator lint_off IMPLICIT
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not #(0.108) NT0 (nt0, a[0]);
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and #1 AN0 (an0, a[0], b[0]);
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nand #(2,3) ND0 (nd0, a[0], b[0], b[1]);
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nand #(2,3,4) ND0 (nd0, a[0], b[0], b[1]);
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or OR0 (or0, a[0], b[0]);
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nor NR0 (nr0, a[0], b[0], b[2]);
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xor (xo0, a[0], b[0]);
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@ -1,6 +1,6 @@
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%Warning-RISEFALLDLY: t/t_gate_basic.v:25:11: Unsupported: rising/falling/turn-off delays. Using the first delay
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25 | nand #(2,3) ND0 (nd0, a[0], b[0], b[1]);
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| ^
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%Warning-RISEFALLDLY: t/t_gate_basic.v:25:15: Unsupported: turn-off delays. Ignoring the third delay
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25 | nand #(2,3,4) ND0 (nd0, a[0], b[0], b[1]);
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| ^
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... For warning description see https://verilator.org/warn/RISEFALLDLY?v=latest
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... Use "/* verilator lint_off RISEFALLDLY */" and lint_on around source to disable this message.
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%Warning-SPECIFYIGN: t/t_gate_basic.v:49:25: Ignoring unsupported: specify block construct
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@ -1,6 +1,6 @@
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%Warning-RISEFALLDLY: t/t_gate_basic.v:25:11: Unsupported: rising/falling/turn-off delays. Using the first delay
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25 | nand #(2,3) ND0 (nd0, a[0], b[0], b[1]);
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| ^
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%Warning-RISEFALLDLY: t/t_gate_basic.v:25:15: Unsupported: turn-off delays. Ignoring the third delay
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25 | nand #(2,3,4) ND0 (nd0, a[0], b[0], b[1]);
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| ^
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... For warning description see https://verilator.org/warn/RISEFALLDLY?v=latest
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... Use "/* verilator lint_off RISEFALLDLY */" and lint_on around source to disable this message.
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%Error: Exiting due to
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@ -9,11 +9,12 @@
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import vltest_bootstrap
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test.scenarios('linter')
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test.scenarios('vlt')
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test.top_filename = "t/t_gate_basic.v"
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test.lint(verilator_flags2=["-Wall", "-Wno-DECLFILENAME -Wno-SPECIFYIGN -Wno-UNUSED"],
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fails=True,
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expect_filename=test.golden_filename)
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test.compile(
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verilator_flags2=["--timing", "-Wall", "-Wno-DECLFILENAME -Wno-SPECIFYIGN -Wno-UNUSED"],
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fails=True,
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expect_filename=test.golden_filename)
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test.passes()
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(timing_loop=True, verilator_flags2=["--timing"])
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test.execute()
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test.passes()
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@ -0,0 +1,104 @@
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// DESCRIPTION: Verilator: Rise/fall delays on continuous assigns and gates
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__, `__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0)
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`define check_scalar(exp) do begin `checkh(out_assign, exp); `checkh(out_buf, exp); `checkh(out_net, exp); end while(0)
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module t;
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logic in = 0;
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logic [3:0] in_vec = 4'h0;
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wire out_assign;
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wire out_buf;
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wire #(5,3) out_net;
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wire [3:0] out_vec_assign;
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assign #(5,3) out_assign = in;
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buf #(5,3) u_buf (out_buf, in);
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assign out_net = in;
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assign #(5,3) out_vec_assign = in_vec;
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initial begin
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#4;
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`check_scalar(1'b0);
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`checkh(out_vec_assign, 4'h0);
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// Rise canceled by a fall before the rise delay expires.
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in = 1'b1;
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#2;
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`check_scalar(1'b0);
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in = 1'b0;
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#4;
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`check_scalar(1'b0);
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// A committed rise.
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in = 1'b1;
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#4;
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`check_scalar(1'b0);
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#1;
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`check_scalar(1'b1);
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// Fall canceled by a new rise before the fall delay expires.
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in = 1'b0;
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#2;
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`check_scalar(1'b1);
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in = 1'b1;
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#4;
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`check_scalar(1'b1);
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#1;
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`check_scalar(1'b1);
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// A committed fall.
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in = 1'b0;
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#2;
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`check_scalar(1'b1);
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#1;
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`check_scalar(1'b0);
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// Whole-value vector rise canceled by a fall back to zero.
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in_vec = 4'h3;
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#2;
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`checkh(out_vec_assign, 4'h0);
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in_vec = 4'h0;
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#4;
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`checkh(out_vec_assign, 4'h0);
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// Zero to nonzero uses the rise delay.
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in_vec = 4'h3;
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#4;
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`checkh(out_vec_assign, 4'h0);
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#1;
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`checkh(out_vec_assign, 4'h3);
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// Nonzero to nonzero still uses the rise delay on the whole value.
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in_vec = 4'h5;
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#4;
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`checkh(out_vec_assign, 4'h3);
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#1;
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`checkh(out_vec_assign, 4'h5);
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// A pending fall back to zero is canceled by a new nonzero value.
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in_vec = 4'h0;
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#2;
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`checkh(out_vec_assign, 4'h5);
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in_vec = 4'h6;
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#4;
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`checkh(out_vec_assign, 4'h5);
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#1;
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`checkh(out_vec_assign, 4'h6);
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// Nonzero to zero uses the fall delay.
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in_vec = 4'h0;
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#2;
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`checkh(out_vec_assign, 4'h6);
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#1;
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`checkh(out_vec_assign, 4'h0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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