Support `foreach` with nested dots (#6991)
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
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@ -1851,11 +1851,15 @@ class LinkDotFindVisitor final : public VNVisitor {
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m_curSymp->fallbackp(VL_RESTORER_PREV(m_curSymp));
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// DOT(x, SELLOOPVARS(var, loops)) -> SELLOOPVARS(DOT(x, var), loops)
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if (AstDot* const dotp = VN_CAST(nodep->arrayp(), Dot)) {
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if (AstSelLoopVars* const loopvarsp = VN_CAST(dotp->rhsp(), SelLoopVars)) {
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AstDot* dotAbovep = dotp;
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while (AstDot* const dotNextp = VN_CAST(dotAbovep->rhsp(), Dot)) {
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dotAbovep = dotNextp;
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}
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if (AstSelLoopVars* const loopvarsp = VN_CAST(dotAbovep->rhsp(), SelLoopVars)) {
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AstNodeExpr* const fromp = loopvarsp->fromp()->unlinkFrBack();
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loopvarsp->unlinkFrBack();
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dotp->replaceWith(loopvarsp);
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dotp->rhsp(fromp);
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dotAbovep->rhsp(fromp);
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loopvarsp->fromp(dotp);
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}
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}
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.execute()
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test.passes()
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@ -0,0 +1,31 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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typedef struct {
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int x[9][9];
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} Foo;
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class Bar;
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Foo foo;
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function automatic void test();
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foreach(this.foo.x[i])
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foreach(this.foo.x[i][j])
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this.foo.x[i][j] = i * j;
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for (int i = 0; i < 9; i++)
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for (int j = 0; j < 9; j++)
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if (this.foo.x[i][j] != i * j) $stop;
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endfunction
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endclass
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module t;
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initial begin
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Bar b = new;
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b.test;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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