Tests: Add t_interface_twoports (#5676)

test_regress/t/t_interface_twoports.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint()
+
+test.passes()

test_regress/t/t_interface_twoports.v

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+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+interface A;
+  logic x;
+endinterface
+
+module B;
+  A a ();
+endmodule
+
+module C (
+    A a0,
+    A a1
+);
+  assign a1.x = a0.x;
+endmodule
+
+module t;
+  B b0 ();
+  B b1 ();
+  C c (
+      b0.a,
+      b1.a
+  );
+  initial $finish;
+endmodule