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Verilog format

This commit is contained in:
Veripool API Bot 2026-03-03 07:21:24 -05:00 committed by Wilson Snyder
parent 5821d0697c
commit ce4d35aa85
340 changed files with 7037 additions and 6797 deletions
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19
test_regress/t/t_a1_first_cc.v
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@ -4,17 +4,14 @@
// SPDX-FileCopyrightText: 2017 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
// Test loop
always @ (posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
// Test loop
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

14
test_regress/t/t_alias_unsup.v
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@ -19,9 +19,9 @@ module t ( /*AUTOARG*/
input clk;
int cyc;
reg [63:0] crc;
reg [63:0] sum;
int cyc;
reg [63:0] crc;
reg [63:0] sum;
// Values to swap and locations for the swapped values.
wire [31:0] x_fwd = crc[31:0];
@ -51,11 +51,11 @@ module t ( /*AUTOARG*/
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end else if (cyc < 10) begin
end
else if (cyc < 10) begin
sum <= '0;
end else
if (cyc < 90) begin
end else if (cyc == 99) begin
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
`checkh(crc, 64'hc77bb9b3784ea091);
// What checksum will we end up with (above print should match)

42
test_regress/t/t_array_backw_index_bad.out
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@ -1,30 +1,30 @@
%Error: t/t_array_backw_index_bad.v:17:19: Slice selection '[1:3]' has reversed range order versus data type's '[3:0]'
%Error: t/t_array_backw_index_bad.v:17:17: Slice selection '[1:3]' has reversed range order versus data type's '[3:0]'
: ... note: In instance 't'
17 | array_assign[1:3] = '{32'd4, 32'd3, 32'd2};
| ^
17 | array_assign[1:3] = '{32'd4, 32'd3, 32'd2};
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_array_backw_index_bad.v:18:20: Slice selection '[3:1]' has reversed range order versus data type's '[0:3]'
%Error: t/t_array_backw_index_bad.v:18:18: Slice selection '[3:1]' has reversed range order versus data type's '[0:3]'
: ... note: In instance 't'
18 | larray_assign[3:1] = '{32'd4, 32'd3, 32'd2};
| ^
%Error: t/t_array_backw_index_bad.v:19:20: Slice selection '[4:6]' has reversed range order versus data type's '[6:3]'
18 | larray_assign[3:1] = '{32'd4, 32'd3, 32'd2};
| ^
%Error: t/t_array_backw_index_bad.v:19:18: Slice selection '[4:6]' has reversed range order versus data type's '[6:3]'
: ... note: In instance 't'
19 | array_assign2[4:6] = '{32'd4, 32'd3, 32'd2};
| ^
%Error: t/t_array_backw_index_bad.v:20:21: Slice selection '[6:4]' has reversed range order versus data type's '[3:6]'
19 | array_assign2[4:6] = '{32'd4, 32'd3, 32'd2};
| ^
%Error: t/t_array_backw_index_bad.v:20:19: Slice selection '[6:4]' has reversed range order versus data type's '[3:6]'
: ... note: In instance 't'
20 | larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2};
| ^
%Error: t/t_array_backw_index_bad.v:22:19: Slice selection index '[4:3]' outside data type's '[3:0]'
: ... note: In instance 't'
22 | array_assign[4:3] = '{32'd4, 32'd3};
20 | larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2};
| ^
%Error: t/t_array_backw_index_bad.v:23:19: Slice selection index '[1:-1]' outside data type's '[3:0]'
%Error: t/t_array_backw_index_bad.v:22:17: Slice selection index '[4:3]' outside data type's '[3:0]'
: ... note: In instance 't'
23 | array_assign[1:-1] = '{32'd4, 32'd3};
| ^
%Error: t/t_array_backw_index_bad.v:23:28: Assignment pattern missed initializing elements: -1
22 | array_assign[4:3] = '{32'd4, 32'd3};
| ^
%Error: t/t_array_backw_index_bad.v:23:17: Slice selection index '[1:-1]' outside data type's '[3:0]'
: ... note: In instance 't'
23 | array_assign[1:-1] = '{32'd4, 32'd3};
| ^~
23 | array_assign[1:-1] = '{32'd4, 32'd3};
| ^
%Error: t/t_array_backw_index_bad.v:23:26: Assignment pattern missed initializing elements: -1
: ... note: In instance 't'
23 | array_assign[1:-1] = '{32'd4, 32'd3};
| ^~
%Error: Exiting due to

36
test_regress/t/t_array_backw_index_bad.v
View File

@ -6,27 +6,27 @@
module t;
logic [31:0] array_assign [3:0];
logic [31:0] array_assign[3:0];
logic [31:0] larray_assign [0:3];
logic [31:0] larray_assign[0:3];
logic [31:0] array_assign2 [6:3];
logic [31:0] array_assign2[6:3];
logic [31:0] larray_assign2 [3:6];
initial begin
array_assign[1:3] = '{32'd4, 32'd3, 32'd2};
larray_assign[3:1] = '{32'd4, 32'd3, 32'd2};
array_assign2[4:6] = '{32'd4, 32'd3, 32'd2};
larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2};
logic [31:0] larray_assign2[3:6];
initial begin
array_assign[1:3] = '{32'd4, 32'd3, 32'd2};
larray_assign[3:1] = '{32'd4, 32'd3, 32'd2};
array_assign2[4:6] = '{32'd4, 32'd3, 32'd2};
larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2};
array_assign[4:3] = '{32'd4, 32'd3};
array_assign[1:-1] = '{32'd4, 32'd3};
array_assign[1:1] = '{32'd4}; // Ok
larray_assign[1:1] = '{32'd4}; // Ok
array_assign2[4:4] = '{32'd4}; // Ok
larray_assign2[4:4] = '{32'd4}; // Ok
array_assign[4:3] = '{32'd4, 32'd3};
array_assign[1:-1] = '{32'd4, 32'd3};
array_assign[1:1] = '{32'd4}; // Ok
larray_assign[1:1] = '{32'd4}; // Ok
array_assign2[4:4] = '{32'd4}; // Ok
larray_assign2[4:4] = '{32'd4}; // Ok
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

70
test_regress/t/t_array_compare.v
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@ -8,52 +8,52 @@
module t;
reg [3:0] array_1 [2:0];
reg [3:0] array_2 [2:0];
reg [3:0] array_3 [3:1];
reg [3:0] array_1[2:0];
reg [3:0] array_2[2:0];
reg [3:0] array_3[3:1];
reg [3:0] elem;
reg [3:0] elem;
reg array_1_ne_array_2;
reg array_1_eq_array_2;
reg array_1_ne_array_3;
reg array_1_eq_array_3;
reg array_1_ne_array_2;
reg array_1_eq_array_2;
reg array_1_ne_array_3;
reg array_1_eq_array_3;
initial begin
array_1[0] = 4'b1000;
array_1[1] = 4'b1000;
array_1[2] = 4'b1000;
initial begin
array_1[0] = 4'b1000;
array_1[1] = 4'b1000;
array_1[2] = 4'b1000;
array_2[0] = 4'b1000;
array_2[1] = 4'b1000;
array_2[2] = 4'b1000;
array_2[0] = 4'b1000;
array_2[1] = 4'b1000;
array_2[2] = 4'b1000;
array_3[1] = 4'b1000;
array_3[2] = 4'b0100;
array_3[3] = 4'b0100;
array_3[1] = 4'b1000;
array_3[2] = 4'b0100;
array_3[3] = 4'b0100;
array_1_ne_array_2 = array_1 != array_2; // 0
array_1_eq_array_2 = array_1 == array_2; // 0
array_1_ne_array_3 = array_1 != array_3; // 1
array_1_eq_array_3 = array_1 == array_3; // 1
array_1_ne_array_2 = array_1 != array_2; // 0
array_1_eq_array_2 = array_1 == array_2; // 0
array_1_ne_array_3 = array_1 != array_3; // 1
array_1_eq_array_3 = array_1 == array_3; // 1
//Not legal: array_rxor = ^ array_1;
//Not legal: array_rxnor = ^~ array_1;
//Not legal: array_ror = | array_1;
//Not legal: array_rand = & array_1;
//Not legal: array_rxor = ^ array_1;
//Not legal: array_rxnor = ^~ array_1;
//Not legal: array_ror = | array_1;
//Not legal: array_rand = & array_1;
`ifdef TEST_VERBOSE
$write("array_1_ne_array2==%0d\n", array_1_ne_array_2);
$write("array_1_ne_array3==%0d\n", array_1_ne_array_3);
$write("array_1_ne_array2==%0d\n", array_1_ne_array_2);
$write("array_1_ne_array3==%0d\n", array_1_ne_array_3);
`endif
if (array_1_ne_array_2 !== 0) $stop;
if (array_1_eq_array_2 !== 1) $stop;
if (array_1_ne_array_3 !== 1) $stop;
if (array_1_eq_array_3 !== 0) $stop;
if (array_1_ne_array_2 !== 0) $stop;
if (array_1_eq_array_2 !== 1) $stop;
if (array_1_ne_array_3 !== 1) $stop;
if (array_1_eq_array_3 !== 0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

76
test_regress/t/t_array_in_struct.v
View File

@ -7,55 +7,51 @@
//bug991
module t;
typedef struct {
logic [31:0] arr [3:0];
} a_t;
typedef struct {logic [31:0] arr[3:0];} a_t;
typedef struct {
logic [31:0] arr [0:3];
} b_t;
typedef struct {logic [31:0] arr[0:3];} b_t;
a_t array_assign;
a_t array_other;
a_t array_assign;
a_t array_other;
b_t larray_assign;
b_t larray_other;
b_t larray_assign;
b_t larray_other;
initial begin
array_assign.arr[0] = 32'd1;
array_assign.arr[3:1] = '{32'd4, 32'd3, 32'd2};
initial begin
array_assign.arr[0] = 32'd1;
array_assign.arr[3:1] = '{32'd4, 32'd3, 32'd2};
array_other.arr[0] = array_assign.arr[0]+10;
array_other.arr[3:1] = array_assign.arr[3:1];
if (array_other.arr[0] != 11) $stop;
if (array_other.arr[1] != 2) $stop;
if (array_other.arr[2] != 3) $stop;
if (array_other.arr[3] != 4) $stop;
array_other.arr[0] = array_assign.arr[0] + 10;
array_other.arr[3:1] = array_assign.arr[3:1];
if (array_other.arr[0] != 11) $stop;
if (array_other.arr[1] != 2) $stop;
if (array_other.arr[2] != 3) $stop;
if (array_other.arr[3] != 4) $stop;
larray_assign.arr[0] = 32'd1;
larray_assign.arr[1:3] = '{32'd4, 32'd3, 32'd2};
larray_assign.arr[0] = 32'd1;
larray_assign.arr[1:3] = '{32'd4, 32'd3, 32'd2};
larray_other.arr[0] = larray_assign.arr[0]+10;
larray_other.arr[1:3] = larray_assign.arr[1:3];
if (larray_other.arr[0] != 11) $stop;
if (larray_other.arr[1] != 4) $stop;
if (larray_other.arr[2] != 3) $stop;
if (larray_other.arr[3] != 2) $stop;
larray_other.arr[0] = larray_assign.arr[0] + 10;
larray_other.arr[1:3] = larray_assign.arr[1:3];
if (larray_other.arr[0] != 11) $stop;
if (larray_other.arr[1] != 4) $stop;
if (larray_other.arr[2] != 3) $stop;
if (larray_other.arr[3] != 2) $stop;
larray_other.arr = '{5, 6, 7, 8};
if (larray_other.arr[0] != 5) $stop;
if (larray_other.arr[1] != 6) $stop;
if (larray_other.arr[2] != 7) $stop;
if (larray_other.arr[3] != 8) $stop;
larray_other.arr = '{5, 6, 7, 8};
if (larray_other.arr[0] != 5) $stop;
if (larray_other.arr[1] != 6) $stop;
if (larray_other.arr[2] != 7) $stop;
if (larray_other.arr[3] != 8) $stop;
larray_other.arr = larray_assign.arr;
if (larray_other.arr[0] != 1) $stop;
if (larray_other.arr[1] != 4) $stop;
if (larray_other.arr[2] != 3) $stop;
if (larray_other.arr[3] != 2) $stop;
larray_other.arr = larray_assign.arr;
if (larray_other.arr[0] != 1) $stop;
if (larray_other.arr[1] != 4) $stop;
if (larray_other.arr[2] != 3) $stop;
if (larray_other.arr[3] != 2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

216
test_regress/t/t_array_index_increment.v
View File

@ -6,122 +6,124 @@
module t;
string test_string = "abcd";
string test_string = "abcd";
int array3d[2][3][4] = '{
'{
'{ 0, 1, 2, 3},
'{ 4, 5, 6, 7},
'{ 8, 9, 10, 11}
},
'{
'{ 12, 13, 14, 15},
'{ 16, 17, 18, 19},
'{ 20, 21, 22, 23}
}
};
int pos;
int val;
int i;
byte b;
// verilog_format: off
int array3d[2][3][4] = '{
'{'{ 0, 1, 2, 3},
'{ 4, 5, 6, 7},
'{ 8, 9, 10, 11}
},
'{'{ 12, 13, 14, 15},
'{ 16, 17, 18, 19},
'{ 20, 21, 22, 23}
}
};
// verilog_format: on
int pos;
int val;
int i;
byte b;
int data[4] = '{1, 2, 3, 4};
int data[4] = '{1, 2, 3, 4};
generate
genvar j;
int gdata[4];
for (j=0; j < 5; j++) begin
initial if (j >= 5) $stop;
end
generate
genvar j;
int gdata[4];
for (j = 0; j < 5; j++) begin
initial if (j >= 5) $stop;
end
for (j=0; j < 5; ++j) begin
initial if (j >= 5) $stop;
end
for (j = 0; j < 5; ++j) begin
initial if (j >= 5) $stop;
end
for (j=10; j >= 5; j--) begin
initial if (j < 5) $stop;
end
for (j = 10; j >= 5; j--) begin
initial if (j < 5) $stop;
end
for (j=10; j >= 5; --j) begin
initial if (j < 5) $stop;
end
endgenerate
for (j = 10; j >= 5; --j) begin
initial if (j < 5) $stop;
end
endgenerate
initial begin
pos = 0;
initial begin
pos = 0;
pos++;
if (pos != 1) $stop;
array3d[0][0][0]++;
if (array3d[0][0][0] != 1) $stop;
--array3d[0][0][0];
if (array3d[0][0][0] != 0) $stop;
pos = 2;
b = test_string[--pos];
if (b !== "b") $stop;
if (pos !== 1) $stop;
pos = 1;
b = test_string[++pos];
if (b !== "c") $stop;
if (pos !== 2) $stop;
pos = 3;
b = test_string[pos--];
if (b !== "d") $stop;
if (pos !== 2) $stop;
pos = 0;
b = test_string[pos++];
if (b !== "a") $stop;
if (pos !== 1) $stop;
pos = 0;
val = array3d[++pos][--pos][++pos];
if (pos !== 1) $stop;
if (val !== 13) $stop;
pos = 0;
val = array3d[++pos][pos--][++pos];
if (pos !== 1) $stop;
if (val !== 17) $stop;
for (i = 0; data[++i] < 4;) begin
// loop with multiple statements
pos = i;
val = data[i];
end
if (pos !== 2) $stop;
if (i !== 3) $stop;
if (val !== 3) $stop;
i = 0;
while (data[
i++
] < 4) begin
// loop with multiple statements
pos = i;
val = data[i];
end
if (pos !== 3) $stop;
if (i !== 4) $stop;
if (val !== 4) $stop;
pos = 0;
if (1 == 1) begin
pos++;
if (pos != 1) $stop;
end
if (pos != 1) $stop;
array3d[0][0][0]++;
if (array3d[0][0][0] != 1) $stop;
pos = 0;
if (1 == 1) pos++;
if (pos != 1) $stop;
--array3d[0][0][0];
if (array3d[0][0][0] != 0) $stop;
$write("*-* All Finished *-*\n");
$finish;
pos = 2;
b = test_string[--pos];
if (b !== "b") $stop;
if (pos !== 1) $stop;
pos = 1;
b = test_string[++pos];
if (b !== "c") $stop;
if (pos !== 2) $stop;
pos = 3;
b = test_string[pos--];
if (b !== "d") $stop;
if (pos !== 2) $stop;
pos = 0;
b = test_string[pos++];
if (b !== "a") $stop;
if (pos !== 1) $stop;
pos = 0;
val = array3d[++pos][--pos][++pos];
if (pos !== 1) $stop;
if (val !== 13) $stop;
pos = 0;
val = array3d[++pos][pos--][++pos];
if (pos !== 1) $stop;
if (val !== 17) $stop;
for (i=0; data[++i]<4;) begin
// loop with multiple statements
pos = i;
val = data[i];
end
if (pos !== 2) $stop;
if (i !== 3) $stop;
if (val !== 3) $stop;
i = 0;
while (data[i++]<4) begin
// loop with multiple statements
pos = i;
val = data[i];
end
if (pos !== 3) $stop;
if (i !== 4) $stop;
if (val !== 4) $stop;
pos = 0;
if (1 == 1) begin
pos++;
end
if (pos != 1) $stop;
pos = 0;
if (1 == 1) pos++;
if (pos != 1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule

60
test_regress/t/t_array_index_side.v
View File

@ -10,47 +10,47 @@
// verilog_format: on
class Cls;
int m_index;
int m_index;
function automatic int get_index();
int rtn;
rtn = m_index;
++m_index;
function automatic int get_index();
int rtn;
rtn = m_index;
++m_index;
`ifdef VERILATOR
return $c(rtn); // Avoid optimizations
return $c(rtn); // Avoid optimizations
`else
return rtn;
return rtn;
`endif
endfunction
endfunction
endclass
module t;
Cls cls;
int array[10];
Cls cls;
int array[10];
initial begin
cls = new;
// Common UVM construct 'id_cnt[get_id()]++;'
// Properly avoid/handle SIDEEFF warnings
cls.m_index = 5;
array[5] = 50;
array[6] = 60;
array[7] = 70;
array[8] = 80;
initial begin
cls = new;
// Common UVM construct 'id_cnt[get_id()]++;'
// Properly avoid/handle SIDEEFF warnings
cls.m_index = 5;
array[5] = 50;
array[6] = 60;
array[7] = 70;
array[8] = 80;
array[cls.get_index()]++;
`checkd(array[5], 51);
array[cls.get_index()]++;
`checkd(array[6], 61);
array[cls.get_index()]++;
`checkd(array[5], 51);
array[cls.get_index()]++;
`checkd(array[6], 61);
++array[cls.get_index()];
`checkd(array[7], 71);
++array[cls.get_index()];
`checkd(array[8], 81);
++array[cls.get_index()];
`checkd(array[7], 71);
++array[cls.get_index()];
`checkd(array[8], 81);
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

12
test_regress/t/t_array_list_bad.out
View File

@ -1,12 +1,12 @@
%Error: t/t_array_list_bad.v:38:25: Assignment pattern missed initializing elements: 'logic' 't3'
%Error: t/t_array_list_bad.v:37:21: Assignment pattern missed initializing elements: 'logic' 't3'
: ... note: In instance 't'
38 | test_out <= '{'0, '0};
| ^~
37 | test_out <= '{'0, '0};
| ^~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Warning-WIDTHEXPAND: t/t_array_list_bad.v:38:22: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits.
%Warning-WIDTHEXPAND: t/t_array_list_bad.v:37:18: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits.
: ... note: In instance 't'
38 | test_out <= '{'0, '0};
| ^~
37 | test_out <= '{'0, '0};
| ^~
... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest
... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message.
%Error: Exiting due to

53
test_regress/t/t_array_list_bad.v
View File

@ -5,38 +5,37 @@
// SPDX-License-Identifier: CC0-1.0
package pkg;
typedef struct packed {
logic t1;
logic t2;
logic t3;
} type_t;
typedef struct packed {
logic t1;
logic t2;
logic t3;
} type_t;
endpackage : pkg
module t
(
input logic sys_clk,
input logic sys_rst_n,
input logic sys_ena,
module t (
input logic sys_clk,
input logic sys_rst_n,
input logic sys_ena,
input pkg::type_t test_in,
output pkg::type_t test_out
);
input pkg::type_t test_in,
output pkg::type_t test_out
);
import pkg::*;
import pkg::*;
always_ff @(posedge sys_clk or negedge sys_rst_n) begin
if (~sys_rst_n) begin
test_out <= '{'0, '0, '0};
always_ff @(posedge sys_clk or negedge sys_rst_n) begin
if (~sys_rst_n) begin
test_out <= '{'0, '0, '0};
end
else begin
if (sys_ena) begin
test_out.t1 <= ~test_in.t1;
test_out.t2 <= ~test_in.t2;
test_out.t3 <= ~test_in.t3;
end
else begin
if(sys_ena) begin
test_out.t1 <= ~test_in.t1;
test_out.t2 <= ~test_in.t2;
test_out.t3 <= ~test_in.t3;
end
else begin
test_out <= '{'0, '0}; /* Inconsistent array list; */
end
test_out <= '{'0, '0}; /* Inconsistent array list; */
end
end
endmodule: t
end
end
endmodule : t

114
test_regress/t/t_array_mda.v
View File

@ -4,66 +4,66 @@
// SPDX-FileCopyrightText: 2019 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t ( /*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// msg2946
int A [7][1], B [8][1];
int a [1], b [1];
always_ff @(posedge clk) begin
a <= A[crc[2:0]];
b <= B[crc[2:0]];
end
wire [63:0] result = {a[0], b[0]};
// msg2946
int A[7][1], B[8][1];
int a[1], b[1];
always_ff @(posedge clk) begin
a <= A[crc[2:0]];
b <= B[crc[2:0]];
end
wire [63:0] result = {a[0], b[0]};
// Test loop
always @ (posedge clk) begin
// Test loop
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
A[0][0] <= 32'h1_0;
A[1][0] <= 32'h1_1;
A[2][0] <= 32'h1_2;
A[3][0] <= 32'h1_3;
A[4][0] <= 32'h1_4;
A[5][0] <= 32'h1_5;
A[6][0] <= 32'h1_6;
B[0][0] <= 32'h2_0;
B[1][0] <= 32'h2_1;
B[2][0] <= 32'h2_2;
B[3][0] <= 32'h2_3;
B[4][0] <= 32'h2_4;
B[5][0] <= 32'h2_5;
B[6][0] <= 32'h2_6;
B[7][0] <= 32'h2_7;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h619f75c3a6d948bd
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
A[0][0] <= 32'h1_0;
A[1][0] <= 32'h1_1;
A[2][0] <= 32'h1_2;
A[3][0] <= 32'h1_3;
A[4][0] <= 32'h1_4;
A[5][0] <= 32'h1_5;
A[6][0] <= 32'h1_6;
B[0][0] <= 32'h2_0;
B[1][0] <= 32'h2_1;
B[2][0] <= 32'h2_2;
B[3][0] <= 32'h2_3;
B[4][0] <= 32'h2_4;
B[5][0] <= 32'h2_5;
B[6][0] <= 32'h2_6;
B[7][0] <= 32'h2_7;
end
else if (cyc < 10) begin
sum <= '0;
end
else if (cyc < 90) begin
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h619f75c3a6d948bd
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule

6
test_regress/t/t_array_method_bad.out
View File

@ -1,6 +1,6 @@
%Error: t/t_array_method_bad.v:11:9: Unknown built-in array method 'mex'
%Error: t/t_array_method_bad.v:11:7: Unknown built-in array method 'mex'
: ... note: In instance 't'
11 | q.mex;
| ^~~
11 | q.mex;
| ^~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

12
test_regress/t/t_array_method_bad.v
View File

@ -5,12 +5,12 @@
// SPDX-License-Identifier: CC0-1.0
module t;
initial begin
int q[5];
initial begin
int q[5];
q.mex;
q.mex;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

12
test_regress/t/t_array_method_map.out
View File

@ -1,11 +1,11 @@
%Error-UNSUPPORTED: t/t_array_method_map.v:19:15: Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5)
%Error-UNSUPPORTED: t/t_array_method_map.v:19:13: Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5)
: ... note: In instance 't'
19 | res = a.map(el) with (el == 200);
| ^~~
19 | res = a.map(el) with (el == 200);
| ^~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: t/t_array_method_map.v:19:15: Unknown built-in array method 'map'
%Error: t/t_array_method_map.v:19:13: Unknown built-in array method 'map'
: ... note: In instance 't'
19 | res = a.map(el) with (el == 200);
| ^~~
19 | res = a.map(el) with (el == 200);
| ^~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

20
test_regress/t/t_array_method_map.v
View File

@ -11,15 +11,15 @@
module t;
initial begin
automatic int res[];
automatic int a[3] = '{100, 200, 300};
initial begin
automatic int res[];
automatic int a[3] = '{100, 200, 300};
// TODO results not known to be correct
res = a.map(el) with (el == 200);
`checkh(res.size, 3);
`checkh(res[0], 0);
`checkh(res[1], 1);
`checkh(res[2], 0);
end
// TODO results not known to be correct
res = a.map(el) with (el == 200);
`checkh(res.size, 3);
`checkh(res[0], 0);
`checkh(res[1], 1);
`checkh(res[2], 0);
end
endmodule

47
test_regress/t/t_array_non_blocking_loop.v
View File

@ -5,34 +5,31 @@
// SPDX-License-Identifier: CC0-1.0
interface intf
#(
parameter int WRITE_DATA_WIDTH) ();
logic [WRITE_DATA_WIDTH-1:0] writedata;
interface intf #(
parameter int WRITE_DATA_WIDTH
) ();
logic [WRITE_DATA_WIDTH-1:0] writedata;
endinterface
module t( /*AUTOARG*/
module t ( /*AUTOARG*/
clk
);
input clk;
generate
genvar num_chunks;
for (num_chunks = 1; num_chunks <= 2; num_chunks++) begin : gen_n
localparam int decoded_width = 55 * num_chunks;
intf #(
.WRITE_DATA_WIDTH(decoded_width))
the_intf ();
always @(posedge clk) begin
for (int i = 0; i < decoded_width; i++)
the_intf.writedata[i] <= '1;
$display("%0d", the_intf.writedata);
end
end
endgenerate
input clk;
generate
genvar num_chunks;
for (num_chunks = 1; num_chunks <= 2; num_chunks++) begin : gen_n
localparam int decoded_width = 55 * num_chunks;
intf #(.WRITE_DATA_WIDTH(decoded_width)) the_intf ();
always @(posedge clk) begin
for (int i = 0; i < decoded_width; i++) the_intf.writedata[i] <= '1;
$display("%0d", the_intf.writedata);
end
end
endgenerate
// finish report
always @ (posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
// finish report
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

134
test_regress/t/t_array_packed_endian.v
View File

@ -4,28 +4,28 @@
// SPDX-FileCopyrightText: 2020 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
// verilog_format: off
typedef struct packed {logic [7:0] a;} tb_t;
typedef struct packed {
logic [7:0] a;
} tb_t;
typedef struct packed {
// verilator lint_off ASCRANGE
logic [0:7] a;
// verilator lint_on ASCRANGE
// verilator lint_off ASCRANGE
logic [0:7] a;
// verilator lint_on ASCRANGE
} tl_t;
typedef struct packed {
logic [7:0] bb;
// verilator lint_off ASCRANGE
tb_t [0:1] cbl;
tb_t [1:0] cbb;
tl_t [0:1] cll;
tl_t [1:0] clb;
logic [0:7] dl;
// verilator lint_on ASCRANGE
logic [7:0] bb;
// verilator lint_off ASCRANGE
tb_t [0:1] cbl;
tb_t [1:0] cbb;
tl_t [0:1] cll;
tl_t [1:0] clb;
logic [0:7] dl;
// verilator lint_on ASCRANGE
} t2;
logic [2:0][31:0] test2l;
@ -36,60 +36,60 @@ logic [0:2][31:0] test1b;
logic [2:0][31:0] test1l;
module t;
t2 t;
initial begin
t = 80'hcd_1f2f3f4f_5f6f7f8f_c2;
`checkh(t.bb, 8'hcd);
`checkh(t.cbl[0].a, 8'h1f);
`checkh(t.cbl[1].a, 8'h2f);
`checkh(t.cbb[0].a, 8'h4f);
`checkh(t.cbb[1].a, 8'h3f);
`checkh(t.cll[0].a, 8'h5f);
`checkh(t.cll[1].a, 8'h6f);
`checkh(t.clb[0].a, 8'h8f);
`checkh(t.clb[1].a, 8'h7f);
`checkh(t.dl, 8'hc2);
t2 t;
initial begin
t = 80'hcd_1f2f3f4f_5f6f7f8f_c2;
`checkh(t.bb, 8'hcd);
`checkh(t.cbl[0].a, 8'h1f);
`checkh(t.cbl[1].a, 8'h2f);
`checkh(t.cbb[0].a, 8'h4f);
`checkh(t.cbb[1].a, 8'h3f);
`checkh(t.cll[0].a, 8'h5f);
`checkh(t.cll[1].a, 8'h6f);
`checkh(t.clb[0].a, 8'h8f);
`checkh(t.clb[1].a, 8'h7f);
`checkh(t.dl, 8'hc2);
t = '0;
t.bb = 8'h13;
t.cbl[0].a = 8'hac;
t.cbl[1].a = 8'had;
t.cbb[0].a = 8'hae;
t.cbb[1].a = 8'haf;
t.cll[0].a = 8'hbc;
t.cll[1].a = 8'hbd;
t.clb[0].a = 8'hbe;
t.clb[1].a = 8'hbf;
t.dl = 8'h31;
`checkh(t, 80'h13_acadafae_bcbdbfbe_31);
t = '0;
t.bb = 8'h13;
t.cbl[0].a = 8'hac;
t.cbl[1].a = 8'had;
t.cbb[0].a = 8'hae;
t.cbb[1].a = 8'haf;
t.cll[0].a = 8'hbc;
t.cll[1].a = 8'hbd;
t.clb[0].a = 8'hbe;
t.clb[1].a = 8'hbf;
t.dl = 8'h31;
`checkh(t, 80'h13_acadafae_bcbdbfbe_31);
t = '0;
t.bb[7] = 1'b1;
t.cbl[1].a[1] = 1'b1;
t.cbb[1].a[2] = 1'b1;
t.cll[1].a[3] = 1'b1;
t.clb[1].a[4] = 1'b1;
t.dl[7] = 1'b1;
`checkh(t, 80'h80_0002040000100800_01);
t = '0;
t.bb[7] = 1'b1;
t.cbl[1].a[1] = 1'b1;
t.cbb[1].a[2] = 1'b1;
t.cll[1].a[3] = 1'b1;
t.clb[1].a[4] = 1'b1;
t.dl[7] = 1'b1;
`checkh(t, 80'h80_0002040000100800_01);
test1b = '{0, 1, 2};
test1l = test1b;
test2l = '{2, 1, 0};
test2b = test2l;
`checkh(test2l[0], 0);
`checkh(test2l[2], 2);
`checkh(test2l, {32'h2, 32'h1, 32'h0});
`checkh(test2b[0], 2);
`checkh(test2b[2], 0);
`checkh(test2b, {32'h2, 32'h1, 32'h0});
`checkh(test1b[0], 0);
`checkh(test1b[2], 2);
`checkh(test1b, {32'h0, 32'h1, 32'h2});
`checkh(test1l[0], 2);
`checkh(test1l[2], 0);
`checkh(test1l, {32'h0, 32'h1, 32'h2});
test1b = '{0, 1, 2};
test1l = test1b;
test2l = '{2, 1, 0};
test2b = test2l;
`checkh(test2l[0], 0);
`checkh(test2l[2], 2);
`checkh(test2l, {32'h2, 32'h1, 32'h0});
`checkh(test2b[0], 2);
`checkh(test2b[2], 0);
`checkh(test2b, {32'h2, 32'h1, 32'h0});
`checkh(test1b[0], 0);
`checkh(test1b[2], 2);
`checkh(test1b, {32'h0, 32'h1, 32'h2});
`checkh(test1l[0], 2);
`checkh(test1l[2], 0);
`checkh(test1l, {32'h0, 32'h1, 32'h2});
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

82
test_regress/t/t_array_packed_sign.v
View File

@ -11,50 +11,50 @@
// unless they are of a named type declared as signed.
module t;
typedef logic signed [2:0] named_t;
typedef named_t [1:0] named_named_t;
typedef logic signed [1:0][2:0] named_unnamed_t;
typedef logic signed [2:0] named_t;
typedef named_t [1:0] named_named_t;
typedef logic signed [1:0][2:0] named_unnamed_t;
named_named_t [1:0] named_named;
named_unnamed_t [1:0] named_unnamed;
logic signed [1:0][1:0][2:0] unnamed;
named_named_t [1:0] named_named;
named_unnamed_t [1:0] named_unnamed;
logic signed [1:0][1:0][2:0] unnamed;
initial begin
// Set 1 to MSB(=sign bit)
named_named = 12'b100000_000000;
named_unnamed = 12'b100000_000000;
unnamed = 12'b100000_000000;
initial begin
// Set 1 to MSB(=sign bit)
named_named = 12'b100000_000000;
named_unnamed = 12'b100000_000000;
unnamed = 12'b100000_000000;
if ($signed((named_named >>> 1) >> 11) != 0) begin
$stop;
end
if ($signed((named_named[1] >>> 1) >> 5) != 0) begin
$stop;
end
if ($signed((named_named[1][1] >>> 1) >> 2) != 1) begin
$stop;
end
if ($signed((named_named >>> 1) >> 11) != 0) begin
$stop;
end
if ($signed((named_named[1] >>> 1) >> 5) != 0) begin
$stop;
end
if ($signed((named_named[1][1] >>> 1) >> 2) != 1) begin
$stop;
end
if ($signed((named_unnamed >>> 1) >> 11) != 0) begin
$stop;
end
if ($signed((named_unnamed[1] >>> 1) >> 5) != 1) begin
$stop;
end
if ($signed((named_unnamed[1][1] >>> 1) >> 2) != 0) begin
$stop;
end
if ($signed((named_unnamed >>> 1) >> 11) != 0) begin
$stop;
end
if ($signed((named_unnamed[1] >>> 1) >> 5) != 1) begin
$stop;
end
if ($signed((named_unnamed[1][1] >>> 1) >> 2) != 0) begin
$stop;
end
if ($signed((unnamed >>> 1) >> 11) != 1) begin
$stop;//
end
if ($signed((unnamed[1] >>> 1) >> 5) != 0) begin
$stop;
end
if ($signed((unnamed[1][1] >>> 1) >> 2) != 0) begin
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
if ($signed((unnamed >>> 1) >> 11) != 1) begin
$stop; //
end
if ($signed((unnamed[1] >>> 1) >> 5) != 0) begin
$stop;
end
if ($signed((unnamed[1][1] >>> 1) >> 2) != 0) begin
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

285
test_regress/t/t_array_packed_sysfunct.v
View File

@ -4,168 +4,167 @@
// SPDX-FileCopyrightText: 2009 Iztok Jeras
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
// parameters for array sizes
localparam WA = 4;
localparam WB = 6;
localparam WC = 8;
// parameters for array sizes
localparam WA = 4;
localparam WB = 6;
localparam WC = 8;
// 2D packed arrays
logic [WA+1:2] [WB+1:2] [WC+1:2] array_dsc; // descending range array
/* verilator lint_off ASCRANGE */
logic [2:WA+1] [2:WB+1] [2:WC+1] array_asc; // ascending range array
/* verilator lint_on ASCRANGE */
// 2D packed arrays
logic [WA+1:2] [WB+1:2] [WC+1:2] array_dsc; // descending range array
/* verilator lint_off ASCRANGE */
logic [2:WA+1] [2:WB+1] [2:WC+1] array_asc; // ascending range array
/* verilator lint_on ASCRANGE */
logic [1:0] array_unpk [3:2][1:0];
logic [1:0] array_unpk [3:2][1:0];
integer cnt = 0;
integer slc = 0; // slice type
integer dim = 0; // dimension
integer wdt = 0; // width
integer cnt = 0;
integer slc = 0; // slice type
integer dim = 0; // dimension
integer wdt = 0; // width
initial begin
`checkh($dimensions (array_unpk), 3);
initial begin
`checkh($dimensions (array_unpk), 3);
`ifndef VCS
`checkh($unpacked_dimensions (array_unpk), 2); // IEEE 2009
`checkh($unpacked_dimensions (array_unpk), 2); // IEEE 2009
`endif
`checkh($bits (array_unpk), 2*2*2);
`checkh($low (array_unpk), 2);
`checkh($high (array_unpk), 3);
`checkh($left (array_unpk), 3);
`checkh($right(array_unpk), 2);
`checkh($increment(array_unpk), 1);
`checkh($size (array_unpk), 2);
end
`checkh($bits (array_unpk), 2*2*2);
`checkh($low (array_unpk), 2);
`checkh($high (array_unpk), 3);
`checkh($left (array_unpk), 3);
`checkh($right(array_unpk), 2);
`checkh($increment(array_unpk), 1);
`checkh($size (array_unpk), 2);
end
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ( (cnt[30:4]==3) && (cnt[3:2]==2'd3) && (cnt[1:0]==2'd3) ) begin
$write("*-* All Finished *-*\n");
$finish;
end
// finish report
always @ (posedge clk)
if ( (cnt[30:4]==3) && (cnt[3:2]==2'd3) && (cnt[1:0]==2'd3) ) begin
$write("*-* All Finished *-*\n");
$finish;
end
integer slc_next;
integer slc_next;
// calculation of dimention sizes
always @ (posedge clk) begin
// slicing type counter
case (cnt[3:2])
2'd0 : begin slc_next = 0; end // full array
2'd1 : begin slc_next = 1; end // single array element
2'd2 : begin slc_next = 2; end // half array
default: begin slc_next = 0; end
endcase
slc <= slc_next;
// dimension counter
case (cnt[1:0])
2'd0 : begin dim <= 1; wdt <= (slc_next==1) ? WA/2 : (slc_next==2) ? WA/2 : WA; end
2'd1 : begin dim <= 2; wdt <= WB; end
2'd2 : begin dim <= 3; wdt <= WC; end
default: begin dim <= 0; wdt <= 0; end
endcase
end
// calculation of dimention sizes
always @ (posedge clk) begin
// slicing type counter
case (cnt[3:2])
2'd0 : begin slc_next = 0; end // full array
2'd1 : begin slc_next = 1; end // single array element
2'd2 : begin slc_next = 2; end // half array
default: begin slc_next = 0; end
endcase
slc <= slc_next;
// dimension counter
case (cnt[1:0])
2'd0 : begin dim <= 1; wdt <= (slc_next==1) ? WA/2 : (slc_next==2) ? WA/2 : WA; end
2'd1 : begin dim <= 2; wdt <= WB; end
2'd2 : begin dim <= 3; wdt <= WC; end
default: begin dim <= 0; wdt <= 0; end
endcase
end
always @ (posedge clk) begin
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("cnt[30:4]=%0d slc=%0d dim=%0d wdt=%0d\n", cnt[30:4], slc, dim, wdt);
$write("cnt[30:4]=%0d slc=%0d dim=%0d wdt=%0d\n", cnt[30:4], slc, dim, wdt);
`endif
if (cnt[30:4]==1) begin
// descending range
if (slc==0) begin
// full array
`checkh($dimensions (array_dsc), 3);
`checkh($bits (array_dsc), WA*WB*WC);
if ((dim>=1)&&(dim<=3)) begin
`checkh($left (array_dsc, dim), wdt+1);
`checkh($right (array_dsc, dim), 2 );
`checkh($low (array_dsc, dim), 2 );
`checkh($high (array_dsc, dim), wdt+1);
`checkh($increment (array_dsc, dim), 1 );
`checkh($size (array_dsc, dim), wdt );
end
end else if (slc==1) begin
// single array element
`checkh($dimensions (array_dsc[2]), 2);
`checkh($bits (array_dsc[2]), WB*WC);
if ((dim>=2)&&(dim<=3)) begin
`checkh($left (array_dsc[2], dim-1), wdt+1);
`checkh($right (array_dsc[2], dim-1), 2 );
`checkh($low (array_dsc[2], dim-1), 2 );
`checkh($high (array_dsc[2], dim-1), wdt+1);
`checkh($increment (array_dsc[2], dim-1), 1 );
`checkh($size (array_dsc[2], dim-1), wdt );
end
if (cnt[30:4]==1) begin
// descending range
if (slc==0) begin
// full array
`checkh($dimensions (array_dsc), 3);
`checkh($bits (array_dsc), WA*WB*WC);
if ((dim>=1)&&(dim<=3)) begin
`checkh($left (array_dsc, dim), wdt+1);
`checkh($right (array_dsc, dim), 2 );
`checkh($low (array_dsc, dim), 2 );
`checkh($high (array_dsc, dim), wdt+1);
`checkh($increment (array_dsc, dim), 1 );
`checkh($size (array_dsc, dim), wdt );
end
end else if (slc==1) begin
// single array element
`checkh($dimensions (array_dsc[2]), 2);
`checkh($bits (array_dsc[2]), WB*WC);
if ((dim>=2)&&(dim<=3)) begin
`checkh($left (array_dsc[2], dim-1), wdt+1);
`checkh($right (array_dsc[2], dim-1), 2 );
`checkh($low (array_dsc[2], dim-1), 2 );
`checkh($high (array_dsc[2], dim-1), wdt+1);
`checkh($increment (array_dsc[2], dim-1), 1 );
`checkh($size (array_dsc[2], dim-1), wdt );
end
`ifndef VERILATOR // Unsupported slices don't maintain size correctly
end else if (slc==2) begin
// half array
`checkh($dimensions (array_dsc[WA/2+1:2]), 3);
`checkh($bits (array_dsc[WA/2+1:2]), WA/2*WB*WC);
if ((dim>=1)&&(dim<=3)) begin
`checkh($left (array_dsc[WA/2+1:2], dim), wdt+1);
`checkh($right (array_dsc[WA/2+1:2], dim), 2 );
`checkh($low (array_dsc[WA/2+1:2], dim), 2 );
`checkh($high (array_dsc[WA/2+1:2], dim), wdt+1);
`checkh($increment (array_dsc[WA/2+1:2], dim), 1 );
`checkh($size (array_dsc[WA/2+1:2], dim), wdt);
end
end else if (slc==2) begin
// half array
`checkh($dimensions (array_dsc[WA/2+1:2]), 3);
`checkh($bits (array_dsc[WA/2+1:2]), WA/2*WB*WC);
if ((dim>=1)&&(dim<=3)) begin
`checkh($left (array_dsc[WA/2+1:2], dim), wdt+1);
`checkh($right (array_dsc[WA/2+1:2], dim), 2 );
`checkh($low (array_dsc[WA/2+1:2], dim), 2 );
`checkh($high (array_dsc[WA/2+1:2], dim), wdt+1);
`checkh($increment (array_dsc[WA/2+1:2], dim), 1 );
`checkh($size (array_dsc[WA/2+1:2], dim), wdt);
end
`endif
end
end else if (cnt[30:4]==2) begin
// ascending range
if (slc==0) begin
// full array
`checkh($dimensions (array_asc), 3);
`checkh($bits (array_asc), WA*WB*WC);
if ((dim>=1)&&(dim<=3)) begin
`checkh($left (array_asc, dim), 2 );
`checkh($right (array_asc, dim), wdt+1);
`checkh($low (array_asc, dim), 2 );
`checkh($high (array_asc, dim), wdt+1);
`checkh($increment (array_asc, dim), -1 );
`checkh($size (array_asc, dim), wdt );
end
end else if (slc==1) begin
// single array element
`checkh($dimensions (array_asc[2]), 2);
`checkh($bits (array_asc[2]), WB*WC);
if ((dim>=2)&&(dim<=3)) begin
`checkh($left (array_asc[2], dim-1), 2 );
`checkh($right (array_asc[2], dim-1), wdt+1);
`checkh($low (array_asc[2], dim-1), 2 );
`checkh($high (array_asc[2], dim-1), wdt+1);
`checkh($increment (array_asc[2], dim-1), -1 );
`checkh($size (array_asc[2], dim-1), wdt );
end
`ifndef VERILATOR // Unsupported slices don't maintain size correctly
end else if (slc==2) begin
// half array
`checkh($dimensions (array_asc[2:WA/2+1]), 3);
`checkh($bits (array_asc[2:WA/2+1]), WA/2*WB*WC);
if ((dim>=1)&&(dim<=3)) begin
`checkh($left (array_asc[2:WA/2+1], dim), 2 );
`checkh($right (array_asc[2:WA/2+1], dim), wdt+1);
`checkh($low (array_asc[2:WA/2+1], dim), 2 );
`checkh($high (array_asc[2:WA/2+1], dim), wdt+1);
`checkh($increment (array_asc[2:WA/2+1], dim), -1 );
`checkh($size (array_asc[2:WA/2+1], dim), wdt );
end
`endif
end
end
end
end else if (cnt[30:4]==2) begin
// ascending range
if (slc==0) begin
// full array
`checkh($dimensions (array_asc), 3);
`checkh($bits (array_asc), WA*WB*WC);
if ((dim>=1)&&(dim<=3)) begin
`checkh($left (array_asc, dim), 2 );
`checkh($right (array_asc, dim), wdt+1);
`checkh($low (array_asc, dim), 2 );
`checkh($high (array_asc, dim), wdt+1);
`checkh($increment (array_asc, dim), -1 );
`checkh($size (array_asc, dim), wdt );
end
end else if (slc==1) begin
// single array element
`checkh($dimensions (array_asc[2]), 2);
`checkh($bits (array_asc[2]), WB*WC);
if ((dim>=2)&&(dim<=3)) begin
`checkh($left (array_asc[2], dim-1), 2 );
`checkh($right (array_asc[2], dim-1), wdt+1);
`checkh($low (array_asc[2], dim-1), 2 );
`checkh($high (array_asc[2], dim-1), wdt+1);
`checkh($increment (array_asc[2], dim-1), -1 );
`checkh($size (array_asc[2], dim-1), wdt );
end
`ifndef VERILATOR // Unsupported slices don't maintain size correctly
end else if (slc==2) begin
// half array
`checkh($dimensions (array_asc[2:WA/2+1]), 3);
`checkh($bits (array_asc[2:WA/2+1]), WA/2*WB*WC);
if ((dim>=1)&&(dim<=3)) begin
`checkh($left (array_asc[2:WA/2+1], dim), 2 );
`checkh($right (array_asc[2:WA/2+1], dim), wdt+1);
`checkh($low (array_asc[2:WA/2+1], dim), 2 );
`checkh($high (array_asc[2:WA/2+1], dim), wdt+1);
`checkh($increment (array_asc[2:WA/2+1], dim), -1 );
`checkh($size (array_asc[2:WA/2+1], dim), wdt );
end
`endif
end
end
end
endmodule

256
test_regress/t/t_array_packed_write_read.v
View File

@ -4,145 +4,143 @@
// SPDX-FileCopyrightText: 2012 Iztok Jeras
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
// parameters for array sizes
localparam WA = 8; // address dimension size
localparam WB = 8; // bit dimension size
// parameters for array sizes
localparam WA = 8; // address dimension size
localparam WB = 8; // bit dimension size
localparam NO = 10; // number of access events
localparam NO = 10; // number of access events
// 2D packed arrays
logic [WA-1:0][WB-1:0] array_dsc; // descending range array
/* verilator lint_off ASCRANGE */
logic [0:WA-1][0:WB-1] array_asc; // ascending range array
/* verilator lint_on ASCRANGE */
// 2D packed arrays
logic [WA-1:0] [WB-1:0] array_dsc; // descending range array
/* verilator lint_off ASCRANGE */
logic [0:WA-1] [0:WB-1] array_asc; // ascending range array
/* verilator lint_on ASCRANGE */
integer cnt = 0;
integer cnt = 0;
// msg926
logic [3:0][31:0] packedArray;
initial packedArray = '0;
// msg926
logic [3:0][31:0] packedArray;
initial packedArray = '0;
// event counter
always @(posedge clk) begin
cnt <= cnt + 1;
end
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin
// finish report
always @(posedge clk)
if ((cnt[30:2] == NO) && (cnt[1:0] == 2'd0)) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
// descending range
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaaults (all bits to 0)
if (cnt[30:2]==0) array_dsc <= '0;
else if (cnt[30:2]==1) array_dsc <= '0;
else if (cnt[30:2]==2) array_dsc <= '0;
else if (cnt[30:2]==3) array_dsc <= '0;
else if (cnt[30:2]==4) array_dsc <= '0;
else if (cnt[30:2]==5) array_dsc <= '0;
else if (cnt[30:2]==6) array_dsc <= '0;
else if (cnt[30:2]==7) array_dsc <= '0;
else if (cnt[30:2]==8) array_dsc <= '0;
else if (cnt[30:2]==9) array_dsc <= '0;
end else if (cnt[1:0]==2'd1) begin
// write value to array
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) array_dsc <= {WA *WB +0{1'b1}};
else if (cnt[30:2]==2) array_dsc [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==3) array_dsc [WA -1:WA/2] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==4) array_dsc [ 0 ] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==5) array_dsc [WA -1 ] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==6) array_dsc [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==7) array_dsc [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==8) array_dsc [ 0 ][ 0 ] <= {1 *1 +0{1'b1}};
else if (cnt[30:2]==9) array_dsc [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}};
end else if (cnt[1:0]==2'd2) begin
// check array value
if (cnt[30:2]==0) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]==1) begin if (array_dsc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]==2) begin if (array_dsc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]==3) begin if (array_dsc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]==4) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]==5) begin if (array_dsc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]==6) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]==7) begin if (array_dsc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]==8) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]==9) begin if (array_dsc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
end else if (cnt[1:0]==2'd3) begin
// read value from array (not a very good test for now)
if (cnt[30:2]==0) begin if (array_dsc !== {WA *WB {1'b0}}) $stop(); end
else if (cnt[30:2]==1) begin if (array_dsc !== {WA *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (array_dsc [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (array_dsc [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (array_dsc [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (array_dsc [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==6) begin if (array_dsc [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==7) begin if (array_dsc [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==8) begin if (array_dsc [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end
else if (cnt[30:2]==9) begin if (array_dsc [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end
end
// descending range
// verilog_format: off
always @ (posedge clk)
if (cnt[1:0] == 2'd0) begin
// initialize to defaaults (all bits to 0)
if (cnt[30:2] == 0) array_dsc <= '0;
else if (cnt[30:2] == 1) array_dsc <= '0;
else if (cnt[30:2] == 2) array_dsc <= '0;
else if (cnt[30:2] == 3) array_dsc <= '0;
else if (cnt[30:2] == 4) array_dsc <= '0;
else if (cnt[30:2] == 5) array_dsc <= '0;
else if (cnt[30:2] == 6) array_dsc <= '0;
else if (cnt[30:2] == 7) array_dsc <= '0;
else if (cnt[30:2] == 8) array_dsc <= '0;
else if (cnt[30:2] == 9) array_dsc <= '0;
end else if (cnt[1:0] == 2'd1) begin
// write value to array
if (cnt[30:2] == 0) begin end
else if (cnt[30:2] == 1) array_dsc <= {WA *WB +0{1'b1}};
else if (cnt[30:2] == 2) array_dsc [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2] == 3) array_dsc [WA -1:WA/2] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2] == 4) array_dsc [ 0 ] <= {1 *WB +0{1'b1}};
else if (cnt[30:2] == 5) array_dsc [WA -1 ] <= {1 *WB +0{1'b1}};
else if (cnt[30:2] == 6) array_dsc [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2] == 7) array_dsc [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2] == 8) array_dsc [ 0 ][ 0 ] <= {1 *1 +0{1'b1}};
else if (cnt[30:2] == 9) array_dsc [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}};
end else if (cnt[1:0] == 2'd2) begin
// check array value
if (cnt[30:2] == 0) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2] == 1) begin if (array_dsc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2] == 2) begin if (array_dsc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2] == 3) begin if (array_dsc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2] == 4) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2] == 5) begin if (array_dsc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2] == 6) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2] == 7) begin if (array_dsc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2] == 8) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2] == 9) begin if (array_dsc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
end else if (cnt[1:0] == 2'd3) begin
// read value from array (not a very good test for now)
if (cnt[30:2] == 0) begin if (array_dsc !== {WA *WB {1'b0}}) $stop(); end
else if (cnt[30:2] == 1) begin if (array_dsc !== {WA *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2] == 2) begin if (array_dsc [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2] == 3) begin if (array_dsc [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2] == 4) begin if (array_dsc [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2] == 5) begin if (array_dsc [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2] == 6) begin if (array_dsc [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2] == 7) begin if (array_dsc [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2] == 8) begin if (array_dsc [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end
else if (cnt[30:2] == 9) begin if (array_dsc [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end
end
// ascending range
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaaults (all bits to 0)
if (cnt[30:2]==0) array_asc <= '0;
else if (cnt[30:2]==1) array_asc <= '0;
else if (cnt[30:2]==2) array_asc <= '0;
else if (cnt[30:2]==3) array_asc <= '0;
else if (cnt[30:2]==4) array_asc <= '0;
else if (cnt[30:2]==5) array_asc <= '0;
else if (cnt[30:2]==6) array_asc <= '0;
else if (cnt[30:2]==7) array_asc <= '0;
else if (cnt[30:2]==8) array_asc <= '0;
else if (cnt[30:2]==9) array_asc <= '0;
end else if (cnt[1:0]==2'd1) begin
// write value to array
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) array_asc <= {WA *WB +0{1'b1}};
else if (cnt[30:2]==2) array_asc [0 :WA/2-1] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==3) array_asc [WA/2:WA -1] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==4) array_asc [0 ] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==5) array_asc [ WA -1] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==6) array_asc [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==7) array_asc [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==8) array_asc [0 ][0 ] <= {1 *1 +0{1'b1}};
else if (cnt[30:2]==9) array_asc [ WA -1][ WB -1] <= {1 *1 +0{1'b1}};
end else if (cnt[1:0]==2'd2) begin
// check array value
if (cnt[30:2]==0) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==1) begin if (array_asc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==2) begin if (array_asc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==3) begin if (array_asc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==4) begin if (array_asc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==5) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==6) begin if (array_asc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==7) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==8) begin if (array_asc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==9) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_asc); $stop(); end end
end else if (cnt[1:0]==2'd3) begin
// read value from array (not a very good test for now)
if (cnt[30:2]==0) begin if (array_asc !== {WA *WB {1'b0}}) $stop(); end
else if (cnt[30:2]==1) begin if (array_asc !== {WA *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (array_asc [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (array_asc [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (array_asc [0 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (array_asc [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==6) begin if (array_asc [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==7) begin if (array_asc [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==8) begin if (array_asc [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end
else if (cnt[30:2]==9) begin if (array_asc [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end
end
// ascending range
always @ (posedge clk)
if (cnt[1:0] == 2'd0) begin
// initialize to defaaults (all bits to 0)
if (cnt[30:2] == 0) array_asc <= '0;
else if (cnt[30:2] == 1) array_asc <= '0;
else if (cnt[30:2] == 2) array_asc <= '0;
else if (cnt[30:2] == 3) array_asc <= '0;
else if (cnt[30:2] == 4) array_asc <= '0;
else if (cnt[30:2] == 5) array_asc <= '0;
else if (cnt[30:2] == 6) array_asc <= '0;
else if (cnt[30:2] == 7) array_asc <= '0;
else if (cnt[30:2] == 8) array_asc <= '0;
else if (cnt[30:2] == 9) array_asc <= '0;
end else if (cnt[1:0] == 2'd1) begin
// write value to array
if (cnt[30:2] == 0) begin end
else if (cnt[30:2] == 1) array_asc <= {WA *WB +0{1'b1}};
else if (cnt[30:2] == 2) array_asc [0 :WA/2-1] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2] == 3) array_asc [WA/2:WA -1] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2] == 4) array_asc [0 ] <= {1 *WB +0{1'b1}};
else if (cnt[30:2] == 5) array_asc [ WA -1] <= {1 *WB +0{1'b1}};
else if (cnt[30:2] == 6) array_asc [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2] == 7) array_asc [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2] == 8) array_asc [0 ][0 ] <= {1 *1 +0{1'b1}};
else if (cnt[30:2] == 9) array_asc [ WA -1][ WB -1] <= {1 *1 +0{1'b1}};
end else if (cnt[1:0] == 2'd2) begin
// check array value
if (cnt[30:2] == 0) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2] == 1) begin if (array_asc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2] == 2) begin if (array_asc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2] == 3) begin if (array_asc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2] == 4) begin if (array_asc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2] == 5) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2] == 6) begin if (array_asc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2] == 7) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2] == 8) begin if (array_asc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2] == 9) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_asc); $stop(); end end
end else if (cnt[1:0] == 2'd3) begin
// read value from array (not a very good test for now)
if (cnt[30:2] == 0) begin if (array_asc !== {WA *WB {1'b0}}) $stop(); end
else if (cnt[30:2] == 1) begin if (array_asc !== {WA *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2] == 2) begin if (array_asc [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2] == 3) begin if (array_asc [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2] == 4) begin if (array_asc [0 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2] == 5) begin if (array_asc [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2] == 6) begin if (array_asc [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2] == 7) begin if (array_asc [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2] == 8) begin if (array_asc [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end
else if (cnt[30:2] == 9) begin if (array_asc [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end
end
endmodule

58
test_regress/t/t_array_pattern_2d.v
View File

@ -7,41 +7,41 @@
//bug991
module t;
logic [31:0] array_assign [3:0];
logic [31:0] array_other [3:0];
logic [31:0] array_assign[3:0];
logic [31:0] array_other[3:0];
logic [31:0] larray_assign [0:3];
logic [31:0] larray_other [0:3];
logic [31:0] larray_assign[0:3];
logic [31:0] larray_other[0:3];
logic [31:0] array_neg [-1:1];
logic [31:0] array_neg[-1:1];
initial begin
array_assign[0] = 32'd1;
array_assign[3:1] = '{32'd4, 32'd3, 32'd2};
initial begin
array_assign[0] = 32'd1;
array_assign[3:1] = '{32'd4, 32'd3, 32'd2};
array_other[0] = array_assign[0]+10;
array_other[3:1] = array_assign[3:1];
if (array_other[0] != 11) $stop;
if (array_other[1] != 2) $stop;
if (array_other[2] != 3) $stop;
if (array_other[3] != 4) $stop;
array_other[0] = array_assign[0] + 10;
array_other[3:1] = array_assign[3:1];
if (array_other[0] != 11) $stop;
if (array_other[1] != 2) $stop;
if (array_other[2] != 3) $stop;
if (array_other[3] != 4) $stop;
larray_assign[0] = 32'd1;
larray_assign[1:3] = '{32'd4, 32'd3, 32'd2};
larray_assign[0] = 32'd1;
larray_assign[1:3] = '{32'd4, 32'd3, 32'd2};
larray_other[0] = larray_assign[0]+10;
larray_other[1:3] = larray_assign[1:3];
if (larray_other[0] != 11) $stop;
if (larray_other[1] != 4) $stop;
if (larray_other[2] != 3) $stop;
if (larray_other[3] != 2) $stop;
larray_other[0] = larray_assign[0] + 10;
larray_other[1:3] = larray_assign[1:3];
if (larray_other[0] != 11) $stop;
if (larray_other[1] != 4) $stop;
if (larray_other[2] != 3) $stop;
if (larray_other[3] != 2) $stop;
array_neg = '{-1: 5, 1: 7, default: 'd6};
if (array_neg[-1] != 5) $stop;
if (array_neg[0] != 6) $stop;
if (array_neg[1] != 7) $stop;
array_neg = '{-1: 5, 1: 7, default: 'd6};
if (array_neg[-1] != 5) $stop;
if (array_neg[0] != 6) $stop;
if (array_neg[1] != 7) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

6
test_regress/t/t_array_pattern_bad.out
View File

@ -1,6 +1,6 @@
%Error: t/t_array_pattern_bad.v:24:18: Assignment pattern key 'valids' not found as member
%Error: t/t_array_pattern_bad.v:21:39: Assignment pattern key 'valids' not found as member
: ... note: In instance 't'
24 | valids: '1};
| ^~~~~~
21 | always_comb myinfo = '{default: '0, valids: '1};
| ^~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

23
test_regress/t/t_array_pattern_bad.v
View File

@ -6,21 +6,18 @@
// bug1364
module t (/*AUTOARG*/
// Inputs
clk, res
);
input clk;
input res;
module t ( /*AUTOARG*/
// Inputs
clk,
res
);
input clk;
input res;
typedef struct packed {
logic [3:0] port_num;
} info_t;
typedef struct packed {logic [3:0] port_num;} info_t;
info_t myinfo;
info_t myinfo;
always_comb
myinfo = '{default: '0,
valids: '1};
always_comb myinfo = '{default: '0, valids: '1};
endmodule

6
test_regress/t/t_array_pattern_bad2.out
View File

@ -1,6 +1,6 @@
%Error: t/t_array_pattern_bad2.v:22:16: Multiple '{ default: } clauses
%Error: t/t_array_pattern_bad2.v:20:24: Multiple '{ default: } clauses
: ... note: In instance 't'
22 | myinfo = '{default: '0,
| ^~
20 | always_comb myinfo = '{default: '0, default: '1};
| ^~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

23
test_regress/t/t_array_pattern_bad2.v
View File

@ -6,20 +6,17 @@
// bug1364
module t (/*AUTOARG*/
// Inputs
clk, res
);
input clk;
input res;
module t ( /*AUTOARG*/
// Inputs
clk,
res
);
input clk;
input res;
typedef struct packed {
logic [3:0] port_num;
} info_t;
typedef struct packed {logic [3:0] port_num;} info_t;
info_t myinfo;
always_comb
myinfo = '{default: '0,
default: '1}; // Bad
info_t myinfo;
always_comb myinfo = '{default: '0, default: '1}; // Bad
endmodule

20
test_regress/t/t_array_pattern_bad3.out
View File

@ -1,14 +1,14 @@
%Error: t/t_array_pattern_bad3.v:20:15: Assignment pattern key used multiple times: 1
: ... note: In instance 't'
20 | 1: '1};
| ^
%Error: t/t_array_pattern_bad3.v:19:9: Assignment pattern key used multiple times: 1
: ... note: In instance 't'
19 | 1: '1
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_array_pattern_bad3.v:21:13: Assignment pattern with too many elements
%Error: t/t_array_pattern_bad3.v:21:11: Assignment pattern with too many elements
: ... note: In instance 't'
21 | arr = '{'0, '1, '0, '1};
| ^~
%Error: t/t_array_pattern_bad3.v:22:13: Assignment pattern missed initializing elements: 2
21 | arr = '{'0, '1, '0, '1};
| ^~
%Error: t/t_array_pattern_bad3.v:22:11: Assignment pattern missed initializing elements: 2
: ... note: In instance 't'
22 | arr = '{'0, '1};
| ^~
22 | arr = '{'0, '1};
| ^~
%Error: Exiting due to

28
test_regress/t/t_array_pattern_bad3.v
View File

@ -6,20 +6,20 @@
// bug1364
module t (/*AUTOARG*/
// Inputs
clk, res
);
input clk;
input res;
module t (
input clk,
input res
);
int arr[3];
initial begin
arr = '{default: '0,
1: '0,
1: '1}; // Bad
arr = '{'0, '1, '0, '1}; // Bad, too many
arr = '{'0, '1}; // Bad, too few
end
int arr[3];
initial begin
arr = '{
default: '0, //
1: '0, //
1: '1
}; // Bad
arr = '{'0, '1, '0, '1}; // Bad, too many
arr = '{'0, '1}; // Bad, too few
end
endmodule

32
test_regress/t/t_array_pattern_enum.v
View File

@ -5,28 +5,24 @@
// SPDX-License-Identifier: CC0-1.0
package Pkg;
typedef enum {
RED=0,
GREEN=1,
BLUE=2
} color_t;
typedef enum {
RED = 0,
GREEN = 1,
BLUE = 2
} color_t;
typedef struct {
color_t pixels[32];
} line_t;
typedef struct {color_t pixels[32];} line_t;
typedef struct {
line_t line[32];
} screen_t;
typedef struct {line_t line[32];} screen_t;
endpackage
module t;
Pkg::screen_t screen;
Pkg::screen_t screen;
initial begin
screen = '{ default: '0, Pkg::color_t: Pkg::RED};
$display("%p", screen);
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
screen = '{default: '0, Pkg::color_t: Pkg::RED};
$display("%p", screen);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

246
test_regress/t/t_array_pattern_packed.v
View File

@ -4,150 +4,148 @@
// SPDX-FileCopyrightText: 2009 Iztok Jeras
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
logic [1:0][3:0][3:0] array_simp; // descending range array
logic [1:0] [3:0] [3:0] array_simp; // descending range array
logic [3:0] array_oned;
logic [3:0] array_oned;
// verilog_format: off
initial begin
array_oned = '{2:1'b1, 0:1'b1, default:1'b0};
if (array_oned != 4'b0101) $stop;
initial begin
array_oned = '{2:1'b1, 0:1'b1, default:1'b0};
if (array_oned != 4'b0101) $stop;
array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
if (array_simp[0] !== 16'h3210) $stop;
array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
if (array_simp[0] !== 16'h3210) $stop;
// verilator lint_off WIDTH
array_simp[0] = '{ 3 ,2 ,1, 0 };
// verilator lint_on WIDTH
if (array_simp[0] !== 16'h3210) $stop;
// verilator lint_off WIDTH
array_simp[0] = '{ 3 ,2 ,1, 0 };
// verilator lint_on WIDTH
if (array_simp[0] !== 16'h3210) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
//if (array_simp[0] !== 16'h3210) $stop;
//array_simp[0] = '{ 1:4'd3, default:13};
//if (array_simp[0] !== 16'hDD3D) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
//if (array_simp[0] !== 16'h3210) $stop;
//array_simp[0] = '{ 1:4'd3, default:13};
//if (array_simp[0] !== 16'hDD3D) $stop;
array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
if (array_simp !== 32'h3210_1234) $stop;
array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
if (array_simp !== 32'h3210_1234) $stop;
// IEEE says '{} allowed only on assignments, not !=, ==.
// IEEE says '{} allowed only on assignments, not !=, ==.
// Doesn't seem to work for unpacked arrays in other simulators
array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }};
if (array_simp !== 32'h3210_3210) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }};
if (array_simp !== 32'h3210_3210) $stop;
array_simp = '{2{ '{4{ 4'd3 }} }};
if (array_simp !== 32'h3333_3333) $stop;
array_simp = '{2{ '{4{ 4'd3 }} }};
if (array_simp !== 32'h3333_3333) $stop;
// Not legal in other simulators - replication doesn't match
// However IEEE suggests this is legal.
//array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2}
// Not legal in other simulators - replication doesn't match
// However IEEE suggests this is legal.
//array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2}
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
//====================
//====================
// parameters for array sizes
localparam WA = 4; // address dimension size
localparam WB = 4; // bit dimension size
// parameters for array sizes
localparam WA = 4; // address dimension size
localparam WB = 4; // bit dimension size
localparam NO = 11; // number of access events
localparam NO = 11; // number of access events
// 2D packed arrays
logic [WA-1:0] [WB-1:0] array_dsc; // descending range array
/* verilator lint_off ASCRANGE */
logic [0:WA-1] [0:WB-1] array_asc; // ascending range array
/* verilator lint_on ASCRANGE */
// 2D packed arrays
logic [WA-1:0] [WB-1:0] array_dsc; // descending range array
/* verilator lint_off ASCRANGE */
logic [0:WA-1] [0:WB-1] array_asc; // ascending range array
/* verilator lint_on ASCRANGE */
integer cnt = 0;
integer cnt = 0;
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// descending range
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'b0)
if (cnt[30:2]== 0) array_dsc <= '0;
else if (cnt[30:2]== 1) array_dsc <= '0;
else if (cnt[30:2]== 2) array_dsc <= '0;
else if (cnt[30:2]== 3) array_dsc <= '0;
else if (cnt[30:2]== 4) array_dsc <= '0;
else if (cnt[30:2]== 5) array_dsc <= '0;
else if (cnt[30:2]== 6) array_dsc <= '0;
else if (cnt[30:2]== 7) array_dsc <= '0;
else if (cnt[30:2]== 8) array_dsc <= '0;
else if (cnt[30:2]== 9) array_dsc <= '0;
else if (cnt[30:2]==10) array_dsc <= '0;
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]== 0) begin end
else if (cnt[30:2]== 1) array_dsc <= '{ 3 ,2 ,1, 0 };
else if (cnt[30:2]== 2) array_dsc <= '{default:13};
else if (cnt[30:2]== 3) array_dsc <= '{0:4, 1:5, 2:6, 3:7};
else if (cnt[30:2]== 4) array_dsc <= '{2:15, default:13};
else if (cnt[30:2]== 5) array_dsc <= '{WA { {WB/2 {2'b10}} }};
else if (cnt[30:2]== 6) array_dsc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]== 0) begin if (array_dsc !== 16'b0000000000000000) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]== 1) begin if (array_dsc !== 16'b0011001000010000) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]== 2) begin if (array_dsc !== 16'b1101110111011101) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]== 3) begin if (array_dsc !== 16'b0111011001010100) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]== 4) begin if (array_dsc !== 16'b1101111111011101) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]== 5) begin if (array_dsc !== 16'b1010101010101010) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]== 6) begin if (array_dsc !== 16'b1001101010111100) begin $display("%b", array_dsc); $stop(); end end
end
// descending range
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'b0)
if (cnt[30:2]== 0) array_dsc <= '0;
else if (cnt[30:2]== 1) array_dsc <= '0;
else if (cnt[30:2]== 2) array_dsc <= '0;
else if (cnt[30:2]== 3) array_dsc <= '0;
else if (cnt[30:2]== 4) array_dsc <= '0;
else if (cnt[30:2]== 5) array_dsc <= '0;
else if (cnt[30:2]== 6) array_dsc <= '0;
else if (cnt[30:2]== 7) array_dsc <= '0;
else if (cnt[30:2]== 8) array_dsc <= '0;
else if (cnt[30:2]== 9) array_dsc <= '0;
else if (cnt[30:2]==10) array_dsc <= '0;
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]== 0) begin end
else if (cnt[30:2]== 1) array_dsc <= '{ 3 ,2 ,1, 0 };
else if (cnt[30:2]== 2) array_dsc <= '{default:13};
else if (cnt[30:2]== 3) array_dsc <= '{0:4, 1:5, 2:6, 3:7};
else if (cnt[30:2]== 4) array_dsc <= '{2:15, default:13};
else if (cnt[30:2]== 5) array_dsc <= '{WA { {WB/2 {2'b10}} }};
else if (cnt[30:2]== 6) array_dsc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]== 0) begin if (array_dsc !== 16'b0000000000000000) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]== 1) begin if (array_dsc !== 16'b0011001000010000) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]== 2) begin if (array_dsc !== 16'b1101110111011101) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]== 3) begin if (array_dsc !== 16'b0111011001010100) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]== 4) begin if (array_dsc !== 16'b1101111111011101) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]== 5) begin if (array_dsc !== 16'b1010101010101010) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]== 6) begin if (array_dsc !== 16'b1001101010111100) begin $display("%b", array_dsc); $stop(); end end
end
// ascending range
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'b0)
if (cnt[30:2]== 0) array_asc <= '0;
else if (cnt[30:2]== 1) array_asc <= '0;
else if (cnt[30:2]== 2) array_asc <= '0;
else if (cnt[30:2]== 3) array_asc <= '0;
else if (cnt[30:2]== 4) array_asc <= '0;
else if (cnt[30:2]== 5) array_asc <= '0;
else if (cnt[30:2]== 6) array_asc <= '0;
else if (cnt[30:2]== 7) array_asc <= '0;
else if (cnt[30:2]== 8) array_asc <= '0;
else if (cnt[30:2]== 9) array_asc <= '0;
else if (cnt[30:2]==10) array_asc <= '0;
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]== 0) begin end
else if (cnt[30:2]== 1) array_asc <= '{ 3 ,2 ,1, 0 };
else if (cnt[30:2]== 2) array_asc <= '{default:13};
else if (cnt[30:2]== 3) array_asc <= '{3:4, 2:5, 1:6, 0:7};
else if (cnt[30:2]== 4) array_asc <= '{1:15, default:13};
else if (cnt[30:2]== 5) array_asc <= '{WA { {WB/2 {2'b10}} }};
else if (cnt[30:2]==10) array_asc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]== 0) begin if (array_asc !== 16'b0000000000000000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]== 1) begin if (array_asc !== 16'b0011001000010000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]== 2) begin if (array_asc !== 16'b1101110111011101) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]== 3) begin if (array_asc !== 16'b0111011001010100) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]== 4) begin if (array_asc !== 16'b1101111111011101) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]== 5) begin if (array_asc !== 16'b1010101010101010) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==10) begin if (array_asc !== 16'b1001101010111100) begin $display("%b", array_asc); $stop(); end end
end
// ascending range
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'b0)
if (cnt[30:2]== 0) array_asc <= '0;
else if (cnt[30:2]== 1) array_asc <= '0;
else if (cnt[30:2]== 2) array_asc <= '0;
else if (cnt[30:2]== 3) array_asc <= '0;
else if (cnt[30:2]== 4) array_asc <= '0;
else if (cnt[30:2]== 5) array_asc <= '0;
else if (cnt[30:2]== 6) array_asc <= '0;
else if (cnt[30:2]== 7) array_asc <= '0;
else if (cnt[30:2]== 8) array_asc <= '0;
else if (cnt[30:2]== 9) array_asc <= '0;
else if (cnt[30:2]==10) array_asc <= '0;
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]== 0) begin end
else if (cnt[30:2]== 1) array_asc <= '{ 3 ,2 ,1, 0 };
else if (cnt[30:2]== 2) array_asc <= '{default:13};
else if (cnt[30:2]== 3) array_asc <= '{3:4, 2:5, 1:6, 0:7};
else if (cnt[30:2]== 4) array_asc <= '{1:15, default:13};
else if (cnt[30:2]== 5) array_asc <= '{WA { {WB/2 {2'b10}} }};
else if (cnt[30:2]==10) array_asc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]== 0) begin if (array_asc !== 16'b0000000000000000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]== 1) begin if (array_asc !== 16'b0011001000010000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]== 2) begin if (array_asc !== 16'b1101110111011101) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]== 3) begin if (array_asc !== 16'b0111011001010100) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]== 4) begin if (array_asc !== 16'b1101111111011101) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]== 5) begin if (array_asc !== 16'b1010101010101010) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==10) begin if (array_asc !== 16'b1001101010111100) begin $display("%b", array_asc); $stop(); end end
end
endmodule

84
test_regress/t/t_array_pattern_unpacked.v
View File

@ -6,58 +6,58 @@
module t;
logic [3:0] array_simp [1:0] [3:0]; // descending range array
wire [2:0] array_wire [1:0] = '{3'd1, 3'd2};
logic [3:0] array_simp [1:0] [3:0]; // descending range array
wire [2:0] array_wire [1:0] = '{3'd1, 3'd2};
int irep[1:2][1:6];
int irep[1:2][1:6];
initial begin
if (array_wire[0] !== 3'd2) $stop;
if (array_wire[1] !== 3'd1) $stop;
initial begin
if (array_wire[0] !== 3'd2) $stop;
if (array_wire[1] !== 3'd1) $stop;
array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 16'h3210) $stop;
array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 16'h3210) $stop;
// verilator lint_off WIDTH
array_simp[0] = '{ 3 ,2 ,1, 0 };
// verilator lint_on WIDTH
if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 16'h3210) $stop;
// verilator lint_off WIDTH
array_simp[0] = '{ 3 ,2 ,1, 0 };
// verilator lint_on WIDTH
if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 16'h3210) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
//array_simp[0] = '{ 1:4'd3, default:13 };
//if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'hDD3D) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
//array_simp[0] = '{ 1:4'd3, default:13 };
//if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'hDD3D) $stop;
array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 32'h3210_1234) $stop;
array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 32'h3210_1234) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }};
if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 32'h3210_3210) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }};
if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 32'h3210_3210) $stop;
array_simp = '{2{ '{4{ 4'd3 }} }};
if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 32'h3333_3333) $stop;
array_simp = '{2{ '{4{ 4'd3 }} }};
if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 32'h3333_3333) $stop;
// Not legal in other simulators - replication doesn't match
// However IEEE suggests this is legal.
//array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2}
// Not legal in other simulators - replication doesn't match
// However IEEE suggests this is legal.
//array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2}
// Replication
irep = '{2{ '{3 {4, 5}}}};
if ({irep[1][1], irep[1][2], irep[1][3], irep[1][4], irep[1][5], irep[1][6]}
!= {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop;
if ({irep[2][1], irep[2][2], irep[2][3], irep[2][4], irep[2][5], irep[2][6]}
!= {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop;
// Replication
irep = '{2{ '{3 {4, 5}}}};
if ({irep[1][1], irep[1][2], irep[1][3], irep[1][4], irep[1][5], irep[1][6]}
!= {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop;
if ({irep[2][1], irep[2][2], irep[2][3], irep[2][4], irep[2][5], irep[2][6]}
!= {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

74
test_regress/t/t_array_query.v
View File

@ -7,60 +7,56 @@
// SPDX-FileCopyrightText: 2012 Jeremy Bennett, Embecosm
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
input clk
);
wire a = clk;
wire b = 1'b0;
reg c;
wire a = clk;
wire b = 1'b0;
reg c;
array_test array_test_i (/*AUTOINST*/
// Inputs
.clk (clk));
array_test array_test_i ( /*AUTOINST*/
// Inputs
.clk(clk)
);
endmodule
// Check the array sizing functions work correctly.
module array_test
module array_test #(
parameter LEFT = 5,
RIGHT = 55
) ( /*AUTOARG*/
// Inputs
clk
);
#( parameter
LEFT = 5,
RIGHT = 55)
input clk;
(/*AUTOARG*/
// Inputs
clk
);
// verilator lint_off ASCRANGE
reg [7:0] a[LEFT:RIGHT];
// verilator lint_on ASCRANGE
input clk;
typedef reg [7:0] r_t;
// verilator lint_off ASCRANGE
reg [7:0] a [LEFT:RIGHT];
// verilator lint_on ASCRANGE
integer l;
integer r;
integer s;
typedef reg [7:0] r_t;
integer l;
integer r;
integer s;
always @(posedge clk) begin
l = $left (a);
r = $right (a);
s = $size (a);
always @(posedge clk) begin
l = $left(a);
r = $right(a);
s = $size(a);
`ifdef TEST_VERBOSE
$write ("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s);
$write("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s);
`endif
if ((l != LEFT) || (r != RIGHT) || (s != (RIGHT - LEFT + 1))) $stop;
if ($left(r_t)!=7 || $right(r_t)!=0 || $size(r_t)!=8 || $bits(r_t) !=8) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
if ((l != LEFT) || (r != RIGHT) || (s != (RIGHT - LEFT + 1))) $stop;
if ($left(r_t) != 7 || $right(r_t) != 0 || $size(r_t) != 8 || $bits(r_t) != 8) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

110
test_regress/t/t_array_query_with.v
View File

@ -5,70 +5,70 @@
// SPDX-License-Identifier: CC0-1.0
class Cls;
static function bit get_true();
return 1'b1;
endfunction
static function bit get_true();
return 1'b1;
endfunction
static function bit test_find_index_in_class();
if (get_true) begin
int q[$] = {0, -1, 3, 1, 4, 1};
int found_idx[$];
found_idx = q.find_index(node) with (node == 1);
return found_idx[0] == 3;
end
return 0;
endfunction
static function bit test_find_index_in_class();
if (get_true) begin
int q[$] = {0, -1, 3, 1, 4, 1};
int found_idx[$];
found_idx = q.find_index(node) with (node == 1);
return found_idx[0] == 3;
end
return 0;
endfunction
endclass
module t (/*AUTOARG*/
);
module t ( /*AUTOARG*/
);
function bit test_find;
string bar[$];
string found[$];
bar.push_back("baz");
bar.push_back("qux");
found = bar.find(x) with (x == "baz");
return found.size() == 1;
endfunction
function bit test_find;
string bar[$];
string found[$];
bar.push_back("baz");
bar.push_back("qux");
found = bar.find(x) with (x == "baz");
return found.size() == 1;
endfunction
function static bit test_find_index;
int q[$] = {1, 2, 3, 4};
int found[$] = q.find_index(x) with (x <= 2);
return found.size() == 2;
endfunction
function static bit test_find_index;
int q[$] = {1, 2, 3, 4};
int found[$] = q.find_index(x) with (x <= 2);
return found.size() == 2;
endfunction
function static bit test_find_first_index;
int q[] = {1, 2, 3, 4, 5, 6};
int first_even_idx[$] = q.find_first_index(x) with (x % 2 == 0);
return first_even_idx[0] == 1;
endfunction
function static bit test_find_first_index;
int q[] = {1, 2, 3, 4, 5, 6};
int first_even_idx[$] = q.find_first_index(x) with (x % 2 == 0);
return first_even_idx[0] == 1;
endfunction
function bit is_even(int a);
return a % 2 == 0;
endfunction
function bit is_even(int a);
return a % 2 == 0;
endfunction
function static bit test_find_first_index_by_func;
int q[] = {1, 2, 3, 4, 5, 6};
int first_even_idx[$] = q.find_first_index(x) with (is_even(x));
return first_even_idx[0] == 1;
endfunction
function static bit test_find_first_index_by_func;
int q[] = {1, 2, 3, 4, 5, 6};
int first_even_idx[$] = q.find_first_index(x) with (is_even(x));
return first_even_idx[0] == 1;
endfunction
function automatic bit test_sort;
int q[] = {-5, 2, -3, 0, 4};
q.sort(x) with (x >= 0 ? x : -x);
return q[1] == 2;
endfunction
function automatic bit test_sort;
int q[] = {-5, 2, -3, 0, 4};
q.sort(x) with (x >= 0 ? x : -x);
return q[1] == 2;
endfunction
initial begin
if (!test_find()) $stop;
if (!test_find_index()) $stop;
if (!test_find_first_index()) $stop;
if (!test_find_first_index_by_func()) $stop;
if (!test_sort()) $stop;
if (!Cls::test_find_index_in_class()) $stop;
initial begin
if (!test_find()) $stop;
if (!test_find_index()) $stop;
if (!test_find_first_index()) $stop;
if (!test_find_first_index_by_func()) $stop;
if (!test_sort()) $stop;
if (!Cls::test_find_index_in_class()) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

76
test_regress/t/t_array_rev.v
View File

@ -4,58 +4,54 @@
// SPDX-FileCopyrightText: 2016 Geoff Barrett
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
integer cyc = 0;
// verilator lint_off ASCRANGE
logic arrd[0:1] = '{1'b1, 1'b0};
// verilator lint_on ASCRANGE
logic y0, y1;
logic localbkw[1:0];
integer cyc = 0;
// verilator lint_off ASCRANGE
logic arrd [0:1] = '{ 1'b1, 1'b0 };
// verilator lint_on ASCRANGE
logic y0, y1;
logic localbkw [1:0];
arr_rev arr_rev_u (
.arrbkw(arrd),
.y0(y0),
.y1(y1)
);
arr_rev arr_rev_u (
.arrbkw (arrd),
.y0(y0),
.y1(y1)
);
always @(posedge clk) begin
if (arrd[0] != 1'b1) $stop;
if (arrd[1] != 1'b0) $stop;
always @ (posedge clk) begin
if (arrd[0] != 1'b1) $stop;
if (arrd[1] != 1'b0) $stop;
localbkw = arrd;
localbkw = arrd;
`ifdef TEST_VERBOSE
$write("localbkw[0]=%b\n", localbkw[0]);
$write("localbkw[1]=%b\n", localbkw[1]);
$write("localbkw[0]=%b\n", localbkw[0]);
$write("localbkw[1]=%b\n", localbkw[1]);
`endif
if (localbkw[0] != 1'b0) $stop;
if (localbkw[1] != 1'b1) $stop;
if (localbkw[0] != 1'b0) $stop;
if (localbkw[1] != 1'b1) $stop;
`ifdef TEST_VERBOSE
$write("y0=%b\n", y0);
$write("y1=%b\n", y1);
$write("y0=%b\n", y0);
$write("y1=%b\n", y1);
`endif
if (y0 != 1'b0) $stop;
if (y1 != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
if (y0 != 1'b0) $stop;
if (y1 != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module arr_rev
(
input var logic arrbkw [1:0],
output var logic y0,
output var logic y1
);
module arr_rev (
input var logic arrbkw[1:0],
output var logic y0,
output var logic y1
);
always_comb y0 = arrbkw[0];
always_comb y1 = arrbkw[1];
always_comb y0 = arrbkw[0];
always_comb y1 = arrbkw[1];
endmodule

34
test_regress/t/t_array_sel_wide.v
View File

@ -5,26 +5,26 @@
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
nnext,
// Inputs
inibble, onibble
);
// Outputs
nnext,
// Inputs
inibble, onibble
);
input [3:0] inibble;
input [106:0] onibble;
input [3:0] inibble;
input [106:0] onibble;
output reg [3:0] nnext [0:7];
output reg [3:0] nnext [0:7];
// verilator lint_off WIDTH
wire [2:0] selline = (onibble >>> 102) & 7;
// verilator lint_on WIDTH
// verilator lint_off WIDTH
wire [2:0] selline = (onibble >>> 102) & 7;
// verilator lint_on WIDTH
always_comb begin
for (integer i=0; i<8; i=i+1) begin
nnext[i] = '0;
end
nnext[selline] = inibble;
end
always_comb begin
for (integer i=0; i<8; i=i+1) begin
nnext[i] = '0;
end
nnext[selline] = inibble;
end
endmodule

34
test_regress/t/t_array_type_methods.v
View File

@ -4,30 +4,32 @@
// SPDX-FileCopyrightText: 2014 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t;
logic [3:0] foo [1:0];
logic [3:0] fooe [1:0];
initial begin
foo[0] = 4'b0101;
foo[1] = 4'b0011;
logic [3:0] foo[1:0];
logic [3:0] fooe[1:0];
initial begin
foo[0] = 4'b0101;
foo[1] = 4'b0011;
`checkh(foo.or, 4'b0111);
`checkh(foo.and, 4'b0001);
`checkh(foo.xor, 4'b0110);
`checkh(foo.sum, 4'b1000);
`checkh(foo.product, 4'b1111);
`checkh(foo.or, 4'b0111);
`checkh(foo.and, 4'b0001);
`checkh(foo.xor, 4'b0110);
`checkh(foo.sum, 4'b1000);
`checkh(foo.product, 4'b1111);
fooe[0] = 4'b0101;
fooe[1] = 4'b0011;
if (foo != fooe) $stop;
fooe[0] = 4'b0101;
fooe[1] = 4'b0011;
if (foo != fooe) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

10
test_regress/t/t_array_unpacked_public.v
View File

@ -4,10 +4,10 @@
// SPDX-FileCopyrightText: 2020 Stefan Wallentowitz
// SPDX-License-Identifier: CC0-1.0
module t();
logic din [0:15];
module t;
logic din[0:15];
array_test array_test_inst(.din(din));
array_test array_test_inst (.din(din));
initial begin
$write("*-* All Finished *-*\n");
@ -15,7 +15,7 @@ module t();
end
endmodule
module array_test(
input din [0:15]
module array_test (
input din[0:15]
);
endmodule

24
test_regress/t/t_assert_always_unsup.out
View File

@ -1,16 +1,16 @@
%Error-UNSUPPORTED: t/t_assert_always_unsup.v:21:7: Unsupported: always[] (in property expression)
21 | always [2:5] a;
| ^~~~~~
%Error-UNSUPPORTED: t/t_assert_always_unsup.v:20:5: Unsupported: always[] (in property expression)
20 | always [2:5] a;
| ^~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_assert_always_unsup.v:25:7: Unsupported: s_always (in property expression)
25 | s_always [2:5] a;
| ^~~~~~~~
%Error-UNSUPPORTED: t/t_assert_always_unsup.v:29:7: Unsupported: eventually[] (in property expression)
29 | eventually [2:5] a;
| ^~~~~~~~~~
%Error: t/t_assert_always_unsup.v:33:20: syntax error, unexpected ']', expecting ':'
33 | eventually [2] a;
| ^
%Error-UNSUPPORTED: t/t_assert_always_unsup.v:24:5: Unsupported: s_always (in property expression)
24 | s_always [2:5] a;
| ^~~~~~~~
%Error-UNSUPPORTED: t/t_assert_always_unsup.v:28:5: Unsupported: eventually[] (in property expression)
28 | eventually [2:5] a;
| ^~~~~~~~~~
%Error: t/t_assert_always_unsup.v:32:18: syntax error, unexpected ']', expecting ':'
32 | eventually [2] a;
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Cannot continue
... This fatal error may be caused by the earlier error(s); resolve those first.

61
test_regress/t/t_assert_always_unsup.v
View File

@ -4,45 +4,44 @@
// SPDX-FileCopyrightText: 2022-2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
clk
);
module t (
input clk
);
input clk;
int cyc = 0;
logic val = 0;
int cyc = 0;
logic val = 0;
always @(posedge clk) begin
cyc <= cyc + 1;
val = ~val;
end
always @(posedge clk) begin
cyc <= cyc + 1;
val = ~val;
end
property p_alw;
always [2:5] a;
endproperty
property p_alw;
always [2:5] a;
endproperty
property p_s_alw;
s_always [2:5] a;
endproperty
property p_s_alw;
s_always [2:5] a;
endproperty
property p_ev;
eventually [2:5] a;
endproperty
property p_ev;
eventually [2:5] a;
endproperty
property p_evc;
eventually [2] a;
endproperty
property p_evc;
eventually [2] a;
endproperty
property p_s_ev;
s_eventually [2:5] a;
endproperty
property p_s_ev;
s_eventually [2:5] a;
endproperty
property p_s_alw_ev;
always s_eventually [2:5] a;
endproperty
property p_s_alw_ev;
always s_eventually [2:5] a;
endproperty
property p_s_ev_alw;
s_eventually always [2:5] a;
endproperty
property p_s_ev_alw;
s_eventually always [2:5] a;
endproperty
endmodule

88
test_regress/t/t_assert_basic.v
View File

@ -4,50 +4,62 @@
// SPDX-FileCopyrightText: 2007 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
reg toggle;
reg toggle;
integer cyc;
initial cyc = 1;
wire [7:0] cyc_copy = cyc[7:0];
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
always @(negedge clk) begin
AssertionFalse1 : assert (cyc < 100);
assert (!(cyc == 5) || toggle);
// FIX cover {cyc==3 || cyc==4};
// FIX cover {cyc==9} report "DefaultClock,expect=1";
// FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1";
end
always @ (negedge clk) begin
AssertionFalse1: assert (cyc<100);
assert (!(cyc==5) || toggle);
// FIX cover {cyc==3 || cyc==4};
// FIX cover {cyc==9} report "DefaultClock,expect=1";
// FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1";
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==7) assert (cyc[0] == cyc[1]); // bug743
if (cyc==9) begin
always @(posedge clk) begin
if (cyc != 0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc == 7) assert (cyc[0] == cyc[1]); // bug743
if (cyc == 9) begin
`ifdef FAILING_ASSERTIONS
assert (0) else $info;
assert (0) else $info("Info message");
assume (0) else $info("Info message from failing assumption");
assert (0) else $info("Info message, cyc=%d", cyc);
InWarningBlock: assert (0) else $warning;
InWarningMBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0);
InErrorBlock: assert (0) else $error;
InErrorMBlock: assert (0) else $error("Error....");
assert (0) else $fatal(1, "Fatal....");
assert (0) else $fatal;
assert (0)
else $info;
assert (0)
else $info("Info message");
assume (0)
else $info("Info message from failing assumption");
assert (0)
else $info("Info message, cyc=%d", cyc);
InWarningBlock :
assert (0)
else $warning;
InWarningMBlock :
assert (0)
else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0);
InErrorBlock :
assert (0)
else $error;
InErrorMBlock :
assert (0)
else $error("Error....");
assert (0)
else $fatal(1, "Fatal....");
assert (0)
else $fatal;
`endif
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
if (cyc == 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule

40
test_regress/t/t_assert_casez.v
View File

@ -6,25 +6,25 @@
module t;
reg [1:0] value;
reg [1:0] value;
initial begin
value = 2'b00;
unique casez (value)
2'b00 : ;
2'b01 : ;
2'b1? : ;
endcase
value = 2'b11;
unique casez (value)
2'b00 : ;
2'b01 : ;
2'b1? : ;
endcase
unique casez (1'b1)
default: ;
endcase
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
value = 2'b00;
unique casez (value)
2'b00: ;
2'b01: ;
2'b1?: ;
endcase
value = 2'b11;
unique casez (value)
2'b00: ;
2'b01: ;
2'b1?: ;
endcase
unique casez (1'b1)
default: ;
endcase
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

6
test_regress/t/t_assert_clock_event_unsup.out
View File

@ -1,5 +1,5 @@
%Error-UNSUPPORTED: t/t_assert_clock_event_unsup.v:26:7: Unsupported: Clock event before property call and in its body
26 | @(negedge clk)
| ^
%Error-UNSUPPORTED: t/t_assert_clock_event_unsup.v:24:5: Unsupported: Clock event before property call and in its body
24 | @(negedge clk) check(
| ^
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

47
test_regress/t/t_assert_clock_event_unsup.v
View File

@ -4,34 +4,33 @@
// SPDX-FileCopyrightText: 2022 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
clk
);
module t (
input clk
);
input clk;
int cyc = 0;
logic val = 0;
int cyc = 0;
logic val = 0;
always @(posedge clk) begin
cyc <= cyc + 1;
val = ~val;
end
always @(posedge clk) begin
cyc <= cyc + 1;
val = ~val;
end
property check(int cyc_mod_2, logic expected);
@(posedge clk)
cyc % 2 == cyc_mod_2 |=> val == expected;
endproperty
property check(int cyc_mod_2, logic expected);
@(posedge clk) cyc % 2 == cyc_mod_2 |=> val == expected;
endproperty
property check_if_1(int cyc_mod_2);
@(negedge clk)
check(cyc_mod_2, 1);
endproperty
property check_if_1(int cyc_mod_2);
@(negedge clk) check(
cyc_mod_2, 1
);
endproperty
assert property(check_if_1(1))
else begin
// Assertion should fail
$write("*-* All Finished *-*\n");
$finish;
end
assert property (check_if_1(1))
else begin
// Assertion should fail
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

42
test_regress/t/t_assert_comp.v
View File

@ -6,28 +6,28 @@
module t;
localparam TEN = 10;
localparam string PCTPCT = "%%";
localparam TEN = 10;
localparam string PCTPCT = "%%";
if (0) begin
$info;
$info("User elaboration-time info");
$info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN);
$warning;
$warning("User elaboration-time warning");
$warning(1); // Check can convert arguments to format
$error("User elaboration-time error");
end
if (0) begin
$info;
$info("User elaboration-time info");
$info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN);
$warning;
$warning("User elaboration-time warning");
$warning(1); // Check can convert arguments to format
$error("User elaboration-time error");
end
initial begin
$info;
$info("User run-time info");
$info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN);
$warning;
$warning("User run-time warning");
$warning(1); // Check can convert arguments to format
initial begin
$info;
$info("User run-time info");
$info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN);
$warning;
$warning("User run-time warning");
$warning(1); // Check can convert arguments to format
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

230
test_regress/t/t_assert_cover.v
View File

@ -4,156 +4,154 @@
// SPDX-FileCopyrightText: 2007 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
reg toggle;
integer cyc; initial cyc=1;
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Sub sub1 (.*);
Sub sub2 (.*);
Sub sub1 (.*);
Sub sub2 (.*);
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
end
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input toggle,
input [31:0] cyc
);
input clk,
input toggle,
input [31:0] cyc
);
// Simple cover
cover property (@(posedge clk) cyc==3);
// Simple cover
cover property (@(posedge clk) cyc==3);
// With statement, in generate
generate if (1) begin
cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4");
end
endgenerate
// With statement, in generate
generate if (1) begin
cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4");
end
endgenerate
// Labeled cover
cyc_eq_5:
cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
// Labeled cover
cyc_eq_5:
cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
// Using default clock
default clocking @(posedge clk); endclocking
cover property (cyc==6) $display("*COVER: Cyc==6");
// Using default clock
default clocking @(posedge clk); endclocking
cover property (cyc==6) $display("*COVER: Cyc==6");
// Disable statement
// Note () after disable are required
cover property (@(posedge clk) disable iff (toggle) cyc==8)
$display("*COVER: Cyc==8");
cover property (@(posedge clk) disable iff (!toggle) cyc==8)
$stop;
// Disable statement
// Note () after disable are required
cover property (@(posedge clk) disable iff (toggle) cyc==8)
$display("*COVER: Cyc==8");
cover property (@(posedge clk) disable iff (!toggle) cyc==8)
$stop;
always_ff @ (posedge clk) begin
labeled_icov: cover (cyc==3 || cyc==4);
end
always_ff @ (posedge clk) begin
labeled_icov: cover (cyc==3 || cyc==4);
end
// Immediate cover
labeled_imm0: cover #0 (cyc == 0);
labeled_immf: cover final (cyc == 0);
// Immediate cover
labeled_imm0: cover #0 (cyc == 0);
labeled_immf: cover final (cyc == 0);
// Immediate assert
labeled_imas: assert #0 (1);
assert final (1);
// Immediate assert
labeled_imas: assert #0 (1);
assert final (1);
//============================================================
// Using a macro and generate
wire reset = (cyc < 2);
//============================================================
// Using a macro and generate
wire reset = (cyc < 2);
`define covclk(eqn) cover property (@(posedge clk) disable iff (reset) (eqn))
genvar i;
generate
for (i=0; i<32; i=i+1)
begin: cycval
CycCover_i: `covclk( cyc[i] );
end
endgenerate
genvar i;
generate
for (i=0; i<32; i=i+1)
begin: cycval
CycCover_i: `covclk( cyc[i] );
end
endgenerate
//============================================================
// Using a more complicated property
property C1;
@(posedge clk)
disable iff (!toggle)
cyc==5;
endproperty
cover property (C1) $display("*COVER: Cyc==5");
//============================================================
// Using a more complicated property
property C1;
@(posedge clk)
disable iff (!toggle)
cyc==5;
endproperty
cover property (C1) $display("*COVER: Cyc==5");
`ifndef verilator // Unsupported
//============================================================
// Using covergroup
// Note a covergroup is really inheritance of a special system "covergroup" class.
covergroup counter1 @ (posedge cyc);
// Automatic methods: stop(), start(), sample(), set_inst_name()
//============================================================
// Using covergroup
// Note a covergroup is really inheritance of a special system "covergroup" class.
covergroup counter1 @ (posedge cyc);
// Automatic methods: stop(), start(), sample(), set_inst_name()
// Each bin value must be <= 32 bits. Strange.
cyc_value : coverpoint cyc {
}
cyc_bined : coverpoint cyc {
bins zero = {0};
bins low = {1,5};
// Note 5 is also in the bin above. Only the first bin matching is counted.
bins mid = {[5:$]};
// illegal_bins // Has precidence over "first matching bin", creates assertion
// ignore_bins // Not counted, and not part of total
}
toggle : coverpoint (toggle) {
bins off = {0};
bins on = {1};
}
cyc5 : coverpoint (cyc==5) {
bins five = {1};
// Each bin value must be <= 32 bits. Strange.
cyc_value : coverpoint cyc {
}
// option.at_least = {number}; // Default 1 - Hits to be considered covered
// option.auto_bin_max = {number}; // Default 64
// option.comment = {string}; // Default ""
// option.goal = {number}; // Default 90%
// option.name = {string}; // Default ""
// option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1)
// option.weight = {number}; // Default 1
cyc_bined : coverpoint cyc {
bins zero = {0};
bins low = {1,5};
// Note 5 is also in the bin above. Only the first bin matching is counted.
bins mid = {[5:$]};
// illegal_bins // Has precidence over "first matching bin", creates assertion
// ignore_bins // Not counted, and not part of total
}
toggle : coverpoint (toggle) {
bins off = {0};
bins on = {1};
}
cyc5 : coverpoint (cyc==5) {
bins five = {1};
}
// CROSS
value_and_toggle: // else default is __<firstlabel>_X_<secondlabel>_<n>
cross cyc_value, toggle;
endgroup
counter1 c1 = new();
// option.at_least = {number}; // Default 1 - Hits to be considered covered
// option.auto_bin_max = {number}; // Default 64
// option.comment = {string}; // Default ""
// option.goal = {number}; // Default 90%
// option.name = {string}; // Default ""
// option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1)
// option.weight = {number}; // Default 1
// CROSS
value_and_toggle: // else default is __<firstlabel>_X_<secondlabel>_<n>
cross cyc_value, toggle;
endgroup
counter1 c1 = new();
`endif
endmodule
module Sub
(
input clk,
input integer cyc
);
input clk,
input integer cyc
);
// Simple cover, per-instance
pi_sub:
cover property (@(posedge clk) cyc == 3);
// Simple cover, per-instance
pi_sub:
cover property (@(posedge clk) cyc == 3);
endmodule

304
test_regress/t/t_assert_ctl_arg.dat.out
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@ -1,153 +1,153 @@
# SystemC::Coverage-3
C 'ft/t_assert_ctl_arg.vl100n32tuserpagev_user/tocover_simple_immediate_100htop.t.cover_simple_immediate_100' 1
C 'ft/t_assert_ctl_arg.vl100n37tuserpagev_user/tocover_simple_immediate_stmt_100htop.t.cover_simple_immediate_stmt_100' 1
C 'ft/t_assert_ctl_arg.vl100n40tuserpagev_user/tocover_final_deferred_immediate_100htop.t.cover_final_deferred_immediate_100' 1
C 'ft/t_assert_ctl_arg.vl100n43tuserpagev_user/tocover_observed_deferred_immediate_100htop.t.cover_observed_deferred_immediate_100' 1
C 'ft/t_assert_ctl_arg.vl100n45tuserpagev_user/tocover_final_deferred_immediate_stmt_100htop.t.cover_final_deferred_immediate_stmt_100' 1
C 'ft/t_assert_ctl_arg.vl100n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_100htop.t.cover_observed_deferred_immediate_stmt_100' 1
C 'ft/t_assert_ctl_arg.vl103n32tuserpagev_user/tocover_simple_immediate_103htop.t.cover_simple_immediate_103' 0
C 'ft/t_assert_ctl_arg.vl103n37tuserpagev_user/tocover_simple_immediate_stmt_103htop.t.cover_simple_immediate_stmt_103' 0
C 'ft/t_assert_ctl_arg.vl103n40tuserpagev_user/tocover_final_deferred_immediate_103htop.t.cover_final_deferred_immediate_103' 0
C 'ft/t_assert_ctl_arg.vl103n43tuserpagev_user/tocover_observed_deferred_immediate_103htop.t.cover_observed_deferred_immediate_103' 0
C 'ft/t_assert_ctl_arg.vl103n45tuserpagev_user/tocover_final_deferred_immediate_stmt_103htop.t.cover_final_deferred_immediate_stmt_103' 0
C 'ft/t_assert_ctl_arg.vl103n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_103htop.t.cover_observed_deferred_immediate_stmt_103' 0
C 'ft/t_assert_ctl_arg.vl106n32tuserpagev_user/tocover_simple_immediate_106htop.t.cover_simple_immediate_106' 1
C 'ft/t_assert_ctl_arg.vl106n37tuserpagev_user/tocover_simple_immediate_stmt_106htop.t.cover_simple_immediate_stmt_106' 1
C 'ft/t_assert_ctl_arg.vl106n40tuserpagev_user/tocover_final_deferred_immediate_106htop.t.cover_final_deferred_immediate_106' 1
C 'ft/t_assert_ctl_arg.vl106n43tuserpagev_user/tocover_observed_deferred_immediate_106htop.t.cover_observed_deferred_immediate_106' 1
C 'ft/t_assert_ctl_arg.vl106n45tuserpagev_user/tocover_final_deferred_immediate_stmt_106htop.t.cover_final_deferred_immediate_stmt_106' 1
C 'ft/t_assert_ctl_arg.vl106n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_106htop.t.cover_observed_deferred_immediate_stmt_106' 1
C 'ft/t_assert_ctl_arg.vl108n32tuserpagev_user/tocover_simple_immediate_108htop.t.cover_simple_immediate_108' 1
C 'ft/t_assert_ctl_arg.vl108n37tuserpagev_user/tocover_simple_immediate_stmt_108htop.t.cover_simple_immediate_stmt_108' 1
C 'ft/t_assert_ctl_arg.vl108n40tuserpagev_user/tocover_final_deferred_immediate_108htop.t.cover_final_deferred_immediate_108' 1
C 'ft/t_assert_ctl_arg.vl108n43tuserpagev_user/tocover_observed_deferred_immediate_108htop.t.cover_observed_deferred_immediate_108' 1
C 'ft/t_assert_ctl_arg.vl108n45tuserpagev_user/tocover_final_deferred_immediate_stmt_108htop.t.cover_final_deferred_immediate_stmt_108' 1
C 'ft/t_assert_ctl_arg.vl108n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_108htop.t.cover_observed_deferred_immediate_stmt_108' 1
C 'ft/t_assert_ctl_arg.vl110n32tuserpagev_user/tocover_simple_immediate_110htop.t.cover_simple_immediate_110' 0
C 'ft/t_assert_ctl_arg.vl110n37tuserpagev_user/tocover_simple_immediate_stmt_110htop.t.cover_simple_immediate_stmt_110' 0
C 'ft/t_assert_ctl_arg.vl110n40tuserpagev_user/tocover_final_deferred_immediate_110htop.t.cover_final_deferred_immediate_110' 0
C 'ft/t_assert_ctl_arg.vl110n43tuserpagev_user/tocover_observed_deferred_immediate_110htop.t.cover_observed_deferred_immediate_110' 0
C 'ft/t_assert_ctl_arg.vl110n45tuserpagev_user/tocover_final_deferred_immediate_stmt_110htop.t.cover_final_deferred_immediate_stmt_110' 0
C 'ft/t_assert_ctl_arg.vl110n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_110htop.t.cover_observed_deferred_immediate_stmt_110' 0
C 'ft/t_assert_ctl_arg.vl112n32tuserpagev_user/tocover_simple_immediate_112htop.t.cover_simple_immediate_112' 1
C 'ft/t_assert_ctl_arg.vl112n37tuserpagev_user/tocover_simple_immediate_stmt_112htop.t.cover_simple_immediate_stmt_112' 1
C 'ft/t_assert_ctl_arg.vl112n40tuserpagev_user/tocover_final_deferred_immediate_112htop.t.cover_final_deferred_immediate_112' 1
C 'ft/t_assert_ctl_arg.vl112n43tuserpagev_user/tocover_observed_deferred_immediate_112htop.t.cover_observed_deferred_immediate_112' 0
C 'ft/t_assert_ctl_arg.vl112n45tuserpagev_user/tocover_final_deferred_immediate_stmt_112htop.t.cover_final_deferred_immediate_stmt_112' 1
C 'ft/t_assert_ctl_arg.vl112n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_112htop.t.cover_observed_deferred_immediate_stmt_112' 0
C 'ft/t_assert_ctl_arg.vl192n22tuserpagev_user/concurrentocover_concurrenthtop.t.concurrent.cover_concurrent' 0
C 'ft/t_assert_ctl_arg.vl193n27tuserpagev_user/concurrentocover_concurrent_stmthtop.t.concurrent.cover_concurrent_stmt' 0
C 'ft/t_assert_ctl_arg.vl49n31tuserpagev_user/tocover_simple_immediate_49htop.t.cover_simple_immediate_49' 1
C 'ft/t_assert_ctl_arg.vl49n36tuserpagev_user/tocover_simple_immediate_stmt_49htop.t.cover_simple_immediate_stmt_49' 1
C 'ft/t_assert_ctl_arg.vl49n39tuserpagev_user/tocover_final_deferred_immediate_49htop.t.cover_final_deferred_immediate_49' 0
C 'ft/t_assert_ctl_arg.vl49n42tuserpagev_user/tocover_observed_deferred_immediate_49htop.t.cover_observed_deferred_immediate_49' 0
C 'ft/t_assert_ctl_arg.vl49n44tuserpagev_user/tocover_final_deferred_immediate_stmt_49htop.t.cover_final_deferred_immediate_stmt_49' 0
C 'ft/t_assert_ctl_arg.vl49n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_49htop.t.cover_observed_deferred_immediate_stmt_49' 0
C 'ft/t_assert_ctl_arg.vl51n31tuserpagev_user/tocover_simple_immediate_51htop.t.cover_simple_immediate_51' 0
C 'ft/t_assert_ctl_arg.vl51n36tuserpagev_user/tocover_simple_immediate_stmt_51htop.t.cover_simple_immediate_stmt_51' 0
C 'ft/t_assert_ctl_arg.vl51n39tuserpagev_user/tocover_final_deferred_immediate_51htop.t.cover_final_deferred_immediate_51' 0
C 'ft/t_assert_ctl_arg.vl51n42tuserpagev_user/tocover_observed_deferred_immediate_51htop.t.cover_observed_deferred_immediate_51' 0
C 'ft/t_assert_ctl_arg.vl51n44tuserpagev_user/tocover_final_deferred_immediate_stmt_51htop.t.cover_final_deferred_immediate_stmt_51' 0
C 'ft/t_assert_ctl_arg.vl51n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_51htop.t.cover_observed_deferred_immediate_stmt_51' 0
C 'ft/t_assert_ctl_arg.vl56n31tuserpagev_user/tocover_simple_immediate_56htop.t.cover_simple_immediate_56' 0
C 'ft/t_assert_ctl_arg.vl56n36tuserpagev_user/tocover_simple_immediate_stmt_56htop.t.cover_simple_immediate_stmt_56' 0
C 'ft/t_assert_ctl_arg.vl56n39tuserpagev_user/tocover_final_deferred_immediate_56htop.t.cover_final_deferred_immediate_56' 0
C 'ft/t_assert_ctl_arg.vl56n42tuserpagev_user/tocover_observed_deferred_immediate_56htop.t.cover_observed_deferred_immediate_56' 1
C 'ft/t_assert_ctl_arg.vl56n44tuserpagev_user/tocover_final_deferred_immediate_stmt_56htop.t.cover_final_deferred_immediate_stmt_56' 0
C 'ft/t_assert_ctl_arg.vl56n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_56htop.t.cover_observed_deferred_immediate_stmt_56' 1
C 'ft/t_assert_ctl_arg.vl58n31tuserpagev_user/tocover_simple_immediate_58htop.t.cover_simple_immediate_58' 0
C 'ft/t_assert_ctl_arg.vl58n36tuserpagev_user/tocover_simple_immediate_stmt_58htop.t.cover_simple_immediate_stmt_58' 0
C 'ft/t_assert_ctl_arg.vl58n39tuserpagev_user/tocover_final_deferred_immediate_58htop.t.cover_final_deferred_immediate_58' 0
C 'ft/t_assert_ctl_arg.vl58n42tuserpagev_user/tocover_observed_deferred_immediate_58htop.t.cover_observed_deferred_immediate_58' 0
C 'ft/t_assert_ctl_arg.vl58n44tuserpagev_user/tocover_final_deferred_immediate_stmt_58htop.t.cover_final_deferred_immediate_stmt_58' 0
C 'ft/t_assert_ctl_arg.vl58n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_58htop.t.cover_observed_deferred_immediate_stmt_58' 0
C 'ft/t_assert_ctl_arg.vl63n31tuserpagev_user/tocover_simple_immediate_63htop.t.cover_simple_immediate_63' 0
C 'ft/t_assert_ctl_arg.vl63n36tuserpagev_user/tocover_simple_immediate_stmt_63htop.t.cover_simple_immediate_stmt_63' 0
C 'ft/t_assert_ctl_arg.vl63n39tuserpagev_user/tocover_final_deferred_immediate_63htop.t.cover_final_deferred_immediate_63' 1
C 'ft/t_assert_ctl_arg.vl63n42tuserpagev_user/tocover_observed_deferred_immediate_63htop.t.cover_observed_deferred_immediate_63' 0
C 'ft/t_assert_ctl_arg.vl63n44tuserpagev_user/tocover_final_deferred_immediate_stmt_63htop.t.cover_final_deferred_immediate_stmt_63' 1
C 'ft/t_assert_ctl_arg.vl63n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_63htop.t.cover_observed_deferred_immediate_stmt_63' 0
C 'ft/t_assert_ctl_arg.vl65n31tuserpagev_user/tocover_simple_immediate_65htop.t.cover_simple_immediate_65' 0
C 'ft/t_assert_ctl_arg.vl65n36tuserpagev_user/tocover_simple_immediate_stmt_65htop.t.cover_simple_immediate_stmt_65' 0
C 'ft/t_assert_ctl_arg.vl65n39tuserpagev_user/tocover_final_deferred_immediate_65htop.t.cover_final_deferred_immediate_65' 0
C 'ft/t_assert_ctl_arg.vl65n42tuserpagev_user/tocover_observed_deferred_immediate_65htop.t.cover_observed_deferred_immediate_65' 0
C 'ft/t_assert_ctl_arg.vl65n44tuserpagev_user/tocover_final_deferred_immediate_stmt_65htop.t.cover_final_deferred_immediate_stmt_65' 0
C 'ft/t_assert_ctl_arg.vl65n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_65htop.t.cover_observed_deferred_immediate_stmt_65' 0
C 'ft/t_assert_ctl_arg.vl69n31tuserpagev_user/tocover_simple_immediate_69htop.t.cover_simple_immediate_69' 0
C 'ft/t_assert_ctl_arg.vl69n36tuserpagev_user/tocover_simple_immediate_stmt_69htop.t.cover_simple_immediate_stmt_69' 0
C 'ft/t_assert_ctl_arg.vl69n39tuserpagev_user/tocover_final_deferred_immediate_69htop.t.cover_final_deferred_immediate_69' 0
C 'ft/t_assert_ctl_arg.vl69n42tuserpagev_user/tocover_observed_deferred_immediate_69htop.t.cover_observed_deferred_immediate_69' 0
C 'ft/t_assert_ctl_arg.vl69n44tuserpagev_user/tocover_final_deferred_immediate_stmt_69htop.t.cover_final_deferred_immediate_stmt_69' 0
C 'ft/t_assert_ctl_arg.vl69n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_69htop.t.cover_observed_deferred_immediate_stmt_69' 0
C 'ft/t_assert_ctl_arg.vl71n31tuserpagev_user/tocover_simple_immediate_71htop.t.cover_simple_immediate_71' 1
C 'ft/t_assert_ctl_arg.vl71n36tuserpagev_user/tocover_simple_immediate_stmt_71htop.t.cover_simple_immediate_stmt_71' 1
C 'ft/t_assert_ctl_arg.vl71n39tuserpagev_user/tocover_final_deferred_immediate_71htop.t.cover_final_deferred_immediate_71' 1
C 'ft/t_assert_ctl_arg.vl71n42tuserpagev_user/tocover_observed_deferred_immediate_71htop.t.cover_observed_deferred_immediate_71' 1
C 'ft/t_assert_ctl_arg.vl71n44tuserpagev_user/tocover_final_deferred_immediate_stmt_71htop.t.cover_final_deferred_immediate_stmt_71' 1
C 'ft/t_assert_ctl_arg.vl71n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_71htop.t.cover_observed_deferred_immediate_stmt_71' 1
C 'ft/t_assert_ctl_arg.vl73n31tuserpagev_user/tocover_simple_immediate_73htop.t.cover_simple_immediate_73' 0
C 'ft/t_assert_ctl_arg.vl73n36tuserpagev_user/tocover_simple_immediate_stmt_73htop.t.cover_simple_immediate_stmt_73' 0
C 'ft/t_assert_ctl_arg.vl73n39tuserpagev_user/tocover_final_deferred_immediate_73htop.t.cover_final_deferred_immediate_73' 0
C 'ft/t_assert_ctl_arg.vl73n42tuserpagev_user/tocover_observed_deferred_immediate_73htop.t.cover_observed_deferred_immediate_73' 0
C 'ft/t_assert_ctl_arg.vl73n44tuserpagev_user/tocover_final_deferred_immediate_stmt_73htop.t.cover_final_deferred_immediate_stmt_73' 0
C 'ft/t_assert_ctl_arg.vl73n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_73htop.t.cover_observed_deferred_immediate_stmt_73' 0
C 'ft/t_assert_ctl_arg.vl76n31tuserpagev_user/tocover_simple_immediate_76htop.t.cover_simple_immediate_76' 1
C 'ft/t_assert_ctl_arg.vl76n36tuserpagev_user/tocover_simple_immediate_stmt_76htop.t.cover_simple_immediate_stmt_76' 1
C 'ft/t_assert_ctl_arg.vl76n39tuserpagev_user/tocover_final_deferred_immediate_76htop.t.cover_final_deferred_immediate_76' 0
C 'ft/t_assert_ctl_arg.vl76n42tuserpagev_user/tocover_observed_deferred_immediate_76htop.t.cover_observed_deferred_immediate_76' 1
C 'ft/t_assert_ctl_arg.vl76n44tuserpagev_user/tocover_final_deferred_immediate_stmt_76htop.t.cover_final_deferred_immediate_stmt_76' 0
C 'ft/t_assert_ctl_arg.vl76n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_76htop.t.cover_observed_deferred_immediate_stmt_76' 1
C 'ft/t_assert_ctl_arg.vl78n31tuserpagev_user/tocover_simple_immediate_78htop.t.cover_simple_immediate_78' 1
C 'ft/t_assert_ctl_arg.vl78n36tuserpagev_user/tocover_simple_immediate_stmt_78htop.t.cover_simple_immediate_stmt_78' 1
C 'ft/t_assert_ctl_arg.vl78n39tuserpagev_user/tocover_final_deferred_immediate_78htop.t.cover_final_deferred_immediate_78' 1
C 'ft/t_assert_ctl_arg.vl78n42tuserpagev_user/tocover_observed_deferred_immediate_78htop.t.cover_observed_deferred_immediate_78' 1
C 'ft/t_assert_ctl_arg.vl78n44tuserpagev_user/tocover_final_deferred_immediate_stmt_78htop.t.cover_final_deferred_immediate_stmt_78' 1
C 'ft/t_assert_ctl_arg.vl78n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_78htop.t.cover_observed_deferred_immediate_stmt_78' 1
C 'ft/t_assert_ctl_arg.vl80n31tuserpagev_user/tocover_simple_immediate_80htop.t.cover_simple_immediate_80' 1
C 'ft/t_assert_ctl_arg.vl80n36tuserpagev_user/tocover_simple_immediate_stmt_80htop.t.cover_simple_immediate_stmt_80' 1
C 'ft/t_assert_ctl_arg.vl80n39tuserpagev_user/tocover_final_deferred_immediate_80htop.t.cover_final_deferred_immediate_80' 0
C 'ft/t_assert_ctl_arg.vl80n42tuserpagev_user/tocover_observed_deferred_immediate_80htop.t.cover_observed_deferred_immediate_80' 0
C 'ft/t_assert_ctl_arg.vl80n44tuserpagev_user/tocover_final_deferred_immediate_stmt_80htop.t.cover_final_deferred_immediate_stmt_80' 0
C 'ft/t_assert_ctl_arg.vl80n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_80htop.t.cover_observed_deferred_immediate_stmt_80' 0
C 'ft/t_assert_ctl_arg.vl82n31tuserpagev_user/tocover_simple_immediate_82htop.t.cover_simple_immediate_82' 1
C 'ft/t_assert_ctl_arg.vl82n36tuserpagev_user/tocover_simple_immediate_stmt_82htop.t.cover_simple_immediate_stmt_82' 1
C 'ft/t_assert_ctl_arg.vl82n39tuserpagev_user/tocover_final_deferred_immediate_82htop.t.cover_final_deferred_immediate_82' 0
C 'ft/t_assert_ctl_arg.vl82n42tuserpagev_user/tocover_observed_deferred_immediate_82htop.t.cover_observed_deferred_immediate_82' 0
C 'ft/t_assert_ctl_arg.vl82n44tuserpagev_user/tocover_final_deferred_immediate_stmt_82htop.t.cover_final_deferred_immediate_stmt_82' 0
C 'ft/t_assert_ctl_arg.vl82n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_82htop.t.cover_observed_deferred_immediate_stmt_82' 0
C 'ft/t_assert_ctl_arg.vl84n31tuserpagev_user/tocover_simple_immediate_84htop.t.cover_simple_immediate_84' 0
C 'ft/t_assert_ctl_arg.vl84n36tuserpagev_user/tocover_simple_immediate_stmt_84htop.t.cover_simple_immediate_stmt_84' 0
C 'ft/t_assert_ctl_arg.vl84n39tuserpagev_user/tocover_final_deferred_immediate_84htop.t.cover_final_deferred_immediate_84' 0
C 'ft/t_assert_ctl_arg.vl84n42tuserpagev_user/tocover_observed_deferred_immediate_84htop.t.cover_observed_deferred_immediate_84' 0
C 'ft/t_assert_ctl_arg.vl84n44tuserpagev_user/tocover_final_deferred_immediate_stmt_84htop.t.cover_final_deferred_immediate_stmt_84' 0
C 'ft/t_assert_ctl_arg.vl84n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_84htop.t.cover_observed_deferred_immediate_stmt_84' 0
C 'ft/t_assert_ctl_arg.vl86n31tuserpagev_user/tocover_simple_immediate_86htop.t.cover_simple_immediate_86' 1
C 'ft/t_assert_ctl_arg.vl86n36tuserpagev_user/tocover_simple_immediate_stmt_86htop.t.cover_simple_immediate_stmt_86' 1
C 'ft/t_assert_ctl_arg.vl86n39tuserpagev_user/tocover_final_deferred_immediate_86htop.t.cover_final_deferred_immediate_86' 0
C 'ft/t_assert_ctl_arg.vl86n42tuserpagev_user/tocover_observed_deferred_immediate_86htop.t.cover_observed_deferred_immediate_86' 0
C 'ft/t_assert_ctl_arg.vl86n44tuserpagev_user/tocover_final_deferred_immediate_stmt_86htop.t.cover_final_deferred_immediate_stmt_86' 0
C 'ft/t_assert_ctl_arg.vl86n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_86htop.t.cover_observed_deferred_immediate_stmt_86' 0
C 'ft/t_assert_ctl_arg.vl88n31tuserpagev_user/tocover_simple_immediate_88htop.t.cover_simple_immediate_88' 0
C 'ft/t_assert_ctl_arg.vl88n36tuserpagev_user/tocover_simple_immediate_stmt_88htop.t.cover_simple_immediate_stmt_88' 0
C 'ft/t_assert_ctl_arg.vl88n39tuserpagev_user/tocover_final_deferred_immediate_88htop.t.cover_final_deferred_immediate_88' 0
C 'ft/t_assert_ctl_arg.vl88n42tuserpagev_user/tocover_observed_deferred_immediate_88htop.t.cover_observed_deferred_immediate_88' 0
C 'ft/t_assert_ctl_arg.vl88n44tuserpagev_user/tocover_final_deferred_immediate_stmt_88htop.t.cover_final_deferred_immediate_stmt_88' 0
C 'ft/t_assert_ctl_arg.vl88n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_88htop.t.cover_observed_deferred_immediate_stmt_88' 0
C 'ft/t_assert_ctl_arg.vl90n31tuserpagev_user/tocover_simple_immediate_90htop.t.cover_simple_immediate_90' 1
C 'ft/t_assert_ctl_arg.vl90n36tuserpagev_user/tocover_simple_immediate_stmt_90htop.t.cover_simple_immediate_stmt_90' 1
C 'ft/t_assert_ctl_arg.vl90n39tuserpagev_user/tocover_final_deferred_immediate_90htop.t.cover_final_deferred_immediate_90' 1
C 'ft/t_assert_ctl_arg.vl90n42tuserpagev_user/tocover_observed_deferred_immediate_90htop.t.cover_observed_deferred_immediate_90' 1
C 'ft/t_assert_ctl_arg.vl90n44tuserpagev_user/tocover_final_deferred_immediate_stmt_90htop.t.cover_final_deferred_immediate_stmt_90' 1
C 'ft/t_assert_ctl_arg.vl90n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_90htop.t.cover_observed_deferred_immediate_stmt_90' 1
C 'ft/t_assert_ctl_arg.vl92n31tuserpagev_user/tocover_simple_immediate_92htop.t.cover_simple_immediate_92' 0
C 'ft/t_assert_ctl_arg.vl92n36tuserpagev_user/tocover_simple_immediate_stmt_92htop.t.cover_simple_immediate_stmt_92' 0
C 'ft/t_assert_ctl_arg.vl92n39tuserpagev_user/tocover_final_deferred_immediate_92htop.t.cover_final_deferred_immediate_92' 0
C 'ft/t_assert_ctl_arg.vl92n42tuserpagev_user/tocover_observed_deferred_immediate_92htop.t.cover_observed_deferred_immediate_92' 0
C 'ft/t_assert_ctl_arg.vl92n44tuserpagev_user/tocover_final_deferred_immediate_stmt_92htop.t.cover_final_deferred_immediate_stmt_92' 0
C 'ft/t_assert_ctl_arg.vl92n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_92htop.t.cover_observed_deferred_immediate_stmt_92' 0
C 'ft/t_assert_ctl_arg.vl97n31tuserpagev_user/tocover_simple_immediate_97htop.t.cover_simple_immediate_97' 0
C 'ft/t_assert_ctl_arg.vl97n36tuserpagev_user/tocover_simple_immediate_stmt_97htop.t.cover_simple_immediate_stmt_97' 0
C 'ft/t_assert_ctl_arg.vl97n39tuserpagev_user/tocover_final_deferred_immediate_97htop.t.cover_final_deferred_immediate_97' 0
C 'ft/t_assert_ctl_arg.vl97n42tuserpagev_user/tocover_observed_deferred_immediate_97htop.t.cover_observed_deferred_immediate_97' 0
C 'ft/t_assert_ctl_arg.vl97n44tuserpagev_user/tocover_final_deferred_immediate_stmt_97htop.t.cover_final_deferred_immediate_stmt_97' 0
C 'ft/t_assert_ctl_arg.vl97n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_97htop.t.cover_observed_deferred_immediate_stmt_97' 0
C 'ft/t_assert_ctl_arg.vl102n31tuserpagev_user/tocover_simple_immediate_102htop.t.cover_simple_immediate_102' 0
C 'ft/t_assert_ctl_arg.vl102n36tuserpagev_user/tocover_simple_immediate_stmt_102htop.t.cover_simple_immediate_stmt_102' 0
C 'ft/t_assert_ctl_arg.vl102n39tuserpagev_user/tocover_final_deferred_immediate_102htop.t.cover_final_deferred_immediate_102' 0
C 'ft/t_assert_ctl_arg.vl102n42tuserpagev_user/tocover_observed_deferred_immediate_102htop.t.cover_observed_deferred_immediate_102' 0
C 'ft/t_assert_ctl_arg.vl102n44tuserpagev_user/tocover_final_deferred_immediate_stmt_102htop.t.cover_final_deferred_immediate_stmt_102' 0
C 'ft/t_assert_ctl_arg.vl102n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_102htop.t.cover_observed_deferred_immediate_stmt_102' 0
C 'ft/t_assert_ctl_arg.vl105n31tuserpagev_user/tocover_simple_immediate_105htop.t.cover_simple_immediate_105' 1
C 'ft/t_assert_ctl_arg.vl105n36tuserpagev_user/tocover_simple_immediate_stmt_105htop.t.cover_simple_immediate_stmt_105' 1
C 'ft/t_assert_ctl_arg.vl105n39tuserpagev_user/tocover_final_deferred_immediate_105htop.t.cover_final_deferred_immediate_105' 1
C 'ft/t_assert_ctl_arg.vl105n42tuserpagev_user/tocover_observed_deferred_immediate_105htop.t.cover_observed_deferred_immediate_105' 1
C 'ft/t_assert_ctl_arg.vl105n44tuserpagev_user/tocover_final_deferred_immediate_stmt_105htop.t.cover_final_deferred_immediate_stmt_105' 1
C 'ft/t_assert_ctl_arg.vl105n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_105htop.t.cover_observed_deferred_immediate_stmt_105' 1
C 'ft/t_assert_ctl_arg.vl107n31tuserpagev_user/tocover_simple_immediate_107htop.t.cover_simple_immediate_107' 1
C 'ft/t_assert_ctl_arg.vl107n36tuserpagev_user/tocover_simple_immediate_stmt_107htop.t.cover_simple_immediate_stmt_107' 1
C 'ft/t_assert_ctl_arg.vl107n39tuserpagev_user/tocover_final_deferred_immediate_107htop.t.cover_final_deferred_immediate_107' 1
C 'ft/t_assert_ctl_arg.vl107n42tuserpagev_user/tocover_observed_deferred_immediate_107htop.t.cover_observed_deferred_immediate_107' 1
C 'ft/t_assert_ctl_arg.vl107n44tuserpagev_user/tocover_final_deferred_immediate_stmt_107htop.t.cover_final_deferred_immediate_stmt_107' 1
C 'ft/t_assert_ctl_arg.vl107n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_107htop.t.cover_observed_deferred_immediate_stmt_107' 1
C 'ft/t_assert_ctl_arg.vl109n31tuserpagev_user/tocover_simple_immediate_109htop.t.cover_simple_immediate_109' 0
C 'ft/t_assert_ctl_arg.vl109n36tuserpagev_user/tocover_simple_immediate_stmt_109htop.t.cover_simple_immediate_stmt_109' 0
C 'ft/t_assert_ctl_arg.vl109n39tuserpagev_user/tocover_final_deferred_immediate_109htop.t.cover_final_deferred_immediate_109' 0
C 'ft/t_assert_ctl_arg.vl109n42tuserpagev_user/tocover_observed_deferred_immediate_109htop.t.cover_observed_deferred_immediate_109' 0
C 'ft/t_assert_ctl_arg.vl109n44tuserpagev_user/tocover_final_deferred_immediate_stmt_109htop.t.cover_final_deferred_immediate_stmt_109' 0
C 'ft/t_assert_ctl_arg.vl109n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_109htop.t.cover_observed_deferred_immediate_stmt_109' 0
C 'ft/t_assert_ctl_arg.vl111n31tuserpagev_user/tocover_simple_immediate_111htop.t.cover_simple_immediate_111' 1
C 'ft/t_assert_ctl_arg.vl111n36tuserpagev_user/tocover_simple_immediate_stmt_111htop.t.cover_simple_immediate_stmt_111' 1
C 'ft/t_assert_ctl_arg.vl111n39tuserpagev_user/tocover_final_deferred_immediate_111htop.t.cover_final_deferred_immediate_111' 1
C 'ft/t_assert_ctl_arg.vl111n42tuserpagev_user/tocover_observed_deferred_immediate_111htop.t.cover_observed_deferred_immediate_111' 0
C 'ft/t_assert_ctl_arg.vl111n44tuserpagev_user/tocover_final_deferred_immediate_stmt_111htop.t.cover_final_deferred_immediate_stmt_111' 1
C 'ft/t_assert_ctl_arg.vl111n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_111htop.t.cover_observed_deferred_immediate_stmt_111' 0
C 'ft/t_assert_ctl_arg.vl191n21tuserpagev_user/concurrentocover_concurrenthtop.t.concurrent.cover_concurrent' 0
C 'ft/t_assert_ctl_arg.vl192n26tuserpagev_user/concurrentocover_concurrent_stmthtop.t.concurrent.cover_concurrent_stmt' 0
C 'ft/t_assert_ctl_arg.vl48n30tuserpagev_user/tocover_simple_immediate_48htop.t.cover_simple_immediate_48' 1
C 'ft/t_assert_ctl_arg.vl48n35tuserpagev_user/tocover_simple_immediate_stmt_48htop.t.cover_simple_immediate_stmt_48' 1
C 'ft/t_assert_ctl_arg.vl48n38tuserpagev_user/tocover_final_deferred_immediate_48htop.t.cover_final_deferred_immediate_48' 0
C 'ft/t_assert_ctl_arg.vl48n41tuserpagev_user/tocover_observed_deferred_immediate_48htop.t.cover_observed_deferred_immediate_48' 0
C 'ft/t_assert_ctl_arg.vl48n43tuserpagev_user/tocover_final_deferred_immediate_stmt_48htop.t.cover_final_deferred_immediate_stmt_48' 0
C 'ft/t_assert_ctl_arg.vl48n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_48htop.t.cover_observed_deferred_immediate_stmt_48' 0
C 'ft/t_assert_ctl_arg.vl50n30tuserpagev_user/tocover_simple_immediate_50htop.t.cover_simple_immediate_50' 0
C 'ft/t_assert_ctl_arg.vl50n35tuserpagev_user/tocover_simple_immediate_stmt_50htop.t.cover_simple_immediate_stmt_50' 0
C 'ft/t_assert_ctl_arg.vl50n38tuserpagev_user/tocover_final_deferred_immediate_50htop.t.cover_final_deferred_immediate_50' 0
C 'ft/t_assert_ctl_arg.vl50n41tuserpagev_user/tocover_observed_deferred_immediate_50htop.t.cover_observed_deferred_immediate_50' 0
C 'ft/t_assert_ctl_arg.vl50n43tuserpagev_user/tocover_final_deferred_immediate_stmt_50htop.t.cover_final_deferred_immediate_stmt_50' 0
C 'ft/t_assert_ctl_arg.vl50n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_50htop.t.cover_observed_deferred_immediate_stmt_50' 0
C 'ft/t_assert_ctl_arg.vl55n30tuserpagev_user/tocover_simple_immediate_55htop.t.cover_simple_immediate_55' 0
C 'ft/t_assert_ctl_arg.vl55n35tuserpagev_user/tocover_simple_immediate_stmt_55htop.t.cover_simple_immediate_stmt_55' 0
C 'ft/t_assert_ctl_arg.vl55n38tuserpagev_user/tocover_final_deferred_immediate_55htop.t.cover_final_deferred_immediate_55' 0
C 'ft/t_assert_ctl_arg.vl55n41tuserpagev_user/tocover_observed_deferred_immediate_55htop.t.cover_observed_deferred_immediate_55' 1
C 'ft/t_assert_ctl_arg.vl55n43tuserpagev_user/tocover_final_deferred_immediate_stmt_55htop.t.cover_final_deferred_immediate_stmt_55' 0
C 'ft/t_assert_ctl_arg.vl55n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_55htop.t.cover_observed_deferred_immediate_stmt_55' 1
C 'ft/t_assert_ctl_arg.vl57n30tuserpagev_user/tocover_simple_immediate_57htop.t.cover_simple_immediate_57' 0
C 'ft/t_assert_ctl_arg.vl57n35tuserpagev_user/tocover_simple_immediate_stmt_57htop.t.cover_simple_immediate_stmt_57' 0
C 'ft/t_assert_ctl_arg.vl57n38tuserpagev_user/tocover_final_deferred_immediate_57htop.t.cover_final_deferred_immediate_57' 0
C 'ft/t_assert_ctl_arg.vl57n41tuserpagev_user/tocover_observed_deferred_immediate_57htop.t.cover_observed_deferred_immediate_57' 0
C 'ft/t_assert_ctl_arg.vl57n43tuserpagev_user/tocover_final_deferred_immediate_stmt_57htop.t.cover_final_deferred_immediate_stmt_57' 0
C 'ft/t_assert_ctl_arg.vl57n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_57htop.t.cover_observed_deferred_immediate_stmt_57' 0
C 'ft/t_assert_ctl_arg.vl62n30tuserpagev_user/tocover_simple_immediate_62htop.t.cover_simple_immediate_62' 0
C 'ft/t_assert_ctl_arg.vl62n35tuserpagev_user/tocover_simple_immediate_stmt_62htop.t.cover_simple_immediate_stmt_62' 0
C 'ft/t_assert_ctl_arg.vl62n38tuserpagev_user/tocover_final_deferred_immediate_62htop.t.cover_final_deferred_immediate_62' 1
C 'ft/t_assert_ctl_arg.vl62n41tuserpagev_user/tocover_observed_deferred_immediate_62htop.t.cover_observed_deferred_immediate_62' 0
C 'ft/t_assert_ctl_arg.vl62n43tuserpagev_user/tocover_final_deferred_immediate_stmt_62htop.t.cover_final_deferred_immediate_stmt_62' 1
C 'ft/t_assert_ctl_arg.vl62n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_62htop.t.cover_observed_deferred_immediate_stmt_62' 0
C 'ft/t_assert_ctl_arg.vl64n30tuserpagev_user/tocover_simple_immediate_64htop.t.cover_simple_immediate_64' 0
C 'ft/t_assert_ctl_arg.vl64n35tuserpagev_user/tocover_simple_immediate_stmt_64htop.t.cover_simple_immediate_stmt_64' 0
C 'ft/t_assert_ctl_arg.vl64n38tuserpagev_user/tocover_final_deferred_immediate_64htop.t.cover_final_deferred_immediate_64' 0
C 'ft/t_assert_ctl_arg.vl64n41tuserpagev_user/tocover_observed_deferred_immediate_64htop.t.cover_observed_deferred_immediate_64' 0
C 'ft/t_assert_ctl_arg.vl64n43tuserpagev_user/tocover_final_deferred_immediate_stmt_64htop.t.cover_final_deferred_immediate_stmt_64' 0
C 'ft/t_assert_ctl_arg.vl64n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_64htop.t.cover_observed_deferred_immediate_stmt_64' 0
C 'ft/t_assert_ctl_arg.vl68n30tuserpagev_user/tocover_simple_immediate_68htop.t.cover_simple_immediate_68' 0
C 'ft/t_assert_ctl_arg.vl68n35tuserpagev_user/tocover_simple_immediate_stmt_68htop.t.cover_simple_immediate_stmt_68' 0
C 'ft/t_assert_ctl_arg.vl68n38tuserpagev_user/tocover_final_deferred_immediate_68htop.t.cover_final_deferred_immediate_68' 0
C 'ft/t_assert_ctl_arg.vl68n41tuserpagev_user/tocover_observed_deferred_immediate_68htop.t.cover_observed_deferred_immediate_68' 0
C 'ft/t_assert_ctl_arg.vl68n43tuserpagev_user/tocover_final_deferred_immediate_stmt_68htop.t.cover_final_deferred_immediate_stmt_68' 0
C 'ft/t_assert_ctl_arg.vl68n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_68htop.t.cover_observed_deferred_immediate_stmt_68' 0
C 'ft/t_assert_ctl_arg.vl70n30tuserpagev_user/tocover_simple_immediate_70htop.t.cover_simple_immediate_70' 1
C 'ft/t_assert_ctl_arg.vl70n35tuserpagev_user/tocover_simple_immediate_stmt_70htop.t.cover_simple_immediate_stmt_70' 1
C 'ft/t_assert_ctl_arg.vl70n38tuserpagev_user/tocover_final_deferred_immediate_70htop.t.cover_final_deferred_immediate_70' 1
C 'ft/t_assert_ctl_arg.vl70n41tuserpagev_user/tocover_observed_deferred_immediate_70htop.t.cover_observed_deferred_immediate_70' 1
C 'ft/t_assert_ctl_arg.vl70n43tuserpagev_user/tocover_final_deferred_immediate_stmt_70htop.t.cover_final_deferred_immediate_stmt_70' 1
C 'ft/t_assert_ctl_arg.vl70n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_70htop.t.cover_observed_deferred_immediate_stmt_70' 1
C 'ft/t_assert_ctl_arg.vl72n30tuserpagev_user/tocover_simple_immediate_72htop.t.cover_simple_immediate_72' 0
C 'ft/t_assert_ctl_arg.vl72n35tuserpagev_user/tocover_simple_immediate_stmt_72htop.t.cover_simple_immediate_stmt_72' 0
C 'ft/t_assert_ctl_arg.vl72n38tuserpagev_user/tocover_final_deferred_immediate_72htop.t.cover_final_deferred_immediate_72' 0
C 'ft/t_assert_ctl_arg.vl72n41tuserpagev_user/tocover_observed_deferred_immediate_72htop.t.cover_observed_deferred_immediate_72' 0
C 'ft/t_assert_ctl_arg.vl72n43tuserpagev_user/tocover_final_deferred_immediate_stmt_72htop.t.cover_final_deferred_immediate_stmt_72' 0
C 'ft/t_assert_ctl_arg.vl72n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_72htop.t.cover_observed_deferred_immediate_stmt_72' 0
C 'ft/t_assert_ctl_arg.vl75n30tuserpagev_user/tocover_simple_immediate_75htop.t.cover_simple_immediate_75' 1
C 'ft/t_assert_ctl_arg.vl75n35tuserpagev_user/tocover_simple_immediate_stmt_75htop.t.cover_simple_immediate_stmt_75' 1
C 'ft/t_assert_ctl_arg.vl75n38tuserpagev_user/tocover_final_deferred_immediate_75htop.t.cover_final_deferred_immediate_75' 0
C 'ft/t_assert_ctl_arg.vl75n41tuserpagev_user/tocover_observed_deferred_immediate_75htop.t.cover_observed_deferred_immediate_75' 1
C 'ft/t_assert_ctl_arg.vl75n43tuserpagev_user/tocover_final_deferred_immediate_stmt_75htop.t.cover_final_deferred_immediate_stmt_75' 0
C 'ft/t_assert_ctl_arg.vl75n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_75htop.t.cover_observed_deferred_immediate_stmt_75' 1
C 'ft/t_assert_ctl_arg.vl77n30tuserpagev_user/tocover_simple_immediate_77htop.t.cover_simple_immediate_77' 1
C 'ft/t_assert_ctl_arg.vl77n35tuserpagev_user/tocover_simple_immediate_stmt_77htop.t.cover_simple_immediate_stmt_77' 1
C 'ft/t_assert_ctl_arg.vl77n38tuserpagev_user/tocover_final_deferred_immediate_77htop.t.cover_final_deferred_immediate_77' 1
C 'ft/t_assert_ctl_arg.vl77n41tuserpagev_user/tocover_observed_deferred_immediate_77htop.t.cover_observed_deferred_immediate_77' 1
C 'ft/t_assert_ctl_arg.vl77n43tuserpagev_user/tocover_final_deferred_immediate_stmt_77htop.t.cover_final_deferred_immediate_stmt_77' 1
C 'ft/t_assert_ctl_arg.vl77n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_77htop.t.cover_observed_deferred_immediate_stmt_77' 1
C 'ft/t_assert_ctl_arg.vl79n30tuserpagev_user/tocover_simple_immediate_79htop.t.cover_simple_immediate_79' 1
C 'ft/t_assert_ctl_arg.vl79n35tuserpagev_user/tocover_simple_immediate_stmt_79htop.t.cover_simple_immediate_stmt_79' 1
C 'ft/t_assert_ctl_arg.vl79n38tuserpagev_user/tocover_final_deferred_immediate_79htop.t.cover_final_deferred_immediate_79' 0
C 'ft/t_assert_ctl_arg.vl79n41tuserpagev_user/tocover_observed_deferred_immediate_79htop.t.cover_observed_deferred_immediate_79' 0
C 'ft/t_assert_ctl_arg.vl79n43tuserpagev_user/tocover_final_deferred_immediate_stmt_79htop.t.cover_final_deferred_immediate_stmt_79' 0
C 'ft/t_assert_ctl_arg.vl79n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_79htop.t.cover_observed_deferred_immediate_stmt_79' 0
C 'ft/t_assert_ctl_arg.vl81n30tuserpagev_user/tocover_simple_immediate_81htop.t.cover_simple_immediate_81' 1
C 'ft/t_assert_ctl_arg.vl81n35tuserpagev_user/tocover_simple_immediate_stmt_81htop.t.cover_simple_immediate_stmt_81' 1
C 'ft/t_assert_ctl_arg.vl81n38tuserpagev_user/tocover_final_deferred_immediate_81htop.t.cover_final_deferred_immediate_81' 0
C 'ft/t_assert_ctl_arg.vl81n41tuserpagev_user/tocover_observed_deferred_immediate_81htop.t.cover_observed_deferred_immediate_81' 0
C 'ft/t_assert_ctl_arg.vl81n43tuserpagev_user/tocover_final_deferred_immediate_stmt_81htop.t.cover_final_deferred_immediate_stmt_81' 0
C 'ft/t_assert_ctl_arg.vl81n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_81htop.t.cover_observed_deferred_immediate_stmt_81' 0
C 'ft/t_assert_ctl_arg.vl83n30tuserpagev_user/tocover_simple_immediate_83htop.t.cover_simple_immediate_83' 0
C 'ft/t_assert_ctl_arg.vl83n35tuserpagev_user/tocover_simple_immediate_stmt_83htop.t.cover_simple_immediate_stmt_83' 0
C 'ft/t_assert_ctl_arg.vl83n38tuserpagev_user/tocover_final_deferred_immediate_83htop.t.cover_final_deferred_immediate_83' 0
C 'ft/t_assert_ctl_arg.vl83n41tuserpagev_user/tocover_observed_deferred_immediate_83htop.t.cover_observed_deferred_immediate_83' 0
C 'ft/t_assert_ctl_arg.vl83n43tuserpagev_user/tocover_final_deferred_immediate_stmt_83htop.t.cover_final_deferred_immediate_stmt_83' 0
C 'ft/t_assert_ctl_arg.vl83n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_83htop.t.cover_observed_deferred_immediate_stmt_83' 0
C 'ft/t_assert_ctl_arg.vl85n30tuserpagev_user/tocover_simple_immediate_85htop.t.cover_simple_immediate_85' 1
C 'ft/t_assert_ctl_arg.vl85n35tuserpagev_user/tocover_simple_immediate_stmt_85htop.t.cover_simple_immediate_stmt_85' 1
C 'ft/t_assert_ctl_arg.vl85n38tuserpagev_user/tocover_final_deferred_immediate_85htop.t.cover_final_deferred_immediate_85' 0
C 'ft/t_assert_ctl_arg.vl85n41tuserpagev_user/tocover_observed_deferred_immediate_85htop.t.cover_observed_deferred_immediate_85' 0
C 'ft/t_assert_ctl_arg.vl85n43tuserpagev_user/tocover_final_deferred_immediate_stmt_85htop.t.cover_final_deferred_immediate_stmt_85' 0
C 'ft/t_assert_ctl_arg.vl85n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_85htop.t.cover_observed_deferred_immediate_stmt_85' 0
C 'ft/t_assert_ctl_arg.vl87n30tuserpagev_user/tocover_simple_immediate_87htop.t.cover_simple_immediate_87' 0
C 'ft/t_assert_ctl_arg.vl87n35tuserpagev_user/tocover_simple_immediate_stmt_87htop.t.cover_simple_immediate_stmt_87' 0
C 'ft/t_assert_ctl_arg.vl87n38tuserpagev_user/tocover_final_deferred_immediate_87htop.t.cover_final_deferred_immediate_87' 0
C 'ft/t_assert_ctl_arg.vl87n41tuserpagev_user/tocover_observed_deferred_immediate_87htop.t.cover_observed_deferred_immediate_87' 0
C 'ft/t_assert_ctl_arg.vl87n43tuserpagev_user/tocover_final_deferred_immediate_stmt_87htop.t.cover_final_deferred_immediate_stmt_87' 0
C 'ft/t_assert_ctl_arg.vl87n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_87htop.t.cover_observed_deferred_immediate_stmt_87' 0
C 'ft/t_assert_ctl_arg.vl89n30tuserpagev_user/tocover_simple_immediate_89htop.t.cover_simple_immediate_89' 1
C 'ft/t_assert_ctl_arg.vl89n35tuserpagev_user/tocover_simple_immediate_stmt_89htop.t.cover_simple_immediate_stmt_89' 1
C 'ft/t_assert_ctl_arg.vl89n38tuserpagev_user/tocover_final_deferred_immediate_89htop.t.cover_final_deferred_immediate_89' 1
C 'ft/t_assert_ctl_arg.vl89n41tuserpagev_user/tocover_observed_deferred_immediate_89htop.t.cover_observed_deferred_immediate_89' 1
C 'ft/t_assert_ctl_arg.vl89n43tuserpagev_user/tocover_final_deferred_immediate_stmt_89htop.t.cover_final_deferred_immediate_stmt_89' 1
C 'ft/t_assert_ctl_arg.vl89n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_89htop.t.cover_observed_deferred_immediate_stmt_89' 1
C 'ft/t_assert_ctl_arg.vl91n30tuserpagev_user/tocover_simple_immediate_91htop.t.cover_simple_immediate_91' 0
C 'ft/t_assert_ctl_arg.vl91n35tuserpagev_user/tocover_simple_immediate_stmt_91htop.t.cover_simple_immediate_stmt_91' 0
C 'ft/t_assert_ctl_arg.vl91n38tuserpagev_user/tocover_final_deferred_immediate_91htop.t.cover_final_deferred_immediate_91' 0
C 'ft/t_assert_ctl_arg.vl91n41tuserpagev_user/tocover_observed_deferred_immediate_91htop.t.cover_observed_deferred_immediate_91' 0
C 'ft/t_assert_ctl_arg.vl91n43tuserpagev_user/tocover_final_deferred_immediate_stmt_91htop.t.cover_final_deferred_immediate_stmt_91' 0
C 'ft/t_assert_ctl_arg.vl91n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_91htop.t.cover_observed_deferred_immediate_stmt_91' 0
C 'ft/t_assert_ctl_arg.vl96n30tuserpagev_user/tocover_simple_immediate_96htop.t.cover_simple_immediate_96' 0
C 'ft/t_assert_ctl_arg.vl96n35tuserpagev_user/tocover_simple_immediate_stmt_96htop.t.cover_simple_immediate_stmt_96' 0
C 'ft/t_assert_ctl_arg.vl96n38tuserpagev_user/tocover_final_deferred_immediate_96htop.t.cover_final_deferred_immediate_96' 0
C 'ft/t_assert_ctl_arg.vl96n41tuserpagev_user/tocover_observed_deferred_immediate_96htop.t.cover_observed_deferred_immediate_96' 0
C 'ft/t_assert_ctl_arg.vl96n43tuserpagev_user/tocover_final_deferred_immediate_stmt_96htop.t.cover_final_deferred_immediate_stmt_96' 0
C 'ft/t_assert_ctl_arg.vl96n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_96htop.t.cover_observed_deferred_immediate_stmt_96' 0
C 'ft/t_assert_ctl_arg.vl99n30tuserpagev_user/tocover_simple_immediate_99htop.t.cover_simple_immediate_99' 1
C 'ft/t_assert_ctl_arg.vl99n35tuserpagev_user/tocover_simple_immediate_stmt_99htop.t.cover_simple_immediate_stmt_99' 1
C 'ft/t_assert_ctl_arg.vl99n38tuserpagev_user/tocover_final_deferred_immediate_99htop.t.cover_final_deferred_immediate_99' 1
C 'ft/t_assert_ctl_arg.vl99n41tuserpagev_user/tocover_observed_deferred_immediate_99htop.t.cover_observed_deferred_immediate_99' 1
C 'ft/t_assert_ctl_arg.vl99n43tuserpagev_user/tocover_final_deferred_immediate_stmt_99htop.t.cover_final_deferred_immediate_stmt_99' 1
C 'ft/t_assert_ctl_arg.vl99n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_99htop.t.cover_observed_deferred_immediate_stmt_99' 1

726
test_regress/t/t_assert_ctl_arg.out
View File

@ -1,416 +1,416 @@
==========
Running all asserts at: t/t_assert_ctl_arg.v:49
Running all asserts at: t/t_assert_ctl_arg.v:48
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:49
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
-Info: t/t_assert_ctl_arg.v:137: Verilog $stop, ignored due to +verilator+error+limit
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:49
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:49
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:49
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:49
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:49
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:49
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:49
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:49
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:49
Passed 'top.t.cover_simple_immediate_stmt_49' at t/t_assert_ctl_arg.v:49
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:48
[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
-Info: t/t_assert_ctl_arg.v:136: Verilog $stop, ignored due to +verilator+error+limit
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:48
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:48
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:48
[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:48
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:48
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:48
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:48
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:48
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:48
Passed 'top.t.cover_simple_immediate_stmt_48' at t/t_assert_ctl_arg.v:48
==========
Running all asserts at: t/t_assert_ctl_arg.v:51
Running all asserts at: t/t_assert_ctl_arg.v:50
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:51
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:51
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:51
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:51
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:51
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:51
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:50
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:50
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:50
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:50
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:50
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:50
==========
Running all asserts at: t/t_assert_ctl_arg.v:56
Running all asserts at: t/t_assert_ctl_arg.v:55
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:56
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:56
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:56
[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:56
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:56
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:56
[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:56
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:56
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:56
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:56
Passed 'top.t.cover_observed_deferred_immediate_stmt_56' at t/t_assert_ctl_arg.v:56
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:55
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:55
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:55
[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:55
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:55
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:55
[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:55
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:55
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:55
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:55
Passed 'top.t.cover_observed_deferred_immediate_stmt_55' at t/t_assert_ctl_arg.v:55
==========
Running all asserts at: t/t_assert_ctl_arg.v:58
Running all asserts at: t/t_assert_ctl_arg.v:57
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:58
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:58
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:58
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:58
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:58
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:58
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:57
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:57
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:57
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:57
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:57
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:57
==========
Running all asserts at: t/t_assert_ctl_arg.v:63
Running all asserts at: t/t_assert_ctl_arg.v:62
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:63
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:63
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:63
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:63
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:63
[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:63
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:63
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:63
[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:63
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:63
Passed 'top.t.cover_final_deferred_immediate_stmt_63' at t/t_assert_ctl_arg.v:63
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:62
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:62
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:62
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:62
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:62
[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:62
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:62
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:62
[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:62
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:62
Passed 'top.t.cover_final_deferred_immediate_stmt_62' at t/t_assert_ctl_arg.v:62
==========
Running all asserts at: t/t_assert_ctl_arg.v:65
Running all asserts at: t/t_assert_ctl_arg.v:64
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:65
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:65
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:65
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:65
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:65
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:65
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:64
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:64
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:64
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:64
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:64
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:64
==========
Running all asserts at: t/t_assert_ctl_arg.v:69
Running all asserts at: t/t_assert_ctl_arg.v:68
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:69
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:69
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:69
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:69
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:69
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:69
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:68
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:68
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:68
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:68
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:68
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:68
==========
Running all asserts at: t/t_assert_ctl_arg.v:71
Running all asserts at: t/t_assert_ctl_arg.v:70
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:71
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:71
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:71
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:71
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:71
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:71
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:71
[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:71
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:71
[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:71
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:71
[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:71
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:71
[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:71
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71
Passed 'top.t.cover_simple_immediate_stmt_71' at t/t_assert_ctl_arg.v:71
Passed 'top.t.cover_observed_deferred_immediate_stmt_71' at t/t_assert_ctl_arg.v:71
Passed 'top.t.cover_final_deferred_immediate_stmt_71' at t/t_assert_ctl_arg.v:71
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:70
[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:70
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:70
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:70
[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:70
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:70
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:70
[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:70
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:70
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:70
[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:70
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:70
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:70
[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:70
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:70
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:70
[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:70
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:70
Passed 'top.t.cover_simple_immediate_stmt_70' at t/t_assert_ctl_arg.v:70
Passed 'top.t.cover_observed_deferred_immediate_stmt_70' at t/t_assert_ctl_arg.v:70
Passed 'top.t.cover_final_deferred_immediate_stmt_70' at t/t_assert_ctl_arg.v:70
==========
Running all asserts at: t/t_assert_ctl_arg.v:73
Running all asserts at: t/t_assert_ctl_arg.v:72
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:73
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:73
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:73
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:73
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:73
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:73
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:72
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:72
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:72
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:72
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:72
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:72
==========
Running all asserts at: t/t_assert_ctl_arg.v:76
Running all asserts at: t/t_assert_ctl_arg.v:75
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:76
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:76
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:76
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:76
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:76
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:76
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:76
[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:76
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:76
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:76
[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:76
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:76
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:76
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:76
Passed 'top.t.cover_simple_immediate_stmt_76' at t/t_assert_ctl_arg.v:76
Passed 'top.t.cover_observed_deferred_immediate_stmt_76' at t/t_assert_ctl_arg.v:76
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:75
[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:75
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:75
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:75
[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:75
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:75
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:75
[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:75
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:75
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:75
[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:75
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:75
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:75
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:75
Passed 'top.t.cover_simple_immediate_stmt_75' at t/t_assert_ctl_arg.v:75
Passed 'top.t.cover_observed_deferred_immediate_stmt_75' at t/t_assert_ctl_arg.v:75
==========
Running all asserts at: t/t_assert_ctl_arg.v:78
Running all asserts at: t/t_assert_ctl_arg.v:77
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:78
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:78
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:78
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:78
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:78
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:78
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:78
[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:78
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:78
[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:78
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:78
[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:78
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:78
[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:78
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78
Passed 'top.t.cover_simple_immediate_stmt_78' at t/t_assert_ctl_arg.v:78
Passed 'top.t.cover_observed_deferred_immediate_stmt_78' at t/t_assert_ctl_arg.v:78
Passed 'top.t.cover_final_deferred_immediate_stmt_78' at t/t_assert_ctl_arg.v:78
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:77
[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:77
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:77
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:77
[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:77
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:77
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:77
[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:77
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:77
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:77
[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:77
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:77
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:77
[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:77
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:77
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:77
[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:77
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:77
Passed 'top.t.cover_simple_immediate_stmt_77' at t/t_assert_ctl_arg.v:77
Passed 'top.t.cover_observed_deferred_immediate_stmt_77' at t/t_assert_ctl_arg.v:77
Passed 'top.t.cover_final_deferred_immediate_stmt_77' at t/t_assert_ctl_arg.v:77
==========
Running all asserts at: t/t_assert_ctl_arg.v:80
Running all asserts at: t/t_assert_ctl_arg.v:79
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:80
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:80
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:80
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:80
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:80
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:80
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:80
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:80
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:80
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:80
Passed 'top.t.cover_simple_immediate_stmt_80' at t/t_assert_ctl_arg.v:80
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:79
[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:79
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:79
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:79
[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:79
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:79
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:79
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:79
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:79
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:79
Passed 'top.t.cover_simple_immediate_stmt_79' at t/t_assert_ctl_arg.v:79
==========
Running all asserts at: t/t_assert_ctl_arg.v:82
Running all asserts at: t/t_assert_ctl_arg.v:81
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:82
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:82
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:82
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:82
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:82
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:82
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:82
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:82
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:82
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:82
Passed 'top.t.cover_simple_immediate_stmt_82' at t/t_assert_ctl_arg.v:82
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:81
[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:81
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:81
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:81
[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:81
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:81
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:81
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:81
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:81
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:81
Passed 'top.t.cover_simple_immediate_stmt_81' at t/t_assert_ctl_arg.v:81
==========
Running all asserts at: t/t_assert_ctl_arg.v:84
Running all asserts at: t/t_assert_ctl_arg.v:83
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:84
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:84
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:84
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:84
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:84
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:84
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:83
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:83
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:83
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:83
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:83
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:83
==========
Running all asserts at: t/t_assert_ctl_arg.v:86
Running all asserts at: t/t_assert_ctl_arg.v:85
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:86
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:86
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:86
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:86
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:86
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:86
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:86
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:86
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:86
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:86
Passed 'top.t.cover_simple_immediate_stmt_86' at t/t_assert_ctl_arg.v:86
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:85
[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:85
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:85
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:85
[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:85
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:85
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:85
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:85
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:85
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:85
Passed 'top.t.cover_simple_immediate_stmt_85' at t/t_assert_ctl_arg.v:85
==========
Running all asserts at: t/t_assert_ctl_arg.v:88
Running all asserts at: t/t_assert_ctl_arg.v:87
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:88
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:88
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:88
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:88
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:88
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:88
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:87
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:87
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:87
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:87
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:87
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:87
==========
Running all asserts at: t/t_assert_ctl_arg.v:90
Running all asserts at: t/t_assert_ctl_arg.v:89
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:90
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:90
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:90
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:90
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:90
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:90
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:90
[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:90
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:90
[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:90
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:90
[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:90
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:90
[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:90
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90
Passed 'top.t.cover_simple_immediate_stmt_90' at t/t_assert_ctl_arg.v:90
Passed 'top.t.cover_observed_deferred_immediate_stmt_90' at t/t_assert_ctl_arg.v:90
Passed 'top.t.cover_final_deferred_immediate_stmt_90' at t/t_assert_ctl_arg.v:90
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:89
[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:89
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:89
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:89
[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:89
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:89
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:89
[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:89
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:89
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:89
[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:89
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:89
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:89
[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:89
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:89
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:89
[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:89
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:89
Passed 'top.t.cover_simple_immediate_stmt_89' at t/t_assert_ctl_arg.v:89
Passed 'top.t.cover_observed_deferred_immediate_stmt_89' at t/t_assert_ctl_arg.v:89
Passed 'top.t.cover_final_deferred_immediate_stmt_89' at t/t_assert_ctl_arg.v:89
==========
Running all asserts at: t/t_assert_ctl_arg.v:92
Running all asserts at: t/t_assert_ctl_arg.v:91
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:92
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:92
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:92
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:92
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:92
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:92
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:91
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:91
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:91
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:91
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:91
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:91
==========
Running all asserts at: t/t_assert_ctl_arg.v:97
Running all asserts at: t/t_assert_ctl_arg.v:96
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:97
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:97
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:97
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:97
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:97
[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:97
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:97
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:97
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:97
[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:97
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:97
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:97
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:96
[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:96
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:96
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:96
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:96
[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:96
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:96
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:96
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:96
[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:96
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:96
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:96
==========
Running all asserts at: t/t_assert_ctl_arg.v:100
Running all asserts at: t/t_assert_ctl_arg.v:99
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:100
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:100
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:100
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:100
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:100
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:100
Passed 'top.t.cover_simple_immediate_stmt_100' at t/t_assert_ctl_arg.v:100
Passed 'top.t.cover_observed_deferred_immediate_stmt_100' at t/t_assert_ctl_arg.v:100
Passed 'top.t.cover_final_deferred_immediate_stmt_100' at t/t_assert_ctl_arg.v:100
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:99
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:99
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:99
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:99
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:99
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:99
Passed 'top.t.cover_simple_immediate_stmt_99' at t/t_assert_ctl_arg.v:99
Passed 'top.t.cover_observed_deferred_immediate_stmt_99' at t/t_assert_ctl_arg.v:99
Passed 'top.t.cover_final_deferred_immediate_stmt_99' at t/t_assert_ctl_arg.v:99
==========
Running all asserts at: t/t_assert_ctl_arg.v:103
Running all asserts at: t/t_assert_ctl_arg.v:102
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:103
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:103
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:103
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:103
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:103
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:103
[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:103
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:103
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:103
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:103
[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:103
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:103
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:102
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:102
[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:102
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:102
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:102
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:102
[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:102
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:102
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:102
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:102
[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:102
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:102
==========
Running all asserts at: t/t_assert_ctl_arg.v:106
Running all asserts at: t/t_assert_ctl_arg.v:105
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:106
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:106
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:106
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:106
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:106
[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:106
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:106
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:106
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:106
[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:106
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:106
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:106
Passed 'top.t.cover_simple_immediate_stmt_106' at t/t_assert_ctl_arg.v:106
Passed 'top.t.cover_observed_deferred_immediate_stmt_106' at t/t_assert_ctl_arg.v:106
Passed 'top.t.cover_final_deferred_immediate_stmt_106' at t/t_assert_ctl_arg.v:106
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:105
[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:105
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:105
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:105
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:105
[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:105
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:105
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:105
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:105
[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:105
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:105
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:105
Passed 'top.t.cover_simple_immediate_stmt_105' at t/t_assert_ctl_arg.v:105
Passed 'top.t.cover_observed_deferred_immediate_stmt_105' at t/t_assert_ctl_arg.v:105
Passed 'top.t.cover_final_deferred_immediate_stmt_105' at t/t_assert_ctl_arg.v:105
==========
Running all asserts at: t/t_assert_ctl_arg.v:108
Running all asserts at: t/t_assert_ctl_arg.v:107
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:108
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:108
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:108
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:108
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:108
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:108
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:108
[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:108
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:108
[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:108
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:108
[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:108
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:108
[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:108
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108
Passed 'top.t.cover_simple_immediate_stmt_108' at t/t_assert_ctl_arg.v:108
Passed 'top.t.cover_observed_deferred_immediate_stmt_108' at t/t_assert_ctl_arg.v:108
Passed 'top.t.cover_final_deferred_immediate_stmt_108' at t/t_assert_ctl_arg.v:108
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:107
[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:107
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:107
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:107
[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:107
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:107
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:107
[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:107
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:107
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:107
[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:107
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:107
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:107
[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:107
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:107
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:107
[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:107
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:107
Passed 'top.t.cover_simple_immediate_stmt_107' at t/t_assert_ctl_arg.v:107
Passed 'top.t.cover_observed_deferred_immediate_stmt_107' at t/t_assert_ctl_arg.v:107
Passed 'top.t.cover_final_deferred_immediate_stmt_107' at t/t_assert_ctl_arg.v:107
==========
Running all asserts at: t/t_assert_ctl_arg.v:110
Running all asserts at: t/t_assert_ctl_arg.v:109
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:110
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:110
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:110
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:110
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:110
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:110
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:109
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:109
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:109
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:109
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:109
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:109
==========
Running all asserts at: t/t_assert_ctl_arg.v:112
Running all asserts at: t/t_assert_ctl_arg.v:111
==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:112
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:112
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:112
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:112
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:112
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:112
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:112
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:112
[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:112
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:112
Passed 'top.t.cover_simple_immediate_stmt_112' at t/t_assert_ctl_arg.v:112
Passed 'top.t.cover_final_deferred_immediate_stmt_112' at t/t_assert_ctl_arg.v:112
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:111
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:111
[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:111
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:111
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:111
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:111
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:111
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:111
[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:111
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:111
Passed 'top.t.cover_simple_immediate_stmt_111' at t/t_assert_ctl_arg.v:111
Passed 'top.t.cover_final_deferred_immediate_stmt_111' at t/t_assert_ctl_arg.v:111
Disabling concurrent asserts, time: 10
Enabling concurrent asserts, time: 20
*-* All Finished *-*
[20] %Error: t_assert_ctl_arg.v:182: Assertion failed in top.t.concurrent.assert_concurrent: 'assert' failed.
Failed 'top.t.concurrent.assert_concurrent_else' at t/t_assert_ctl_arg.v:183
Failed 'top.t.concurrent.assert_concurrent_stmt_else' at t/t_assert_ctl_arg.v:185
[20] %Error: t_assert_ctl_arg.v:187: Assertion failed in top.t.concurrent.assume_concurrent: 'assert' failed.
Failed 'top.t.concurrent.assume_concurrent_else' at t/t_assert_ctl_arg.v:188
Failed 'top.t.concurrent.assume_concurrent_stmt_else' at t/t_assert_ctl_arg.v:190
[20] %Error: t_assert_ctl_arg.v:181: Assertion failed in top.t.concurrent.assert_concurrent: 'assert' failed.
Failed 'top.t.concurrent.assert_concurrent_else' at t/t_assert_ctl_arg.v:182
Failed 'top.t.concurrent.assert_concurrent_stmt_else' at t/t_assert_ctl_arg.v:184
[20] %Error: t_assert_ctl_arg.v:186: Assertion failed in top.t.concurrent.assume_concurrent: 'assert' failed.
Failed 'top.t.concurrent.assume_concurrent_else' at t/t_assert_ctl_arg.v:187
Failed 'top.t.concurrent.assume_concurrent_stmt_else' at t/t_assert_ctl_arg.v:189

293
test_regress/t/t_assert_ctl_arg.v
View File

@ -5,190 +5,189 @@
// SPDX-License-Identifier: CC0-1.0
`define DISPLAY_PASS(file, line) \
$display("Passed '%m' at %s:%g", file, line)
$display("Passed '%m' at %s:%g", file, line)
`define DISPLAY_FAIL(file, line) \
$display("Failed '%m' at %s:%g", file, line)
$display("Failed '%m' at %s:%g", file, line)
`define RUN_ALL_ASSERTS \
$display("==========\nRunning all asserts at: %s:%g\n==========", `__FILE__, `__LINE__); \
run_all_asserts(`__FILE__, `__LINE__); \
cover_simple_immediate_`__LINE__: cover(1); \
cover_simple_immediate_stmt_`__LINE__: cover(1) `DISPLAY_PASS(`__FILE__, `__LINE__); \
cover_observed_deferred_immediate_`__LINE__: cover #0 (1); \
cover_observed_deferred_immediate_stmt_`__LINE__: cover #0 (1) `DISPLAY_PASS(`__FILE__, `__LINE__); \
cover_final_deferred_immediate_`__LINE__: cover final (1); \
cover_final_deferred_immediate_stmt_`__LINE__: cover final (1) `DISPLAY_PASS(`__FILE__, `__LINE__); \
$display("==========\nRunning all asserts at: %s:%g\n==========", `__FILE__, `__LINE__); \
run_all_asserts(`__FILE__, `__LINE__); \
cover_simple_immediate_`__LINE__: cover(1); \
cover_simple_immediate_stmt_`__LINE__: cover(1) `DISPLAY_PASS(`__FILE__, `__LINE__); \
cover_observed_deferred_immediate_`__LINE__: cover #0 (1); \
cover_observed_deferred_immediate_stmt_`__LINE__: cover #0 (1) `DISPLAY_PASS(`__FILE__, `__LINE__); \
cover_final_deferred_immediate_`__LINE__: cover final (1); \
cover_final_deferred_immediate_stmt_`__LINE__: cover final (1) `DISPLAY_PASS(`__FILE__, `__LINE__); \
module t (/*AUTOARG*/
clk
);
input clk;
module t (
input clk
);
let On = 3;
let Off = 4;
let Kill = 5;
let On = 3;
let Off = 4;
let Kill = 5;
let CONCURRENT = 1;
let SIMPLE_IMMEDIATE = 2;
let OBSERVED_DEFERRED_IMMEDIATE = 4;
let FINAL_DEFERRED_IMMEDIATE = 8;
let CONCURRENT = 1;
let SIMPLE_IMMEDIATE = 2;
let OBSERVED_DEFERRED_IMMEDIATE = 4;
let FINAL_DEFERRED_IMMEDIATE = 8;
let ALL_TYPES = CONCURRENT|SIMPLE_IMMEDIATE|OBSERVED_DEFERRED_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE;
let ALL_TYPES = CONCURRENT|SIMPLE_IMMEDIATE|OBSERVED_DEFERRED_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE;
let ASSERT = 1;
let COVER = 2;
let ASSUME = 4;
let ASSERT = 1;
let COVER = 2;
let ASSUME = 4;
concurrent concurrent(.clk(clk));
concurrent concurrent(.clk(clk));
initial begin
// simple immediate
$assertcontrol(Off, ALL_TYPES);
$assertcontrol(On, SIMPLE_IMMEDIATE);
`RUN_ALL_ASSERTS
$assertcontrol(Off, SIMPLE_IMMEDIATE);
`RUN_ALL_ASSERTS
initial begin
// simple immediate
$assertcontrol(Off, ALL_TYPES);
$assertcontrol(On, SIMPLE_IMMEDIATE);
`RUN_ALL_ASSERTS
$assertcontrol(Off, SIMPLE_IMMEDIATE);
`RUN_ALL_ASSERTS
// observed deferred immediate
$assertcontrol(Off, ALL_TYPES);
$assertcontrol(On, OBSERVED_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS
$assertcontrol(Off, OBSERVED_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS
// observed deferred immediate
$assertcontrol(Off, ALL_TYPES);
$assertcontrol(On, OBSERVED_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS
$assertcontrol(Off, OBSERVED_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS
// final deferred immediate
$assertcontrol(Off, ALL_TYPES);
$assertcontrol(On, FINAL_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS
$assertcontrol(Off, FINAL_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS
// final deferred immediate
$assertcontrol(Off, ALL_TYPES);
$assertcontrol(On, FINAL_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS
$assertcontrol(Off, FINAL_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS
// on, off, kill test
$assertoff;
`RUN_ALL_ASSERTS;
$asserton;
`RUN_ALL_ASSERTS;
$assertkill;
`RUN_ALL_ASSERTS;
// on, off, kill test
$assertoff;
`RUN_ALL_ASSERTS;
$asserton;
`RUN_ALL_ASSERTS;
$assertkill;
`RUN_ALL_ASSERTS;
$assertcontrol(On, SIMPLE_IMMEDIATE|OBSERVED_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS;
$assertcontrol(On, FINAL_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS;
$assertcontrol(Off, OBSERVED_DEFERRED_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS;
$assertcontrol(Off, FINAL_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS;
$assertcontrol(Off, SIMPLE_IMMEDIATE);
`RUN_ALL_ASSERTS;
$assertcontrol(On, SIMPLE_IMMEDIATE);
`RUN_ALL_ASSERTS;
$assertcontrol(Off, ALL_TYPES);
`RUN_ALL_ASSERTS;
$assertcontrol(On, ALL_TYPES);
`RUN_ALL_ASSERTS;
$assertcontrol(Kill, ALL_TYPES);
`RUN_ALL_ASSERTS;
$assertcontrol(On, SIMPLE_IMMEDIATE|OBSERVED_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS;
$assertcontrol(On, FINAL_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS;
$assertcontrol(Off, OBSERVED_DEFERRED_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS;
$assertcontrol(Off, FINAL_DEFERRED_IMMEDIATE);
`RUN_ALL_ASSERTS;
$assertcontrol(Off, SIMPLE_IMMEDIATE);
`RUN_ALL_ASSERTS;
$assertcontrol(On, SIMPLE_IMMEDIATE);
`RUN_ALL_ASSERTS;
$assertcontrol(Off, ALL_TYPES);
`RUN_ALL_ASSERTS;
$assertcontrol(On, ALL_TYPES);
`RUN_ALL_ASSERTS;
$assertcontrol(Kill, ALL_TYPES);
`RUN_ALL_ASSERTS;
// directive_type test
$assertoff;
$assertcontrol(On, ALL_TYPES, ASSERT);
`RUN_ALL_ASSERTS;
$assertcontrol(Off, ALL_TYPES, ASSERT);
$assertcontrol(On, ALL_TYPES, COVER);
`RUN_ALL_ASSERTS;
$assertcontrol(Off, ALL_TYPES, COVER);
$assertcontrol(On, ALL_TYPES, ASSUME);
`RUN_ALL_ASSERTS;
$assertcontrol(Off, ALL_TYPES, ASSUME);
$assertcontrol(On, ALL_TYPES, ASSERT|COVER);
`RUN_ALL_ASSERTS;
$assertcontrol(On, ALL_TYPES, ASSUME);
`RUN_ALL_ASSERTS;
$assertoff;
`RUN_ALL_ASSERTS;
$assertcontrol(On, SIMPLE_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE, COVER|ASSUME);
`RUN_ALL_ASSERTS;
$assertoff;
// directive_type test
$assertoff;
$assertcontrol(On, ALL_TYPES, ASSERT);
`RUN_ALL_ASSERTS;
$assertcontrol(Off, ALL_TYPES, ASSERT);
$assertcontrol(On, ALL_TYPES, COVER);
`RUN_ALL_ASSERTS;
$assertcontrol(Off, ALL_TYPES, COVER);
$assertcontrol(On, ALL_TYPES, ASSUME);
`RUN_ALL_ASSERTS;
$assertcontrol(Off, ALL_TYPES, ASSUME);
$assertcontrol(On, ALL_TYPES, ASSERT|COVER);
`RUN_ALL_ASSERTS;
$assertcontrol(On, ALL_TYPES, ASSUME);
`RUN_ALL_ASSERTS;
$assertoff;
`RUN_ALL_ASSERTS;
$assertcontrol(On, SIMPLE_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE, COVER|ASSUME);
`RUN_ALL_ASSERTS;
$assertoff;
// concurrent test
#10;
$display("Disabling concurrent asserts, time: %g", $time);
$assertcontrol(On, ALL_TYPES);
$assertcontrol(Off, CONCURRENT);
#10;
$display("Enabling concurrent asserts, time: %g", $time);
$assertcontrol(On, CONCURRENT);
// concurrent test
#10;
$display("Disabling concurrent asserts, time: %g", $time);
$assertcontrol(On, ALL_TYPES);
$assertcontrol(Off, CONCURRENT);
#10;
$display("Enabling concurrent asserts, time: %g", $time);
$assertcontrol(On, CONCURRENT);
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
task run_all_asserts(string file, integer line);
run_simple_immediate(file, line);
run_observed_deferred_immediate(file, line);
run_final_deferred_immediate(file, line);
run_simple_immediate(file, line);
run_observed_deferred_immediate(file, line);
run_final_deferred_immediate(file, line);
endtask
task run_simple_immediate(string file, integer line);
$display("Testing assert_simple_immediate at %s:%g", file, line);
assert_simple_immediate: assert(0);
assert_simple_immediate_else: assert(0) else `DISPLAY_FAIL(file, line);
assert_simple_immediate_stmt: assert(0) `DISPLAY_PASS(file, line);
assert_simple_immediate_stmt_else: assert(0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line);
$display("Testing assert_simple_immediate at %s:%g", file, line);
assert_simple_immediate: assert(0);
assert_simple_immediate_else: assert(0) else `DISPLAY_FAIL(file, line);
assert_simple_immediate_stmt: assert(0) `DISPLAY_PASS(file, line);
assert_simple_immediate_stmt_else: assert(0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line);
$display("Testing assume_simple_immediate at %s:%g", file, line);
assume_simple_immediate: assume(0);
assume_simple_immediate_else: assume(0) else `DISPLAY_FAIL(file, line);
assume_simple_immediate_stmt: assume(0) `DISPLAY_PASS(file, line);
assume_simple_immediate_stmt_else: assume(0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line);
$display("Testing assume_simple_immediate at %s:%g", file, line);
assume_simple_immediate: assume(0);
assume_simple_immediate_else: assume(0) else `DISPLAY_FAIL(file, line);
assume_simple_immediate_stmt: assume(0) `DISPLAY_PASS(file, line);
assume_simple_immediate_stmt_else: assume(0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line);
endtask
task run_observed_deferred_immediate(string file, integer line);
$display("Testing assert_observed_deferred_immediate at %s:%g", file, line);
assert_observed_deferred_immediate: assert #0 (0);
assert_observed_deferred_immediate_else: assert #0 (0) else `DISPLAY_FAIL(file, line);
assert_observed_deferred_immediate_stmt: assert #0 (0) `DISPLAY_PASS(file, line);
assert_observed_deferred_immediate_stmt_else: assert #0 (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line);
$display("Testing assert_observed_deferred_immediate at %s:%g", file, line);
assert_observed_deferred_immediate: assert #0 (0);
assert_observed_deferred_immediate_else: assert #0 (0) else `DISPLAY_FAIL(file, line);
assert_observed_deferred_immediate_stmt: assert #0 (0) `DISPLAY_PASS(file, line);
assert_observed_deferred_immediate_stmt_else: assert #0 (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line);
$display("Testing assume_observed_deferred_immediate at %s:%g", file, line);
assume_observed_deferred_immediate: assume #0 (0);
assume_observed_deferred_immediate_else: assume #0 (0) else `DISPLAY_FAIL(file, line);
assume_observed_deferred_immediate_stmt: assume #0 (0) `DISPLAY_PASS(file, line);
assume_observed_deferred_immediate_stmt_else: assume #0 (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line);
$display("Testing assume_observed_deferred_immediate at %s:%g", file, line);
assume_observed_deferred_immediate: assume #0 (0);
assume_observed_deferred_immediate_else: assume #0 (0) else `DISPLAY_FAIL(file, line);
assume_observed_deferred_immediate_stmt: assume #0 (0) `DISPLAY_PASS(file, line);
assume_observed_deferred_immediate_stmt_else: assume #0 (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line);
endtask
task run_final_deferred_immediate(string file, integer line);
$display("Testing assert_final_deferred_immediate at %s:%g", file, line);
assert_final_deferred_immediate: assert final (0);
assert_final_deferred_immediate_else: assert final (0) else `DISPLAY_FAIL(file, line);
assert_final_deferred_immediate_stmt: assert final (0) `DISPLAY_PASS(file, line);
assert_final_deferred_immediate_stmt_else: assert final (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line);
$display("Testing assert_final_deferred_immediate at %s:%g", file, line);
assert_final_deferred_immediate: assert final (0);
assert_final_deferred_immediate_else: assert final (0) else `DISPLAY_FAIL(file, line);
assert_final_deferred_immediate_stmt: assert final (0) `DISPLAY_PASS(file, line);
assert_final_deferred_immediate_stmt_else: assert final (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line);
$display("Testing assume_final_deferred_immediate at %s:%g", file, line);
assume_final_deferred_immediate: assume final (0);
assume_final_deferred_immediate_else: assume final (0) else `DISPLAY_FAIL(file, line);
assume_final_deferred_immediate_stmt: assume final (0) `DISPLAY_PASS(file, line);
assume_final_deferred_immediate_stmt_else: assume final (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line);
$display("Testing assume_final_deferred_immediate at %s:%g", file, line);
assume_final_deferred_immediate: assume final (0);
assume_final_deferred_immediate_else: assume final (0) else `DISPLAY_FAIL(file, line);
assume_final_deferred_immediate_stmt: assume final (0) `DISPLAY_PASS(file, line);
assume_final_deferred_immediate_stmt_else: assume final (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line);
endtask
module concurrent(input clk);
property prop();
@(posedge clk) 0
endproperty
property prop();
@(posedge clk) 0
endproperty
assert_concurrent: assert property (prop);
assert_concurrent_else: assert property(prop) else `DISPLAY_FAIL(`__FILE__, `__LINE__);
assert_concurrent_stmt: assert property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__);
assert_concurrent_stmt_else: assert property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); else `DISPLAY_FAIL(`__FILE__, `__LINE__);
assert_concurrent: assert property (prop);
assert_concurrent_else: assert property(prop) else `DISPLAY_FAIL(`__FILE__, `__LINE__);
assert_concurrent_stmt: assert property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__);
assert_concurrent_stmt_else: assert property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); else `DISPLAY_FAIL(`__FILE__, `__LINE__);
assume_concurrent: assume property(prop);
assume_concurrent_else: assume property(prop) else `DISPLAY_FAIL(`__FILE__, `__LINE__);
assume_concurrent_stmt: assume property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__);
assume_concurrent_stmt_else: assume property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); else `DISPLAY_FAIL(`__FILE__, `__LINE__);
assume_concurrent: assume property(prop);
assume_concurrent_else: assume property(prop) else `DISPLAY_FAIL(`__FILE__, `__LINE__);
assume_concurrent_stmt: assume property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__);
assume_concurrent_stmt_else: assume property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); else `DISPLAY_FAIL(`__FILE__, `__LINE__);
cover_concurrent: cover property(prop);
cover_concurrent_stmt: cover property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__);
cover_concurrent: cover property(prop);
cover_concurrent_stmt: cover property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__);
endmodule

24
test_regress/t/t_assert_ctl_arg_unsup.out
View File

@ -1,18 +1,18 @@
%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:15:7: Unsupported: assert control assertion_type
%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:15:5: Unsupported: assert control assertion_type
: ... note: In instance 't'
15 | $assertcontrol(OFF, EXPECT);
| ^~~~~~~~~~~~~~
15 | $assertcontrol(OFF, EXPECT);
| ^~~~~~~~~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:16:7: Unsupported: assert control assertion_type
%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:16:5: Unsupported: assert control assertion_type
: ... note: In instance 't'
16 | $assertcontrol(OFF, UNIQUE);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:17:7: Unsupported: assert control assertion_type
16 | $assertcontrol(OFF, UNIQUE);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:17:5: Unsupported: assert control assertion_type
: ... note: In instance 't'
17 | $assertcontrol(OFF, UNIQUE0);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:18:7: Unsupported: assert control assertion_type
17 | $assertcontrol(OFF, UNIQUE0);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:18:5: Unsupported: assert control assertion_type
: ... note: In instance 't'
18 | $assertcontrol(OFF, PRIORITY);
| ^~~~~~~~~~~~~~
18 | $assertcontrol(OFF, PRIORITY);
| ^~~~~~~~~~~~~~
%Error: Exiting due to

22
test_regress/t/t_assert_ctl_arg_unsup.v
View File

@ -5,16 +5,16 @@
// SPDX-License-Identifier: CC0-1.0
module t;
let OFF = 4;
let EXPECT = 16;
let UNIQUE = 32;
let UNIQUE0 = 64;
let PRIORITY = 128;
let OFF = 4;
let EXPECT = 16;
let UNIQUE = 32;
let UNIQUE0 = 64;
let PRIORITY = 128;
initial begin
$assertcontrol(OFF, EXPECT);
$assertcontrol(OFF, UNIQUE);
$assertcontrol(OFF, UNIQUE0);
$assertcontrol(OFF, PRIORITY);
end
initial begin
$assertcontrol(OFF, EXPECT);
$assertcontrol(OFF, UNIQUE);
$assertcontrol(OFF, UNIQUE0);
$assertcontrol(OFF, PRIORITY);
end
endmodule

44
test_regress/t/t_assert_ctl_concurrent.v
View File

@ -6,39 +6,33 @@
module t;
bit clock = 1'b0;
bit reset = 1'b0;
bit clock = 1'b0;
bit reset = 1'b0;
initial begin
$assertkill;
initial begin
$assertkill;
#10
#10 reset = 1'b1;
$display("%t: deassert reset %d", $time, reset);
reset = 1'b1;
$display("%t: deassert reset %d", $time, reset);
#40 $asserton;
#40
reset = 1'b0;
$display("%t: deassert reset %d", $time, reset);
$asserton;
#200 $display("%t: finish", $time);
$write("*-* All Finished *-*\n");
$finish;
reset = 1'b0;
$display("%t: deassert reset %d", $time, reset);
end
#200
always #10 clock = ~clock;
reg r = 1'b0;
$display("%t: finish", $time);
$write("*-* All Finished *-*\n");
$finish;
always @(posedge clock) if (reset) r <= 1'b1;
end
always #10 clock = ~clock;
reg r = 1'b0;
always @(posedge clock) if (reset) r <= 1'b1;
assert_test:
assert property (@(posedge clock) (reset | r))
else $error("%t: assertion triggered", $time);
assert_test :
assert property (@(posedge clock) (reset | r))
else $error("%t: assertion triggered", $time);
endmodule

10
test_regress/t/t_assert_ctl_immediate.out
View File

@ -1,6 +1,6 @@
[0] %Error: t_assert_ctl_immediate.v:47: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
-Info: t/t_assert_ctl_immediate.v:47: Verilog $stop, ignored due to +verilator+error+limit
[0] %Error: t_assert_ctl_immediate.v:53: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
[0] %Error: t_assert_ctl_immediate.v:41: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed.
[0] %Error: t_assert_ctl_immediate.v:41: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed.
[0] %Error: t_assert_ctl_immediate.v:51: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
-Info: t/t_assert_ctl_immediate.v:51: Verilog $stop, ignored due to +verilator+error+limit
[0] %Error: t_assert_ctl_immediate.v:57: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
[0] %Error: t_assert_ctl_immediate.v:45: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed.
[0] %Error: t_assert_ctl_immediate.v:45: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed.
*-* All Finished *-*

90
test_regress/t/t_assert_ctl_immediate.v
View File

@ -4,58 +4,62 @@
// SPDX-FileCopyrightText: 2024 Antmicro
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
module_with_assert module_with_assert (clk);
module_with_assertctl module_with_assertctl (clk);
module_with_assert module_with_assert(clk);
module_with_assertctl module_with_assertctl(clk);
always @(posedge clk) begin
assert (0);
end
always @ (posedge clk) begin
assert(0);
end
always @ (negedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
always @(negedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module module_with_assert(input clk);
always @(posedge clk) assert(0);
module module_with_assert (
input clk
);
always @(posedge clk) assert (0);
endmodule
module module_with_assertctl(input clk);
function void assert_off; begin
module module_with_assertctl (
input clk
);
function void assert_off;
begin
$assertoff;
end
endfunction
function void assert_on; begin
end
endfunction
function void assert_on;
begin
$asserton;
end
endfunction
function void f_assert; begin
assert(0);
end
endfunction
end
endfunction
function void f_assert;
begin
assert (0);
end
endfunction
initial begin
assert_on();
assert(0);
assert_off();
assert_off();
assert(0);
assert_on();
assert_on();
assert(0);
initial begin
assert_on();
assert (0);
assert_off();
assert_off();
assert (0);
assert_on();
assert_on();
assert (0);
f_assert();
f_assert();
assert_off();
f_assert();
f_assert();
end
f_assert();
f_assert();
assert_off();
f_assert();
f_assert();
end
endmodule

200
test_regress/t/t_assert_ctl_unsup.out
View File

@ -1,123 +1,123 @@
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:25:7: Unsupported: non-constant assert assertion-type expression
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:25:5: Unsupported: non-constant assert assertion-type expression
: ... note: In instance 't.unsupported_ctl_type'
25 | $assertcontrol(Lock, a);
| ^~~~~~~~~~~~~~
25 | $assertcontrol(Lock, a);
| ^~~~~~~~~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:27:7: Unsupported: $assertcontrol control_type '2'
27 | $assertcontrol(Unlock);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:29:7: Unsupported: $assertcontrol control_type '6'
29 | $assertcontrol(PassOn);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:30:7: Unsupported: assert control assertion_type
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:27:5: Unsupported: $assertcontrol control_type '2'
27 | $assertcontrol(Unlock);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:29:5: Unsupported: $assertcontrol control_type '6'
29 | $assertcontrol(PassOn);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:30:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
30 | $assertpasson;
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:31:7: Unsupported: assert control assertion_type
30 | $assertpasson;
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:31:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
31 | $assertpasson(a);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:32:7: Unsupported: assert control assertion_type
31 | $assertpasson(a);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:32:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
32 | $assertpasson(a, t);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:34:7: Unsupported: $assertcontrol control_type '7'
34 | $assertcontrol(PassOff);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:35:7: Unsupported: assert control assertion_type
32 | $assertpasson(a, t);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:34:5: Unsupported: $assertcontrol control_type '7'
34 | $assertcontrol(PassOff);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:35:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
35 | $assertpassoff;
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:36:7: Unsupported: assert control assertion_type
35 | $assertpassoff;
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:36:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
36 | $assertpassoff(a);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:37:7: Unsupported: assert control assertion_type
36 | $assertpassoff(a);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:37:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
37 | $assertpassoff(a, t);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:39:7: Unsupported: $assertcontrol control_type '8'
39 | $assertcontrol(FailOn);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:40:7: Unsupported: assert control assertion_type
37 | $assertpassoff(a, t);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:39:5: Unsupported: $assertcontrol control_type '8'
39 | $assertcontrol(FailOn);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:40:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
40 | $assertfailon;
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:41:7: Unsupported: assert control assertion_type
40 | $assertfailon;
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:41:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
41 | $assertfailon(a);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:42:7: Unsupported: assert control assertion_type
41 | $assertfailon(a);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:42:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
42 | $assertfailon(a, t);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:44:7: Unsupported: $assertcontrol control_type '9'
44 | $assertcontrol(FailOff);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:45:7: Unsupported: assert control assertion_type
42 | $assertfailon(a, t);
| ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:44:5: Unsupported: $assertcontrol control_type '9'
44 | $assertcontrol(FailOff);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:45:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
45 | $assertfailoff;
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:46:7: Unsupported: assert control assertion_type
45 | $assertfailoff;
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:46:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
46 | $assertfailoff(a);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:47:7: Unsupported: assert control assertion_type
46 | $assertfailoff(a);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:47:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
47 | $assertfailoff(a, t);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:49:7: Unsupported: $assertcontrol control_type '10'
49 | $assertcontrol(NonvacuousOn);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:50:7: Unsupported: assert control assertion_type
47 | $assertfailoff(a, t);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:49:5: Unsupported: $assertcontrol control_type '10'
49 | $assertcontrol(NonvacuousOn);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:50:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
50 | $assertnonvacuouson;
| ^~~~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:51:7: Unsupported: assert control assertion_type
50 | $assertnonvacuouson;
| ^~~~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:51:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
51 | $assertnonvacuouson(a);
| ^~~~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:52:7: Unsupported: assert control assertion_type
51 | $assertnonvacuouson(a);
| ^~~~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:52:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
52 | $assertnonvacuouson(a, t);
| ^~~~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:54:7: Unsupported: $assertcontrol control_type '11'
54 | $assertcontrol(VacuousOff);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:55:7: Unsupported: assert control assertion_type
52 | $assertnonvacuouson(a, t);
| ^~~~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:54:5: Unsupported: $assertcontrol control_type '11'
54 | $assertcontrol(VacuousOff);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:55:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
55 | $assertvacuousoff;
| ^~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:56:7: Unsupported: assert control assertion_type
55 | $assertvacuousoff;
| ^~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:56:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
56 | $assertvacuousoff(a);
| ^~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:57:7: Unsupported: assert control assertion_type
56 | $assertvacuousoff(a);
| ^~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:57:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type'
57 | $assertvacuousoff(a, t);
| ^~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:64:7: Unsupported: non-const assert control type expression
57 | $assertvacuousoff(a, t);
| ^~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:64:5: Unsupported: non-const assert control type expression
: ... note: In instance 't.unsupported_ctl_type_expr'
64 | $assertcontrol(ctl_type);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:93:10: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_class'
93 | $asserton;
| ^~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:99:10: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_class'
99 | $assertoff;
| ^~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:172:7: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_iface'
172 | $assertoff;
| ^~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:138:7: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_iface_class'
138 | $assertoff;
| ^~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:145:7: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_iface_class'
145 | $asserton;
64 | $assertcontrol(ctl_type);
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:93:7: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_class'
93 | $asserton;
| ^~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:99:7: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_class'
99 | $assertoff;
| ^~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:172:5: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_iface'
172 | $assertoff;
| ^~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:138:5: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_iface_class'
138 | $assertoff;
| ^~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:145:5: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_iface_class'
145 | $asserton;
| ^~~~~~~~~
%Error: Exiting due to

274
test_regress/t/t_assert_ctl_unsup.v
View File

@ -5,181 +5,181 @@
// SPDX-License-Identifier: CC0-1.0
module t(input logic clk);
unsupported_ctl_type unsupported_ctl_type(clk ? 1 : 2);
unsupported_ctl_type_expr unsupported_ctl_type_expr();
assert_class assert_class();
assert_iface assert_iface();
assert_iface_class assert_iface_class();
unsupported_ctl_type unsupported_ctl_type(clk ? 1 : 2);
unsupported_ctl_type_expr unsupported_ctl_type_expr();
assert_class assert_class();
assert_iface assert_iface();
assert_iface_class assert_iface_class();
endmodule
module unsupported_ctl_type(input int a);
initial begin
let Lock = 1;
let Unlock = 2;
let PassOn = 6;
let PassOff = 7;
let FailOn = 8;
let FailOff = 9;
let NonvacuousOn = 10;
let VacuousOff = 11;
$assertcontrol(Lock, a);
initial begin
let Lock = 1;
let Unlock = 2;
let PassOn = 6;
let PassOff = 7;
let FailOn = 8;
let FailOff = 9;
let NonvacuousOn = 10;
let VacuousOff = 11;
$assertcontrol(Lock, a);
$assertcontrol(Unlock);
$assertcontrol(Unlock);
$assertcontrol(PassOn);
$assertpasson;
$assertpasson(a);
$assertpasson(a, t);
$assertcontrol(PassOn);
$assertpasson;
$assertpasson(a);
$assertpasson(a, t);
$assertcontrol(PassOff);
$assertpassoff;
$assertpassoff(a);
$assertpassoff(a, t);
$assertcontrol(PassOff);
$assertpassoff;
$assertpassoff(a);
$assertpassoff(a, t);
$assertcontrol(FailOn);
$assertfailon;
$assertfailon(a);
$assertfailon(a, t);
$assertcontrol(FailOn);
$assertfailon;
$assertfailon(a);
$assertfailon(a, t);
$assertcontrol(FailOff);
$assertfailoff;
$assertfailoff(a);
$assertfailoff(a, t);
$assertcontrol(FailOff);
$assertfailoff;
$assertfailoff(a);
$assertfailoff(a, t);
$assertcontrol(NonvacuousOn);
$assertnonvacuouson;
$assertnonvacuouson(a);
$assertnonvacuouson(a, t);
$assertcontrol(NonvacuousOn);
$assertnonvacuouson;
$assertnonvacuouson(a);
$assertnonvacuouson(a, t);
$assertcontrol(VacuousOff);
$assertvacuousoff;
$assertvacuousoff(a);
$assertvacuousoff(a, t);
end
$assertcontrol(VacuousOff);
$assertvacuousoff;
$assertvacuousoff(a);
$assertvacuousoff(a, t);
end
endmodule
module unsupported_ctl_type_expr;
int ctl_type = 1;
initial begin
$assertcontrol(ctl_type);
end
int ctl_type = 1;
initial begin
$assertcontrol(ctl_type);
end
endmodule
module assert_class;
virtual class AssertCtl;
pure virtual function void virtual_assert_ctl();
endclass
virtual class AssertCtl;
pure virtual function void virtual_assert_ctl();
endclass
class AssertCls;
static function void static_function();
assert(0);
endfunction
static task static_task();
assert(0);
endtask
function void assert_function();
assert(0);
endfunction
task assert_task();
assert(0);
endtask
virtual function void virtual_assert();
assert(0);
endfunction
endclass
class AssertCls;
static function void static_function();
assert(0);
endfunction
static task static_task();
assert(0);
endtask
function void assert_function();
assert(0);
endfunction
task assert_task();
assert(0);
endtask
virtual function void virtual_assert();
assert(0);
endfunction
endclass
class AssertOn extends AssertCtl;
virtual function void virtual_assert_ctl();
$asserton;
endfunction
endclass
class AssertOff extends AssertCtl;
virtual function void virtual_assert_ctl();
$assertoff;
endfunction
endclass
AssertCls assertCls;
AssertOn assertOn;
AssertOff assertOff;
initial begin
$assertoff;
AssertCls::static_function();
AssertCls::static_task();
class AssertOn extends AssertCtl;
virtual function void virtual_assert_ctl();
$asserton;
AssertCls::static_function();
AssertCls::static_task();
endfunction
endclass
assertCls = new;
assertOn = new;
assertOff = new;
class AssertOff extends AssertCtl;
virtual function void virtual_assert_ctl();
$assertoff;
endfunction
endclass
assertOff.virtual_assert_ctl();
assertCls.assert_function();
assertCls.assert_task();
assertCls.virtual_assert();
AssertCls assertCls;
AssertOn assertOn;
AssertOff assertOff;
initial begin
$assertoff;
AssertCls::static_function();
AssertCls::static_task();
$asserton;
AssertCls::static_function();
AssertCls::static_task();
assertOn.virtual_assert_ctl();
assertCls.assert_function();
assertCls.assert_task();
assertCls.virtual_assert();
assertOff.virtual_assert_ctl();
assertCls.assert_function();
end
assertCls = new;
assertOn = new;
assertOff = new;
assertOff.virtual_assert_ctl();
assertCls.assert_function();
assertCls.assert_task();
assertCls.virtual_assert();
assertOn.virtual_assert_ctl();
assertCls.assert_function();
assertCls.assert_task();
assertCls.virtual_assert();
assertOff.virtual_assert_ctl();
assertCls.assert_function();
end
endmodule
interface Iface;
function void assert_func();
assert(0);
endfunction
function void assert_func();
assert(0);
endfunction
function void assertoff_func();
$assertoff;
endfunction
function void assertoff_func();
$assertoff;
endfunction
initial begin
assertoff_func();
assert(0);
assert_func();
$asserton;
assert(0);
assert_func();
end
initial begin
assertoff_func();
assert(0);
assert_func();
$asserton;
assert(0);
assert_func();
end
endinterface
module assert_iface;
Iface iface();
virtual Iface vIface = iface;
initial begin
vIface.assert_func();
vIface.assertoff_func();
vIface.assert_func();
Iface iface();
virtual Iface vIface = iface;
initial begin
vIface.assert_func();
vIface.assertoff_func();
vIface.assert_func();
iface.assert_func();
iface.assertoff_func();
iface.assert_func();
end
iface.assert_func();
iface.assertoff_func();
iface.assert_func();
end
endmodule
interface class IfaceClass;
pure virtual function void assertoff_func();
pure virtual function void assert_func();
pure virtual function void assertoff_func();
pure virtual function void assert_func();
endclass
class IfaceClassImpl implements IfaceClass;
virtual function void assertoff_func();
$assertoff;
endfunction
virtual function void assert_func();
assert(0);
endfunction
virtual function void assertoff_func();
$assertoff;
endfunction
virtual function void assert_func();
assert(0);
endfunction
endclass
module assert_iface_class;
IfaceClassImpl ifaceClassImpl = new;
initial begin
ifaceClassImpl.assertoff_func();
ifaceClassImpl.assert_func();
end
IfaceClassImpl ifaceClassImpl = new;
initial begin
ifaceClassImpl.assertoff_func();
ifaceClassImpl.assert_func();
end
endmodule

6
test_regress/t/t_assert_disable_bad.out
View File

@ -1,6 +1,6 @@
%Error: t/t_assert_disable_bad.v:27:38: disable iff expression before property call and in its body is not legal
%Error: t/t_assert_disable_bad.v:25:37: disable iff expression before property call and in its body is not legal
: ... note: In instance 't'
27 | assert property (disable iff (val == 0) check(1, 1));
| ^~
25 | assert property (disable iff (val == 0) check(1, 1));
| ^~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

32
test_regress/t/t_assert_disable_bad.v
View File

@ -4,25 +4,23 @@
// SPDX-FileCopyrightText: 2022 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
int cyc = 0;
logic val = 0;
int cyc = 0;
logic val = 0;
always @(posedge clk) begin
cyc <= cyc + 1;
val = ~val;
end
always @(posedge clk) begin
cyc <= cyc + 1;
val = ~val;
end
property check(int cyc_mod_2, logic expected);
@(posedge clk) disable iff (cyc == 0) cyc % 2 == cyc_mod_2 |=> val == expected;
endproperty
property check(int cyc_mod_2, logic expected);
@(posedge clk) disable iff (cyc == 0) cyc % 2 == cyc_mod_2 |=> val == expected;
endproperty
// Test should fail due to duplicated disable iff statements
// (IEEE 1800-2012 16.12.1).
assert property (disable iff (val == 0) check(1, 1));
// Test should fail due to duplicated disable iff statements
// (IEEE 1800-2012 16.12.1).
assert property (disable iff (val == 0) check(1, 1));
endmodule

93
test_regress/t/t_assert_disable_count.v
View File

@ -4,66 +4,69 @@
// SPDX-FileCopyrightText: 2024 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
int cyc;
int cyc;
Sub sub ();
Sub sub ();
default disable iff (cyc[0]);
default disable iff (cyc[0]);
int a_false;
always @(posedge clk iff !cyc[0]) begin
if (cyc < 4 || cyc > 9);
else a_false = a_false + 1;
end
int a_false;
always @(posedge clk iff !cyc[0]) begin
if (cyc < 4 || cyc > 9) ;
else a_false = a_false + 1;
end
int a0_false;
a0 :
assert property (@(posedge clk) disable iff (cyc[0]) (cyc < 4 || cyc > 9))
else a0_false = a0_false + 1;
int a0_false;
a0: assert property (@(posedge clk) disable iff (cyc[0]) (cyc < 4 || cyc > 9))
else a0_false = a0_false + 1;
int a1_false;
// Note that Verilator supports $inferred_disable in general expression locations
// This is a superset of what IEEE specifies
a1 :
assert property (@(posedge clk) disable iff ($inferred_disable) (cyc < 4 || cyc > 9))
else a1_false = a1_false + 1;
int a1_false;
// Note that Verilator supports $inferred_disable in general expression locations
// This is a superset of what IEEE specifies
a1: assert property (@(posedge clk) disable iff ($inferred_disable) (cyc < 4 || cyc > 9))
else a1_false = a1_false + 1;
int a2_false;
// Implicitly uses $inferred_disable
a2 :
assert property (@(posedge clk) (cyc < 4 || cyc > 9))
else a2_false = a2_false + 1;
int a2_false;
// Implicitly uses $inferred_disable
a2: assert property (@(posedge clk) (cyc < 4 || cyc > 9))
else a2_false = a2_false + 1;
int a3_false;
// A different disable iff expression
a3 :
assert property (@(posedge clk) disable iff (cyc == 5) (cyc < 4 || cyc > 9))
else a3_false = a3_false + 1;
int a3_false;
// A different disable iff expression
a3: assert property (@(posedge clk) disable iff (cyc == 5) (cyc < 4 || cyc > 9))
else a3_false = a3_false + 1;
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 20) begin
`checkd(a_false, 3);
`checkd(a0_false, a_false);
`checkd(a1_false, a_false);
`checkd(a2_false, a_false);
`checkd(a3_false, 5);
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 20) begin
`checkd(a_false, 3);
`checkd(a0_false, a_false);
`checkd(a1_false, a_false);
`checkd(a2_false, a_false);
`checkd(a3_false, 5);
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Sub;
initial begin
if ($inferred_disable !== 0) $stop;
end
initial begin
if ($inferred_disable !== 0) $stop;
end
endmodule

12
test_regress/t/t_assert_dup_bad.out
View File

@ -1,8 +1,8 @@
%Error: t/t_assert_dup_bad.v:17:4: Duplicate declaration of block: 'covlabel'
17 | covlabel:
| ^~~~~~~~
t/t_assert_dup_bad.v:15:4: ... Location of original declaration
15 | covlabel:
| ^~~~~~~~
%Error: t/t_assert_dup_bad.v:15:3: Duplicate declaration of block: 'covlabel'
15 | covlabel :
| ^~~~~~~~
t/t_assert_dup_bad.v:13:3: ... Location of original declaration
13 | covlabel :
| ^~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

18
test_regress/t/t_assert_dup_bad.v
View File

@ -4,17 +4,15 @@
// SPDX-FileCopyrightText: 2007 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
integer cyc = 0;
int cyc;
covlabel:
cover property (@(posedge clk) cyc==5);
covlabel: // Error: Duplicate block_identifier
cover property (@(posedge clk) cyc==5);
covlabel :
cover property (@(posedge clk) cyc == 5);
covlabel : // Error: Duplicate block_identifier
cover property (@(posedge clk) cyc == 5);
endmodule

31
test_regress/t/t_assert_elab.v
View File

@ -5,26 +5,25 @@
// SPDX-License-Identifier: CC0-1.0
module t;
localparam STR = "string";
function logic checkParameter(input logic [8:0] N);
$info("For %m, x is %d.", N);
if (N == 1)
return 0;
$fatal(1, "Parameter %d is invalid...%s and %s", N, STR, "constant both work");
endfunction
localparam STR = "string";
function logic checkParameter(input logic [8:0] N);
$info("For %m, x is %d.", N);
if (N == 1) return 0;
$fatal(1, "Parameter %d is invalid...%s and %s", N, STR, "constant both work");
endfunction
`ifdef FAILING_ASSERTIONS
localparam X = checkParameter(5);
localparam X = checkParameter(5);
`else
localparam X = checkParameter(1);
localparam X = checkParameter(1);
`endif
generate
$info("%m: In generate"); // Issue 6445
endgenerate
generate
$info("%m: In generate"); // Issue 6445
endgenerate
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

72
test_regress/t/t_assert_iff.v
View File

@ -4,54 +4,46 @@
// SPDX-FileCopyrightText: 2023 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic[3:0] enable;
int cyc = 0;
module t (
input clk
);
Test test(.*);
logic [3:0] enable;
int cyc = 0;
always @ (posedge clk) begin
cyc <= cyc + 1;
`ifdef FAIL1 enable[0] <= 1; `endif
enable[1] <= 1;
`ifdef FAIL2 enable[2] <= 1; `endif
enable[3] <= 1;
if (cyc != 0) begin
if (cyc == 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
Test test (.*);
always @(posedge clk) begin
cyc <= cyc + 1;
`ifdef FAIL1
enable[0] <= 1;
`endif
enable[1] <= 1;
`ifdef FAIL2
enable[2] <= 1;
`endif
enable[3] <= 1;
if (cyc != 0) begin
if (cyc == 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
end
endmodule
module Test(
input clk,
input[3:0] enable
);
module Test (
input clk,
input [3:0] enable
);
assert property (
@(posedge clk iff enable[0])
0
) else $stop;
assert property (@(posedge clk iff enable[0]) 0)
else $stop;
assert property (
@(posedge clk iff enable[1])
1
);
assert property (@(posedge clk iff enable[1]) 1);
cover property (
@(posedge clk iff enable[2])
1
) $stop;
cover property (@(posedge clk iff enable[2]) 1) $stop;
cover property (
@(posedge clk iff enable[3])
0
) $stop;
cover property (@(posedge clk iff enable[3]) 0) $stop;
endmodule

6
test_regress/t/t_assert_iff_clk_unsup.out
View File

@ -1,6 +1,6 @@
%Error-UNSUPPORTED: t/t_assert_iff_clk_unsup.v:20:21: Unsupported: property '(disable iff (...) @ (...)'
%Error-UNSUPPORTED: t/t_assert_iff_clk_unsup.v:20:20: Unsupported: property '(disable iff (...) @ (...)'
: ... Suggest use property '(@(...) disable iff (...))'
20 | assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5);
| ^~~~~~~
20 | assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5);
| ^~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

22
test_regress/t/t_assert_iff_clk_unsup.v
View File

@ -4,19 +4,19 @@
// SPDX-FileCopyrightText: 2022 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
clk
);
module t (
input clk
);
input clk;
int cyc = 0;
logic val = 0;
input clk;
int cyc = 0;
logic val = 0;
always @(posedge clk) begin
cyc <= cyc + 1;
val = ~val;
end
always @(posedge clk) begin
cyc <= cyc + 1;
val = ~val;
end
assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5);
assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5);
endmodule

6
test_regress/t/t_assert_imm_nz_bad.out
View File

@ -1,5 +1,5 @@
%Error: t/t_assert_imm_nz_bad.v:13:26: Deferred assertions must use '#0' (IEEE 1800-2023 16.4)
13 | labeled_imas: assert #1 (clk);
| ^
%Error: t/t_assert_imm_nz_bad.v:14:11: Deferred assertions must use '#0' (IEEE 1800-2023 16.4)
14 | assert #1 (clk);
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

11
test_regress/t/t_assert_imm_nz_bad.v
View File

@ -4,12 +4,13 @@
// SPDX-FileCopyrightText: 2022 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
clk
);
module t (
input clk
);
input clk;
input clk;
labeled_imas: assert #1 (clk); // BAD: #1
labeled_imas :
assert #1 (clk); // BAD: #1
endmodule

145
test_regress/t/t_assert_implication.v
View File

@ -4,127 +4,84 @@
// SPDX-FileCopyrightText: 2019 Peter Monsson
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
integer cyc; initial cyc=1;
integer cyc;
initial cyc = 1;
Test test (/*AUTOINST*/
// Inputs
.clk(clk),
.cyc(cyc));
Test test ( /*AUTOINST*/
// Inputs
.clk(clk),
.cyc(cyc)
);
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
always @(posedge clk) begin
if (cyc != 0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$display("cyc=%0d", cyc);
$display("cyc=%0d", cyc);
`endif
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
if (cyc == 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
end
endmodule
module Test
(
input clk,
input integer cyc
);
module Test (
input clk,
input integer cyc
);
`ifdef FAIL_ASSERT_1
assert property (
@(posedge clk)
1 |-> 0
) else $display("[%0t] wrong implication", $time);
assert property (@(posedge clk) 1 |-> 0)
else $display("[%0t] wrong implication", $time);
assert property (
@(posedge clk)
1 |=> 0
) else $display("[%0t] wrong implication", $time);
assert property (@(posedge clk) 1 |=> 0)
else $display("[%0t] wrong implication", $time);
assert property (
@(posedge clk)
cyc%3==1 |=> cyc%3==1
) else $display("[%0t] wrong implication (step)", $time);
assert property (@(posedge clk) cyc % 3 == 1 |=> cyc % 3 == 1)
else $display("[%0t] wrong implication (step)", $time);
assert property (
@(posedge clk)
cyc%3==1 |=> cyc%3==0
) else $display("[%0t] wrong implication (step)", $time);
assert property (@(posedge clk) cyc % 3 == 1 |=> cyc % 3 == 0)
else $display("[%0t] wrong implication (step)", $time);
assert property (
@(posedge clk) disable iff (cyc == 3)
(cyc == 4) |=> 0
) else $display("[%0t] wrong implication (disable)", $time);
assert property (@(posedge clk) disable iff (cyc == 3) (cyc == 4) |=> 0)
else $display("[%0t] wrong implication (disable)", $time);
assert property (
@(posedge clk) disable iff (cyc == 6)
(cyc == 4) |=> 0
) else $display("[%0t] wrong implication (disable)", $time);
assert property (@(posedge clk) disable iff (cyc == 6) (cyc == 4) |=> 0)
else $display("[%0t] wrong implication (disable)", $time);
`endif
// Test |->
assert property (
@(posedge clk)
1 |-> 1
);
// Test |->
assert property (@(posedge clk) 1 |-> 1);
assert property (
@(posedge clk)
0 |-> 0
);
assert property (@(posedge clk) 0 |-> 0);
assert property (
@(posedge clk)
0 |-> 1
);
assert property (@(posedge clk) 0 |-> 1);
// Test |=>
assert property (
@(posedge clk)
1 |=> 1
);
// Test |=>
assert property (@(posedge clk) 1 |=> 1);
assert property (
@(posedge clk)
0 |=> 0
);
assert property (@(posedge clk) 0 |=> 0);
assert property (
@(posedge clk)
0 |=> 1
);
assert property (@(posedge clk) 0 |=> 1);
// Test correct handling of time step in |=>
assert property (
@(posedge clk)
cyc%3==1 |=> cyc%3==2
);
// Test correct handling of time step in |=>
assert property (@(posedge clk) cyc % 3 == 1 |=> cyc % 3 == 2);
// Test correct handling of disable iff
assert property (
@(posedge clk) disable iff ($sampled(cyc) < 3)
1 |=> cyc > 3
);
// Test correct handling of disable iff
assert property (@(posedge clk) disable iff ($sampled(cyc) < 3) 1 |=> cyc > 3);
// Test correct handling of disable iff in current cycle
assert property (
@(posedge clk) disable iff ($sampled(cyc) == 4)
(cyc == 4) |=> 0
);
// Test correct handling of disable iff in current cycle
assert property (@(posedge clk) disable iff ($sampled(cyc) == 4) (cyc == 4) |=> 0);
// Test correct handling of disable iff in previous cycle
assert property (
@(posedge clk) disable iff (cyc == 5)
(cyc == 4) |=> 0
);
// Test correct handling of disable iff in previous cycle
assert property (@(posedge clk) disable iff (cyc == 5) (cyc == 4) |=> 0);
endmodule

44
test_regress/t/t_assert_inside_cond.v
View File

@ -11,36 +11,36 @@ module t (/*AUTOARG*/
clk
);
input clk;
output logic hit;
input clk;
output logic hit;
logic [31:0] addr;
int cyc;
logic [31:0] addr;
int cyc;
initial addr = 32'h380;
initial addr = 32'h380;
always @ (posedge clk) begin
cyc <= cyc + 1;
always @ (posedge clk) begin
cyc <= cyc + 1;
`ifdef T_ASSERT_INSIDE_COND
addr <= 32'h380;
addr <= 32'h380;
`elsif T_ASSERT_INSIDE_COND_BAD
addr <= 32'h389;
addr <= 32'h389;
`else
`error "Bad test define"
`endif
if (cyc == 9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
if (cyc == 9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always_comb begin
hit = 0;
unique case (addr[11:0]) inside
[12'h380 : 12'h388]: begin
hit = 1;
end
endcase
end
always_comb begin
hit = 0;
unique case (addr[11:0]) inside
[12'h380 : 12'h388]: begin
hit = 1;
end
endcase
end
endmodule

19
test_regress/t/t_assert_on.v
View File

@ -4,17 +4,14 @@
// SPDX-FileCopyrightText: 2007 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
always @ (posedge clk) begin
assert (0);
$write("*-* All Finished *-*\n");
$finish;
end
always @(posedge clk) begin
assert (0);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

41
test_regress/t/t_assert_past.v
View File

@ -4,25 +4,24 @@
// SPDX-FileCopyrightText: 2022 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
clk
);
input clk;
int cyc = 0;
logic val = 0;
// Example:
always @(posedge clk) begin
cyc <= cyc + 1;
val = ~val;
$display("t=%0t cyc=%0d val=%b", $time, cyc, val);
if (cyc == 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
assert property(@(posedge clk) cyc % 2 == 0 |=> $past(val) == 0)
else $display("$past assert 1 failed");
assert property(@(posedge clk) cyc % 2 == 1 |=> $past(val) == 1)
else $display("$past assert 2 failed");
// Example end
module t (
input clk
);
int cyc = 0;
logic val = 0;
// Example:
always @(posedge clk) begin
cyc <= cyc + 1;
val = ~val;
$display("t=%0t cyc=%0d val=%b", $time, cyc, val);
if (cyc == 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
assert property (@(posedge clk) cyc % 2 == 0 |=> $past(val) == 0)
else $display("$past assert 1 failed");
assert property (@(posedge clk) cyc % 2 == 1 |=> $past(val) == 1)
else $display("$past assert 2 failed");
// Example end
endmodule

16
test_regress/t/t_assert_procedural_clk_bad.out
View File

@ -1,10 +1,10 @@
%Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:21:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6)
: ... note: In instance 't'
21 | assume property (@(posedge clk) cyc == 9);
| ^~~~~~
%Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:19:9: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6)
: ... note: In instance 't'
19 | assume property (@(posedge clk) cyc == 9);
| ^~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:22:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6)
: ... note: In instance 't'
22 | assume property (@(negedge clk) cyc == 9);
| ^~~~~~
%Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:20:9: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6)
: ... note: In instance 't'
20 | assume property (@(negedge clk) cyc == 9);
| ^~~~~~
%Error: Exiting due to

38
test_regress/t/t_assert_procedural_clk_bad.v
View File

@ -4,28 +4,26 @@
// SPDX-FileCopyrightText: 2023 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
integer cyc;
initial cyc = 1;
wire [7:0] cyc_copy = cyc[7:0];
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==9) begin
assume property (@(posedge clk) cyc == 9);
assume property (@(negedge clk) cyc == 9);
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
always @(posedge clk) begin
if (cyc != 0) begin
cyc <= cyc + 1;
if (cyc == 9) begin
assume property (@(posedge clk) cyc == 9);
assume property (@(negedge clk) cyc == 9);
end
end
if (cyc == 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule

34
test_regress/t/t_assert_question.v
View File

@ -11,24 +11,24 @@ module t (/*AUTOARG*/
clk, sel, a, c
);
input clk;
input bit [3:0] sel;
input bit [3:0] a;
input bit c;
output bit dout;
input clk;
input bit [3:0] sel;
input bit [3:0] a;
input bit c;
output bit dout;
localparam logic DC = 1'b?;
localparam logic DC = 1'b?;
always_ff @(posedge clk) begin
unique casez(sel)
4'b0000: dout <= a[0];
4'b001?: dout <= a[1];
{1'b0, 1'b1, 1'b?, 1'b?}: dout <= a[2];
{1'b1, 1'b?, 1'b?, DC}: dout <= a[3];
default: dout <= '0;
endcase
$write("*-* All Finished *-*\n");
$finish;
end
always_ff @(posedge clk) begin
unique casez(sel)
4'b0000: dout <= a[0];
4'b001?: dout <= a[1];
{1'b0, 1'b1, 1'b?, 1'b?}: dout <= a[2];
{1'b1, 1'b?, 1'b?, DC}: dout <= a[3];
default: dout <= '0;
endcase
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

134
test_regress/t/t_assert_sampled.v
View File

@ -4,87 +4,109 @@
// SPDX-FileCopyrightText: 2022 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
input clk
);
reg [3:0] a, b;
reg [3:0] a, b;
Test1 t1(clk, a, b);
Test2 t2(clk, a, b);
Test3 t3(clk, a, b);
Test1 t1 (
clk,
a,
b
);
Test2 t2 (
clk,
a,
b
);
Test3 t3 (
clk,
a,
b
);
initial begin
a = 0;
b = 0;
end
initial begin
a = 0;
b = 0;
end
always @(posedge clk) begin
a <= a + 1;
b = b + 1;
always @(posedge clk) begin
a <= a + 1;
b = b + 1;
$display("a = %0d, b = %0d, %0d == %0d", a, b, $sampled(a), $sampled(b));
$display("a = %0d, b = %0d, %0d == %0d", a, b, $sampled(a), $sampled(b));
if (b >= 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
if (b >= 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test1(
clk, a, b
);
module Test1 (
clk,
a,
b
);
input clk;
input [3:0] a, b;
input clk;
input [3:0] a, b;
assert property (@(posedge clk) $sampled(a) == $sampled(b));
assert property (@(posedge clk) $sampled(a) == $sampled(b));
endmodule
module Test2(
clk, a, b
);
module Test2 (
clk,
a,
b
);
input clk;
input [3:0] a, b;
input clk;
input [3:0] a, b;
assert property (@(posedge clk) a == b);
assert property (@(posedge clk) a == b);
endmodule
module Test3(
clk, a, b
);
module Test3 (
clk,
a,
b
);
input clk;
input [3:0] a, b;
input clk;
input [3:0] a, b;
int hits[10];
int hits[10];
assert property (@(posedge clk) a == b) hits[1]=1;
assert property (@(posedge clk) a == b) else hits[2]=1;
assert property (@(posedge clk) a == b) hits[3]=1; else hits[4]=1;
assert property (@(posedge clk) a == b) hits[1] = 1;
assert property (@(posedge clk) a == b)
else hits[2] = 1;
assert property (@(posedge clk) a == b) hits[3] = 1;
else hits[4] = 1;
assert property (@(posedge clk) a != b) hits[5]=1;
assert property (@(posedge clk) a != b) else hits[6]=1;
assert property (@(posedge clk) a != b) hits[7]=1; else hits[8]=1;
assert property (@(posedge clk) a != b) hits[5] = 1;
assert property (@(posedge clk) a != b)
else hits[6] = 1;
assert property (@(posedge clk) a != b) hits[7] = 1;
else hits[8] = 1;
final begin
`checkd(hits[1], 1);
`checkd(hits[2], 0);
`checkd(hits[3], 1);
`checkd(hits[4], 0);
`checkd(hits[5], 0);
`checkd(hits[6], 1);
`checkd(hits[7], 0);
`checkd(hits[8], 1);
end
final begin
`checkd(hits[1], 1);
`checkd(hits[2], 0);
`checkd(hits[3], 1);
`checkd(hits[4], 0);
`checkd(hits[5], 0);
`checkd(hits[6], 1);
`checkd(hits[7], 0);
`checkd(hits[8], 1);
end
endmodule

155
test_regress/t/t_assert_synth.v
View File

@ -4,112 +4,109 @@
// SPDX-FileCopyrightText: 2005 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
reg a; initial a = 1'b1;
reg b_fc; initial b_fc = 1'b0;
reg b_pc; initial b_pc = 1'b0;
reg b_oh; initial b_oh = 1'b0;
reg b_oc; initial b_oc = 1'b0;
wire a_l = ~a;
wire b_oc_l = ~b_oc;
reg a; initial a = 1'b1;
reg b_fc; initial b_fc = 1'b0;
reg b_pc; initial b_pc = 1'b0;
reg b_oh; initial b_oh = 1'b0;
reg b_oc; initial b_oc = 1'b0;
wire a_l = ~a;
wire b_oc_l = ~b_oc;
// Note we must ensure that full, parallel, etc, only fire during
// edges (not mid-cycle), and must provide a way to turn them off.
// SystemVerilog provides: $asserton and $assertoff.
// Note we must ensure that full, parallel, etc, only fire during
// edges (not mid-cycle), and must provide a way to turn them off.
// SystemVerilog provides: $asserton and $assertoff.
// verilator lint_off CASEINCOMPLETE
// verilator lint_off CASEINCOMPLETE
always @* begin
// Note not all tools support directives on casez's
always @* begin
// Note not all tools support directives on casez's
`ifdef ATTRIBUTES
case ({a,b_fc}) // synopsys full_case
case ({a,b_fc}) // synopsys full_case
`else
case ({a,b_fc})
case ({a,b_fc})
`endif
2'b0_0: ;
2'b0_1: ;
2'b1_0: ;
// Note no default
endcase
priority case ({a,b_fc})
2'b0_0: ;
2'b0_1: ;
2'b1_0: ;
// Note no default
endcase
end
2'b0_0: ;
2'b0_1: ;
2'b1_0: ;
// Note no default
endcase
priority case ({a,b_fc})
2'b0_0: ;
2'b0_1: ;
2'b1_0: ;
// Note no default
endcase
end
always @* begin
always @* begin
`ifdef ATTRIBUTES
case (1'b1) // synopsys full_case parallel_case
case (1'b1) // synopsys full_case parallel_case
`else
`ifdef FAILING_FULL
case (1'b1) // synopsys parallel_case
case (1'b1) // synopsys parallel_case
`else
case (1'b1) // synopsys parallel_full
case (1'b1) // synopsys parallel_full
`endif
`endif
a: ;
b_pc: ;
endcase
end
a: ;
b_pc: ;
endcase
end
`ifdef NOT_YET_VERILATOR // Unsupported
// ambit synthesis one_hot "a, b_oh"
// cadence one_cold "a_l, b_oc_l"
// ambit synthesis one_hot "a, b_oh"
// cadence one_cold "a_l, b_oc_l"
`endif
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 1'b1;
b_fc <= 1'b0;
b_pc <= 1'b0;
b_oh <= 1'b0;
b_oc <= 1'b0;
end
if (cyc==2) begin
a <= 1'b0;
b_fc <= 1'b1;
b_pc <= 1'b1;
b_oh <= 1'b1;
b_oc <= 1'b1;
end
if (cyc==3) begin
a <= 1'b1;
b_fc <= 1'b0;
b_pc <= 1'b0;
b_oh <= 1'b0;
b_oc <= 1'b0;
end
if (cyc==4) begin
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 1'b1;
b_fc <= 1'b0;
b_pc <= 1'b0;
b_oh <= 1'b0;
b_oc <= 1'b0;
end
if (cyc==2) begin
a <= 1'b0;
b_fc <= 1'b1;
b_pc <= 1'b1;
b_oh <= 1'b1;
b_oc <= 1'b1;
end
if (cyc==3) begin
a <= 1'b1;
b_fc <= 1'b0;
b_pc <= 1'b0;
b_oh <= 1'b0;
b_oc <= 1'b0;
end
if (cyc==4) begin
`ifdef FAILING_FULL
b_fc <= 1'b1;
b_fc <= 1'b1;
`endif
`ifdef FAILING_PARALLEL
b_pc <= 1'b1;
b_pc <= 1'b1;
`endif
`ifdef FAILING_OH
b_oh <= 1'b1;
b_oh <= 1'b1;
`endif
`ifdef FAILING_OC
b_oc <= 1'b1;
b_oc <= 1'b1;
`endif
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
initial begin : test_info
$info ("Start of $info test");

10
test_regress/t/t_assert_synth_full.out
View File

@ -1,6 +1,6 @@
[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test
[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test
[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test
[40] %Error: t_assert_synth.v:31: Assertion failed in top.t: synthesis full_case, but non-match found for '2'h3'
%Error: t/t_assert_synth.v:31: Verilog $stop
[0] -Info: t_assert_synth.v:112: top.t.test_info: Start of $info test
[0] -Info: t_assert_synth.v:113: top.t.test_info: Middle of $info test
[0] -Info: t_assert_synth.v:114: top.t.test_info: End of $info test
[40] %Error: t_assert_synth.v:28: Assertion failed in top.t: synthesis full_case, but non-match found for '2'h3'
%Error: t/t_assert_synth.v:28: Verilog $stop
Aborting...

10
test_regress/t/t_assert_synth_full_vlt.out
View File

@ -1,6 +1,6 @@
[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test
[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test
[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test
[40] %Error: t_assert_synth.v:40: Assertion failed in top.t: priority case, but non-match found for '2'h3'
%Error: t/t_assert_synth.v:40: Verilog $stop
[0] -Info: t_assert_synth.v:112: top.t.test_info: Start of $info test
[0] -Info: t_assert_synth.v:113: top.t.test_info: Middle of $info test
[0] -Info: t_assert_synth.v:114: top.t.test_info: End of $info test
[40] %Error: t_assert_synth.v:37: Assertion failed in top.t: priority case, but non-match found for '2'h3'
%Error: t/t_assert_synth.v:37: Verilog $stop
Aborting...

10
test_regress/t/t_assert_synth_parallel.out
View File

@ -1,6 +1,6 @@
[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test
[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test
[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test
[40] %Error: t_assert_synth.v:50: Assertion failed in top.t: synthesis full_case parallel_case, but multiple matches found for '1'h1'
%Error: t/t_assert_synth.v:50: Verilog $stop
[0] -Info: t_assert_synth.v:112: top.t.test_info: Start of $info test
[0] -Info: t_assert_synth.v:113: top.t.test_info: Middle of $info test
[0] -Info: t_assert_synth.v:114: top.t.test_info: End of $info test
[40] %Error: t_assert_synth.v:47: Assertion failed in top.t: synthesis full_case parallel_case, but multiple matches found for '1'h1'
%Error: t/t_assert_synth.v:47: Verilog $stop
Aborting...

2
test_regress/t/t_assert_synth_parallel.vlt
View File

@ -6,4 +6,4 @@
`verilator_config
parallel_case -file "t/t_assert_synth.v" -lines 55
parallel_case -file "t/t_assert_synth.v" -lines 52

10
test_regress/t/t_assert_synth_parallel_vlt.out
View File

@ -1,6 +1,6 @@
[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test
[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test
[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test
[40] %Error: t_assert_synth.v:55: Assertion failed in top.t: synthesis parallel_case, but multiple matches found for '1'h1'
%Error: t/t_assert_synth.v:55: Verilog $stop
[0] -Info: t_assert_synth.v:112: top.t.test_info: Start of $info test
[0] -Info: t_assert_synth.v:113: top.t.test_info: Middle of $info test
[0] -Info: t_assert_synth.v:114: top.t.test_info: End of $info test
[40] %Error: t_assert_synth.v:52: Assertion failed in top.t: synthesis parallel_case, but multiple matches found for '1'h1'
%Error: t/t_assert_synth.v:52: Verilog $stop
Aborting...

96
test_regress/t/t_assert_unique_case_bad.v
View File

@ -4,61 +4,61 @@
// SPDX-FileCopyrightText: 2024 Yutetsu TAKATSUKASA
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
hit,
// Inputs
clk
);
module t ( /*AUTOARG*/
// Outputs
hit,
// Inputs
clk
);
input clk;
output logic hit;
input clk;
output logic hit;
logic [31:0] addr;
logic [11:0] match_item0, match_item1;
int cyc;
string s;
logic [31:0] addr;
logic [11:0] match_item0, match_item1;
int cyc;
string s;
initial addr = 32'h380;
initial addr = 32'h380;
always @ (posedge clk) begin
cyc <= cyc + 1;
addr <= 32'h380 + cyc;
match_item0 = 12'h 380 + cyc[11:0];
match_item1 = 12'h 390 - cyc[11:0];
$sformat(s, "%1d", cyc);
if (cyc == 9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge clk) begin
cyc <= cyc + 1;
addr <= 32'h380 + cyc;
match_item0 = 12'h380 + cyc[11:0];
match_item1 = 12'h390 - cyc[11:0];
$sformat(s, "%1d", cyc);
if (cyc == 9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always_comb begin
hit = 1;
unique case (addr[11:0])
match_item0: $display("match_item0");
match_item1: $display("match_item1");
default: hit = 0;
endcase
end
always_comb begin
hit = 1;
unique case (addr[11:0])
match_item0: $display("match_item0");
match_item1: $display("match_item1");
default: hit = 0;
endcase
end
`ifdef NO_STOP_FAIL
always_comb begin
unique case (s)
"": ;
"0": ;
"2": ;
"4": ;
"6": ;
endcase
end
always_comb begin
priority case (s)
$sformatf("%1d", cyc - 1): ;
"0": ;
"6": ;
endcase
end
always_comb begin
unique case (s)
"": ;
"0": ;
"2": ;
"4": ;
"6": ;
endcase
end
always_comb begin
priority case (s)
$sformatf("%1d", cyc - 1): ;
"0": ;
"6": ;
endcase
end
`endif
endmodule

120
test_regress/t/t_assign_expr.v
View File

@ -4,76 +4,94 @@
// SPDX-FileCopyrightText: 2022 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t;
int a;
int b;
int i;
int a;
int b;
int i;
// verilator lint_off ASSIGNEQEXPR
initial begin
a = 10;
i = (a = 2);
`checkd(a, 2); `checkd(i, 2);
// verilator lint_off ASSIGNEQEXPR
initial begin
a = 10;
i = (a = 2);
`checkd(a, 2);
`checkd(i, 2);
a = 10;
i = (a += 2);
`checkd(a, 12); `checkd(i, 12);
a = 10;
i = (a += 2);
`checkd(a, 12);
`checkd(i, 12);
a = 10;
i = (a -= 2);
`checkd(a, 8); `checkd(i, 8);
a = 10;
i = (a -= 2);
`checkd(a, 8);
`checkd(i, 8);
a = 10;
i = (a *= 2);
`checkd(a, 20); `checkd(i, 20);
a = 10;
i = (a *= 2);
`checkd(a, 20);
`checkd(i, 20);
a = 10;
i = (a /= 2);
`checkd(a, 5); `checkd(i, 5);
a = 10;
i = (a /= 2);
`checkd(a, 5);
`checkd(i, 5);
a = 11;
i = (a %= 2);
`checkd(a, 1); `checkd(i, 1);
a = 11;
i = (a %= 2);
`checkd(a, 1);
`checkd(i, 1);
a = 10;
i = (a &= 2);
`checkd(a, 2); `checkd(i, 2);
a = 10;
i = (a &= 2);
`checkd(a, 2);
`checkd(i, 2);
a = 8;
i = (a |= 2);
`checkd(a, 10); `checkd(i, 10);
a = 8;
i = (a |= 2);
`checkd(a, 10);
`checkd(i, 10);
a = 10;
i = (a ^= 2);
`checkd(a, 8); `checkd(i, 8);
a = 10;
i = (a ^= 2);
`checkd(a, 8);
`checkd(i, 8);
a = 10;
i = (a <<= 2);
`checkd(a, 40); `checkd(i, 40);
a = 10;
i = (a <<= 2);
`checkd(a, 40);
`checkd(i, 40);
a = 10;
i = (a >>= 2);
`checkd(a, 2); `checkd(i, 2);
a = 10;
i = (a >>= 2);
`checkd(a, 2);
`checkd(i, 2);
a = 10;
i = (a >>>= 2);
`checkd(a, 2); `checkd(i, 2);
a = 10;
i = (a >>>= 2);
`checkd(a, 2);
`checkd(i, 2);
a = 10;
i = (a = (b = 5));
`checkd(a, 5); `checkd(i, 5); `checkd(b, 5);
a = 10;
i = (a = (b = 5));
`checkd(a, 5);
`checkd(i, 5);
`checkd(b, 5);
a = 10;
b = 6;
i = ((a += (b += 1) + 1));
`checkd(a, 18); `checkd(i, 18); `checkd(b, 7);
a = 10;
b = 6;
i = ((a += (b += 1) + 1));
`checkd(a, 18);
`checkd(i, 18);
`checkd(b, 7);
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

74
test_regress/t/t_assign_inline.v
View File

@ -4,50 +4,48 @@
// SPDX-FileCopyrightText: 2015 Mike Thyer
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
input clk
);
int cycle=0;
int cycle = 0;
// verilator lint_off UNOPTFLAT
reg [7:0] a_r;
wire [7:0] a_w;
reg [7:0] b_r;
reg [7:0] c_d_r, c_q_r;
// verilator lint_off UNOPTFLAT
reg [7:0] a_r;
wire [7:0] a_w;
reg [7:0] b_r;
reg [7:0] c_d_r, c_q_r;
assign a_w = a_r;
assign a_w = a_r;
always @(*) begin
a_r = 0;
b_r = a_w; // Substituting the a_w assignment to get b_r = 0 is wrong, as a_r is not "complete"
a_r = c_q_r;
c_d_r = c_q_r;
end
always @(*) begin
a_r = 0;
b_r = a_w; // Substituting the a_w assignment to get b_r = 0 is wrong, as a_r is not "complete"
a_r = c_q_r;
c_d_r = c_q_r;
end
// stimulus + checks
always @(posedge clk) begin
cycle <= cycle+1;
if (cycle==0) begin
c_q_r <= 8'b0;
end
else begin
c_q_r <= c_d_r+1;
// stimulus + checks
always @(posedge clk) begin
cycle <= cycle + 1;
if (cycle == 0) begin
c_q_r <= 8'b0;
end
else begin
c_q_r <= c_d_r + 1;
`ifdef TEST_VERBOSE
$display("[%0t] a_r=%0d, b_r=%0d", $time, a_r, b_r); // a_r and b_r should always be the same
$display("[%0t] a_r=%0d, b_r=%0d", $time, a_r, b_r); // a_r and b_r should always be the same
`endif
end
if (cycle >= 10) begin
if (b_r==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
$stop;
end
end
end
end
if (cycle >= 10) begin
if (b_r == 9) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
$stop;
end
end
end
endmodule

265
test_regress/t/t_assign_slice_overflow.v
View File

@ -23,157 +23,158 @@
// SPDX-FileCopyrightText: 2021 David Turner
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
input clk
);
integer cyc = 0;
// Non-constant offsets
reg varoffset1;
reg [6:0] varoffset2;
reg [6:0] varoffset3;
integer cyc = 0;
// Non-constant offsets
reg varoffset1;
reg [6:0] varoffset2;
reg [6:0] varoffset3;
// Destinations for variable-offset assignments
reg [69:0] dstwide1;
reg [69:0] dstwide2;
reg [1:0] dstnarrow;
// Destinations for variable-offset assignments
reg [69:0] dstwide1;
reg [69:0] dstwide2;
reg [1:0] dstnarrow;
// Constant offsets
reg [6:0] constoffset;
// Constant offsets
reg [6:0] constoffset;
// Destinations for constant-offset assignments
reg [2:0] dst_cdata;
reg [11:0] dst_sdata;
reg [29:0] dst_idata;
reg [59:0] dst_qdata;
reg [69:0] dst_wdata1; // assign idata within word
reg [69:0] dst_wdata2; // assign idata crossing word boundary
reg [69:0] dst_wdata3; // assign idata corresponding to whole word
reg [69:0] dst_wdata4; // assign qdata
reg [69:0] dst_wdata5; // assign wdata corresponding to several whole words
reg [69:0] dst_wdata6; // assign wdata starting at word-offset
reg [69:0] dst_wdata7; // assign wdata unaligned
// Destinations for constant-offset assignments
reg [2:0] dst_cdata;
reg [11:0] dst_sdata;
reg [29:0] dst_idata;
reg [59:0] dst_qdata;
reg [69:0] dst_wdata1; // assign idata within word
reg [69:0] dst_wdata2; // assign idata crossing word boundary
reg [69:0] dst_wdata3; // assign idata corresponding to whole word
reg [69:0] dst_wdata4; // assign qdata
reg [69:0] dst_wdata5; // assign wdata corresponding to several whole words
reg [69:0] dst_wdata6; // assign wdata starting at word-offset
reg [69:0] dst_wdata7; // assign wdata unaligned
always @(*) begin
// Non-constant select offset, destination narrow
dstnarrow = 2'd0;
dstnarrow[varoffset1 +: 2'd2] = 2'd2;
always @(*) begin
// Non-constant select offset, destination narrow
dstnarrow = 2'd0;
dstnarrow[varoffset1+:2'd2] = 2'd2;
// Non-constant select offset, destination wide, width == 1
dstwide1 = 70'd0;
dstwide1[varoffset2 +: 1'd1] = 1'd1;
// Non-constant select offset, destination wide, width == 1
dstwide1 = 70'd0;
dstwide1[varoffset2+:1'd1] = 1'd1;
// Non-constant select offset, destination wide, width != 1
dstwide2 = 70'd0;
dstwide2[varoffset3 +: 2'd2] = 2'd2;
// Non-constant select offset, destination wide, width != 1
dstwide2 = 70'd0;
dstwide2[varoffset3+:2'd2] = 2'd2;
// Constant offset, IData into CData
constoffset = 7'd2;
dst_cdata = 3'd0;
dst_cdata[constoffset[0 +: 2] +: 3'd3] = 3'd6;
// Constant offset, IData into CData
constoffset = 7'd2;
dst_cdata = 3'd0;
dst_cdata[constoffset[0+:2]+:3'd3] = 3'd6;
// Constant offset, IData into SData
constoffset = 7'd11;
dst_sdata = 12'd0;
dst_sdata[constoffset[0 +: 4] +: 2'd2] = 2'd2;
// Constant offset, IData into SData
constoffset = 7'd11;
dst_sdata = 12'd0;
dst_sdata[constoffset[0+:4]+:2'd2] = 2'd2;
// Constant offset, IData into IData
constoffset = 7'd29;
dst_idata = 30'd0;
dst_idata[constoffset[0 +: 5] +: 2'd2] = 2'd2;
// Constant offset, IData into IData
constoffset = 7'd29;
dst_idata = 30'd0;
dst_idata[constoffset[0+:5]+:2'd2] = 2'd2;
// Constant offset, QData into QData
constoffset = 7'd59;
dst_qdata = 60'd0;
dst_qdata[constoffset[0 +: 6] +: 2'd2] = 2'd2;
// Constant offset, QData into QData
constoffset = 7'd59;
dst_qdata = 60'd0;
dst_qdata[constoffset[0+:6]+:2'd2] = 2'd2;
// Constant offset, IData into WData within word
constoffset = 7'd69;
dst_wdata1 = 70'd0;
dst_wdata1[constoffset +: 2'd2] = 2'd2;
// Constant offset, IData into WData within word
constoffset = 7'd69;
dst_wdata1 = 70'd0;
dst_wdata1[constoffset+:2'd2] = 2'd2;
// Constant offset, IData into WData crossing word boundary
constoffset = 7'd61;
dst_wdata2 = 70'd0;
dst_wdata2[constoffset +: 4'd10] = 10'd1 << 4'd9;
// Constant offset, IData into WData crossing word boundary
constoffset = 7'd61;
dst_wdata2 = 70'd0;
dst_wdata2[constoffset+:4'd10] = 10'd1 << 4'd9;
// Constant offset, IData into WData replacing a whole word
constoffset = 7'd64;
dst_wdata3 = 70'd0;
dst_wdata3[constoffset +: 6'd32] = 32'd1 << 3'd6;
// Constant offset, IData into WData replacing a whole word
constoffset = 7'd64;
dst_wdata3 = 70'd0;
dst_wdata3[constoffset+:6'd32] = 32'd1 << 3'd6;
// Constant offset, QData into WData
constoffset = 7'd31;
dst_wdata4 = 70'd0;
dst_wdata4[constoffset +: 7'd40] = 40'd1 << 7'd39;
// Constant offset, QData into WData
constoffset = 7'd31;
dst_wdata4 = 70'd0;
dst_wdata4[constoffset+:7'd40] = 40'd1 << 7'd39;
// Constant offset, WData into WData replacing whole words
constoffset = 7'd32;
dst_wdata5 = 70'd0;
dst_wdata5[constoffset +: 7'd64] = 64'd1 << 7'd38;
// Constant offset, WData into WData replacing whole words
constoffset = 7'd32;
dst_wdata5 = 70'd0;
dst_wdata5[constoffset+:7'd64] = 64'd1 << 7'd38;
// Constant offset, WData into WData offset word aligned
constoffset = 7'd32;
dst_wdata6 = 70'd0;
dst_wdata6[constoffset +: 7'd40] = 40'd1 << 7'd38;
// Constant offset, WData into WData offset word aligned
constoffset = 7'd32;
dst_wdata6 = 70'd0;
dst_wdata6[constoffset+:7'd40] = 40'd1 << 7'd38;
// Constant offset, WData into WData unaligned
constoffset = 7'd1;
dst_wdata7 = 70'd0;
dst_wdata7[constoffset +: 7'd70] = 70'd1 << 7'd69;
end
// Constant offset, WData into WData unaligned
constoffset = 7'd1;
dst_wdata7 = 70'd0;
dst_wdata7[constoffset+:7'd70] = 70'd1 << 7'd69;
end
// Test loop
always @ (posedge clk) begin
// State machine to avoid verilator constant-folding offset
if (cyc == 0) begin
// Initialisation
varoffset1 <= 1'd0;
varoffset2 <= 7'd0;
varoffset3 <= 7'd0;
end else if (cyc == 1) begin
// Variable offsets set here to avoid verilator constant folding
varoffset1 <= 1'd1;
varoffset2 <= 7'd70;
varoffset3 <= 7'd69;
end else if (cyc == 2) begin
// Check all destinations are 0
$write("dstwide1 = %23d, downshifted = %23d\n", dstwide1, dstwide1 >> 1);
$write("dstwide2 = %23d, downshifted = %23d\n", dstwide2, dstwide2 >> 1);
$write("dstnarrow = %23d, downshifted = %23d\n", dstnarrow, dstnarrow >> 1);
$write("dst_cdata = %23d, downshifted = %23d\n", dst_cdata, dst_cdata >> 1);
$write("dst_sdata = %23d, downshifted = %23d\n", dst_sdata, dst_sdata >> 1);
$write("dst_idata = %23d, downshifted = %23d\n", dst_idata, dst_idata >> 1);
$write("dst_qdata = %23d, downshifted = %23d\n", dst_qdata, dst_qdata >> 1);
$write("dst_wdata1 = %23d, downshifted = %23d\n", dst_wdata1, dst_wdata1 >> 1);
$write("dst_wdata2 = %23d, downshifted = %23d\n", dst_wdata2, dst_wdata2 >> 1);
$write("dst_wdata3 = %23d, downshifted = %23d\n", dst_wdata3, dst_wdata3 >> 1);
$write("dst_wdata4 = %23d, downshifted = %23d\n", dst_wdata4, dst_wdata4 >> 1);
$write("dst_wdata5 = %23d, downshifted = %23d\n", dst_wdata5, dst_wdata5 >> 1);
$write("dst_wdata6 = %23d, downshifted = %23d\n", dst_wdata6, dst_wdata6 >> 1);
$write("dst_wdata7 = %23d, downshifted = %23d\n", dst_wdata7, dst_wdata7 >> 1);
// Test loop
always @(posedge clk) begin
// State machine to avoid verilator constant-folding offset
if (cyc == 0) begin
// Initialisation
varoffset1 <= 1'd0;
varoffset2 <= 7'd0;
varoffset3 <= 7'd0;
end
else if (cyc == 1) begin
// Variable offsets set here to avoid verilator constant folding
varoffset1 <= 1'd1;
varoffset2 <= 7'd70;
varoffset3 <= 7'd69;
end
else if (cyc == 2) begin
// Check all destinations are 0
$write("dstwide1 = %23d, downshifted = %23d\n", dstwide1, dstwide1 >> 1);
$write("dstwide2 = %23d, downshifted = %23d\n", dstwide2, dstwide2 >> 1);
$write("dstnarrow = %23d, downshifted = %23d\n", dstnarrow, dstnarrow >> 1);
$write("dst_cdata = %23d, downshifted = %23d\n", dst_cdata, dst_cdata >> 1);
$write("dst_sdata = %23d, downshifted = %23d\n", dst_sdata, dst_sdata >> 1);
$write("dst_idata = %23d, downshifted = %23d\n", dst_idata, dst_idata >> 1);
$write("dst_qdata = %23d, downshifted = %23d\n", dst_qdata, dst_qdata >> 1);
$write("dst_wdata1 = %23d, downshifted = %23d\n", dst_wdata1, dst_wdata1 >> 1);
$write("dst_wdata2 = %23d, downshifted = %23d\n", dst_wdata2, dst_wdata2 >> 1);
$write("dst_wdata3 = %23d, downshifted = %23d\n", dst_wdata3, dst_wdata3 >> 1);
$write("dst_wdata4 = %23d, downshifted = %23d\n", dst_wdata4, dst_wdata4 >> 1);
$write("dst_wdata5 = %23d, downshifted = %23d\n", dst_wdata5, dst_wdata5 >> 1);
$write("dst_wdata6 = %23d, downshifted = %23d\n", dst_wdata6, dst_wdata6 >> 1);
$write("dst_wdata7 = %23d, downshifted = %23d\n", dst_wdata7, dst_wdata7 >> 1);
if (dstwide1 !== 70'd0 || (dstwide1 >> 1) !== 70'd0) $stop;
if (dstwide2 !== 70'd0 || (dstwide2 >> 1) !== 70'd0) $stop;
if (dstnarrow !== 2'd0 || (dstnarrow >> 1) !== 2'd0) $stop;
if (dst_cdata !== 3'd0 || (dst_cdata >> 1) !== 3'd0) $stop;
if (dst_sdata !== 12'd0 || (dst_sdata >> 1) !== 12'd0) $stop;
if (dst_idata !== 30'd0 || (dst_idata >> 1) !== 30'd0) $stop;
if (dst_qdata !== 60'd0 || (dst_qdata >> 1) !== 60'd0) $stop;
if (dst_wdata1 !== 70'd0 || (dst_wdata1 >> 1) !== 70'd0) $stop;
if (dst_wdata2 !== 70'd0 || (dst_wdata2 >> 1) !== 70'd0) $stop;
if (dst_wdata3 !== 70'd0 || (dst_wdata3 >> 1) !== 70'd0) $stop;
if (dst_wdata4 !== 70'd0 || (dst_wdata4 >> 1) !== 70'd0) $stop;
if (dst_wdata5 !== 70'd0 || (dst_wdata5 >> 1) !== 70'd0) $stop;
if (dst_wdata6 !== 70'd0 || (dst_wdata6 >> 1) !== 70'd0) $stop;
if (dst_wdata7 !== 70'd0 || (dst_wdata7 >> 1) !== 70'd0) $stop;
end else begin
$write("*-* All Finished *-*\n");
$finish;
end
if (dstwide1 !== 70'd0 || (dstwide1 >> 1) !== 70'd0) $stop;
if (dstwide2 !== 70'd0 || (dstwide2 >> 1) !== 70'd0) $stop;
if (dstnarrow !== 2'd0 || (dstnarrow >> 1) !== 2'd0) $stop;
if (dst_cdata !== 3'd0 || (dst_cdata >> 1) !== 3'd0) $stop;
if (dst_sdata !== 12'd0 || (dst_sdata >> 1) !== 12'd0) $stop;
if (dst_idata !== 30'd0 || (dst_idata >> 1) !== 30'd0) $stop;
if (dst_qdata !== 60'd0 || (dst_qdata >> 1) !== 60'd0) $stop;
if (dst_wdata1 !== 70'd0 || (dst_wdata1 >> 1) !== 70'd0) $stop;
if (dst_wdata2 !== 70'd0 || (dst_wdata2 >> 1) !== 70'd0) $stop;
if (dst_wdata3 !== 70'd0 || (dst_wdata3 >> 1) !== 70'd0) $stop;
if (dst_wdata4 !== 70'd0 || (dst_wdata4 >> 1) !== 70'd0) $stop;
if (dst_wdata5 !== 70'd0 || (dst_wdata5 >> 1) !== 70'd0) $stop;
if (dst_wdata6 !== 70'd0 || (dst_wdata6 >> 1) !== 70'd0) $stop;
if (dst_wdata7 !== 70'd0 || (dst_wdata7 >> 1) !== 70'd0) $stop;
end
else begin
$write("*-* All Finished *-*\n");
$finish;
end
cyc <= cyc + 1;
end
cyc <= cyc + 1;
end
endmodule

8
test_regress/t/t_assigndly_dynamic_notiming_bad.out
View File

@ -1,6 +1,6 @@
%Error-NOTIMING: t/t_assigndly_dynamic_notiming_bad.v:10:11: Delayed assignment in a non-inlined function/task requires --timing
: ... note: In instance '$unit::Cls'
10 | qux <= '1;
| ^~
%Error-NOTIMING: t/t_assigndly_dynamic_notiming_bad.v:10:9: Delayed assignment in a non-inlined function/task requires --timing
: ... note: In instance '$unit::Cls'
10 | qux <= '1;
| ^~
... For error description see https://verilator.org/warn/NOTIMING?v=latest
%Error: Exiting due to

24
test_regress/t/t_assigndly_dynamic_notiming_bad.v
View File

@ -5,19 +5,19 @@
// SPDX-License-Identifier: CC0-1.0
class Cls;
task bar;
static int qux;
qux <= '1;
// Use qux to prevent V3Dead optimizations
$display("qux = %d\n", qux);
endtask
task bar;
static int qux;
qux <= '1;
// Use qux to prevent V3Dead optimizations
$display("qux = %d\n", qux);
endtask
endclass
module t;
initial begin
Cls c;
c.bar();
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
Cls c;
c.bar();
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

8
test_regress/t/t_assigndly_task.v
View File

@ -5,10 +5,10 @@
// SPDX-License-Identifier: CC0-1.0
module t (
input clk,
input [7:0] d,
input [2:0] a,
output [7:0] q
input clk,
input [7:0] d,
input [2:0] a,
output [7:0] q
);
always_ff @(posedge clk) tick(a);

289
test_regress/t/t_assoc.v
View File

@ -4,149 +4,196 @@
// SPDX-FileCopyrightText: 2019 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0);
// verilog_format: on
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
input clk
);
integer cyc = 0;
integer cyc = 0;
integer i;
integer i;
always @ (posedge clk) begin
cyc <= cyc + 1;
begin
// Type
typedef bit [3:0] nibble_t;
typedef string dict_t [nibble_t];
dict_t a;
string b [nibble_t];
nibble_t k;
string v;
always @(posedge clk) begin
cyc <= cyc + 1;
begin
// Type
typedef bit [3:0] nibble_t;
typedef string dict_t[nibble_t];
dict_t a;
string b[nibble_t];
nibble_t k;
string v;
a[4'd3] = "fooed";
a[4'd2] = "bared";
i = a.num(); `checkh(i, 2);
i = a.size; `checkh(i, 2); // Also checks no parens
v = a[4'd3]; `checks(v, "fooed");
v = a[4'd2]; `checks(v, "bared");
i = a.exists(4'd0); `checkh(i, 0);
if (a.exists(4'd0)) $stop; // Check no width warning
i = a.exists(4'd2); `checkh(i, 1);
if (!a.exists(4'd2)) $stop; // Check no width warning
i = a.first(k); `checkh(i, 1); `checks(k, 4'd2);
i = a.next(k); `checkh(i, 1); `checks(k, 4'd3);
i = a.next(k); `checkh(i, 0);
i = a.last(k); `checkh(i, 1); `checks(k, 4'd3);
i = a.prev(k); `checkh(i, 1); `checks(k, 4'd2);
i = a.prev(k); `checkh(i, 0);
`checkp(a, "'{'h2:\"bared\", 'h3:\"fooed\"}");
a[4'd3] = "fooed";
a[4'd2] = "bared";
i = a.num();
`checkh(i, 2);
i = a.size;
`checkh(i, 2); // Also checks no parens
v = a[4'd3];
`checks(v, "fooed");
v = a[4'd2];
`checks(v, "bared");
i = a.exists(4'd0);
`checkh(i, 0);
if (a.exists(4'd0)) $stop; // Check no width warning
i = a.exists(4'd2);
`checkh(i, 1);
if (!a.exists(4'd2)) $stop; // Check no width warning
i = a.first(k);
`checkh(i, 1);
`checks(k, 4'd2);
i = a.next(k);
`checkh(i, 1);
`checks(k, 4'd3);
i = a.next(k);
`checkh(i, 0);
i = a.last(k);
`checkh(i, 1);
`checks(k, 4'd3);
i = a.prev(k);
`checkh(i, 1);
`checks(k, 4'd2);
i = a.prev(k);
`checkh(i, 0);
`checkp(a, "'{'h2:\"bared\", 'h3:\"fooed\"}");
a.first(k); `checks(k, 4'd2);
a.next(k); `checks(k, 4'd3);
a.next(k);
a.last(k); `checks(k, 4'd3);
a.prev(k); `checks(k, 4'd2);
a.first(k);
`checks(k, 4'd2);
a.next(k);
`checks(k, 4'd3);
a.next(k);
a.last(k);
`checks(k, 4'd3);
a.prev(k);
`checks(k, 4'd2);
a.delete(4'd2);
i = a.size(); `checkh(i, 1);
a.delete(4'd2);
i = a.size();
`checkh(i, 1);
b = a; // Copy assignment
i = b.size(); `checkh(i, 1);
end
b = a; // Copy assignment
i = b.size();
`checkh(i, 1);
end
begin
// Strings
string a [string];
string k;
string v;
begin
// Strings
string a[string];
string k;
string v;
a["foo"] = "fooed";
a["bar"] = "bared";
i = a.num(); `checkh(i, 2);
i = a.size(); `checkh(i, 2);
v = a["foo"]; `checks(v, "fooed");
v = a["bar"]; `checks(v, "bared");
i = a.exists("baz"); `checkh(i, 0);
i = a.exists("bar"); `checkh(i, 1);
i = a.first(k); `checkh(i, 1); `checks(k, "bar");
i = a.next(k); `checkh(i, 1); `checks(k, "foo");
i = a.next(k); `checkh(i, 0);
i = a.last(k); `checkh(i, 1); `checks(k, "foo");
i = a.prev(k); `checkh(i, 1); `checks(k, "bar");
i = a.prev(k); `checkh(i, 0);
`checkp(a["foo"], "\"fooed\"");
`checkp(a, "'{\"bar\":\"bared\", \"foo\":\"fooed\"}");
a["foo"] = "fooed";
a["bar"] = "bared";
i = a.num();
`checkh(i, 2);
i = a.size();
`checkh(i, 2);
v = a["foo"];
`checks(v, "fooed");
v = a["bar"];
`checks(v, "bared");
i = a.exists("baz");
`checkh(i, 0);
i = a.exists("bar");
`checkh(i, 1);
i = a.first(k);
`checkh(i, 1);
`checks(k, "bar");
i = a.next(k);
`checkh(i, 1);
`checks(k, "foo");
i = a.next(k);
`checkh(i, 0);
i = a.last(k);
`checkh(i, 1);
`checks(k, "foo");
i = a.prev(k);
`checkh(i, 1);
`checks(k, "bar");
i = a.prev(k);
`checkh(i, 0);
`checkp(a["foo"], "\"fooed\"");
`checkp(a, "'{\"bar\":\"bared\", \"foo\":\"fooed\"}");
a.delete("bar");
i = a.size(); `checkh(i, 1);
a.delete();
i = a.size(); `checkh(i, 0);
i = a.first(k); `checkh(i, 0);
i = a.last(k); `checkh(i, 0);
a.delete("bar");
i = a.size();
`checkh(i, 1);
a.delete();
i = a.size();
`checkh(i, 0);
i = a.first(k);
`checkh(i, 0);
i = a.last(k);
`checkh(i, 0);
// Patterns & default
a = '{ "f": "fooed", "b": "bared", default: "defaulted" };
i = a.size(); `checkh(i, 2); // Default doesn't count
v = a["f"]; `checks(v, "fooed");
v = a["b"]; `checks(v, "bared");
v = a["NEXISTS"]; `checks(v, "defaulted");
// Patterns & default
a = '{"f": "fooed", "b": "bared", default: "defaulted"};
i = a.size();
`checkh(i, 2); // Default doesn't count
v = a["f"];
`checks(v, "fooed");
v = a["b"];
`checks(v, "bared");
v = a["NEXISTS"];
`checks(v, "defaulted");
a = '{};
i = a.size(); `checkh(i, 0);
end
a = '{};
i = a.size();
`checkh(i, 0);
end
begin
// Wide-wides - need special array container classes, ick.
logic [91:2] a [ logic [65:1] ];
int b [ bit [99:0] ];
a[~65'hfe] = ~ 90'hfee;
`checkh(a[~65'hfe], ~ 90'hfee);
b[100'b1] = 1;
`checkh(b[100'b1], 1);
end
begin
// Wide-wides - need special array container classes, ick.
logic [91:2] a[logic [65:1]];
int b[bit [99:0]];
a[~65'hfe] = ~90'hfee;
`checkh(a[~65'hfe], ~90'hfee);
b[100'b1] = 1;
`checkh(b[100'b1], 1);
end
begin
int a [string];
int sum;
sum = 0;
a["one"] = 1;
a["two"] = 2;
foreach (a[i]) sum += a[i];
`checkh(sum, 1 + 2);
end
begin
int a[string];
int sum;
sum = 0;
a["one"] = 1;
a["two"] = 2;
foreach (a[i]) sum += a[i];
`checkh(sum, 1 + 2);
end
begin // Issue #5435
int a;
int ok;
int dict [int];
begin // Issue #5435
int a;
int ok;
int dict[int];
dict[3] = 'h13;
dict[4] = 'h14;
dict[5] = 'h15;
dict[3] = 'h13;
dict[4] = 'h14;
dict[5] = 'h15;
a = 4;
ok = dict.first(a);
if (a != 3) $stop;
if (ok != 1) $stop;
a = 4;
ok = dict.next(a);
if (a != 5) $stop;
if (ok != 1) $stop;
a = 4;
ok = dict.last(a);
if (a != 5) $stop;
if (ok != 1) $stop;
end
a = 4;
ok = dict.first(a);
if (a != 3) $stop;
if (ok != 1) $stop;
a = 4;
ok = dict.next(a);
if (a != 5) $stop;
if (ok != 1) $stop;
a = 4;
ok = dict.last(a);
if (a != 5) $stop;
if (ok != 1) $stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

62
test_regress/t/t_assoc2.v
View File

@ -4,45 +4,45 @@
// SPDX-FileCopyrightText: 2019 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
input clk
);
integer cyc = 0;
integer cyc = 0;
int imap[int];
int imap[int];
// associative array of an associative array
logic [31:0] a [logic [31:0]][logic [63:0]];
// associative array of an associative array
logic [31:0] a[logic [31:0]][logic [63:0]];
task static disp();
int i = 60;
imap[i++] = 600;
imap[i++] = 601;
foreach (imap[k]) $display("imap[%0d] = %0d", k, imap[k]);
endtask
task static disp();
int i = 60;
imap[i++] = 600;
imap[i++] = 601;
foreach (imap[k]) $display("imap[%0d] = %0d", k, imap[k]);
endtask
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc == 1) begin
a[5][8] = 8;
a[5][9] = 9;
imap[10] = 100;
imap[11] = 101;
end
else if (cyc == 2) begin
`checkh(a[5][8], 8);
`checkh(a[5][9], 9);
disp();
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 1) begin
a[5][8] = 8;
a[5][9] = 9;
imap[10] = 100;
imap[11] = 101;
end
else if (cyc == 2) begin
`checkh(a[5][8], 8);
`checkh(a[5][9], 9);
disp();
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule

104
test_regress/t/t_assoc_compare.v
View File

@ -4,64 +4,66 @@
// SPDX-FileCopyrightText: 2023 Ilya Barkov
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define check_comp(lhs, rhs, op, exp) if ((exp) != ((lhs) op (rhs))) begin $write("%%Error: %s:%0d: op comparison shall return 'b%x\n", `__FILE__, `__LINE__, (exp)); `stop; end
`define check_comp(lhs, rhs, op, expv) if ((expv) != ((lhs) op (rhs))) begin $write("%%Error: %s:%0d: op comparison shall return 'b%x\n", `__FILE__, `__LINE__, (expv)); `stop; end
// Two checks because == and != may not be derived from each other
`define check_eq(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b1) `check_comp(lhs, rhs, !=, 1'b0)
`define check_ne(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b0) `check_comp(lhs, rhs, !=, 1'b1)
// verilog_format: on
class Cls;
int i;
int i;
endclass
module t;
initial begin
begin // simple case
int assoc1[int];
int assoc2[int];
// Empty are equal
`check_eq(assoc1, assoc2)
// Make different
assoc1[10] = 15;
assoc2[-1] = 365;
`check_ne(assoc1, assoc2)
// Make same
assoc1[-1] = 365;
assoc2[10] = 15;
`check_eq(assoc1, assoc2)
// Don't actually change
assoc1[-1] = 365;
`check_eq(assoc1, assoc2)
// Compare different sizes
assoc1[3] = 0;
`check_ne(assoc1, assoc2)
end
begin // check that a class as key is fine
int assoc1[Cls];
int assoc2[Cls];
automatic Cls a = new;
automatic Cls b = new;
int t;
assoc1[a] = 0;
`check_ne(assoc1, assoc2)
assoc2[a] = 0;
`check_eq(assoc1, assoc2)
assoc2.delete(a);
assoc2[b] = 0;
`check_ne(assoc1, assoc2)
end
begin // check that a class as value is fine
Cls assoc1[int];
Cls assoc2[int];
automatic Cls a = new;
automatic Cls b = new;
assoc1[1] = a;
assoc2[1] = b;
`check_ne(assoc1, assoc2)
assoc2[1] = a;
`check_eq(assoc1, assoc2)
end
$write("*-* All Finished *-*\n");
$finish;
end
initial begin
begin // simple case
int assoc1[int];
int assoc2[int];
// Empty are equal
`check_eq(assoc1, assoc2)
// Make different
assoc1[10] = 15;
assoc2[-1] = 365;
`check_ne(assoc1, assoc2)
// Make same
assoc1[-1] = 365;
assoc2[10] = 15;
`check_eq(assoc1, assoc2)
// Don't actually change
assoc1[-1] = 365;
`check_eq(assoc1, assoc2)
// Compare different sizes
assoc1[3] = 0;
`check_ne(assoc1, assoc2)
end
begin // check that a class as key is fine
int assoc1[Cls];
int assoc2[Cls];
automatic Cls a = new;
automatic Cls b = new;
int t;
assoc1[a] = 0;
`check_ne(assoc1, assoc2)
assoc2[a] = 0;
`check_eq(assoc1, assoc2)
assoc2.delete(a);
assoc2[b] = 0;
`check_ne(assoc1, assoc2)
end
begin // check that a class as value is fine
Cls assoc1[int];
Cls assoc2[int];
automatic Cls a = new;
automatic Cls b = new;
assoc1[1] = a;
assoc2[1] = b;
`check_ne(assoc1, assoc2)
assoc2[1] = a;
`check_eq(assoc1, assoc2)
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

40
test_regress/t/t_assoc_enum.v
View File

@ -11,25 +11,31 @@
// verilog_format: on
class X;
typedef enum int {
INITIAL, RUNNING, SUSPENDED, COMPLETING, DONE
} state_t;
typedef enum int {
INITIAL,
RUNNING,
SUSPENDED,
COMPLETING,
DONE
} state_t;
static string state_names[state_t] = '{
INITIAL: "INITIAL",
RUNNING: "RUNNING",
SUSPENDED: "SUSPENDED",
COMPLETING: "COMPLETING",
DONE: "DONE"
};
protected state_t state;
static
string
state_names[state_t] = '{
INITIAL: "INITIAL",
RUNNING: "RUNNING",
SUSPENDED: "SUSPENDED",
COMPLETING: "COMPLETING",
DONE: "DONE"
};
protected state_t state;
function new();
this.state = INITIAL;
`checks(state_names[this.state], "INITIAL");
this.state = RUNNING;
`checks(state_names[this.state], "RUNNING");
endfunction
function new();
this.state = INITIAL;
`checks(state_names[this.state], "INITIAL");
this.state = RUNNING;
`checks(state_names[this.state], "RUNNING");
endfunction
endclass

7
test_regress/t/t_assoc_method.v
View File

@ -4,10 +4,11 @@
// SPDX-FileCopyrightText: 2024 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0);
// verilog_format: on
module t;
typedef struct {int x, y;} point;
@ -51,7 +52,7 @@ module t;
points_q[1] = point'{2, 4};
points_q[5] = point'{1, 4};
points_qv = points_q.unique(p) with (p.x);
points_qv = points_q.unique(p) with (p.x);
`checkh(points_qv.size, 2);
qi = points_q.unique_index (p) with (p.x + p.y);
qi.sort;
@ -189,7 +190,7 @@ module t;
i = qe.xor();
`checkh(i, 32'b0);
q = '{10: 1, 11: 2};
q = '{10: 1, 11: 2};
qe = '{10: 1, 11: 2};
`checkh(q == qe, 1'b1);
`checkh(q != qe, 1'b0);

96
test_regress/t/t_assoc_method_bad.out
View File

@ -1,67 +1,67 @@
%Error: t/t_assoc_method_bad.v:14:13: The 1 arguments passed to .num method does not match its requiring 0 arguments
%Error: t/t_assoc_method_bad.v:14:11: The 1 arguments passed to .num method does not match its requiring 0 arguments
: ... note: In instance 't'
14 | v = a.num("badarg");
| ^~~
14 | v = a.num("badarg");
| ^~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_assoc_method_bad.v:15:13: The 1 arguments passed to .size method does not match its requiring 0 arguments
%Error: t/t_assoc_method_bad.v:15:11: The 1 arguments passed to .size method does not match its requiring 0 arguments
: ... note: In instance 't'
15 | v = a.size("badarg");
| ^~~~
%Error: t/t_assoc_method_bad.v:16:13: The 0 arguments passed to .exists method does not match its requiring 1 arguments
15 | v = a.size("badarg");
| ^~~~
%Error: t/t_assoc_method_bad.v:16:11: The 0 arguments passed to .exists method does not match its requiring 1 arguments
: ... note: In instance 't'
16 | v = a.exists();
| ^~~~~~
%Error: t/t_assoc_method_bad.v:17:13: The 2 arguments passed to .exists method does not match its requiring 1 arguments
16 | v = a.exists();
| ^~~~~~
%Error: t/t_assoc_method_bad.v:17:11: The 2 arguments passed to .exists method does not match its requiring 1 arguments
: ... note: In instance 't'
17 | v = a.exists(k, "bad2");
| ^~~~~~
%Error: t/t_assoc_method_bad.v:18:13: The 0 arguments passed to .first method does not match its requiring 1 arguments
17 | v = a.exists(k, "bad2");
| ^~~~~~
%Error: t/t_assoc_method_bad.v:18:11: The 0 arguments passed to .first method does not match its requiring 1 arguments
: ... note: In instance 't'
18 | v = a.first();
| ^~~~~
%Error-UNSUPPORTED: t/t_assoc_method_bad.v:18:13: Unsupported: Non-variable on LHS of built-in method 'first'
18 | v = a.first();
| ^~~~~
%Error-UNSUPPORTED: t/t_assoc_method_bad.v:18:11: Unsupported: Non-variable on LHS of built-in method 'first'
: ... note: In instance 't'
18 | v = a.first();
| ^~~~~
18 | v = a.first();
| ^~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: t/t_assoc_method_bad.v:19:13: The 2 arguments passed to .next method does not match its requiring 1 arguments
%Error: t/t_assoc_method_bad.v:19:11: The 2 arguments passed to .next method does not match its requiring 1 arguments
: ... note: In instance 't'
19 | v = a.next(k, "bad2");
| ^~~~
%Error: t/t_assoc_method_bad.v:20:13: The 0 arguments passed to .last method does not match its requiring 1 arguments
19 | v = a.next(k, "bad2");
| ^~~~
%Error: t/t_assoc_method_bad.v:20:11: The 0 arguments passed to .last method does not match its requiring 1 arguments
: ... note: In instance 't'
20 | v = a.last();
| ^~~~
%Error-UNSUPPORTED: t/t_assoc_method_bad.v:20:13: Unsupported: Non-variable on LHS of built-in method 'last'
20 | v = a.last();
| ^~~~
%Error-UNSUPPORTED: t/t_assoc_method_bad.v:20:11: Unsupported: Non-variable on LHS of built-in method 'last'
: ... note: In instance 't'
20 | v = a.last();
| ^~~~
%Error: t/t_assoc_method_bad.v:21:13: The 2 arguments passed to .prev method does not match its requiring 1 arguments
20 | v = a.last();
| ^~~~
%Error: t/t_assoc_method_bad.v:21:11: The 2 arguments passed to .prev method does not match its requiring 1 arguments
: ... note: In instance 't'
21 | v = a.prev(k, "bad2");
| ^~~~
%Error: t/t_assoc_method_bad.v:22:9: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments
21 | v = a.prev(k, "bad2");
| ^~~~
%Error: t/t_assoc_method_bad.v:22:7: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments
: ... note: In instance 't'
22 | a.delete(k, "bad2");
| ^~~~~~
%Error: t/t_assoc_method_bad.v:24:9: Array method 'sort' not legal on associative arrays
22 | a.delete(k, "bad2");
| ^~~~~~
%Error: t/t_assoc_method_bad.v:24:7: Array method 'sort' not legal on associative arrays
: ... note: In instance 't'
24 | a.sort;
| ^~~~
%Error: t/t_assoc_method_bad.v:25:9: Array method 'rsort' not legal on associative arrays
24 | a.sort;
| ^~~~
%Error: t/t_assoc_method_bad.v:25:7: Array method 'rsort' not legal on associative arrays
: ... note: In instance 't'
25 | a.rsort;
| ^~~~~
%Error: t/t_assoc_method_bad.v:26:9: Array method 'reverse' not legal on associative arrays
25 | a.rsort;
| ^~~~~
%Error: t/t_assoc_method_bad.v:26:7: Array method 'reverse' not legal on associative arrays
: ... note: In instance 't'
26 | a.reverse;
| ^~~~~~~
%Error: t/t_assoc_method_bad.v:27:9: Array method 'shuffle' not legal on associative arrays
26 | a.reverse;
| ^~~~~~~
%Error: t/t_assoc_method_bad.v:27:7: Array method 'shuffle' not legal on associative arrays
: ... note: In instance 't'
27 | a.shuffle;
| ^~~~~~~
%Error: t/t_assoc_method_bad.v:29:9: Unknown built-in associative array method 'bad_not_defined'
27 | a.shuffle;
| ^~~~~~~
%Error: t/t_assoc_method_bad.v:29:7: Unknown built-in associative array method 'bad_not_defined'
: ... note: In instance 't'
29 | a.bad_not_defined();
| ^~~~~~~~~~~~~~~
29 | a.bad_not_defined();
| ^~~~~~~~~~~~~~~
%Error: Exiting due to

38
test_regress/t/t_assoc_method_bad.v
View File

@ -6,26 +6,26 @@
module t;
initial begin
string a [string];
string k;
string v;
initial begin
string a[string];
string k;
string v;
v = a.num("badarg");
v = a.size("badarg");
v = a.exists(); // Bad
v = a.exists(k, "bad2");
v = a.first(); // Bad
v = a.next(k, "bad2"); // Bad
v = a.last(); // Bad
v = a.prev(k, "bad2"); // Bad
a.delete(k, "bad2");
v = a.num("badarg");
v = a.size("badarg");
v = a.exists(); // Bad
v = a.exists(k, "bad2");
v = a.first(); // Bad
v = a.next(k, "bad2"); // Bad
v = a.last(); // Bad
v = a.prev(k, "bad2"); // Bad
a.delete(k, "bad2");
a.sort; // Not legal on assoc
a.rsort; // Not legal on assoc
a.reverse; // Not legal on assoc
a.shuffle; // Not legal on assoc
a.sort; // Not legal on assoc
a.rsort; // Not legal on assoc
a.reverse; // Not legal on assoc
a.shuffle; // Not legal on assoc
a.bad_not_defined();
end
a.bad_not_defined();
end
endmodule

6
test_regress/t/t_assoc_method_map.out
View File

@ -1,6 +1,6 @@
%Error-UNSUPPORTED: t/t_assoc_method_map.v:17:15: Unsupported: Associative array 'map' method (IEEE 1800-2023 7.12.5)
%Error-UNSUPPORTED: t/t_assoc_method_map.v:19:13: Unsupported: Associative array 'map' method (IEEE 1800-2023 7.12.5)
: ... note: In instance 't'
17 | res = a.map(el) with (el == 2);
| ^~~
19 | res = a.map(el) with (el == 2);
| ^~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

22
test_regress/t/t_assoc_method_map.v
View File

@ -4,20 +4,22 @@
// SPDX-FileCopyrightText: 2024 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t;
initial begin
automatic int res[];
automatic int a[int] = '{1: 100, 2: 200, 3: 300};
initial begin
automatic int res[];
automatic int a[int] = '{1: 100, 2: 200, 3: 300};
// TODO results not known to be correct
res = a.map(el) with (el == 2);
`checkh(res.size, 3);
`checkh(res[0], 0);
`checkh(res[1], 1);
`checkh(res[2], 0);
end
// TODO results not known to be correct
res = a.map(el) with (el == 2);
`checkh(res.size, 3);
`checkh(res[0], 0);
`checkh(res[1], 1);
`checkh(res[2], 0);
end
endmodule

108
test_regress/t/t_assoc_ref_type.v
View File

@ -5,87 +5,91 @@
// SPDX-License-Identifier: CC0-1.0
class Foo1;
int x = 1;
function int get_x;
return x;
endfunction
int x = 1;
function int get_x;
return x;
endfunction
endclass
class Foo2;
int x = 2;
function int get_x;
return x;
endfunction
int x = 2;
function int get_x;
return x;
endfunction
endclass
class Bar;
typedef Foo1 foo_t;
protected foo_t m_dict[int];
typedef Foo1 foo_t;
protected foo_t m_dict[int];
function void set(int key);
foo_t default_value = new;
m_dict[key] = default_value;
endfunction
function foo_t get(int key);
return m_dict[key];
endfunction
function void set(int key);
foo_t default_value = new;
m_dict[key] = default_value;
endfunction
function foo_t get(int key);
return m_dict[key];
endfunction
endclass
class Baz #(type T=Foo1);
class Baz #(
type T = Foo1
);
protected T m_dict[int];
function void set(int key);
T default_value = new;
m_dict[key] = default_value;
endfunction
function T get(int key);
return m_dict[key];
endfunction
T default_value = new;
m_dict[key] = default_value;
endfunction
function T get(int key);
return m_dict[key];
endfunction
endclass
class WBase;
endclass
class Wrapper#(type VAL_T=int);
VAL_T value;
class Wrapper #(
type VAL_T = int
);
VAL_T value;
endclass
class Bum;
typedef int map_t[string];
map_t m_value;
function new(map_t value);
m_value = value;
endfunction
typedef int map_t[string];
map_t m_value;
function new(map_t value);
m_value = value;
endfunction
endclass
module t;
typedef WBase wrap_map_t[string];
typedef WBase wrap_queue_t[$];
typedef WBase wrap_map_t[string];
typedef WBase wrap_queue_t[$];
localparam string str_key = "the_key";
localparam string str_key = "the_key";
initial begin
automatic Bar bar_i = new;
automatic Baz baz_1_i = new;
automatic Baz #(Foo2) baz_2_i = new;
automatic Bum bum_i;
initial begin
automatic Bar bar_i = new;
automatic Baz baz_1_i = new;
automatic Baz #(Foo2) baz_2_i = new;
automatic Bum bum_i;
automatic Wrapper#(wrap_map_t) wrap_map = new();
automatic Wrapper#(wrap_queue_t) wrap_queue = new();
automatic Wrapper #(wrap_map_t) wrap_map = new();
automatic Wrapper #(wrap_queue_t) wrap_queue = new();
bar_i.set(1);
baz_1_i.set(2);
baz_2_i.set(3);
bar_i.set(1);
baz_1_i.set(2);
baz_2_i.set(3);
if (bar_i.get(1).get_x() != 1) $stop;
if (baz_1_i.get(2).get_x() != 1) $stop;
if (baz_2_i.get(3).get_x() != 2) $stop;
if (bar_i.get(1).get_x() != 1) $stop;
if (baz_1_i.get(2).get_x() != 1) $stop;
if (baz_2_i.get(3).get_x() != 2) $stop;
bum_i = new('{str_key: 42});
if (bum_i.m_value["the_key"] != 42) $stop;
bum_i = new('{str_key: 42});
if (bum_i.m_value["the_key"] != 42) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

84
test_regress/t/t_assoc_wildcard.v
View File

@ -4,51 +4,63 @@
// SPDX-FileCopyrightText: 2019 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
input clk
);
integer cyc = 0;
integer cyc = 0;
integer i;
integer i;
always @ (posedge clk) begin
cyc <= cyc + 1;
begin
// Wildcard
typedef string dict_t [*];
static string a [*] = '{default: "nope", "BBBBB": "fooing", 23'h434343: "baring"};
static dict_t b = '{default: "nope", "BBBBB": "fooing", 23'h434343: "baring"};
int k;
string v;
always @(posedge clk) begin
cyc <= cyc + 1;
begin
// Wildcard
typedef string dict_t [*];
static string a [*] = '{default: "nope", "BBBBB": "fooing", 23'h434343: "baring"};
static dict_t b = '{default: "nope", "BBBBB": "fooing", 23'h434343: "baring"};
int k;
string v;
v = b["CCC"]; `checks(v, "baring");
v = b["BBBBB"]; `checks(v, "fooing");
v = b["CCC"];
`checks(v, "baring");
v = b["BBBBB"];
`checks(v, "fooing");
v = a["CCC"]; `checks(v, "baring");
v = a["BBBBB"]; `checks(v, "fooing");
v = a["CCC"];
`checks(v, "baring");
v = a["BBBBB"];
`checks(v, "fooing");
a[32'd1234] = "fooed";
a[4'd3] = "bared";
a[79'h4141] = "bazed";
i = a.num(); `checkh(i, 5);
i = a.size(); `checkh(i, 5);
v = a[39'd1234]; `checks(v, "fooed");
v = a["AA"]; `checks(v, "bazed");
v = a[4'd3]; `checks(v, "bared");
i = a.exists("baz"); `checkh(i, 0);
i = a.exists(4'd3); `checkh(i, 1);
a.delete(4'd3);
i = a.size(); `checkh(i, 4);
end
a[32'd1234] = "fooed";
a[4'd3] = "bared";
a[79'h4141] = "bazed";
i = a.num();
`checkh(i, 5);
i = a.size();
`checkh(i, 5);
v = a[39'd1234];
`checks(v, "fooed");
v = a["AA"];
`checks(v, "bazed");
v = a[4'd3];
`checks(v, "bared");
i = a.exists("baz");
`checkh(i, 0);
i = a.exists(4'd3);
`checkh(i, 1);
a.delete(4'd3);
i = a.size();
`checkh(i, 4);
end
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

114
test_regress/t/t_assoc_wildcard_bad.out
View File

@ -1,78 +1,78 @@
%Error: t/t_assoc_wildcard_bad.v:23:13: The 1 arguments passed to .num method does not match its requiring 0 arguments
%Error: t/t_assoc_wildcard_bad.v:23:11: The 1 arguments passed to .num method does not match its requiring 0 arguments
: ... note: In instance 't'
23 | v = a.num("badarg");
| ^~~
23 | v = a.num("badarg");
| ^~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_assoc_wildcard_bad.v:24:13: The 1 arguments passed to .size method does not match its requiring 0 arguments
%Error: t/t_assoc_wildcard_bad.v:24:11: The 1 arguments passed to .size method does not match its requiring 0 arguments
: ... note: In instance 't'
24 | v = a.size("badarg");
| ^~~~
%Error: t/t_assoc_wildcard_bad.v:25:13: The 0 arguments passed to .exists method does not match its requiring 1 arguments
24 | v = a.size("badarg");
| ^~~~
%Error: t/t_assoc_wildcard_bad.v:25:11: The 0 arguments passed to .exists method does not match its requiring 1 arguments
: ... note: In instance 't'
25 | v = a.exists();
| ^~~~~~
%Error: t/t_assoc_wildcard_bad.v:26:13: The 2 arguments passed to .exists method does not match its requiring 1 arguments
25 | v = a.exists();
| ^~~~~~
%Error: t/t_assoc_wildcard_bad.v:26:11: The 2 arguments passed to .exists method does not match its requiring 1 arguments
: ... note: In instance 't'
26 | v = a.exists(k, "bad2");
| ^~~~~~
%Error: t/t_assoc_wildcard_bad.v:27:9: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments
26 | v = a.exists(k, "bad2");
| ^~~~~~
%Error: t/t_assoc_wildcard_bad.v:27:7: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments
: ... note: In instance 't'
27 | a.delete(k, "bad2");
| ^~~~~~
%Error: t/t_assoc_wildcard_bad.v:29:9: Array method 'sort' not legal on associative arrays
27 | a.delete(k, "bad2");
| ^~~~~~
%Error: t/t_assoc_wildcard_bad.v:29:7: Array method 'sort' not legal on associative arrays
: ... note: In instance 't'
29 | a.sort;
| ^~~~
%Error: t/t_assoc_wildcard_bad.v:30:9: Array method 'rsort' not legal on associative arrays
29 | a.sort;
| ^~~~
%Error: t/t_assoc_wildcard_bad.v:30:7: Array method 'rsort' not legal on associative arrays
: ... note: In instance 't'
30 | a.rsort;
| ^~~~~
%Error: t/t_assoc_wildcard_bad.v:31:9: Array method 'reverse' not legal on associative arrays
30 | a.rsort;
| ^~~~~
%Error: t/t_assoc_wildcard_bad.v:31:7: Array method 'reverse' not legal on associative arrays
: ... note: In instance 't'
31 | a.reverse;
| ^~~~~~~
%Error: t/t_assoc_wildcard_bad.v:32:9: Array method 'shuffle' not legal on associative arrays
31 | a.reverse;
| ^~~~~~~
%Error: t/t_assoc_wildcard_bad.v:32:7: Array method 'shuffle' not legal on associative arrays
: ... note: In instance 't'
32 | a.shuffle;
| ^~~~~~~
%Error: t/t_assoc_wildcard_bad.v:34:9: Array method 'first' not legal on wildcard associative arrays
32 | a.shuffle;
| ^~~~~~~
%Error: t/t_assoc_wildcard_bad.v:34:7: Array method 'first' not legal on wildcard associative arrays
: ... note: In instance 't'
34 | a.first;
| ^~~~~
%Error: t/t_assoc_wildcard_bad.v:35:9: Array method 'last' not legal on wildcard associative arrays
34 | a.first;
| ^~~~~
%Error: t/t_assoc_wildcard_bad.v:35:7: Array method 'last' not legal on wildcard associative arrays
: ... note: In instance 't'
35 | a.last;
| ^~~~
%Error: t/t_assoc_wildcard_bad.v:36:9: Array method 'next' not legal on wildcard associative arrays
35 | a.last;
| ^~~~
%Error: t/t_assoc_wildcard_bad.v:36:7: Array method 'next' not legal on wildcard associative arrays
: ... note: In instance 't'
36 | a.next;
| ^~~~
%Error: t/t_assoc_wildcard_bad.v:37:9: Array method 'prev' not legal on wildcard associative arrays
36 | a.next;
| ^~~~
%Error: t/t_assoc_wildcard_bad.v:37:7: Array method 'prev' not legal on wildcard associative arrays
: ... note: In instance 't'
37 | a.prev;
| ^~~~
%Error: t/t_assoc_wildcard_bad.v:38:9: Array method 'unique_index' not legal on wildcard associative arrays
37 | a.prev;
| ^~~~
%Error: t/t_assoc_wildcard_bad.v:38:7: Array method 'unique_index' not legal on wildcard associative arrays
: ... note: In instance 't'
38 | a.unique_index;
| ^~~~~~~~~~~~
%Error: t/t_assoc_wildcard_bad.v:39:9: Array method 'find_index' not legal on wildcard associative arrays
38 | a.unique_index;
| ^~~~~~~~~~~~
%Error: t/t_assoc_wildcard_bad.v:39:7: Array method 'find_index' not legal on wildcard associative arrays
: ... note: In instance 't'
39 | a.find_index;
| ^~~~~~~~~~
%Error: t/t_assoc_wildcard_bad.v:40:9: Array method 'find_first_index' not legal on wildcard associative arrays
39 | a.find_index;
| ^~~~~~~~~~
%Error: t/t_assoc_wildcard_bad.v:40:7: Array method 'find_first_index' not legal on wildcard associative arrays
: ... note: In instance 't'
40 | a.find_first_index;
| ^~~~~~~~~~~~~~~~
%Error: t/t_assoc_wildcard_bad.v:41:9: Array method 'find_last_index' not legal on wildcard associative arrays
40 | a.find_first_index;
| ^~~~~~~~~~~~~~~~
%Error: t/t_assoc_wildcard_bad.v:41:7: Array method 'find_last_index' not legal on wildcard associative arrays
: ... note: In instance 't'
41 | a.find_last_index;
| ^~~~~~~~~~~~~~~
%Error: t/t_assoc_wildcard_bad.v:43:8: Wildcard index must be integral (IEEE 1800-2023 7.8.1)
41 | a.find_last_index;
| ^~~~~~~~~~~~~~~
%Error: t/t_assoc_wildcard_bad.v:43:6: Wildcard index must be integral (IEEE 1800-2023 7.8.1)
: ... note: In instance 't'
43 | a[x] = "bad";
| ^
%Error: t/t_assoc_wildcard_bad.v:45:9: Unknown wildcard associative array method 'bad_not_defined'
43 | a[x] = "bad";
| ^
%Error: t/t_assoc_wildcard_bad.v:45:7: Unknown wildcard associative array method 'bad_not_defined'
: ... note: In instance 't'
45 | a.bad_not_defined();
| ^~~~~~~~~~~~~~~
45 | a.bad_not_defined();
| ^~~~~~~~~~~~~~~
%Error: Exiting due to

54
test_regress/t/t_assoc_wildcard_bad.v
View File

@ -7,41 +7,41 @@
typedef class Cls;
class Cls;
integer imembera;
integer imemberb;
integer imembera;
integer imemberb;
endclass : Cls
module t;
initial begin
string a [*];
string k;
string v;
initial begin
string a [*];
string k;
string v;
Cls x;
Cls x;
v = a.num("badarg");
v = a.size("badarg");
v = a.exists(); // Bad
v = a.exists(k, "bad2");
a.delete(k, "bad2");
v = a.num("badarg");
v = a.size("badarg");
v = a.exists(); // Bad
v = a.exists(k, "bad2");
a.delete(k, "bad2");
a.sort; // Not legal on assoc
a.rsort; // Not legal on assoc
a.reverse; // Not legal on assoc
a.shuffle; // Not legal on assoc
a.sort; // Not legal on assoc
a.rsort; // Not legal on assoc
a.reverse; // Not legal on assoc
a.shuffle; // Not legal on assoc
a.first; // Not legal on wildcard
a.last; // Not legal on wildcard
a.next; // Not legal on wildcard
a.prev; // Not legal on wildcard
a.unique_index; // Not legal on wildcard
a.find_index; // Not legal on wildcard
a.find_first_index; // Not legal on wildcard
a.find_last_index; // Not legal on wildcard
a.first; // Not legal on wildcard
a.last; // Not legal on wildcard
a.next; // Not legal on wildcard
a.prev; // Not legal on wildcard
a.unique_index; // Not legal on wildcard
a.find_index; // Not legal on wildcard
a.find_first_index; // Not legal on wildcard
a.find_last_index; // Not legal on wildcard
a[x] = "bad";
a[x] = "bad";
a.bad_not_defined();
end
a.bad_not_defined();
end
endmodule

6
test_regress/t/t_assoc_wildcard_map.out
View File

@ -1,6 +1,6 @@
%Error-UNSUPPORTED: t/t_assoc_wildcard_map.v:19:15: Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5)
%Error-UNSUPPORTED: t/t_assoc_wildcard_map.v:19:13: Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5)
: ... note: In instance 't'
19 | res = a.map(el) with (el == 2);
| ^~~
19 | res = a.map(el) with (el == 2);
| ^~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

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